Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.67	91.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4045218

1

T1

46

T2

95618

T6

358

full_word

2574199

1

T1

6

T2

60172

T5

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6619137	1			T1	52		T2	155790		T5	8
auto[TlIntgErrCmd]	86	1			T53	7		T54	3		T55	6
auto[TlIntgErrData]	88	1			T53	8		T54	3		T55	3
auto[TlIntgErrBoth]	106	1			T53	5		T54	4		T55	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027878

1

T1

52

T2

23553

T5

8

auto[1]

5591539

1

T2

132237

T7

219116

T21

212552

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	422306	1			T1	46		T2	9635		T6	358
auto[TlIntgErrNone]	partial	auto[1]	3622652	1			T2	85983		T7	141098		T21	136616
auto[TlIntgErrNone]	full_word	auto[0]	605442	1			T1	6		T2	13918		T5	8
auto[TlIntgErrNone]	full_word	auto[1]	1968737	1			T2	46254		T7	78018		T21	75936
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T53	3		T54	2		T55	2
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T53	3		T54	1		T55	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T53	1		T55	2		T91	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T53	2		T91	3		T92	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T53	5		T54	2		T55	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T53	1		T54	1		T91	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T92	1		T93	1		T94	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T53	1		T54	1		T91	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T53	4		T54	3		T55	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T95	1		T96	1		T97	1