Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rom_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.05 100.00 98.28 97.26 100.00 69.70 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 113981646 3005983 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 113981646 3005983 0 0
T2 240335 79216 0 0
T3 233643 0 0 0
T4 49466 0 0 0
T5 310094 0 0 0
T6 25950 0 0 0
T7 385381 114551 0 0
T8 17568 0 0 0
T9 33214 0 0 0
T10 25065 0 0 0
T11 255255 0 0 0
T21 0 112618 0 0
T46 0 46070 0 0
T47 0 77200 0 0
T48 0 303460 0 0
T49 0 140343 0 0
T50 0 150850 0 0
T51 0 240062 0 0
T52 0 59598 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%