Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_tlul_cg	62.50	1	100	1	64	64

---

Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_tlul_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	3	5	62.50

Variables for Group Instance rom_ctrl_tlul_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regs_req_check	3	2	1	33.33	100	1	1	0
cp_rom_invalid_condition	2	1	1	50.00	100	1	1	0
cp_rom_req_check	3	0	3	100.00	100	1	1	0

Summary for Variable cp_regs_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	2	1	33.33

User Defined Bins for cp_regs_req_check

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
req_and_done	0	1	1
req_before_done	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

req_after_done

677818

1

T1

1

T3

16

T6

4710

---

Summary for Variable cp_rom_invalid_condition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_rom_invalid_condition

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
check_invalid	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

check_valid

65814957

1

T1

545129

T2

49810

T3

51724

---

Summary for Variable cp_rom_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rom_req_check

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
req_after_done	648138	1			T3	44		T5	10		T6	978
req_and_done	64	1			T5	1		T6	1		T17	1
req_before_done	107	1			T3	1		T6	4		T10	1