Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

992960

1

T3

3

T5

27

T6

36356

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	267128	1			T3	47		T5	296		T6	9524
values[0x0]	375419	1			T6	13913		T12	17794		T13	31842
values[0x1]	388889	1			T6	14111		T12	18558		T13	33299

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19803	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1011633

1

T3

30

T5

175

T6

36953

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3423	1			T8	6		T12	190		T118	2
valid_sources[0x01]	3302	1			T6	448		T10	1		T17	1
valid_sources[0x02]	5235	1			T6	60		T100	5		T12	200
valid_sources[0x03]	4727	1			T18	1		T12	151		T13	957
valid_sources[0x04]	4604	1			T12	194		T13	7		T119	1
valid_sources[0x05]	3811	1			T17	1		T100	1		T12	197
valid_sources[0x06]	4881	1			T18	1		T120	1		T12	177
valid_sources[0x07]	3583	1			T11	7		T102	1		T120	1
valid_sources[0x08]	4527	1			T18	1		T102	1		T12	189
valid_sources[0x09]	3378	1			T6	87		T19	4		T12	191
valid_sources[0x0a]	3058	1			T19	2		T12	175		T13	126
valid_sources[0x0b]	4304	1			T12	190		T13	1256		T121	2
valid_sources[0x0c]	4295	1			T120	1		T12	220		T13	490
valid_sources[0x0d]	3720	1			T12	187		T13	444		T122	1
valid_sources[0x0e]	3234	1			T100	1		T12	154		T36	25
valid_sources[0x0f]	4000	1			T17	2		T120	2		T12	196
valid_sources[0x10]	3430	1			T6	15		T17	1		T19	2
valid_sources[0x11]	4529	1			T6	342		T18	1		T101	1
valid_sources[0x12]	5102	1			T6	5		T120	1		T12	180
valid_sources[0x13]	3758	1			T6	484		T17	1		T12	205
valid_sources[0x14]	4362	1			T10	2		T11	1		T100	3
valid_sources[0x15]	3575	1			T6	37		T102	1		T12	225
valid_sources[0x16]	4271	1			T8	2		T120	1		T12	159
valid_sources[0x17]	4533	1			T6	1411		T12	171		T13	140
valid_sources[0x18]	4948	1			T19	2		T12	189		T14	2
valid_sources[0x19]	3471	1			T6	102		T100	2		T12	199
valid_sources[0x1a]	3845	1			T6	368		T12	196		T14	1
valid_sources[0x1b]	4368	1			T6	197		T10	1		T101	1
valid_sources[0x1c]	4427	1			T6	31		T11	3		T120	6
valid_sources[0x1d]	3262	1			T41	2		T12	190		T123	1
valid_sources[0x1e]	4118	1			T6	308		T17	1		T12	191
valid_sources[0x1f]	3402	1			T101	1		T102	3		T12	205
valid_sources[0x20]	3672	1			T6	5		T16	9		T102	14
valid_sources[0x21]	4055	1			T6	495		T12	186		T13	360
valid_sources[0x22]	3561	1			T102	3		T12	182		T13	297
valid_sources[0x23]	3853	1			T6	191		T17	1		T12	179
valid_sources[0x24]	4440	1			T5	13		T8	1		T101	1
valid_sources[0x25]	3471	1			T100	1		T12	184		T38	3
valid_sources[0x26]	5517	1			T10	1		T18	4		T12	241
valid_sources[0x27]	4483	1			T6	652		T100	1		T120	4
valid_sources[0x28]	4004	1			T6	88		T40	2		T120	2
valid_sources[0x29]	5076	1			T6	198		T12	176		T13	222
valid_sources[0x2a]	3495	1			T6	228		T17	3		T12	176
valid_sources[0x2b]	3425	1			T120	1		T12	197		T13	377
valid_sources[0x2c]	3825	1			T20	1		T101	1		T40	1
valid_sources[0x2d]	6143	1			T10	1		T18	1		T19	2
valid_sources[0x2e]	3551	1			T17	1		T12	173		T75	2
valid_sources[0x2f]	3761	1			T5	49		T6	87		T8	1
valid_sources[0x30]	4800	1			T6	320		T17	1		T100	2
valid_sources[0x31]	3153	1			T11	1		T101	1		T12	192
valid_sources[0x32]	3444	1			T10	1		T17	1		T19	2
valid_sources[0x33]	3265	1			T6	105		T18	1		T12	199
valid_sources[0x34]	6728	1			T17	1		T12	187		T13	1172
valid_sources[0x35]	3131	1			T3	23		T10	1		T12	183
valid_sources[0x36]	3193	1			T17	2		T18	1		T102	3
valid_sources[0x37]	4000	1			T6	163		T18	1		T11	4
valid_sources[0x38]	3955	1			T6	263		T18	1		T102	2
valid_sources[0x39]	4182	1			T6	897		T17	1		T120	1
valid_sources[0x3a]	3953	1			T6	139		T17	1		T12	186
valid_sources[0x3b]	3099	1			T17	1		T12	206		T13	179
valid_sources[0x3c]	3917	1			T6	2		T17	2		T100	1
valid_sources[0x3d]	3687	1			T101	2		T102	3		T12	150
valid_sources[0x3e]	5323	1			T17	2		T12	193		T13	371
valid_sources[0x3f]	4464	1			T6	215		T100	1		T120	1
valid_sources[0x40]	3349	1			T19	2		T12	177		T13	288
valid_sources[0x41]	4728	1			T6	86		T10	1		T12	198
valid_sources[0x42]	3511	1			T6	43		T10	1		T17	2
valid_sources[0x43]	3516	1			T6	131		T21	3		T12	197
valid_sources[0x44]	3260	1			T6	289		T8	2		T11	4
valid_sources[0x45]	5575	1			T6	312		T12	178		T124	8
valid_sources[0x46]	4081	1			T100	1		T120	1		T12	189
valid_sources[0x47]	5350	1			T6	429		T12	180		T13	1638
valid_sources[0x48]	4108	1			T6	5		T19	3		T120	1
valid_sources[0x49]	3999	1			T6	464		T102	2		T120	2
valid_sources[0x4a]	2761	1			T12	215		T14	2		T124	17
valid_sources[0x4b]	3486	1			T6	3		T17	2		T19	2
valid_sources[0x4c]	4915	1			T6	1836		T10	1		T12	199
valid_sources[0x4d]	4978	1			T17	2		T18	1		T19	3
valid_sources[0x4e]	4547	1			T6	185		T120	1		T12	209
valid_sources[0x4f]	3580	1			T6	199		T10	1		T12	197
valid_sources[0x50]	3257	1			T6	22		T12	202		T14	2
valid_sources[0x51]	4039	1			T100	2		T102	12		T12	203
valid_sources[0x52]	3458	1			T19	2		T101	2		T12	190
valid_sources[0x53]	5377	1			T6	119		T12	175		T13	1056
valid_sources[0x54]	4121	1			T17	1		T12	206		T13	881
valid_sources[0x55]	4292	1			T6	389		T12	212		T14	1
valid_sources[0x56]	3722	1			T6	128		T17	1		T12	192
valid_sources[0x57]	3609	1			T12	219		T13	267		T125	2
valid_sources[0x58]	4593	1			T6	161		T102	6		T12	225
valid_sources[0x59]	6081	1			T6	177		T12	191		T13	2328
valid_sources[0x5a]	3833	1			T102	1		T12	179		T13	338
valid_sources[0x5b]	3521	1			T19	6		T12	196		T13	353
valid_sources[0x5c]	4336	1			T5	11		T12	182		T13	736
valid_sources[0x5d]	3719	1			T12	206		T13	287		T126	11
valid_sources[0x5e]	6704	1			T6	1376		T12	219		T13	1224
valid_sources[0x5f]	6665	1			T6	73		T12	198		T13	1238
valid_sources[0x60]	5050	1			T6	432		T17	2		T12	185
valid_sources[0x61]	3967	1			T120	2		T12	165		T13	449
valid_sources[0x62]	3295	1			T6	6		T12	201		T14	5
valid_sources[0x63]	3644	1			T6	46		T17	1		T20	1
valid_sources[0x64]	4742	1			T6	434		T19	8		T120	1
valid_sources[0x65]	3072	1			T6	4		T17	1		T18	2
valid_sources[0x66]	3650	1			T12	172		T13	284		T119	3
valid_sources[0x67]	3325	1			T17	2		T120	1		T12	208
valid_sources[0x68]	3212	1			T17	3		T12	169		T14	1
valid_sources[0x69]	4193	1			T12	179		T13	361		T119	10
valid_sources[0x6a]	3516	1			T10	1		T12	221		T13	125
valid_sources[0x6b]	4235	1			T6	34		T120	1		T12	184
valid_sources[0x6c]	3939	1			T6	528		T102	6		T12	227
valid_sources[0x6d]	5088	1			T6	980		T18	1		T12	197
valid_sources[0x6e]	3924	1			T6	10		T12	183		T121	2
valid_sources[0x6f]	4383	1			T5	42		T6	150		T17	1
valid_sources[0x70]	3407	1			T6	192		T120	2		T12	199
valid_sources[0x71]	3114	1			T6	110		T12	201		T13	59
valid_sources[0x72]	3660	1			T17	2		T20	1		T12	185
valid_sources[0x73]	3160	1			T12	217		T13	287		T119	7
valid_sources[0x74]	3435	1			T6	137		T12	210		T13	245
valid_sources[0x75]	3473	1			T120	1		T12	174		T14	3
valid_sources[0x76]	4719	1			T6	87		T10	1		T11	1
valid_sources[0x77]	4202	1			T6	376		T19	2		T120	1
valid_sources[0x78]	5766	1			T6	769		T17	1		T19	1
valid_sources[0x79]	3713	1			T10	1		T101	1		T120	2
valid_sources[0x7a]	3994	1			T6	346		T17	1		T11	1
valid_sources[0x7b]	3412	1			T6	107		T102	1		T12	172
valid_sources[0x7c]	4199	1			T6	582		T19	1		T12	196
valid_sources[0x7d]	3431	1			T18	2		T12	198		T13	151
valid_sources[0x7e]	4145	1			T10	1		T19	7		T100	1
valid_sources[0x7f]	3623	1			T12	198		T126	20		T127	2
valid_sources[0x80]	3458	1			T10	1		T12	166		T127	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

249082

1

T3

3

T5

27

T6

9033

values[0x0]

all_enables

biggest_size

372064

1

T6

13795

T12

17650

T13

31528

values[0x1]

all_enables

biggest_size

371814

1

T6

13528

T12

17758

T13

31737

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

751603

1

T1

31

T3

6

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	205186	1			T1	45		T2	1		T3	16
values[0x0]	287980	1			T4	3		T6	10859		T7	4
values[0x1]	333215	1			T4	5		T6	12530		T9	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

792637

1

T1

34

T3

9

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2757	1			T6	86		T12	146		T13	281
valid_sources[0x01]	3402	1			T6	92		T19	6		T12	163
valid_sources[0x02]	2842	1			T6	102		T40	1		T12	139
valid_sources[0x03]	3008	1			T6	84		T62	1		T12	149
valid_sources[0x04]	3226	1			T6	139		T12	147		T13	263
valid_sources[0x05]	3232	1			T6	83		T16	2		T12	168
valid_sources[0x06]	3470	1			T6	142		T12	150		T13	239
valid_sources[0x07]	2998	1			T6	82		T12	154		T13	265
valid_sources[0x08]	3711	1			T1	2		T6	137		T12	130
valid_sources[0x09]	3753	1			T6	118		T12	168		T13	281
valid_sources[0x0a]	3310	1			T1	1		T6	81		T16	1
valid_sources[0x0b]	3432	1			T6	130		T18	2		T16	1
valid_sources[0x0c]	3217	1			T6	123		T12	136		T13	269
valid_sources[0x0d]	3039	1			T6	121		T8	2		T12	112
valid_sources[0x0e]	3531	1			T6	177		T60	3		T62	1
valid_sources[0x0f]	3155	1			T6	96		T12	143		T14	2
valid_sources[0x10]	3674	1			T6	120		T12	153		T13	274
valid_sources[0x11]	3380	1			T6	108		T12	146		T13	232
valid_sources[0x12]	3084	1			T4	3		T6	126		T20	4
valid_sources[0x13]	3106	1			T6	119		T18	2		T19	1
valid_sources[0x14]	2854	1			T6	128		T12	156		T13	257
valid_sources[0x15]	3336	1			T6	108		T12	158		T13	249
valid_sources[0x16]	3001	1			T6	101		T12	138		T13	227
valid_sources[0x17]	2967	1			T6	120		T26	1		T12	179
valid_sources[0x18]	2723	1			T6	97		T12	122		T13	265
valid_sources[0x19]	3508	1			T6	138		T47	1		T12	153
valid_sources[0x1a]	3071	1			T1	1		T3	4		T6	109
valid_sources[0x1b]	3312	1			T6	117		T12	145		T13	288
valid_sources[0x1c]	3057	1			T6	119		T12	125		T13	238
valid_sources[0x1d]	2763	1			T6	151		T12	147		T13	307
valid_sources[0x1e]	3681	1			T6	144		T11	1		T12	146
valid_sources[0x1f]	3336	1			T6	119		T18	1		T12	126
valid_sources[0x20]	3350	1			T6	97		T12	135		T13	285
valid_sources[0x21]	3077	1			T6	162		T19	1		T12	152
valid_sources[0x22]	4234	1			T6	121		T12	159		T13	268
valid_sources[0x23]	3121	1			T6	121		T18	1		T21	32
valid_sources[0x24]	3463	1			T6	165		T12	146		T13	255
valid_sources[0x25]	3041	1			T6	124		T12	160		T13	239
valid_sources[0x26]	2986	1			T6	110		T12	146		T13	278
valid_sources[0x27]	2911	1			T6	149		T12	170		T13	257
valid_sources[0x28]	2698	1			T6	117		T12	140		T13	272
valid_sources[0x29]	3552	1			T6	121		T19	28		T12	142
valid_sources[0x2a]	2917	1			T1	1		T6	122		T12	140
valid_sources[0x2b]	2790	1			T1	1		T3	2		T6	106
valid_sources[0x2c]	2875	1			T6	143		T27	1		T12	148
valid_sources[0x2d]	3185	1			T6	147		T12	160		T13	264
valid_sources[0x2e]	2841	1			T6	97		T12	144		T13	275
valid_sources[0x2f]	3153	1			T6	133		T12	148		T13	271
valid_sources[0x30]	3052	1			T6	184		T12	162		T13	268
valid_sources[0x31]	3169	1			T6	129		T40	2		T12	136
valid_sources[0x32]	3859	1			T6	173		T8	2		T12	134
valid_sources[0x33]	3258	1			T6	120		T62	1		T12	158
valid_sources[0x34]	2983	1			T6	117		T12	143		T13	264
valid_sources[0x35]	3518	1			T6	101		T12	154		T13	316
valid_sources[0x36]	3237	1			T6	126		T12	155		T13	265
valid_sources[0x37]	2884	1			T1	1		T3	1		T6	162
valid_sources[0x38]	3850	1			T1	2		T6	105		T12	145
valid_sources[0x39]	3101	1			T6	161		T8	1		T12	154
valid_sources[0x3a]	2796	1			T1	1		T6	132		T18	1
valid_sources[0x3b]	3936	1			T6	155		T18	1		T12	150
valid_sources[0x3c]	2623	1			T6	87		T40	2		T12	131
valid_sources[0x3d]	3065	1			T4	2		T6	138		T18	1
valid_sources[0x3e]	3453	1			T6	148		T12	142		T13	262
valid_sources[0x3f]	3070	1			T6	123		T12	133		T13	282
valid_sources[0x40]	3446	1			T6	135		T12	157		T13	279
valid_sources[0x41]	3005	1			T6	144		T8	1		T62	1
valid_sources[0x42]	3502	1			T6	112		T8	1		T12	155
valid_sources[0x43]	3571	1			T6	94		T12	168		T13	298
valid_sources[0x44]	3035	1			T6	146		T12	151		T13	268
valid_sources[0x45]	3440	1			T1	1		T3	2		T6	118
valid_sources[0x46]	3858	1			T6	88		T18	1		T12	127
valid_sources[0x47]	3453	1			T6	122		T12	156		T13	251
valid_sources[0x48]	3341	1			T1	1		T6	129		T47	1
valid_sources[0x49]	3426	1			T6	120		T12	147		T13	317
valid_sources[0x4a]	2807	1			T6	133		T61	11		T12	172
valid_sources[0x4b]	3331	1			T6	127		T18	1		T12	142
valid_sources[0x4c]	2791	1			T6	145		T12	160		T13	270
valid_sources[0x4d]	3254	1			T6	128		T12	120		T13	245
valid_sources[0x4e]	2658	1			T6	86		T12	127		T13	275
valid_sources[0x4f]	2883	1			T1	2		T6	134		T12	129
valid_sources[0x50]	2764	1			T6	103		T12	127		T13	254
valid_sources[0x51]	2907	1			T6	105		T12	144		T13	263
valid_sources[0x52]	3001	1			T6	114		T12	170		T13	310
valid_sources[0x53]	3349	1			T6	94		T12	135		T13	293
valid_sources[0x54]	3527	1			T6	143		T40	1		T12	149
valid_sources[0x55]	3004	1			T4	1		T6	141		T12	144
valid_sources[0x56]	3422	1			T1	1		T6	146		T12	128
valid_sources[0x57]	3768	1			T6	117		T16	1		T12	157
valid_sources[0x58]	3076	1			T6	105		T12	142		T13	271
valid_sources[0x59]	3124	1			T6	126		T12	139		T13	278
valid_sources[0x5a]	3270	1			T6	122		T12	143		T13	241
valid_sources[0x5b]	2988	1			T6	140		T20	3		T12	140
valid_sources[0x5c]	2876	1			T6	125		T8	1		T18	2
valid_sources[0x5d]	2983	1			T6	146		T40	1		T12	140
valid_sources[0x5e]	3965	1			T6	134		T12	134		T13	285
valid_sources[0x5f]	3514	1			T1	1		T6	89		T12	150
valid_sources[0x60]	2960	1			T6	145		T12	143		T13	288
valid_sources[0x61]	3045	1			T6	88		T12	147		T13	284
valid_sources[0x62]	3061	1			T1	1		T6	134		T12	132
valid_sources[0x63]	3808	1			T6	86		T62	1		T41	1
valid_sources[0x64]	3413	1			T6	155		T12	148		T13	290
valid_sources[0x65]	3404	1			T6	131		T20	2		T12	123
valid_sources[0x66]	3089	1			T6	145		T12	142		T13	262
valid_sources[0x67]	3781	1			T6	122		T47	1		T12	155
valid_sources[0x68]	2700	1			T6	111		T47	2		T41	2
valid_sources[0x69]	3087	1			T6	107		T8	1		T47	1
valid_sources[0x6a]	3868	1			T1	1		T6	104		T8	2
valid_sources[0x6b]	2867	1			T6	107		T40	1		T12	128
valid_sources[0x6c]	3005	1			T6	125		T12	168		T13	241
valid_sources[0x6d]	2803	1			T4	1		T6	135		T47	1
valid_sources[0x6e]	3294	1			T6	132		T11	6		T12	152
valid_sources[0x6f]	3430	1			T6	113		T8	1		T12	139
valid_sources[0x70]	3332	1			T6	136		T12	145		T13	258
valid_sources[0x71]	3300	1			T6	125		T8	2		T18	1
valid_sources[0x72]	2922	1			T1	2		T6	89		T12	153
valid_sources[0x73]	3122	1			T1	2		T6	124		T12	149
valid_sources[0x74]	3034	1			T6	132		T46	1		T12	158
valid_sources[0x75]	3388	1			T6	78		T18	1		T20	1
valid_sources[0x76]	3099	1			T3	1		T6	147		T12	143
valid_sources[0x77]	3477	1			T6	112		T12	147		T13	303
valid_sources[0x78]	2966	1			T6	154		T12	164		T13	253
valid_sources[0x79]	2993	1			T6	108		T8	2		T12	133
valid_sources[0x7a]	3287	1			T1	1		T6	110		T12	110
valid_sources[0x7b]	3154	1			T6	105		T18	2		T12	157
valid_sources[0x7c]	3212	1			T6	119		T18	1		T16	2
valid_sources[0x7d]	3551	1			T6	125		T12	164		T13	257
valid_sources[0x7e]	3249	1			T6	111		T18	1		T12	125
valid_sources[0x7f]	3103	1			T6	138		T8	1		T12	160
valid_sources[0x80]	3636	1			T1	1		T6	111		T12	138

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

188959

1

T1

31

T3

6

T6

7213

values[0x0]

all_enables

biggest_size

281701

1

T4

1

T6

10636

T7

3

values[0x1]

all_enables

biggest_size

280943

1

T4

1

T6

10573

T9

1