Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1821189

1

T3

44

T5

269

T6

69657

full_word

1160296

1

T3

3

T5

27

T6

42795

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2981205	1			T3	47		T5	296		T6	112452
auto[TlIntgErrCmd]	93	1			T54	6		T55	3		T56	3
auto[TlIntgErrData]	105	1			T54	8		T55	10		T56	5
auto[TlIntgErrBoth]	82	1			T54	6		T55	7		T56	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

471134

1

T3

47

T5

296

T6

17554

auto[1]

2510351

1

T6

94898

T12

116680

T13

224985

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	197398	1			T3	44		T5	269		T6	7589
auto[TlIntgErrNone]	partial	auto[1]	1623537	1			T6	62068		T12	74905		T13	148573
auto[TlIntgErrNone]	full_word	auto[0]	273600	1			T3	3		T5	27		T6	9965
auto[TlIntgErrNone]	full_word	auto[1]	886670	1			T6	32830		T12	41775		T13	76412
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T54	2		T55	1		T106	6
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T54	4		T55	2		T56	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T107	2		T109	1		T110	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T106	1		T111	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T54	2		T55	3		T56	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T54	6		T55	4		T56	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T55	1		T103	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T55	2		T56	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T54	3		T55	3		T56	1
auto[TlIntgErrBoth]	partial	auto[1]	38	1			T54	2		T55	4		T56	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T111	1		T113	1		T104	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T54	1		T106	1		T111	1