Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2919024

1

T1

102

T2

256

T6

127

full_word

1858577

1

T1

8

T2

26

T6

17

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4777311	1			T1	110		T2	282		T6	144
auto[TlIntgErrCmd]	102	1			T53	3		T54	4		T55	1
auto[TlIntgErrData]	87	1			T53	5		T54	2		T55	5
auto[TlIntgErrBoth]	101	1			T53	2		T54	4		T55	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

746509

1

T1

110

T2

282

T6

144

auto[1]

4031092

1

T8

140106

T12

604925

T13

115427

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	308021	1			T1	102		T2	256		T6	127
auto[TlIntgErrNone]	partial	auto[1]	2610743	1			T8	90425		T12	393851		T13	75985
auto[TlIntgErrNone]	full_word	auto[0]	438352	1			T1	8		T2	26		T6	17
auto[TlIntgErrNone]	full_word	auto[1]	1420195	1			T8	49681		T12	211074		T13	39442
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T54	1		T55	1		T103	4
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T53	3		T54	3		T103	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T107	1		T108	1		T101	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T103	1		T107	1		T109	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T53	2		T54	1		T55	3
auto[TlIntgErrData]	partial	auto[1]	29	1			T53	3		T55	2		T103	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T54	1		T107	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T103	1		T99	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T53	1		T54	2		T55	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T54	1		T55	2		T103	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T53	1		T54	1		T99	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T55	1		T107	1		T108	1