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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.68 100.00 98.28 97.30 98.37


Total test records in report: 408
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T288 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1562413324 Aug 06 04:43:54 PM PDT 24 Aug 06 04:46:08 PM PDT 24 2070941693 ps
T289 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.15163204 Aug 06 04:43:50 PM PDT 24 Aug 06 04:44:01 PM PDT 24 176132568 ps
T290 /workspace/coverage/default/15.rom_ctrl_stress_all.2177452301 Aug 06 04:43:53 PM PDT 24 Aug 06 04:44:17 PM PDT 24 536900902 ps
T291 /workspace/coverage/default/10.rom_ctrl_alert_test.942657390 Aug 06 04:43:42 PM PDT 24 Aug 06 04:43:50 PM PDT 24 169133132 ps
T292 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3132515428 Aug 06 04:44:13 PM PDT 24 Aug 06 04:44:23 PM PDT 24 384400909 ps
T293 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2806577605 Aug 06 04:43:53 PM PDT 24 Aug 06 04:44:03 PM PDT 24 182391652 ps
T294 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2182305739 Aug 06 04:44:05 PM PDT 24 Aug 06 04:48:17 PM PDT 24 3375995566 ps
T295 /workspace/coverage/default/46.rom_ctrl_stress_all.2296030631 Aug 06 04:44:14 PM PDT 24 Aug 06 04:44:48 PM PDT 24 1739576199 ps
T296 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4184728165 Aug 06 04:43:54 PM PDT 24 Aug 06 04:44:13 PM PDT 24 1320412815 ps
T297 /workspace/coverage/default/35.rom_ctrl_alert_test.1256311235 Aug 06 04:44:10 PM PDT 24 Aug 06 04:44:19 PM PDT 24 690005464 ps
T298 /workspace/coverage/default/17.rom_ctrl_stress_all.1733727139 Aug 06 04:43:41 PM PDT 24 Aug 06 04:44:16 PM PDT 24 2324514923 ps
T299 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1912623894 Aug 06 04:44:08 PM PDT 24 Aug 06 04:44:26 PM PDT 24 1505728286 ps
T300 /workspace/coverage/default/31.rom_ctrl_alert_test.4084955615 Aug 06 04:44:13 PM PDT 24 Aug 06 04:44:23 PM PDT 24 499416250 ps
T301 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1109495679 Aug 06 04:43:37 PM PDT 24 Aug 06 04:48:11 PM PDT 24 21408433803 ps
T302 /workspace/coverage/default/3.rom_ctrl_stress_all.4147963569 Aug 06 04:43:41 PM PDT 24 Aug 06 04:44:06 PM PDT 24 1542809850 ps
T303 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2760207059 Aug 06 04:44:02 PM PDT 24 Aug 06 05:13:00 PM PDT 24 193310642917 ps
T304 /workspace/coverage/default/27.rom_ctrl_stress_all.3098033426 Aug 06 04:44:10 PM PDT 24 Aug 06 04:44:30 PM PDT 24 1472647249 ps
T305 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3869401964 Aug 06 04:43:58 PM PDT 24 Aug 06 04:44:29 PM PDT 24 2058412073 ps
T306 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1436265250 Aug 06 04:44:16 PM PDT 24 Aug 06 04:44:28 PM PDT 24 275101674 ps
T307 /workspace/coverage/default/36.rom_ctrl_alert_test.2792854759 Aug 06 04:44:14 PM PDT 24 Aug 06 04:44:22 PM PDT 24 332596740 ps
T308 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.555532494 Aug 06 04:43:53 PM PDT 24 Aug 06 04:44:04 PM PDT 24 317285075 ps
T309 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4284261956 Aug 06 04:44:02 PM PDT 24 Aug 06 04:49:02 PM PDT 24 16784813088 ps
T310 /workspace/coverage/default/20.rom_ctrl_alert_test.1394952408 Aug 06 04:43:53 PM PDT 24 Aug 06 04:44:03 PM PDT 24 1124004613 ps
T311 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1934325082 Aug 06 04:43:54 PM PDT 24 Aug 06 04:59:32 PM PDT 24 149171915628 ps
T312 /workspace/coverage/default/7.rom_ctrl_stress_all.4271283997 Aug 06 04:43:41 PM PDT 24 Aug 06 04:44:07 PM PDT 24 4045390032 ps
T313 /workspace/coverage/default/48.rom_ctrl_stress_all.2859943104 Aug 06 04:44:13 PM PDT 24 Aug 06 04:44:52 PM PDT 24 1476480366 ps
T314 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2813688519 Aug 06 04:44:13 PM PDT 24 Aug 06 04:44:32 PM PDT 24 1320805973 ps
T315 /workspace/coverage/default/2.rom_ctrl_stress_all.545876541 Aug 06 04:43:44 PM PDT 24 Aug 06 04:44:15 PM PDT 24 2116230141 ps
T316 /workspace/coverage/default/23.rom_ctrl_alert_test.1897428911 Aug 06 04:44:07 PM PDT 24 Aug 06 04:44:15 PM PDT 24 688354628 ps
T317 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2200688069 Aug 06 04:44:22 PM PDT 24 Aug 06 04:46:22 PM PDT 24 2158430806 ps
T318 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1322680748 Aug 06 05:24:13 PM PDT 24 Aug 06 05:24:24 PM PDT 24 662578102 ps
T59 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3066125193 Aug 06 05:24:19 PM PDT 24 Aug 06 05:25:42 PM PDT 24 1319678863 ps
T319 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3544263785 Aug 06 05:24:29 PM PDT 24 Aug 06 05:24:44 PM PDT 24 515985303 ps
T63 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.390604939 Aug 06 05:24:10 PM PDT 24 Aug 06 05:24:21 PM PDT 24 406399027 ps
T320 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3243025565 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:33 PM PDT 24 499903090 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2807120351 Aug 06 05:24:10 PM PDT 24 Aug 06 05:24:24 PM PDT 24 258191715 ps
T321 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4223173693 Aug 06 05:24:29 PM PDT 24 Aug 06 05:24:37 PM PDT 24 173292042 ps
T322 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3432405172 Aug 06 05:24:28 PM PDT 24 Aug 06 05:24:39 PM PDT 24 1168055760 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3213561356 Aug 06 05:24:22 PM PDT 24 Aug 06 05:24:32 PM PDT 24 1029887932 ps
T323 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.53199177 Aug 06 05:24:26 PM PDT 24 Aug 06 05:24:37 PM PDT 24 255558486 ps
T96 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2429187271 Aug 06 05:24:19 PM PDT 24 Aug 06 05:24:28 PM PDT 24 258446094 ps
T91 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3085776437 Aug 06 05:24:32 PM PDT 24 Aug 06 05:24:40 PM PDT 24 1374317784 ps
T324 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.638986317 Aug 06 05:24:32 PM PDT 24 Aug 06 05:24:41 PM PDT 24 2173726959 ps
T70 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1190449168 Aug 06 05:24:21 PM PDT 24 Aug 06 05:24:29 PM PDT 24 1381294765 ps
T325 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.264916227 Aug 06 05:24:19 PM PDT 24 Aug 06 05:24:32 PM PDT 24 1028752419 ps
T326 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.883069328 Aug 06 05:24:29 PM PDT 24 Aug 06 05:24:42 PM PDT 24 259276505 ps
T60 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2445388014 Aug 06 05:24:28 PM PDT 24 Aug 06 05:25:49 PM PDT 24 335557569 ps
T71 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4045882349 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:26 PM PDT 24 257242864 ps
T72 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1882875810 Aug 06 05:24:30 PM PDT 24 Aug 06 05:24:40 PM PDT 24 259482479 ps
T327 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3170923254 Aug 06 05:24:00 PM PDT 24 Aug 06 05:24:14 PM PDT 24 260154366 ps
T73 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2151002804 Aug 06 05:24:18 PM PDT 24 Aug 06 05:24:28 PM PDT 24 915062700 ps
T328 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2087029883 Aug 06 05:24:19 PM PDT 24 Aug 06 05:24:34 PM PDT 24 1031953961 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.317923086 Aug 06 05:24:29 PM PDT 24 Aug 06 05:24:39 PM PDT 24 516560078 ps
T329 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.446235384 Aug 06 05:24:29 PM PDT 24 Aug 06 05:24:38 PM PDT 24 777788921 ps
T330 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2011479317 Aug 06 05:23:59 PM PDT 24 Aug 06 05:24:13 PM PDT 24 176233325 ps
T331 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4138963786 Aug 06 05:23:58 PM PDT 24 Aug 06 05:24:07 PM PDT 24 2368844341 ps
T332 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.356986524 Aug 06 05:24:11 PM PDT 24 Aug 06 05:24:20 PM PDT 24 2268700433 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.396505794 Aug 06 05:23:54 PM PDT 24 Aug 06 05:26:29 PM PDT 24 849900406 ps
T333 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1629786704 Aug 06 05:24:11 PM PDT 24 Aug 06 05:24:24 PM PDT 24 249510226 ps
T93 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1413316578 Aug 06 05:23:57 PM PDT 24 Aug 06 05:24:12 PM PDT 24 264409865 ps
T94 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.558343382 Aug 06 05:24:20 PM PDT 24 Aug 06 05:24:29 PM PDT 24 498192665 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3535403274 Aug 06 05:24:13 PM PDT 24 Aug 06 05:24:21 PM PDT 24 170266448 ps
T334 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3476253097 Aug 06 05:24:32 PM PDT 24 Aug 06 05:24:40 PM PDT 24 722466963 ps
T335 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3242760569 Aug 06 05:24:11 PM PDT 24 Aug 06 05:24:21 PM PDT 24 199546301 ps
T336 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3775583889 Aug 06 05:23:53 PM PDT 24 Aug 06 05:24:05 PM PDT 24 469375563 ps
T337 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1262135536 Aug 06 05:23:59 PM PDT 24 Aug 06 05:24:15 PM PDT 24 3935704635 ps
T338 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2785253711 Aug 06 05:24:32 PM PDT 24 Aug 06 05:24:49 PM PDT 24 1022236325 ps
T339 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3708736016 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:26 PM PDT 24 393266974 ps
T340 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.640833215 Aug 06 05:24:18 PM PDT 24 Aug 06 05:24:56 PM PDT 24 701991518 ps
T341 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2100536287 Aug 06 05:23:59 PM PDT 24 Aug 06 05:24:09 PM PDT 24 1367911186 ps
T100 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3203251402 Aug 06 05:24:29 PM PDT 24 Aug 06 05:27:01 PM PDT 24 712854365 ps
T103 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.706987347 Aug 06 05:24:29 PM PDT 24 Aug 06 05:27:03 PM PDT 24 307696641 ps
T75 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4180418288 Aug 06 05:23:51 PM PDT 24 Aug 06 05:24:06 PM PDT 24 1027815154 ps
T342 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4081774373 Aug 06 05:24:22 PM PDT 24 Aug 06 05:24:34 PM PDT 24 677047693 ps
T104 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1973779615 Aug 06 05:24:19 PM PDT 24 Aug 06 05:25:39 PM PDT 24 282152475 ps
T343 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.163027531 Aug 06 05:23:52 PM PDT 24 Aug 06 05:24:09 PM PDT 24 260713365 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3612443980 Aug 06 05:24:15 PM PDT 24 Aug 06 05:25:37 PM PDT 24 1207622130 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.750395347 Aug 06 05:24:30 PM PDT 24 Aug 06 05:27:03 PM PDT 24 1287406536 ps
T344 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1834601173 Aug 06 05:24:23 PM PDT 24 Aug 06 05:25:45 PM PDT 24 356430860 ps
T345 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1450501728 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:31 PM PDT 24 473026255 ps
T346 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1602171679 Aug 06 05:24:15 PM PDT 24 Aug 06 05:24:23 PM PDT 24 787292311 ps
T347 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1658550600 Aug 06 05:23:53 PM PDT 24 Aug 06 05:24:05 PM PDT 24 172656733 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2069513824 Aug 06 05:24:04 PM PDT 24 Aug 06 05:26:44 PM PDT 24 2304516120 ps
T348 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.818546268 Aug 06 05:23:53 PM PDT 24 Aug 06 05:26:28 PM PDT 24 1598201487 ps
T349 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4066383600 Aug 06 05:23:52 PM PDT 24 Aug 06 05:24:00 PM PDT 24 167330123 ps
T350 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3918480094 Aug 06 05:24:27 PM PDT 24 Aug 06 05:24:39 PM PDT 24 1271276002 ps
T351 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.247233723 Aug 06 05:24:13 PM PDT 24 Aug 06 05:26:48 PM PDT 24 601846524 ps
T106 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.538302462 Aug 06 05:23:57 PM PDT 24 Aug 06 05:26:34 PM PDT 24 299884386 ps
T76 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.87722526 Aug 06 05:24:32 PM PDT 24 Aug 06 05:24:40 PM PDT 24 196789562 ps
T352 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2301509465 Aug 06 05:24:21 PM PDT 24 Aug 06 05:24:30 PM PDT 24 184725516 ps
T353 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1597631022 Aug 06 05:24:22 PM PDT 24 Aug 06 05:24:32 PM PDT 24 259699110 ps
T354 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.889453428 Aug 06 05:24:23 PM PDT 24 Aug 06 05:24:36 PM PDT 24 300353270 ps
T77 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.586935132 Aug 06 05:24:24 PM PDT 24 Aug 06 05:24:34 PM PDT 24 506013147 ps
T355 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3632833251 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:26 PM PDT 24 176124436 ps
T356 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.119355523 Aug 06 05:24:11 PM PDT 24 Aug 06 05:24:25 PM PDT 24 251595075 ps
T83 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3500688977 Aug 06 05:24:11 PM PDT 24 Aug 06 05:24:21 PM PDT 24 1539781673 ps
T84 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1270655054 Aug 06 05:24:26 PM PDT 24 Aug 06 05:24:36 PM PDT 24 1034198235 ps
T357 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1808277836 Aug 06 05:24:10 PM PDT 24 Aug 06 05:25:33 PM PDT 24 5130857948 ps
T358 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2551175382 Aug 06 05:24:11 PM PDT 24 Aug 06 05:24:21 PM PDT 24 1030329747 ps
T359 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2600932239 Aug 06 05:23:58 PM PDT 24 Aug 06 05:24:08 PM PDT 24 1673767144 ps
T360 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1196500098 Aug 06 05:24:18 PM PDT 24 Aug 06 05:24:28 PM PDT 24 643023801 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2756518332 Aug 06 05:24:17 PM PDT 24 Aug 06 05:26:53 PM PDT 24 776780613 ps
T361 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3984300423 Aug 06 05:24:25 PM PDT 24 Aug 06 05:24:35 PM PDT 24 1451520792 ps
T362 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1180990361 Aug 06 05:24:12 PM PDT 24 Aug 06 05:25:32 PM PDT 24 908453230 ps
T99 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.779569215 Aug 06 05:23:59 PM PDT 24 Aug 06 05:24:37 PM PDT 24 1521454210 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1257945361 Aug 06 05:24:00 PM PDT 24 Aug 06 05:24:10 PM PDT 24 986485861 ps
T363 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2575827175 Aug 06 05:24:30 PM PDT 24 Aug 06 05:24:38 PM PDT 24 1648898453 ps
T364 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1024662060 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:29 PM PDT 24 307911160 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.436977810 Aug 06 05:23:54 PM PDT 24 Aug 06 05:24:04 PM PDT 24 1306945374 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2542365597 Aug 06 05:23:55 PM PDT 24 Aug 06 05:24:05 PM PDT 24 253092503 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4050358495 Aug 06 05:23:54 PM PDT 24 Aug 06 05:24:04 PM PDT 24 1655309966 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2499325641 Aug 06 05:24:01 PM PDT 24 Aug 06 05:24:09 PM PDT 24 176443588 ps
T369 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4006582737 Aug 06 05:24:20 PM PDT 24 Aug 06 05:24:30 PM PDT 24 1037688516 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3292157035 Aug 06 05:24:28 PM PDT 24 Aug 06 05:24:39 PM PDT 24 511139978 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3371407055 Aug 06 05:24:08 PM PDT 24 Aug 06 05:24:17 PM PDT 24 176295094 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2183232502 Aug 06 05:23:59 PM PDT 24 Aug 06 05:24:07 PM PDT 24 2361746286 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3075950611 Aug 06 05:24:34 PM PDT 24 Aug 06 05:27:12 PM PDT 24 1560457486 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2743985237 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:28 PM PDT 24 1018788196 ps
T374 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2846120562 Aug 06 05:24:30 PM PDT 24 Aug 06 05:24:43 PM PDT 24 260300222 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3270538014 Aug 06 05:24:18 PM PDT 24 Aug 06 05:24:27 PM PDT 24 688041228 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4256916334 Aug 06 05:23:57 PM PDT 24 Aug 06 05:24:07 PM PDT 24 1182729959 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1311345812 Aug 06 05:24:12 PM PDT 24 Aug 06 05:24:21 PM PDT 24 767149467 ps
T378 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.890167830 Aug 06 05:24:27 PM PDT 24 Aug 06 05:24:37 PM PDT 24 1034054106 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1404269483 Aug 06 05:24:10 PM PDT 24 Aug 06 05:24:21 PM PDT 24 1061543393 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2820925004 Aug 06 05:23:58 PM PDT 24 Aug 06 05:24:08 PM PDT 24 259978000 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2410049571 Aug 06 05:24:19 PM PDT 24 Aug 06 05:25:40 PM PDT 24 1297161541 ps
T382 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2060677815 Aug 06 05:24:25 PM PDT 24 Aug 06 05:24:37 PM PDT 24 685558254 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1799771986 Aug 06 05:23:54 PM PDT 24 Aug 06 05:24:07 PM PDT 24 638451220 ps
T384 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.293801512 Aug 06 05:24:19 PM PDT 24 Aug 06 05:24:29 PM PDT 24 507785977 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2178971019 Aug 06 05:23:57 PM PDT 24 Aug 06 05:24:07 PM PDT 24 285623299 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2904937756 Aug 06 05:24:25 PM PDT 24 Aug 06 05:24:35 PM PDT 24 1012056968 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1971899519 Aug 06 05:23:52 PM PDT 24 Aug 06 05:24:08 PM PDT 24 1032235302 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2902047778 Aug 06 05:24:25 PM PDT 24 Aug 06 05:24:41 PM PDT 24 1036842249 ps
T87 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3168155061 Aug 06 05:23:58 PM PDT 24 Aug 06 05:24:15 PM PDT 24 538032665 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3412197210 Aug 06 05:23:52 PM PDT 24 Aug 06 05:24:02 PM PDT 24 827129137 ps
T390 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.140627697 Aug 06 05:24:30 PM PDT 24 Aug 06 05:24:46 PM PDT 24 1766144827 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2252109138 Aug 06 05:23:54 PM PDT 24 Aug 06 05:24:05 PM PDT 24 1104411448 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1007771908 Aug 06 05:24:19 PM PDT 24 Aug 06 05:24:31 PM PDT 24 178188292 ps
T392 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1135587438 Aug 06 05:24:26 PM PDT 24 Aug 06 05:27:01 PM PDT 24 1920627898 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4232354863 Aug 06 05:23:55 PM PDT 24 Aug 06 05:24:11 PM PDT 24 712288399 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.237539602 Aug 06 05:24:23 PM PDT 24 Aug 06 05:24:33 PM PDT 24 1039299025 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3679654965 Aug 06 05:24:18 PM PDT 24 Aug 06 05:24:28 PM PDT 24 187356065 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1943283177 Aug 06 05:24:12 PM PDT 24 Aug 06 05:24:25 PM PDT 24 175404638 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1989642786 Aug 06 05:24:12 PM PDT 24 Aug 06 05:24:21 PM PDT 24 506848688 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3510980919 Aug 06 05:24:30 PM PDT 24 Aug 06 05:25:52 PM PDT 24 1238193857 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.535883087 Aug 06 05:24:34 PM PDT 24 Aug 06 05:24:42 PM PDT 24 751879189 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4294937010 Aug 06 05:24:14 PM PDT 24 Aug 06 05:24:24 PM PDT 24 259951269 ps
T398 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4101074910 Aug 06 05:24:27 PM PDT 24 Aug 06 05:24:37 PM PDT 24 375131097 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3849181114 Aug 06 05:24:09 PM PDT 24 Aug 06 05:24:21 PM PDT 24 339563725 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3314020005 Aug 06 05:24:10 PM PDT 24 Aug 06 05:24:24 PM PDT 24 1030597215 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2033705107 Aug 06 05:23:53 PM PDT 24 Aug 06 05:24:05 PM PDT 24 708757993 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3650244207 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:26 PM PDT 24 751944200 ps
T403 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1434882849 Aug 06 05:24:27 PM PDT 24 Aug 06 05:24:38 PM PDT 24 1167515586 ps
T404 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2144043959 Aug 06 05:24:17 PM PDT 24 Aug 06 05:24:59 PM PDT 24 2113678969 ps
T405 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.395701811 Aug 06 05:24:19 PM PDT 24 Aug 06 05:24:27 PM PDT 24 689997920 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1203209896 Aug 06 05:23:57 PM PDT 24 Aug 06 05:24:06 PM PDT 24 589937882 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1194468890 Aug 06 05:24:18 PM PDT 24 Aug 06 05:24:28 PM PDT 24 995172440 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.191557712 Aug 06 05:24:21 PM PDT 24 Aug 06 05:24:29 PM PDT 24 167319584 ps

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2957001832
Short name T1
Test name
Test status
Simulation time 55263251338 ps
CPU time 317.59 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:49:01 PM PDT 24
Peak memory 241852 kb
Host smart-84d05b46-9290-4064-b8d3-6b5aa08c1d22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957001832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2957001832
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.252228480
Short name T12
Test name
Test status
Simulation time 91262437972 ps
CPU time 1628.55 seconds
Started Aug 06 04:44:17 PM PDT 24
Finished Aug 06 05:11:26 PM PDT 24
Peak memory 237240 kb
Host smart-26ba7938-e019-4998-90d4-faa4b7feb191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252228480 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.252228480
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.377262894
Short name T7
Test name
Test status
Simulation time 957215953 ps
CPU time 10.77 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:43 PM PDT 24
Peak memory 219992 kb
Host smart-651b9919-8983-4a3a-9e11-67bdd962b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377262894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.377262894
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.396505794
Short name T61
Test name
Test status
Simulation time 849900406 ps
CPU time 154.68 seconds
Started Aug 06 05:23:54 PM PDT 24
Finished Aug 06 05:26:29 PM PDT 24
Peak memory 219384 kb
Host smart-04c5d1c5-3fb5-4221-b34c-60f85a3c750b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396505794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.396505794
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2625995448
Short name T2
Test name
Test status
Simulation time 2760365799 ps
CPU time 9.98 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:24 PM PDT 24
Peak memory 219184 kb
Host smart-ceb694a0-176c-4710-afe6-63b23b8440c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625995448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2625995448
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2000159114
Short name T27
Test name
Test status
Simulation time 4145036483 ps
CPU time 123.87 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:45:45 PM PDT 24
Peak memory 235888 kb
Host smart-e9faf12a-00fe-4075-89b9-7e828dbefb1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000159114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2000159114
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.390604939
Short name T63
Test name
Test status
Simulation time 406399027 ps
CPU time 10.13 seconds
Started Aug 06 05:24:10 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 211152 kb
Host smart-0332ec3a-a6d9-486b-a153-6be46c319386
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390604939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.390604939
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.818546268
Short name T348
Test name
Test status
Simulation time 1598201487 ps
CPU time 154.29 seconds
Started Aug 06 05:23:53 PM PDT 24
Finished Aug 06 05:26:28 PM PDT 24
Peak memory 214728 kb
Host smart-8f2128fa-e932-4937-87d3-7e7732965d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818546268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.818546268
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.442337307
Short name T45
Test name
Test status
Simulation time 53806971019 ps
CPU time 2078.36 seconds
Started Aug 06 04:44:02 PM PDT 24
Finished Aug 06 05:18:40 PM PDT 24
Peak memory 241352 kb
Host smart-e94ae1eb-f65f-4e9f-8ab7-9ab028f6a18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442337307 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.442337307
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.44452272
Short name T11
Test name
Test status
Simulation time 10778943832 ps
CPU time 136.33 seconds
Started Aug 06 04:43:36 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 220132 kb
Host smart-d653b16e-72e1-4504-8633-e70c3d74e41a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44452272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_co
rrupt_sig_fatal_chk.44452272
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1265836403
Short name T24
Test name
Test status
Simulation time 351274775 ps
CPU time 18.91 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:43:59 PM PDT 24
Peak memory 219944 kb
Host smart-af02d642-8c52-4851-8f5d-20f80cc9116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265836403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1265836403
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2524301450
Short name T200
Test name
Test status
Simulation time 332395466 ps
CPU time 19.11 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:44:02 PM PDT 24
Peak memory 219824 kb
Host smart-f2131e16-d15f-4089-b592-0fc57d489657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524301450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2524301450
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1413316578
Short name T93
Test name
Test status
Simulation time 264409865 ps
CPU time 14.41 seconds
Started Aug 06 05:23:57 PM PDT 24
Finished Aug 06 05:24:12 PM PDT 24
Peak memory 212996 kb
Host smart-1000f260-3ac7-4c0c-be18-70abe4322083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413316578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1413316578
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1973779615
Short name T104
Test name
Test status
Simulation time 282152475 ps
CPU time 79.85 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:25:39 PM PDT 24
Peak memory 213324 kb
Host smart-b0033e03-dff5-4e0d-a74d-7842d77de320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973779615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1973779615
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3510980919
Short name T102
Test name
Test status
Simulation time 1238193857 ps
CPU time 81.89 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:25:52 PM PDT 24
Peak memory 213040 kb
Host smart-7b43fcb2-a7fc-40f7-941e-aa0755459809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510980919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3510980919
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.750395347
Short name T105
Test name
Test status
Simulation time 1287406536 ps
CPU time 152.98 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 219412 kb
Host smart-5f79bf7e-bfe6-4266-9c3c-d116d2d6bc09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750395347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.750395347
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3322551435
Short name T53
Test name
Test status
Simulation time 224032360 ps
CPU time 10.29 seconds
Started Aug 06 04:43:33 PM PDT 24
Finished Aug 06 04:43:43 PM PDT 24
Peak memory 219948 kb
Host smart-86994f3f-ebf6-4535-ba77-6ebed7b1439a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322551435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3322551435
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4180418288
Short name T75
Test name
Test status
Simulation time 1027815154 ps
CPU time 14.8 seconds
Started Aug 06 05:23:51 PM PDT 24
Finished Aug 06 05:24:06 PM PDT 24
Peak memory 212172 kb
Host smart-0d39740b-c8b4-41bc-a18a-93db45e7bbd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180418288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4180418288
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2542365597
Short name T366
Test name
Test status
Simulation time 253092503 ps
CPU time 10.11 seconds
Started Aug 06 05:23:55 PM PDT 24
Finished Aug 06 05:24:05 PM PDT 24
Peak memory 211244 kb
Host smart-4e711281-c5ef-4754-a5dc-71d1584f4b9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542365597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2542365597
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1971899519
Short name T387
Test name
Test status
Simulation time 1032235302 ps
CPU time 15.37 seconds
Started Aug 06 05:23:52 PM PDT 24
Finished Aug 06 05:24:08 PM PDT 24
Peak memory 211408 kb
Host smart-ed61a66a-debd-44bd-b371-c23d45af582d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971899519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1971899519
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.163027531
Short name T343
Test name
Test status
Simulation time 260713365 ps
CPU time 17.01 seconds
Started Aug 06 05:23:52 PM PDT 24
Finished Aug 06 05:24:09 PM PDT 24
Peak memory 211212 kb
Host smart-53ff6188-661d-4a83-a06d-c36e85656e0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163027531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.163027531
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2033705107
Short name T401
Test name
Test status
Simulation time 708757993 ps
CPU time 11.45 seconds
Started Aug 06 05:23:53 PM PDT 24
Finished Aug 06 05:24:05 PM PDT 24
Peak memory 217972 kb
Host smart-1ede60d3-9ff7-42f9-9ec8-dcb6625e63e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033705107 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2033705107
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3412197210
Short name T389
Test name
Test status
Simulation time 827129137 ps
CPU time 9.55 seconds
Started Aug 06 05:23:52 PM PDT 24
Finished Aug 06 05:24:02 PM PDT 24
Peak memory 211096 kb
Host smart-186a4ebd-2120-47a0-a028-33ceb655afe4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412197210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3412197210
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4066383600
Short name T349
Test name
Test status
Simulation time 167330123 ps
CPU time 8.07 seconds
Started Aug 06 05:23:52 PM PDT 24
Finished Aug 06 05:24:00 PM PDT 24
Peak memory 211168 kb
Host smart-4fe0a328-4835-49e3-b1fd-65a7eb11e12a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066383600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4066383600
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3775583889
Short name T336
Test name
Test status
Simulation time 469375563 ps
CPU time 11.94 seconds
Started Aug 06 05:23:53 PM PDT 24
Finished Aug 06 05:24:05 PM PDT 24
Peak memory 213180 kb
Host smart-a08b1cb0-ef1b-4f71-9155-bbe392afe450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775583889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3775583889
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1658550600
Short name T347
Test name
Test status
Simulation time 172656733 ps
CPU time 12.45 seconds
Started Aug 06 05:23:53 PM PDT 24
Finished Aug 06 05:24:05 PM PDT 24
Peak memory 217116 kb
Host smart-5bf65705-baf3-40a8-bd97-355188fe8895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658550600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1658550600
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1257945361
Short name T85
Test name
Test status
Simulation time 986485861 ps
CPU time 10.09 seconds
Started Aug 06 05:24:00 PM PDT 24
Finished Aug 06 05:24:10 PM PDT 24
Peak memory 211572 kb
Host smart-60990874-7244-4aed-aed7-77c193cca0ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257945361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1257945361
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4050358495
Short name T367
Test name
Test status
Simulation time 1655309966 ps
CPU time 10.23 seconds
Started Aug 06 05:23:54 PM PDT 24
Finished Aug 06 05:24:04 PM PDT 24
Peak memory 211660 kb
Host smart-1c71f439-e23f-43e5-9807-5a2ddc87becf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050358495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4050358495
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4232354863
Short name T89
Test name
Test status
Simulation time 712288399 ps
CPU time 15.53 seconds
Started Aug 06 05:23:55 PM PDT 24
Finished Aug 06 05:24:11 PM PDT 24
Peak memory 212652 kb
Host smart-bd0204e8-57a8-4e70-9e02-54e2ae0c8ce2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232354863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4232354863
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2252109138
Short name T391
Test name
Test status
Simulation time 1104411448 ps
CPU time 11.74 seconds
Started Aug 06 05:23:54 PM PDT 24
Finished Aug 06 05:24:05 PM PDT 24
Peak memory 218192 kb
Host smart-40e0a3db-f808-42c5-84a8-b8d9e9bce238
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252109138 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2252109138
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2499325641
Short name T368
Test name
Test status
Simulation time 176443588 ps
CPU time 8.32 seconds
Started Aug 06 05:24:01 PM PDT 24
Finished Aug 06 05:24:09 PM PDT 24
Peak memory 211376 kb
Host smart-9fb8befb-b384-494d-b231-d19a50800e06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499325641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2499325641
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4256916334
Short name T376
Test name
Test status
Simulation time 1182729959 ps
CPU time 9.81 seconds
Started Aug 06 05:23:57 PM PDT 24
Finished Aug 06 05:24:07 PM PDT 24
Peak memory 211080 kb
Host smart-0f616f8f-4b21-431c-9b88-4534e14c0ea8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256916334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4256916334
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.436977810
Short name T365
Test name
Test status
Simulation time 1306945374 ps
CPU time 9.78 seconds
Started Aug 06 05:23:54 PM PDT 24
Finished Aug 06 05:24:04 PM PDT 24
Peak memory 211132 kb
Host smart-e0528b5e-a54e-4c8b-945b-670f4f6c7039
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436977810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
436977810
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.779569215
Short name T99
Test name
Test status
Simulation time 1521454210 ps
CPU time 37.34 seconds
Started Aug 06 05:23:59 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 213856 kb
Host smart-47a302f7-55fb-4c41-822b-73b16718153e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779569215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.779569215
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1799771986
Short name T383
Test name
Test status
Simulation time 638451220 ps
CPU time 13.68 seconds
Started Aug 06 05:23:54 PM PDT 24
Finished Aug 06 05:24:07 PM PDT 24
Peak memory 218020 kb
Host smart-15f57562-2169-442a-a31a-9ad9579bc4db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799771986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1799771986
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2301509465
Short name T352
Test name
Test status
Simulation time 184725516 ps
CPU time 9.2 seconds
Started Aug 06 05:24:21 PM PDT 24
Finished Aug 06 05:24:30 PM PDT 24
Peak memory 217128 kb
Host smart-f2a99775-e83d-4258-b2c4-4bded25796c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301509465 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2301509465
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1989642786
Short name T396
Test name
Test status
Simulation time 506848688 ps
CPU time 9.87 seconds
Started Aug 06 05:24:12 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 211184 kb
Host smart-7977e823-bf03-44e8-8501-84a05832b2ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989642786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1989642786
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3650244207
Short name T402
Test name
Test status
Simulation time 751944200 ps
CPU time 8.57 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:26 PM PDT 24
Peak memory 211688 kb
Host smart-b1efd998-ae3f-43eb-8ee2-f2f383924c9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650244207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3650244207
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1943283177
Short name T395
Test name
Test status
Simulation time 175404638 ps
CPU time 12.36 seconds
Started Aug 06 05:24:12 PM PDT 24
Finished Aug 06 05:24:25 PM PDT 24
Peak memory 219540 kb
Host smart-d3d45ee4-1cf4-48a8-b739-c0b72630e2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943283177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1943283177
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.247233723
Short name T351
Test name
Test status
Simulation time 601846524 ps
CPU time 155.08 seconds
Started Aug 06 05:24:13 PM PDT 24
Finished Aug 06 05:26:48 PM PDT 24
Peak memory 214832 kb
Host smart-f54aaac4-0175-4b95-a90d-9031d5fe3860
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247233723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.247233723
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1404269483
Short name T379
Test name
Test status
Simulation time 1061543393 ps
CPU time 10.4 seconds
Started Aug 06 05:24:10 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 217496 kb
Host smart-5cfa309d-e248-42a4-84c1-d689de527685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404269483 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1404269483
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2551175382
Short name T358
Test name
Test status
Simulation time 1030329747 ps
CPU time 9.98 seconds
Started Aug 06 05:24:11 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 211396 kb
Host smart-37ba50df-c63a-4dba-a2e1-e9cafa5ec461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551175382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2551175382
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1190449168
Short name T70
Test name
Test status
Simulation time 1381294765 ps
CPU time 8.21 seconds
Started Aug 06 05:24:21 PM PDT 24
Finished Aug 06 05:24:29 PM PDT 24
Peak memory 212116 kb
Host smart-6a8e7ef3-2768-4e3d-a687-f35b58e9e77c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190449168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1190449168
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1629786704
Short name T333
Test name
Test status
Simulation time 249510226 ps
CPU time 12.92 seconds
Started Aug 06 05:24:11 PM PDT 24
Finished Aug 06 05:24:24 PM PDT 24
Peak memory 217908 kb
Host smart-76c3062f-d544-4121-a8f7-78403ecaa474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629786704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1629786704
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2904937756
Short name T386
Test name
Test status
Simulation time 1012056968 ps
CPU time 9.97 seconds
Started Aug 06 05:24:25 PM PDT 24
Finished Aug 06 05:24:35 PM PDT 24
Peak memory 214616 kb
Host smart-6a3c3082-26a8-49a4-a8c8-d841fb2f2814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904937756 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2904937756
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1270655054
Short name T84
Test name
Test status
Simulation time 1034198235 ps
CPU time 9.77 seconds
Started Aug 06 05:24:26 PM PDT 24
Finished Aug 06 05:24:36 PM PDT 24
Peak memory 211508 kb
Host smart-b5a8a8c8-ff9a-494d-b3c6-3c6a8b50aa7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270655054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1270655054
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1597631022
Short name T353
Test name
Test status
Simulation time 259699110 ps
CPU time 9.82 seconds
Started Aug 06 05:24:22 PM PDT 24
Finished Aug 06 05:24:32 PM PDT 24
Peak memory 211844 kb
Host smart-a1cc6e41-568a-442a-b2e1-5fe3825d0873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597631022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1597631022
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1024662060
Short name T364
Test name
Test status
Simulation time 307911160 ps
CPU time 11.27 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:29 PM PDT 24
Peak memory 217948 kb
Host smart-7c3c884b-776a-4ae6-b262-5598377ca887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024662060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1024662060
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1834601173
Short name T344
Test name
Test status
Simulation time 356430860 ps
CPU time 81.59 seconds
Started Aug 06 05:24:23 PM PDT 24
Finished Aug 06 05:25:45 PM PDT 24
Peak memory 219440 kb
Host smart-c74b9482-50bd-48b4-8946-2503cef68622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834601173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1834601173
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2902047778
Short name T388
Test name
Test status
Simulation time 1036842249 ps
CPU time 15.74 seconds
Started Aug 06 05:24:25 PM PDT 24
Finished Aug 06 05:24:41 PM PDT 24
Peak memory 217792 kb
Host smart-ed99141c-6018-4f94-9336-5e7204041549
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902047778 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2902047778
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.586935132
Short name T77
Test name
Test status
Simulation time 506013147 ps
CPU time 9.47 seconds
Started Aug 06 05:24:24 PM PDT 24
Finished Aug 06 05:24:34 PM PDT 24
Peak memory 211224 kb
Host smart-50db57e3-a41c-4d05-a0f9-9e86484f9a82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586935132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.586935132
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2060677815
Short name T382
Test name
Test status
Simulation time 685558254 ps
CPU time 12.08 seconds
Started Aug 06 05:24:25 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 213056 kb
Host smart-7da1b332-9873-45b8-bffb-88fb794e87e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060677815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2060677815
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.883069328
Short name T326
Test name
Test status
Simulation time 259276505 ps
CPU time 12.48 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:42 PM PDT 24
Peak memory 217980 kb
Host smart-a8981487-de04-4d01-a5d0-ff0ae198a632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883069328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.883069328
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1135587438
Short name T392
Test name
Test status
Simulation time 1920627898 ps
CPU time 155.75 seconds
Started Aug 06 05:24:26 PM PDT 24
Finished Aug 06 05:27:01 PM PDT 24
Peak memory 219444 kb
Host smart-ae82dbfe-3ad5-4123-8626-477838067738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135587438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1135587438
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3432405172
Short name T322
Test name
Test status
Simulation time 1168055760 ps
CPU time 10.47 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 218188 kb
Host smart-64feb2c9-3242-499a-891c-8898480c1573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432405172 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3432405172
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.237539602
Short name T393
Test name
Test status
Simulation time 1039299025 ps
CPU time 9.82 seconds
Started Aug 06 05:24:23 PM PDT 24
Finished Aug 06 05:24:33 PM PDT 24
Peak memory 211816 kb
Host smart-abd77ee4-d1b3-40bf-9acc-d13631488343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237539602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.237539602
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4101074910
Short name T398
Test name
Test status
Simulation time 375131097 ps
CPU time 9.81 seconds
Started Aug 06 05:24:27 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 212036 kb
Host smart-9413f9a7-9aa2-4632-8238-88d8195f4cb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101074910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4101074910
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.889453428
Short name T354
Test name
Test status
Simulation time 300353270 ps
CPU time 12.8 seconds
Started Aug 06 05:24:23 PM PDT 24
Finished Aug 06 05:24:36 PM PDT 24
Peak memory 218164 kb
Host smart-bd67c5c9-c76c-4847-a30a-693899fb6980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889453428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.889453428
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1434882849
Short name T403
Test name
Test status
Simulation time 1167515586 ps
CPU time 10.92 seconds
Started Aug 06 05:24:27 PM PDT 24
Finished Aug 06 05:24:38 PM PDT 24
Peak memory 218360 kb
Host smart-981e24de-0f60-43ed-825d-dda92e76843a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434882849 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1434882849
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4223173693
Short name T321
Test name
Test status
Simulation time 173292042 ps
CPU time 8.08 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 211408 kb
Host smart-7bc78f31-9c30-4c99-b3c4-8cab2e996ab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223173693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4223173693
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2575827175
Short name T363
Test name
Test status
Simulation time 1648898453 ps
CPU time 8.3 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:24:38 PM PDT 24
Peak memory 212140 kb
Host smart-2ddca0ef-ff74-4fbb-855b-96d6297a2d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575827175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2575827175
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3918480094
Short name T350
Test name
Test status
Simulation time 1271276002 ps
CPU time 11.63 seconds
Started Aug 06 05:24:27 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 218640 kb
Host smart-f7674925-cb4d-4fe5-b291-0008f162b2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918480094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3918480094
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.446235384
Short name T329
Test name
Test status
Simulation time 777788921 ps
CPU time 8.68 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:38 PM PDT 24
Peak memory 217484 kb
Host smart-eab98844-af8e-4add-a59e-bc549e414abf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446235384 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.446235384
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3984300423
Short name T361
Test name
Test status
Simulation time 1451520792 ps
CPU time 9.98 seconds
Started Aug 06 05:24:25 PM PDT 24
Finished Aug 06 05:24:35 PM PDT 24
Peak memory 211764 kb
Host smart-82115029-f094-4477-a1df-02d5f366759a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984300423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3984300423
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1882875810
Short name T72
Test name
Test status
Simulation time 259482479 ps
CPU time 10.15 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:24:40 PM PDT 24
Peak memory 211912 kb
Host smart-f7190cbd-0309-487b-aaa3-b1a4fee90274
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882875810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1882875810
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3544263785
Short name T319
Test name
Test status
Simulation time 515985303 ps
CPU time 14.81 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:44 PM PDT 24
Peak memory 218180 kb
Host smart-2f74f19f-50a4-4c78-b712-fcd3a3553a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544263785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3544263785
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3203251402
Short name T100
Test name
Test status
Simulation time 712854365 ps
CPU time 152.2 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:27:01 PM PDT 24
Peak memory 219296 kb
Host smart-eed77765-7fe0-4d45-959d-4e6434763726
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203251402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3203251402
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3292157035
Short name T370
Test name
Test status
Simulation time 511139978 ps
CPU time 10.12 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 216348 kb
Host smart-d2271c29-b9e7-4e94-95d0-c8e1d031a6d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292157035 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3292157035
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.890167830
Short name T378
Test name
Test status
Simulation time 1034054106 ps
CPU time 9.88 seconds
Started Aug 06 05:24:27 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 211508 kb
Host smart-c62e20ec-f196-4a0c-948d-6b9338389cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890167830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.890167830
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.317923086
Short name T92
Test name
Test status
Simulation time 516560078 ps
CPU time 9.89 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 212104 kb
Host smart-044fe625-14e1-42c8-989d-3922b3e89389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317923086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.317923086
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2846120562
Short name T374
Test name
Test status
Simulation time 260300222 ps
CPU time 12.77 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:24:43 PM PDT 24
Peak memory 217948 kb
Host smart-812f1349-a3d0-4cab-9c8b-c2a435968d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846120562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2846120562
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2445388014
Short name T60
Test name
Test status
Simulation time 335557569 ps
CPU time 80.88 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:25:49 PM PDT 24
Peak memory 213440 kb
Host smart-51376f9d-95fa-4a00-8693-abdd33e5f906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445388014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2445388014
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.53199177
Short name T323
Test name
Test status
Simulation time 255558486 ps
CPU time 10.84 seconds
Started Aug 06 05:24:26 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 216748 kb
Host smart-d703ad7b-0be3-487b-8da8-839ea5bc496a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53199177 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.53199177
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.535883087
Short name T397
Test name
Test status
Simulation time 751879189 ps
CPU time 8.42 seconds
Started Aug 06 05:24:34 PM PDT 24
Finished Aug 06 05:24:42 PM PDT 24
Peak memory 211356 kb
Host smart-c8a82274-4cec-4f48-b1d7-e911e5603c46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535883087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.535883087
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.87722526
Short name T76
Test name
Test status
Simulation time 196789562 ps
CPU time 8.08 seconds
Started Aug 06 05:24:32 PM PDT 24
Finished Aug 06 05:24:40 PM PDT 24
Peak memory 211608 kb
Host smart-b1c751e2-926d-4de2-8bfb-3e301611d23c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87722526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ct
rl_same_csr_outstanding.87722526
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.140627697
Short name T390
Test name
Test status
Simulation time 1766144827 ps
CPU time 15.43 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:24:46 PM PDT 24
Peak memory 218320 kb
Host smart-b145f001-088d-4c01-b01a-934814038f38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140627697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.140627697
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.706987347
Short name T103
Test name
Test status
Simulation time 307696641 ps
CPU time 153.46 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 219456 kb
Host smart-8efda020-11a4-44bf-b0fe-2174b116508f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706987347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.706987347
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.638986317
Short name T324
Test name
Test status
Simulation time 2173726959 ps
CPU time 8.95 seconds
Started Aug 06 05:24:32 PM PDT 24
Finished Aug 06 05:24:41 PM PDT 24
Peak memory 218420 kb
Host smart-7c3d7418-2ee3-4b34-bb92-f50fcf8759b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638986317 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.638986317
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3085776437
Short name T91
Test name
Test status
Simulation time 1374317784 ps
CPU time 8.17 seconds
Started Aug 06 05:24:32 PM PDT 24
Finished Aug 06 05:24:40 PM PDT 24
Peak memory 211776 kb
Host smart-df233c14-621e-4583-b489-ba87c8a110b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085776437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3085776437
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3476253097
Short name T334
Test name
Test status
Simulation time 722466963 ps
CPU time 8.17 seconds
Started Aug 06 05:24:32 PM PDT 24
Finished Aug 06 05:24:40 PM PDT 24
Peak memory 212236 kb
Host smart-4f9bc883-fd75-48f1-95c8-a9e829f11c0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476253097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3476253097
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2785253711
Short name T338
Test name
Test status
Simulation time 1022236325 ps
CPU time 17.6 seconds
Started Aug 06 05:24:32 PM PDT 24
Finished Aug 06 05:24:49 PM PDT 24
Peak memory 218156 kb
Host smart-1450cc5e-c003-4efe-be76-812a5b10e430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785253711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2785253711
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3075950611
Short name T372
Test name
Test status
Simulation time 1560457486 ps
CPU time 158.2 seconds
Started Aug 06 05:24:34 PM PDT 24
Finished Aug 06 05:27:12 PM PDT 24
Peak memory 219492 kb
Host smart-9f024194-1708-479b-a3d5-7651c92542a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075950611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3075950611
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2183232502
Short name T86
Test name
Test status
Simulation time 2361746286 ps
CPU time 7.92 seconds
Started Aug 06 05:23:59 PM PDT 24
Finished Aug 06 05:24:07 PM PDT 24
Peak memory 211508 kb
Host smart-968fbd9d-dec8-4bdf-a39e-e961a1fbedd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183232502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2183232502
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4138963786
Short name T331
Test name
Test status
Simulation time 2368844341 ps
CPU time 9.15 seconds
Started Aug 06 05:23:58 PM PDT 24
Finished Aug 06 05:24:07 PM PDT 24
Peak memory 211648 kb
Host smart-ae44fa00-7934-4538-a33d-ebb01600971c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138963786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4138963786
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3168155061
Short name T87
Test name
Test status
Simulation time 538032665 ps
CPU time 16.39 seconds
Started Aug 06 05:23:58 PM PDT 24
Finished Aug 06 05:24:15 PM PDT 24
Peak memory 212696 kb
Host smart-8a7f4aa7-222c-4be7-b933-027407dafba4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168155061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3168155061
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2600932239
Short name T359
Test name
Test status
Simulation time 1673767144 ps
CPU time 10.05 seconds
Started Aug 06 05:23:58 PM PDT 24
Finished Aug 06 05:24:08 PM PDT 24
Peak memory 217108 kb
Host smart-574daba6-9a01-4897-86a8-277eed2a6fbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600932239 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2600932239
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2178971019
Short name T385
Test name
Test status
Simulation time 285623299 ps
CPU time 9.7 seconds
Started Aug 06 05:23:57 PM PDT 24
Finished Aug 06 05:24:07 PM PDT 24
Peak memory 211512 kb
Host smart-578d9b3c-bc7a-42ab-9de4-81d09718b6dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178971019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2178971019
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2820925004
Short name T380
Test name
Test status
Simulation time 259978000 ps
CPU time 9.7 seconds
Started Aug 06 05:23:58 PM PDT 24
Finished Aug 06 05:24:08 PM PDT 24
Peak memory 211032 kb
Host smart-454dff73-3e08-4033-a62a-1718e6a0402f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820925004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2820925004
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1262135536
Short name T337
Test name
Test status
Simulation time 3935704635 ps
CPU time 15.14 seconds
Started Aug 06 05:23:59 PM PDT 24
Finished Aug 06 05:24:15 PM PDT 24
Peak memory 211320 kb
Host smart-49fd339a-589e-4261-945a-4bf5469be73b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262135536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1262135536
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2100536287
Short name T341
Test name
Test status
Simulation time 1367911186 ps
CPU time 9.91 seconds
Started Aug 06 05:23:59 PM PDT 24
Finished Aug 06 05:24:09 PM PDT 24
Peak memory 211496 kb
Host smart-52b9a1ca-0434-490f-8162-e8abfede5807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100536287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2100536287
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3170923254
Short name T327
Test name
Test status
Simulation time 260154366 ps
CPU time 13.27 seconds
Started Aug 06 05:24:00 PM PDT 24
Finished Aug 06 05:24:14 PM PDT 24
Peak memory 217864 kb
Host smart-0bb0760e-6d6e-4a4e-9b23-589bebbbfa40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170923254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3170923254
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.538302462
Short name T106
Test name
Test status
Simulation time 299884386 ps
CPU time 155.89 seconds
Started Aug 06 05:23:57 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 214724 kb
Host smart-9a7c6739-2919-4d3e-a536-985eb3623e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538302462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.538302462
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3213561356
Short name T95
Test name
Test status
Simulation time 1029887932 ps
CPU time 10.01 seconds
Started Aug 06 05:24:22 PM PDT 24
Finished Aug 06 05:24:32 PM PDT 24
Peak memory 211132 kb
Host smart-bebaa5b6-53ba-42f0-849f-d8b719046321
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213561356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3213561356
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3270538014
Short name T375
Test name
Test status
Simulation time 688041228 ps
CPU time 8.65 seconds
Started Aug 06 05:24:18 PM PDT 24
Finished Aug 06 05:24:27 PM PDT 24
Peak memory 211488 kb
Host smart-d9760f97-013d-4fc5-8f6a-1c3d1f43f459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270538014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3270538014
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3314020005
Short name T400
Test name
Test status
Simulation time 1030597215 ps
CPU time 13.62 seconds
Started Aug 06 05:24:10 PM PDT 24
Finished Aug 06 05:24:24 PM PDT 24
Peak memory 211452 kb
Host smart-ec068c13-85d7-4992-8be0-9e4f1b4ff3ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314020005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3314020005
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.356986524
Short name T332
Test name
Test status
Simulation time 2268700433 ps
CPU time 9.32 seconds
Started Aug 06 05:24:11 PM PDT 24
Finished Aug 06 05:24:20 PM PDT 24
Peak memory 218040 kb
Host smart-5568beb0-be88-4c8e-a120-3e649835ace9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356986524 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.356986524
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1602171679
Short name T346
Test name
Test status
Simulation time 787292311 ps
CPU time 8.02 seconds
Started Aug 06 05:24:15 PM PDT 24
Finished Aug 06 05:24:23 PM PDT 24
Peak memory 211776 kb
Host smart-e92df597-8183-477c-9989-6e42599e9331
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602171679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1602171679
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.191557712
Short name T408
Test name
Test status
Simulation time 167319584 ps
CPU time 7.97 seconds
Started Aug 06 05:24:21 PM PDT 24
Finished Aug 06 05:24:29 PM PDT 24
Peak memory 211000 kb
Host smart-e2307cad-9be1-4ff9-9a85-54c6912d8c46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191557712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.191557712
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1203209896
Short name T406
Test name
Test status
Simulation time 589937882 ps
CPU time 8.2 seconds
Started Aug 06 05:23:57 PM PDT 24
Finished Aug 06 05:24:06 PM PDT 24
Peak memory 211092 kb
Host smart-a979a658-2120-4060-88f9-6fb123498dd5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203209896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1203209896
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2807120351
Short name T64
Test name
Test status
Simulation time 258191715 ps
CPU time 13.38 seconds
Started Aug 06 05:24:10 PM PDT 24
Finished Aug 06 05:24:24 PM PDT 24
Peak memory 212992 kb
Host smart-0b13b40b-2fb9-4eca-847c-7163e07545f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807120351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2807120351
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2011479317
Short name T330
Test name
Test status
Simulation time 176233325 ps
CPU time 13.84 seconds
Started Aug 06 05:23:59 PM PDT 24
Finished Aug 06 05:24:13 PM PDT 24
Peak memory 218032 kb
Host smart-ec38a667-941f-4d68-975a-f95f1e2dc5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011479317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2011479317
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2069513824
Short name T108
Test name
Test status
Simulation time 2304516120 ps
CPU time 159.83 seconds
Started Aug 06 05:24:04 PM PDT 24
Finished Aug 06 05:26:44 PM PDT 24
Peak memory 214640 kb
Host smart-cf2d9330-1150-46cf-8f27-7888901b926d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069513824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2069513824
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4294937010
Short name T90
Test name
Test status
Simulation time 259951269 ps
CPU time 9.76 seconds
Started Aug 06 05:24:14 PM PDT 24
Finished Aug 06 05:24:24 PM PDT 24
Peak memory 211152 kb
Host smart-e183cd34-777b-4b94-8f61-d17390907e8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294937010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4294937010
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1007771908
Short name T88
Test name
Test status
Simulation time 178188292 ps
CPU time 11.79 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:24:31 PM PDT 24
Peak memory 212136 kb
Host smart-905f7570-3653-47ca-b0bc-757a1f6a399b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007771908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1007771908
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1311345812
Short name T377
Test name
Test status
Simulation time 767149467 ps
CPU time 8.93 seconds
Started Aug 06 05:24:12 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 216760 kb
Host smart-c5fcffc3-b3c4-4e7e-8e04-9735fbe74505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311345812 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1311345812
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3535403274
Short name T74
Test name
Test status
Simulation time 170266448 ps
CPU time 8.24 seconds
Started Aug 06 05:24:13 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 211372 kb
Host smart-ae7f65ec-f99f-4033-9bec-9befaebb56ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535403274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3535403274
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2087029883
Short name T328
Test name
Test status
Simulation time 1031953961 ps
CPU time 14.8 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:24:34 PM PDT 24
Peak memory 211040 kb
Host smart-0b20f995-d627-4ac2-b9d1-c3550056f8ba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087029883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2087029883
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3371407055
Short name T371
Test name
Test status
Simulation time 176295094 ps
CPU time 8.1 seconds
Started Aug 06 05:24:08 PM PDT 24
Finished Aug 06 05:24:17 PM PDT 24
Peak memory 211176 kb
Host smart-e63fc1c9-9edc-47c4-9d93-d86c13960445
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371407055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3371407055
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.640833215
Short name T340
Test name
Test status
Simulation time 701991518 ps
CPU time 37.84 seconds
Started Aug 06 05:24:18 PM PDT 24
Finished Aug 06 05:24:56 PM PDT 24
Peak memory 214420 kb
Host smart-3d199c32-9468-4702-9c44-7c505199a09d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640833215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.640833215
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4081774373
Short name T342
Test name
Test status
Simulation time 677047693 ps
CPU time 11.97 seconds
Started Aug 06 05:24:22 PM PDT 24
Finished Aug 06 05:24:34 PM PDT 24
Peak memory 213132 kb
Host smart-d5601947-b01a-4ac3-932a-8bfd96b353af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081774373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4081774373
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3243025565
Short name T320
Test name
Test status
Simulation time 499903090 ps
CPU time 15.07 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:33 PM PDT 24
Peak memory 218244 kb
Host smart-e88daae5-b093-40d8-859d-b40b7eebffca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243025565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3243025565
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3066125193
Short name T59
Test name
Test status
Simulation time 1319678863 ps
CPU time 83.03 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:25:42 PM PDT 24
Peak memory 214400 kb
Host smart-6bdee065-f147-4835-9cc5-e2cbee94112d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066125193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3066125193
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3242760569
Short name T335
Test name
Test status
Simulation time 199546301 ps
CPU time 10.35 seconds
Started Aug 06 05:24:11 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 218364 kb
Host smart-f8e744f4-9d57-4625-aae6-f039bd828f30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242760569 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3242760569
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4045882349
Short name T71
Test name
Test status
Simulation time 257242864 ps
CPU time 9.64 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:26 PM PDT 24
Peak memory 211200 kb
Host smart-2fadf5fa-e08b-4eb5-8800-7110da8c1508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045882349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4045882349
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2144043959
Short name T404
Test name
Test status
Simulation time 2113678969 ps
CPU time 42.39 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:59 PM PDT 24
Peak memory 214716 kb
Host smart-05fdfcf7-01ad-429d-aed5-68150fdb2ad3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144043959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2144043959
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.293801512
Short name T384
Test name
Test status
Simulation time 507785977 ps
CPU time 10.14 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:24:29 PM PDT 24
Peak memory 212032 kb
Host smart-df69931c-b99e-439f-9aaa-6c118da7cdf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293801512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.293801512
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.264916227
Short name T325
Test name
Test status
Simulation time 1028752419 ps
CPU time 12.53 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:24:32 PM PDT 24
Peak memory 217652 kb
Host smart-02db1030-8d54-4c2e-a2df-01141fed7038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264916227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.264916227
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1180990361
Short name T362
Test name
Test status
Simulation time 908453230 ps
CPU time 79.97 seconds
Started Aug 06 05:24:12 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 214172 kb
Host smart-7d149974-8ca8-41ba-98d2-c3bb679348fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180990361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1180990361
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2743985237
Short name T373
Test name
Test status
Simulation time 1018788196 ps
CPU time 10.9 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:28 PM PDT 24
Peak memory 217344 kb
Host smart-7fe784ae-acdb-4d6f-b74f-54c37c8e556b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743985237 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2743985237
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2429187271
Short name T96
Test name
Test status
Simulation time 258446094 ps
CPU time 9.63 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:24:28 PM PDT 24
Peak memory 211616 kb
Host smart-864227f4-b021-4681-b01d-8d84ac4577ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429187271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2429187271
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3632833251
Short name T355
Test name
Test status
Simulation time 176124436 ps
CPU time 8.3 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:26 PM PDT 24
Peak memory 211764 kb
Host smart-d5cc8547-f139-49b7-aac3-501b56f44cd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632833251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3632833251
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1322680748
Short name T318
Test name
Test status
Simulation time 662578102 ps
CPU time 11.59 seconds
Started Aug 06 05:24:13 PM PDT 24
Finished Aug 06 05:24:24 PM PDT 24
Peak memory 219316 kb
Host smart-7de657fe-9523-4ef5-9338-c1565f888fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322680748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1322680748
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2756518332
Short name T101
Test name
Test status
Simulation time 776780613 ps
CPU time 155.57 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:26:53 PM PDT 24
Peak memory 219472 kb
Host smart-5c929e0c-0703-4c0b-9a60-711bcd80eae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756518332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2756518332
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1196500098
Short name T360
Test name
Test status
Simulation time 643023801 ps
CPU time 9.39 seconds
Started Aug 06 05:24:18 PM PDT 24
Finished Aug 06 05:24:28 PM PDT 24
Peak memory 217848 kb
Host smart-8323a80c-0089-4288-a89e-a2b2c981e92b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196500098 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1196500098
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.395701811
Short name T405
Test name
Test status
Simulation time 689997920 ps
CPU time 8.03 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:24:27 PM PDT 24
Peak memory 211852 kb
Host smart-78cebd18-2272-4e97-a302-e6b1b8ebeed4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395701811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.395701811
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2151002804
Short name T73
Test name
Test status
Simulation time 915062700 ps
CPU time 10.16 seconds
Started Aug 06 05:24:18 PM PDT 24
Finished Aug 06 05:24:28 PM PDT 24
Peak memory 212184 kb
Host smart-63930a4c-e6fe-409a-9cdd-823dd8b61423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151002804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2151002804
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1450501728
Short name T345
Test name
Test status
Simulation time 473026255 ps
CPU time 13.05 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:31 PM PDT 24
Peak memory 218112 kb
Host smart-c79831af-3d48-48e3-ae67-740ab0dc1cca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450501728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1450501728
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3612443980
Short name T107
Test name
Test status
Simulation time 1207622130 ps
CPU time 81.92 seconds
Started Aug 06 05:24:15 PM PDT 24
Finished Aug 06 05:25:37 PM PDT 24
Peak memory 213328 kb
Host smart-2a7ae0c7-608b-4d1c-a45e-5202c56add7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612443980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3612443980
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3708736016
Short name T339
Test name
Test status
Simulation time 393266974 ps
CPU time 8.93 seconds
Started Aug 06 05:24:17 PM PDT 24
Finished Aug 06 05:24:26 PM PDT 24
Peak memory 217660 kb
Host smart-00af2ef5-55ab-4df5-a713-f67530167855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708736016 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3708736016
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4006582737
Short name T369
Test name
Test status
Simulation time 1037688516 ps
CPU time 9.74 seconds
Started Aug 06 05:24:20 PM PDT 24
Finished Aug 06 05:24:30 PM PDT 24
Peak memory 211388 kb
Host smart-1e9231ff-698d-4314-bcc7-92ae42e329c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006582737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4006582737
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1194468890
Short name T407
Test name
Test status
Simulation time 995172440 ps
CPU time 9.71 seconds
Started Aug 06 05:24:18 PM PDT 24
Finished Aug 06 05:24:28 PM PDT 24
Peak memory 212108 kb
Host smart-ac61f320-44d3-4f87-b705-badee2a001a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194468890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1194468890
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.119355523
Short name T356
Test name
Test status
Simulation time 251595075 ps
CPU time 14.64 seconds
Started Aug 06 05:24:11 PM PDT 24
Finished Aug 06 05:24:25 PM PDT 24
Peak memory 218308 kb
Host smart-7815d473-b7de-464a-aaa7-1cf285fbe4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119355523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.119355523
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2410049571
Short name T381
Test name
Test status
Simulation time 1297161541 ps
CPU time 81.59 seconds
Started Aug 06 05:24:19 PM PDT 24
Finished Aug 06 05:25:40 PM PDT 24
Peak memory 214260 kb
Host smart-57a17493-dd1f-426f-a24f-887b1bf3cdf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410049571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2410049571
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3679654965
Short name T394
Test name
Test status
Simulation time 187356065 ps
CPU time 9.61 seconds
Started Aug 06 05:24:18 PM PDT 24
Finished Aug 06 05:24:28 PM PDT 24
Peak memory 218276 kb
Host smart-72871063-409d-49bb-94c5-7c2d6a010412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679654965 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3679654965
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3500688977
Short name T83
Test name
Test status
Simulation time 1539781673 ps
CPU time 9.87 seconds
Started Aug 06 05:24:11 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 211160 kb
Host smart-6a95372c-b6f1-4e39-813e-a3fe47a3ddd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500688977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3500688977
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.558343382
Short name T94
Test name
Test status
Simulation time 498192665 ps
CPU time 9.63 seconds
Started Aug 06 05:24:20 PM PDT 24
Finished Aug 06 05:24:29 PM PDT 24
Peak memory 212004 kb
Host smart-79c1d62b-6159-4150-bbcf-4dedc887d51d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558343382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.558343382
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3849181114
Short name T399
Test name
Test status
Simulation time 339563725 ps
CPU time 12.52 seconds
Started Aug 06 05:24:09 PM PDT 24
Finished Aug 06 05:24:21 PM PDT 24
Peak memory 218112 kb
Host smart-b9237144-cf39-4dbf-9551-87fb3c74a0bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849181114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3849181114
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1808277836
Short name T357
Test name
Test status
Simulation time 5130857948 ps
CPU time 83.08 seconds
Started Aug 06 05:24:10 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 214772 kb
Host smart-7bae8d8a-4572-487c-b5de-dc8499f9d0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808277836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1808277836
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3322936421
Short name T223
Test name
Test status
Simulation time 973797414 ps
CPU time 8.52 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:46 PM PDT 24
Peak memory 218916 kb
Host smart-7d181b52-cbfb-451a-b2b1-decad3311b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322936421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3322936421
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2315273730
Short name T109
Test name
Test status
Simulation time 4376703606 ps
CPU time 231.59 seconds
Started Aug 06 04:43:36 PM PDT 24
Finished Aug 06 04:47:28 PM PDT 24
Peak memory 242476 kb
Host smart-b4e5a7ef-e3e2-44e6-b503-c41b25b04e56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315273730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2315273730
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.54258717
Short name T26
Test name
Test status
Simulation time 401545466 ps
CPU time 225.73 seconds
Started Aug 06 04:43:34 PM PDT 24
Finished Aug 06 04:47:20 PM PDT 24
Peak memory 235380 kb
Host smart-9bf21580-b2b9-4b0f-9bde-9c2fd07d7df6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54258717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.54258717
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2759076864
Short name T219
Test name
Test status
Simulation time 1414633232 ps
CPU time 12.22 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:40 PM PDT 24
Peak memory 219832 kb
Host smart-53a552e8-62fb-4506-b752-b4132d61f39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759076864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2759076864
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1820216190
Short name T23
Test name
Test status
Simulation time 564395138 ps
CPU time 31.17 seconds
Started Aug 06 04:43:44 PM PDT 24
Finished Aug 06 04:44:15 PM PDT 24
Peak memory 219880 kb
Host smart-ead87b08-9635-401c-a898-b97b479326ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820216190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1820216190
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2707819195
Short name T51
Test name
Test status
Simulation time 660639939 ps
CPU time 8.39 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:43:52 PM PDT 24
Peak memory 219000 kb
Host smart-27bd8c39-051b-4e50-bf93-cc5a2b8daea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707819195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2707819195
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.379301290
Short name T183
Test name
Test status
Simulation time 11825819739 ps
CPU time 255.46 seconds
Started Aug 06 04:43:33 PM PDT 24
Finished Aug 06 04:47:48 PM PDT 24
Peak memory 238432 kb
Host smart-3fb12d5d-7cf4-42fa-ae1a-ceef0be83fe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379301290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.379301290
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3667626851
Short name T211
Test name
Test status
Simulation time 2055585333 ps
CPU time 22.45 seconds
Started Aug 06 04:43:39 PM PDT 24
Finished Aug 06 04:44:01 PM PDT 24
Peak memory 219944 kb
Host smart-78288642-df8e-4d24-b001-d88f3553bfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667626851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3667626851
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1597386696
Short name T286
Test name
Test status
Simulation time 5150657644 ps
CPU time 12.18 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:51 PM PDT 24
Peak memory 220052 kb
Host smart-2c6f3517-b51e-43a5-8b2d-fbec084a0d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597386696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1597386696
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2757001599
Short name T21
Test name
Test status
Simulation time 1106258678 ps
CPU time 226.17 seconds
Started Aug 06 04:43:33 PM PDT 24
Finished Aug 06 04:47:20 PM PDT 24
Peak memory 235576 kb
Host smart-cf22dcc9-7565-4cfe-a137-d00e6cb2ab7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757001599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2757001599
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3415127855
Short name T81
Test name
Test status
Simulation time 187731229 ps
CPU time 10.78 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 220016 kb
Host smart-ad284801-fdf0-4f02-8598-692fc251eafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415127855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3415127855
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2873161164
Short name T269
Test name
Test status
Simulation time 431735650 ps
CPU time 15.42 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:43:55 PM PDT 24
Peak memory 219852 kb
Host smart-d2cc4a9c-924f-43c7-8be1-61c028a8063d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873161164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2873161164
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.942657390
Short name T291
Test name
Test status
Simulation time 169133132 ps
CPU time 8.04 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:43:50 PM PDT 24
Peak memory 219168 kb
Host smart-0f479e9d-6044-44bd-adb0-07b7019d6766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942657390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.942657390
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3869401964
Short name T305
Test name
Test status
Simulation time 2058412073 ps
CPU time 31.75 seconds
Started Aug 06 04:43:58 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 220024 kb
Host smart-82c6b776-1eb0-4c13-8679-12306c794ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869401964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3869401964
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.525086235
Short name T268
Test name
Test status
Simulation time 335643110 ps
CPU time 12.45 seconds
Started Aug 06 04:43:39 PM PDT 24
Finished Aug 06 04:43:51 PM PDT 24
Peak memory 219876 kb
Host smart-0c16d4d2-d22b-4e4a-b9a8-0b16d5c16791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525086235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.525086235
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1452577623
Short name T209
Test name
Test status
Simulation time 8776997852 ps
CPU time 38.44 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:44:21 PM PDT 24
Peak memory 220672 kb
Host smart-214d88cf-700b-4b9f-a46e-e01554a1b936
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452577623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1452577623
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2822003848
Short name T161
Test name
Test status
Simulation time 169023100 ps
CPU time 8.54 seconds
Started Aug 06 04:43:39 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 219000 kb
Host smart-3e73bf4e-5212-41cb-903a-876de9d76d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822003848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2822003848
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2963105491
Short name T162
Test name
Test status
Simulation time 6192702857 ps
CPU time 379.03 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:50:00 PM PDT 24
Peak memory 238368 kb
Host smart-782fa97b-6a33-4f1e-b328-277c19130d4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963105491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2963105491
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3071972744
Short name T8
Test name
Test status
Simulation time 864390532 ps
CPU time 10.1 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:43:51 PM PDT 24
Peak memory 219792 kb
Host smart-7e393804-bf64-4a34-9479-38f4ae92a8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071972744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3071972744
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1785786902
Short name T17
Test name
Test status
Simulation time 608791468 ps
CPU time 16.82 seconds
Started Aug 06 04:43:45 PM PDT 24
Finished Aug 06 04:44:01 PM PDT 24
Peak memory 219864 kb
Host smart-c6b3b049-fc8a-4d28-ac5b-560b1f2e2a3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785786902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1785786902
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2148575355
Short name T259
Test name
Test status
Simulation time 51989644662 ps
CPU time 9382.12 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 07:20:07 PM PDT 24
Peak memory 236852 kb
Host smart-a40f700a-f01f-4260-bbac-7a7be3354fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148575355 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2148575355
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2436236895
Short name T279
Test name
Test status
Simulation time 662569183 ps
CPU time 8.55 seconds
Started Aug 06 04:43:59 PM PDT 24
Finished Aug 06 04:44:07 PM PDT 24
Peak memory 219068 kb
Host smart-2fa31cb0-56ab-4015-8b13-c04d2da095ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436236895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2436236895
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.65660650
Short name T168
Test name
Test status
Simulation time 2859980087 ps
CPU time 211.59 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:47:10 PM PDT 24
Peak memory 234952 kb
Host smart-32e40737-b94f-4d6b-af1d-e1b9c68405e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65660650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_co
rrupt_sig_fatal_chk.65660650
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.110856095
Short name T132
Test name
Test status
Simulation time 334160398 ps
CPU time 19.28 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:44:00 PM PDT 24
Peak memory 219964 kb
Host smart-bea91e57-a87c-45fc-a006-28add5e39196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110856095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.110856095
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4231573086
Short name T147
Test name
Test status
Simulation time 348434764 ps
CPU time 10.26 seconds
Started Aug 06 04:43:44 PM PDT 24
Finished Aug 06 04:43:54 PM PDT 24
Peak memory 219960 kb
Host smart-2f25a3cd-efc1-4838-a052-2840c485a4a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231573086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4231573086
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.859682785
Short name T185
Test name
Test status
Simulation time 360681544 ps
CPU time 23.65 seconds
Started Aug 06 04:43:52 PM PDT 24
Finished Aug 06 04:44:16 PM PDT 24
Peak memory 219992 kb
Host smart-dae46f70-c322-4e29-bb6e-a5fd1d76e444
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859682785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.859682785
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2571269689
Short name T276
Test name
Test status
Simulation time 989972859 ps
CPU time 15.29 seconds
Started Aug 06 04:43:55 PM PDT 24
Finished Aug 06 04:44:10 PM PDT 24
Peak memory 218884 kb
Host smart-678e1ce4-681c-441a-81b8-e1df075e7ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571269689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2571269689
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2645633738
Short name T197
Test name
Test status
Simulation time 59116253598 ps
CPU time 223.98 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:47:26 PM PDT 24
Peak memory 220292 kb
Host smart-b33a8c75-e15e-4545-b100-12e1bd6df528
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645633738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2645633738
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.559935253
Short name T250
Test name
Test status
Simulation time 2063240384 ps
CPU time 23.05 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 220068 kb
Host smart-720cc6be-667f-4f85-b513-f19b5a4dcf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559935253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.559935253
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4184639467
Short name T270
Test name
Test status
Simulation time 262086509 ps
CPU time 12.21 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:43:52 PM PDT 24
Peak memory 219944 kb
Host smart-d4a81c95-546f-4638-8b58-c076cbac4a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184639467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4184639467
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3783069568
Short name T172
Test name
Test status
Simulation time 213187720 ps
CPU time 18.66 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:44:00 PM PDT 24
Peak memory 219880 kb
Host smart-5f21e88a-4e22-4530-b4a5-1b7419dbae8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783069568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3783069568
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.956275186
Short name T150
Test name
Test status
Simulation time 263084057 ps
CPU time 10.41 seconds
Started Aug 06 04:43:55 PM PDT 24
Finished Aug 06 04:44:05 PM PDT 24
Peak memory 218936 kb
Host smart-75f417f1-5338-40b3-a247-36e15a174181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956275186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.956275186
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3771816622
Short name T37
Test name
Test status
Simulation time 11610218425 ps
CPU time 366.2 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:50:15 PM PDT 24
Peak memory 239392 kb
Host smart-93850dfd-6cee-465c-a81f-20443add8cd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771816622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3771816622
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4095645591
Short name T165
Test name
Test status
Simulation time 1988265207 ps
CPU time 22.77 seconds
Started Aug 06 04:43:57 PM PDT 24
Finished Aug 06 04:44:20 PM PDT 24
Peak memory 220048 kb
Host smart-c1656608-64ac-412d-ba8d-ebcb4f8c639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095645591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4095645591
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2450146661
Short name T196
Test name
Test status
Simulation time 272090713 ps
CPU time 12.49 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:43:54 PM PDT 24
Peak memory 220008 kb
Host smart-b28a597f-0597-44db-8c45-0a67925bba33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2450146661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2450146661
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.502145393
Short name T6
Test name
Test status
Simulation time 1111763771 ps
CPU time 16.32 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:43:57 PM PDT 24
Peak memory 219680 kb
Host smart-3620e4e7-a484-43d7-b9d8-2a22b25d618e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502145393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.502145393
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4280327340
Short name T65
Test name
Test status
Simulation time 172381761 ps
CPU time 8.44 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:44:19 PM PDT 24
Peak memory 219008 kb
Host smart-ea2f7357-2ac7-4601-8d26-ce3011dcc58b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280327340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4280327340
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.955917004
Short name T29
Test name
Test status
Simulation time 28761895880 ps
CPU time 248.84 seconds
Started Aug 06 04:44:01 PM PDT 24
Finished Aug 06 04:48:10 PM PDT 24
Peak memory 225328 kb
Host smart-3f531b77-1988-49f9-8a78-2b01a9ee0620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955917004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.955917004
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2304188576
Short name T180
Test name
Test status
Simulation time 677083030 ps
CPU time 18.74 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:44:01 PM PDT 24
Peak memory 220044 kb
Host smart-ab62cc09-adec-407d-834a-683ce4c66c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304188576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2304188576
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1719010643
Short name T124
Test name
Test status
Simulation time 1848658437 ps
CPU time 12.07 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:43:54 PM PDT 24
Peak memory 219924 kb
Host smart-972ba77a-4ab1-4357-ae1e-e21ca06838f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719010643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1719010643
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2177452301
Short name T290
Test name
Test status
Simulation time 536900902 ps
CPU time 24.51 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 219828 kb
Host smart-48220ee1-db18-47f0-9ec0-89b38f89c10d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177452301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2177452301
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3905123228
Short name T285
Test name
Test status
Simulation time 1456464802 ps
CPU time 9.93 seconds
Started Aug 06 04:43:50 PM PDT 24
Finished Aug 06 04:44:00 PM PDT 24
Peak memory 218968 kb
Host smart-4fa8a501-32ab-41c5-87a1-ac7601f25b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905123228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3905123228
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.85491247
Short name T203
Test name
Test status
Simulation time 2833961422 ps
CPU time 198.7 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:47:02 PM PDT 24
Peak memory 229948 kb
Host smart-5787034b-05fb-49fd-b05e-4508f9141544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85491247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_co
rrupt_sig_fatal_chk.85491247
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3478355158
Short name T129
Test name
Test status
Simulation time 1951498396 ps
CPU time 18.84 seconds
Started Aug 06 04:44:07 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 219984 kb
Host smart-d8fc79c5-0966-4cf0-8e41-50fdc0b9ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478355158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3478355158
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4138400382
Short name T35
Test name
Test status
Simulation time 3174040876 ps
CPU time 11.81 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:43:54 PM PDT 24
Peak memory 220144 kb
Host smart-334107c9-baa3-42f8-b463-3a7512437056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138400382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4138400382
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1212093722
Short name T131
Test name
Test status
Simulation time 570986021 ps
CPU time 24.95 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:44:05 PM PDT 24
Peak memory 219900 kb
Host smart-0b7ac729-7378-42f0-ac3b-f82e465019e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212093722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1212093722
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1934325082
Short name T311
Test name
Test status
Simulation time 149171915628 ps
CPU time 937.78 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:59:32 PM PDT 24
Peak memory 234956 kb
Host smart-821ca07e-c926-4786-ab35-7b83f2ef4f06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934325082 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1934325082
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1186237871
Short name T141
Test name
Test status
Simulation time 1027776465 ps
CPU time 10.12 seconds
Started Aug 06 04:43:52 PM PDT 24
Finished Aug 06 04:44:02 PM PDT 24
Peak memory 218964 kb
Host smart-f1127370-ed54-47e7-a6ed-b1d2d770616e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186237871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1186237871
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2755370573
Short name T173
Test name
Test status
Simulation time 8865292302 ps
CPU time 146.5 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:46:10 PM PDT 24
Peak memory 243056 kb
Host smart-b0ccf044-87df-49bc-b8de-6dbfc0a8ac8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755370573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2755370573
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.708620024
Short name T42
Test name
Test status
Simulation time 347160379 ps
CPU time 19.26 seconds
Started Aug 06 04:44:03 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 220004 kb
Host smart-2fff00fb-18a2-4ccf-b21f-a734f8e7ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708620024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.708620024
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.57214209
Short name T133
Test name
Test status
Simulation time 271624966 ps
CPU time 11.66 seconds
Started Aug 06 04:43:44 PM PDT 24
Finished Aug 06 04:43:56 PM PDT 24
Peak memory 220048 kb
Host smart-c0392f4b-f1c1-406e-b1f9-88ad676c7958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57214209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.57214209
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1733727139
Short name T298
Test name
Test status
Simulation time 2324514923 ps
CPU time 34.34 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:44:16 PM PDT 24
Peak memory 220004 kb
Host smart-6f52de2a-f6a3-4c50-8303-52f51b6df8b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733727139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1733727139
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2804420613
Short name T137
Test name
Test status
Simulation time 250034563 ps
CPU time 10.32 seconds
Started Aug 06 04:43:55 PM PDT 24
Finished Aug 06 04:44:05 PM PDT 24
Peak memory 219040 kb
Host smart-b4cfafe5-3b29-4e15-9fe2-e552588b29c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804420613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2804420613
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1370381232
Short name T38
Test name
Test status
Simulation time 25934912957 ps
CPU time 360.1 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:49:43 PM PDT 24
Peak memory 220256 kb
Host smart-092e8d83-01c1-4b6c-9c5e-1b0dc0bc74e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370381232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1370381232
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.319579700
Short name T120
Test name
Test status
Simulation time 4484133583 ps
CPU time 22.46 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:44:05 PM PDT 24
Peak memory 220064 kb
Host smart-d58a22ef-6bf1-4d6e-b872-b71d714b5394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319579700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.319579700
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1344653474
Short name T192
Test name
Test status
Simulation time 269200542 ps
CPU time 11.75 seconds
Started Aug 06 04:43:44 PM PDT 24
Finished Aug 06 04:43:56 PM PDT 24
Peak memory 219932 kb
Host smart-6d3850eb-8910-415b-9c2e-c6142d9ea2b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344653474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1344653474
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1282054679
Short name T237
Test name
Test status
Simulation time 1049909515 ps
CPU time 16.49 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:10 PM PDT 24
Peak memory 219348 kb
Host smart-3f2c4c6a-1940-443b-bb33-cb2751fd01b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282054679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1282054679
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2012704168
Short name T160
Test name
Test status
Simulation time 988474486 ps
CPU time 14.45 seconds
Started Aug 06 04:43:51 PM PDT 24
Finished Aug 06 04:44:05 PM PDT 24
Peak memory 218964 kb
Host smart-52d1d1eb-f660-4af1-86c1-5ece9ef4e3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012704168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2012704168
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2994795405
Short name T119
Test name
Test status
Simulation time 1378437036 ps
CPU time 19.27 seconds
Started Aug 06 04:43:58 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 219984 kb
Host smart-b11c7c81-dd1c-4bb3-b160-7e65eb19677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994795405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2994795405
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1809706018
Short name T58
Test name
Test status
Simulation time 1033713473 ps
CPU time 12.33 seconds
Started Aug 06 04:43:49 PM PDT 24
Finished Aug 06 04:44:01 PM PDT 24
Peak memory 219972 kb
Host smart-72fd43a4-8343-45ed-8eaf-9a1ac23f3336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809706018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1809706018
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2785701548
Short name T210
Test name
Test status
Simulation time 2076123730 ps
CPU time 31.75 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:44:15 PM PDT 24
Peak memory 219376 kb
Host smart-c63f70e1-e191-4d20-9316-69156b2b86a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785701548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2785701548
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.737838573
Short name T251
Test name
Test status
Simulation time 638601068 ps
CPU time 8.27 seconds
Started Aug 06 04:43:36 PM PDT 24
Finished Aug 06 04:43:44 PM PDT 24
Peak memory 219080 kb
Host smart-17404641-16aa-4e33-af20-eaf17271d500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737838573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.737838573
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2157023792
Short name T271
Test name
Test status
Simulation time 12940812453 ps
CPU time 283.29 seconds
Started Aug 06 04:43:35 PM PDT 24
Finished Aug 06 04:48:18 PM PDT 24
Peak memory 239624 kb
Host smart-23522273-073f-4d63-aaf1-fae64531ab2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157023792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2157023792
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2532457923
Short name T130
Test name
Test status
Simulation time 522389766 ps
CPU time 22.55 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:44:01 PM PDT 24
Peak memory 219944 kb
Host smart-627a0af8-6e8b-4c58-bc26-25e0d9c30045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532457923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2532457923
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4092964817
Short name T284
Test name
Test status
Simulation time 265825931 ps
CPU time 12.03 seconds
Started Aug 06 04:43:36 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 219976 kb
Host smart-a3216945-5587-461b-b3b0-6d1e9f38f179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092964817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4092964817
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.419864812
Short name T22
Test name
Test status
Simulation time 3639715829 ps
CPU time 221.83 seconds
Started Aug 06 04:43:33 PM PDT 24
Finished Aug 06 04:47:15 PM PDT 24
Peak memory 238884 kb
Host smart-33d349d4-8920-44a0-95fd-1219a2178961
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419864812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.419864812
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3355446580
Short name T34
Test name
Test status
Simulation time 706608373 ps
CPU time 12.16 seconds
Started Aug 06 04:43:23 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 219956 kb
Host smart-d9b2d485-2df8-456b-bbba-0d61affc2603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355446580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3355446580
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.545876541
Short name T315
Test name
Test status
Simulation time 2116230141 ps
CPU time 30.99 seconds
Started Aug 06 04:43:44 PM PDT 24
Finished Aug 06 04:44:15 PM PDT 24
Peak memory 219984 kb
Host smart-262ebdf5-1485-473c-b7b1-ed232d2b2f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545876541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.545876541
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1394952408
Short name T310
Test name
Test status
Simulation time 1124004613 ps
CPU time 10.05 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:44:03 PM PDT 24
Peak memory 218952 kb
Host smart-fbf85dca-0a6e-4b94-9f2a-abc513de9dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394952408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1394952408
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2909713355
Short name T116
Test name
Test status
Simulation time 2866929732 ps
CPU time 166.76 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 236340 kb
Host smart-0c3c387c-5d98-4b41-94a9-46c1f977c999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909713355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2909713355
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4192164435
Short name T228
Test name
Test status
Simulation time 502229840 ps
CPU time 22.41 seconds
Started Aug 06 04:44:03 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 220052 kb
Host smart-2683f270-3bd3-4aa4-957b-1b37fc21ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192164435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4192164435
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.555532494
Short name T308
Test name
Test status
Simulation time 317285075 ps
CPU time 11.12 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:44:04 PM PDT 24
Peak memory 219932 kb
Host smart-405c09a0-a906-46e3-ae6a-2e3a9f7a966e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555532494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.555532494
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.18874221
Short name T253
Test name
Test status
Simulation time 590130786 ps
CPU time 28.5 seconds
Started Aug 06 04:44:05 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 219856 kb
Host smart-2a86435c-771d-4579-b239-609782ec965d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18874221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.rom_ctrl_stress_all.18874221
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2760207059
Short name T303
Test name
Test status
Simulation time 193310642917 ps
CPU time 1738.32 seconds
Started Aug 06 04:44:02 PM PDT 24
Finished Aug 06 05:13:00 PM PDT 24
Peak memory 239180 kb
Host smart-bae65909-06bc-4ba2-a8f3-5091d93c0f82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760207059 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2760207059
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4271649630
Short name T218
Test name
Test status
Simulation time 485288882 ps
CPU time 9.98 seconds
Started Aug 06 04:43:59 PM PDT 24
Finished Aug 06 04:44:09 PM PDT 24
Peak memory 218956 kb
Host smart-d7b99509-b13f-496d-a778-572ee2af0225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271649630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4271649630
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1045240787
Short name T236
Test name
Test status
Simulation time 3140562517 ps
CPU time 217.57 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:47:50 PM PDT 24
Peak memory 226736 kb
Host smart-2e31613b-025a-4bb5-bf29-c263d6154801
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045240787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1045240787
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3404709827
Short name T230
Test name
Test status
Simulation time 2055962436 ps
CPU time 23.06 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:44:32 PM PDT 24
Peak memory 220076 kb
Host smart-ad04d903-d6c2-4340-a43f-74cb8cd23463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404709827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3404709827
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3120400084
Short name T195
Test name
Test status
Simulation time 179731616 ps
CPU time 10.7 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:21 PM PDT 24
Peak memory 219976 kb
Host smart-3060ef67-c917-4bc7-a25e-ec8ca6b3e817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120400084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3120400084
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.716318829
Short name T28
Test name
Test status
Simulation time 1455979823 ps
CPU time 23.75 seconds
Started Aug 06 04:44:02 PM PDT 24
Finished Aug 06 04:44:25 PM PDT 24
Peak memory 219932 kb
Host smart-69438dc4-245a-480f-8551-c1fc6b55501c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716318829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.716318829
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3657730391
Short name T246
Test name
Test status
Simulation time 1030157777 ps
CPU time 10.24 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:44:03 PM PDT 24
Peak memory 219128 kb
Host smart-c031d850-685d-4c2c-98cb-4f5c7fc9bdec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657730391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3657730391
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2182305739
Short name T294
Test name
Test status
Simulation time 3375995566 ps
CPU time 252.14 seconds
Started Aug 06 04:44:05 PM PDT 24
Finished Aug 06 04:48:17 PM PDT 24
Peak memory 236828 kb
Host smart-14dd6440-3a56-4f55-81d1-359fd94139e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182305739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2182305739
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3602015439
Short name T177
Test name
Test status
Simulation time 346142957 ps
CPU time 19.04 seconds
Started Aug 06 04:44:07 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 220056 kb
Host smart-23310b1e-984e-42fc-a326-9afc40ed67cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602015439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3602015439
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.463541320
Short name T127
Test name
Test status
Simulation time 265331778 ps
CPU time 11.91 seconds
Started Aug 06 04:44:01 PM PDT 24
Finished Aug 06 04:44:13 PM PDT 24
Peak memory 219980 kb
Host smart-c7c4069b-3950-4414-bbfe-9c1f1ab4c678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463541320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.463541320
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.747245325
Short name T78
Test name
Test status
Simulation time 1564439277 ps
CPU time 35.18 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 219912 kb
Host smart-7bb5f241-98de-4663-9347-50e189f64650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747245325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.747245325
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2215977911
Short name T49
Test name
Test status
Simulation time 105576793979 ps
CPU time 1375.14 seconds
Started Aug 06 04:44:06 PM PDT 24
Finished Aug 06 05:07:02 PM PDT 24
Peak memory 238868 kb
Host smart-1aa3a780-5ad6-4e2e-8357-e564c0890f54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215977911 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2215977911
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1897428911
Short name T316
Test name
Test status
Simulation time 688354628 ps
CPU time 8.13 seconds
Started Aug 06 04:44:07 PM PDT 24
Finished Aug 06 04:44:15 PM PDT 24
Peak memory 219256 kb
Host smart-adf0c0af-3bc2-483b-b1b4-df9557d998be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897428911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1897428911
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1562413324
Short name T288
Test name
Test status
Simulation time 2070941693 ps
CPU time 134.16 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:46:08 PM PDT 24
Peak memory 233268 kb
Host smart-6207aff8-fb98-439c-9363-e037916b3f5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562413324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1562413324
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2687891484
Short name T221
Test name
Test status
Simulation time 1376824406 ps
CPU time 19.01 seconds
Started Aug 06 04:44:05 PM PDT 24
Finished Aug 06 04:44:24 PM PDT 24
Peak memory 219968 kb
Host smart-f5346b7f-0e53-4055-8341-ec9702ecfa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687891484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2687891484
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2656448500
Short name T113
Test name
Test status
Simulation time 526873181 ps
CPU time 12.32 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:06 PM PDT 24
Peak memory 219948 kb
Host smart-bd850e1a-824f-4a7c-9d45-868b197d7530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656448500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2656448500
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2473780409
Short name T235
Test name
Test status
Simulation time 1110746190 ps
CPU time 28.28 seconds
Started Aug 06 04:43:57 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 219872 kb
Host smart-30ceecc4-5688-4f76-9816-a7e10b28b7e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473780409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2473780409
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.723633406
Short name T242
Test name
Test status
Simulation time 1361632157 ps
CPU time 15.35 seconds
Started Aug 06 04:44:07 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 219028 kb
Host smart-c61d58ee-0382-408d-823e-b1a672f378c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723633406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.723633406
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2836872582
Short name T171
Test name
Test status
Simulation time 5502962810 ps
CPU time 121 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:46:14 PM PDT 24
Peak memory 232324 kb
Host smart-5baaf314-420a-4ea0-9958-74896f7fd233
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836872582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2836872582
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2543658485
Short name T164
Test name
Test status
Simulation time 347632037 ps
CPU time 19.34 seconds
Started Aug 06 04:44:02 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 219968 kb
Host smart-a8a1ff6c-0e36-485d-b4e5-937d50b96770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543658485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2543658485
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2806577605
Short name T293
Test name
Test status
Simulation time 182391652 ps
CPU time 10.36 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:44:03 PM PDT 24
Peak memory 219924 kb
Host smart-99bb560c-c476-4d20-af41-9dba94131570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806577605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2806577605
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1724829965
Short name T82
Test name
Test status
Simulation time 294730461 ps
CPU time 16.35 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 219928 kb
Host smart-935a0047-ad7c-42b6-8d14-37341d233cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724829965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1724829965
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2218867563
Short name T205
Test name
Test status
Simulation time 174779676 ps
CPU time 8.22 seconds
Started Aug 06 04:44:07 PM PDT 24
Finished Aug 06 04:44:16 PM PDT 24
Peak memory 219008 kb
Host smart-a2ae55c1-0ad3-4249-b76f-84f2c33a0689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218867563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2218867563
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2759597187
Short name T214
Test name
Test status
Simulation time 5033745583 ps
CPU time 300.11 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:49:09 PM PDT 24
Peak memory 234432 kb
Host smart-35f63950-00be-4e1f-9b0a-265683881050
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759597187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2759597187
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3016937019
Short name T258
Test name
Test status
Simulation time 2916601992 ps
CPU time 22.88 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 220072 kb
Host smart-8df7e10b-58d3-477a-8de7-01888b177d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016937019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3016937019
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2996442094
Short name T191
Test name
Test status
Simulation time 1584503399 ps
CPU time 10.28 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:04 PM PDT 24
Peak memory 219876 kb
Host smart-d60ba8d9-4756-4cb1-9637-e1fa6bf45694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996442094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2996442094
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4033649941
Short name T178
Test name
Test status
Simulation time 853867399 ps
CPU time 27.78 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:44:20 PM PDT 24
Peak memory 220224 kb
Host smart-3f683bd0-8a80-4911-a87f-e4ecf097ee6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033649941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4033649941
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2722554978
Short name T277
Test name
Test status
Simulation time 93152016987 ps
CPU time 9168.07 seconds
Started Aug 06 04:43:52 PM PDT 24
Finished Aug 06 07:16:41 PM PDT 24
Peak memory 234672 kb
Host smart-db13a031-1945-4a00-8d85-5fe43e295ca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722554978 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2722554978
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2114358739
Short name T5
Test name
Test status
Simulation time 612808566 ps
CPU time 8.15 seconds
Started Aug 06 04:44:02 PM PDT 24
Finished Aug 06 04:44:10 PM PDT 24
Peak memory 218956 kb
Host smart-127a90a8-cfd8-4f01-9815-497e09a3b5f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114358739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2114358739
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3447043376
Short name T229
Test name
Test status
Simulation time 5573733781 ps
CPU time 195.21 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:47:08 PM PDT 24
Peak memory 240524 kb
Host smart-0a2dc8ac-f89e-46be-9fdd-c6f7a6248af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447043376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3447043376
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3525353541
Short name T4
Test name
Test status
Simulation time 663078801 ps
CPU time 19.23 seconds
Started Aug 06 04:44:04 PM PDT 24
Finished Aug 06 04:44:23 PM PDT 24
Peak memory 219932 kb
Host smart-87de57d1-dd66-4116-a21d-47e7b5c17fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525353541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3525353541
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.896873899
Short name T283
Test name
Test status
Simulation time 363420392 ps
CPU time 10.3 seconds
Started Aug 06 04:43:56 PM PDT 24
Finished Aug 06 04:44:06 PM PDT 24
Peak memory 219900 kb
Host smart-e0784202-3a98-412a-9a09-c8df393ccef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896873899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.896873899
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.904890114
Short name T261
Test name
Test status
Simulation time 525792865 ps
CPU time 27.18 seconds
Started Aug 06 04:44:06 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 219992 kb
Host smart-ae02bde1-322b-4e48-9500-ec905c98473c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904890114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.904890114
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2442348018
Short name T118
Test name
Test status
Simulation time 1033361820 ps
CPU time 10.26 seconds
Started Aug 06 04:43:57 PM PDT 24
Finished Aug 06 04:44:08 PM PDT 24
Peak memory 218880 kb
Host smart-44377101-635c-445b-aa6a-8737af13ad94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442348018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2442348018
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3619865564
Short name T40
Test name
Test status
Simulation time 8372344120 ps
CPU time 277.68 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:48:48 PM PDT 24
Peak memory 219964 kb
Host smart-5c0fa7fa-5202-4405-a252-48f0bc4279ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619865564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3619865564
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.746847368
Short name T176
Test name
Test status
Simulation time 508172376 ps
CPU time 22.54 seconds
Started Aug 06 04:44:04 PM PDT 24
Finished Aug 06 04:44:27 PM PDT 24
Peak memory 219916 kb
Host smart-3c307f55-544a-4621-9f04-8d105fc1844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746847368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.746847368
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2973519914
Short name T134
Test name
Test status
Simulation time 268627005 ps
CPU time 12.09 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:44:05 PM PDT 24
Peak memory 220048 kb
Host smart-576dd984-eb29-41f0-a579-c062be7f08ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973519914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2973519914
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3098033426
Short name T304
Test name
Test status
Simulation time 1472647249 ps
CPU time 20.05 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 219940 kb
Host smart-7ef985e7-e6b3-4e55-a58c-3b7d38d1fa38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098033426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3098033426
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1680406312
Short name T136
Test name
Test status
Simulation time 1649648078 ps
CPU time 8.35 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:18 PM PDT 24
Peak memory 219008 kb
Host smart-972273ed-a751-460b-839b-e46298d639c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680406312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1680406312
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.412146867
Short name T201
Test name
Test status
Simulation time 13361359583 ps
CPU time 214.81 seconds
Started Aug 06 04:44:01 PM PDT 24
Finished Aug 06 04:47:36 PM PDT 24
Peak memory 235208 kb
Host smart-e22ebd42-86cc-4e55-9ca8-ac1fffb6566b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412146867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.412146867
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.857843663
Short name T166
Test name
Test status
Simulation time 497170603 ps
CPU time 22.89 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 219936 kb
Host smart-554ba652-f2ad-4570-b920-fcc8a3a6dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857843663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.857843663
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2791587946
Short name T234
Test name
Test status
Simulation time 1173967647 ps
CPU time 11.93 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:44:21 PM PDT 24
Peak memory 219912 kb
Host smart-fd0e5bc2-be5a-48ff-b2a7-0a143e9bc7dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791587946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2791587946
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3259356488
Short name T157
Test name
Test status
Simulation time 379856990 ps
CPU time 32.35 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:45 PM PDT 24
Peak memory 219976 kb
Host smart-c14ce0b5-6afb-4003-b277-3d09fe045860
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259356488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3259356488
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2707632921
Short name T69
Test name
Test status
Simulation time 14096709093 ps
CPU time 15.19 seconds
Started Aug 06 04:44:08 PM PDT 24
Finished Aug 06 04:44:23 PM PDT 24
Peak memory 219088 kb
Host smart-0696f14d-1e11-4314-9e25-b0d78ea6fecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707632921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2707632921
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3307656114
Short name T110
Test name
Test status
Simulation time 7381837385 ps
CPU time 139.11 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:46:28 PM PDT 24
Peak memory 230400 kb
Host smart-d92ab846-2aba-48c2-a694-4209fdd6173e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307656114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3307656114
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3537345856
Short name T138
Test name
Test status
Simulation time 342730645 ps
CPU time 19.04 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 219960 kb
Host smart-fded7687-6206-431e-80aa-7adfddc80bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537345856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3537345856
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1049250727
Short name T112
Test name
Test status
Simulation time 259890181 ps
CPU time 11.75 seconds
Started Aug 06 04:44:05 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 219896 kb
Host smart-7eab1878-c767-4d3b-9445-ce93981f4c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049250727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1049250727
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3979623268
Short name T169
Test name
Test status
Simulation time 890232389 ps
CPU time 14.8 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:09 PM PDT 24
Peak memory 219616 kb
Host smart-95a2b1f7-5844-47e1-8deb-6b7978a0c0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979623268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3979623268
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1160880956
Short name T273
Test name
Test status
Simulation time 36481091512 ps
CPU time 1556.29 seconds
Started Aug 06 04:43:58 PM PDT 24
Finished Aug 06 05:09:54 PM PDT 24
Peak memory 244748 kb
Host smart-3be6ba22-e2f8-415d-b7fa-ab692c2a6d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160880956 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1160880956
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2555442607
Short name T32
Test name
Test status
Simulation time 664317272 ps
CPU time 8.25 seconds
Started Aug 06 04:43:48 PM PDT 24
Finished Aug 06 04:43:56 PM PDT 24
Peak memory 218964 kb
Host smart-25a2ca52-424e-4042-8bb8-292fc70d7659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555442607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2555442607
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3232495691
Short name T254
Test name
Test status
Simulation time 9766086853 ps
CPU time 221.72 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:47:36 PM PDT 24
Peak memory 237428 kb
Host smart-df896f04-41db-4a62-b44d-cdf015b40f29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232495691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3232495691
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.834793776
Short name T241
Test name
Test status
Simulation time 1374745412 ps
CPU time 18.91 seconds
Started Aug 06 04:43:25 PM PDT 24
Finished Aug 06 04:43:44 PM PDT 24
Peak memory 220000 kb
Host smart-486aff85-e6f8-4957-b272-86146618f4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834793776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.834793776
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2454963552
Short name T252
Test name
Test status
Simulation time 692686229 ps
CPU time 10.36 seconds
Started Aug 06 04:43:25 PM PDT 24
Finished Aug 06 04:43:36 PM PDT 24
Peak memory 219928 kb
Host smart-73d44e21-408b-49e9-8465-de06e5adc5f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454963552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2454963552
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1828958701
Short name T20
Test name
Test status
Simulation time 305564880 ps
CPU time 117.82 seconds
Started Aug 06 04:43:31 PM PDT 24
Finished Aug 06 04:45:29 PM PDT 24
Peak memory 233820 kb
Host smart-5365de96-c735-4c70-8325-853be8ffdb60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828958701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1828958701
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4147963569
Short name T302
Test name
Test status
Simulation time 1542809850 ps
CPU time 24.67 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:44:06 PM PDT 24
Peak memory 219992 kb
Host smart-cc171b85-715a-4c2e-9748-5630f8b15e1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147963569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4147963569
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2947142463
Short name T194
Test name
Test status
Simulation time 169351211 ps
CPU time 8.33 seconds
Started Aug 06 04:44:02 PM PDT 24
Finished Aug 06 04:44:10 PM PDT 24
Peak memory 219040 kb
Host smart-1f8f35d0-8045-422d-a6d8-99e169b8ea43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947142463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2947142463
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1920039422
Short name T239
Test name
Test status
Simulation time 4647222798 ps
CPU time 177.29 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:47:10 PM PDT 24
Peak memory 219888 kb
Host smart-1aade8e6-f3ec-405e-b57e-363215bcf700
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920039422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1920039422
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1917473190
Short name T44
Test name
Test status
Simulation time 2147216417 ps
CPU time 22.76 seconds
Started Aug 06 04:43:59 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 219940 kb
Host smart-c082c070-f0f6-4c1b-b507-f2f1f26b4bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917473190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1917473190
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1472642499
Short name T14
Test name
Test status
Simulation time 272519467 ps
CPU time 12.11 seconds
Started Aug 06 04:44:02 PM PDT 24
Finished Aug 06 04:44:15 PM PDT 24
Peak memory 219972 kb
Host smart-aeab439c-609b-4f4b-bbab-246cf5845502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472642499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1472642499
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.610390902
Short name T9
Test name
Test status
Simulation time 9584572215 ps
CPU time 41.38 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:44:51 PM PDT 24
Peak memory 220132 kb
Host smart-7ebed16b-5a33-4f06-9418-b03b9bf71250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610390902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.610390902
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4084955615
Short name T300
Test name
Test status
Simulation time 499416250 ps
CPU time 9.93 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:23 PM PDT 24
Peak memory 219024 kb
Host smart-13afc803-ae19-44e3-b5d7-514e9e107805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084955615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4084955615
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3241843448
Short name T240
Test name
Test status
Simulation time 8996727837 ps
CPU time 481.14 seconds
Started Aug 06 04:43:58 PM PDT 24
Finished Aug 06 04:52:00 PM PDT 24
Peak memory 239072 kb
Host smart-958f5b4e-2b87-4d69-9dce-3ac6ed3fbb81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241843448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3241843448
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2695005854
Short name T187
Test name
Test status
Simulation time 1709190871 ps
CPU time 22.46 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 219932 kb
Host smart-288305ae-8ea1-430b-a2b2-d4dd2adbd6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695005854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2695005854
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1997467566
Short name T226
Test name
Test status
Simulation time 289547219 ps
CPU time 11.92 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:25 PM PDT 24
Peak memory 219928 kb
Host smart-bf375602-c517-4785-aad6-c2398686f63a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1997467566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1997467566
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2900115139
Short name T260
Test name
Test status
Simulation time 820279203 ps
CPU time 13.8 seconds
Started Aug 06 04:44:08 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 219764 kb
Host smart-43f2e65f-d947-4457-86b3-f7a010cdf361
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900115139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2900115139
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.846103983
Short name T52
Test name
Test status
Simulation time 489073087 ps
CPU time 10.03 seconds
Started Aug 06 04:43:58 PM PDT 24
Finished Aug 06 04:44:08 PM PDT 24
Peak memory 219048 kb
Host smart-60b3338b-9dfb-4bc3-8fea-00219927263b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846103983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.846103983
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2118139528
Short name T215
Test name
Test status
Simulation time 14137210671 ps
CPU time 175.27 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 229316 kb
Host smart-cabbf161-d3d0-4a01-80a1-ed7c43d59778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118139528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2118139528
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4184728165
Short name T296
Test name
Test status
Simulation time 1320412815 ps
CPU time 19.21 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:13 PM PDT 24
Peak memory 219988 kb
Host smart-f54f5e25-773d-4dc8-bd74-41582f035920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184728165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4184728165
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.249668631
Short name T56
Test name
Test status
Simulation time 980295192 ps
CPU time 10.58 seconds
Started Aug 06 04:44:08 PM PDT 24
Finished Aug 06 04:44:18 PM PDT 24
Peak memory 219952 kb
Host smart-f1ba2e09-d835-41f7-83ee-ae6872975555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249668631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.249668631
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.898040505
Short name T80
Test name
Test status
Simulation time 1485376889 ps
CPU time 24.75 seconds
Started Aug 06 04:44:07 PM PDT 24
Finished Aug 06 04:44:32 PM PDT 24
Peak memory 219864 kb
Host smart-1555c01c-efcc-4717-b405-8a595f5b3ed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898040505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.898040505
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.741665329
Short name T48
Test name
Test status
Simulation time 15540565156 ps
CPU time 648.47 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:54:41 PM PDT 24
Peak memory 236556 kb
Host smart-a0ab2287-3bc3-4751-ba9f-197f464b5670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741665329 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.741665329
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1415772712
Short name T255
Test name
Test status
Simulation time 253552846 ps
CPU time 10.28 seconds
Started Aug 06 04:43:58 PM PDT 24
Finished Aug 06 04:44:08 PM PDT 24
Peak memory 219872 kb
Host smart-8d940aad-fa11-441d-9a48-ef28c48eb8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415772712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1415772712
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4284261956
Short name T309
Test name
Test status
Simulation time 16784813088 ps
CPU time 299.9 seconds
Started Aug 06 04:44:02 PM PDT 24
Finished Aug 06 04:49:02 PM PDT 24
Peak memory 240284 kb
Host smart-801d96f8-6449-415e-94e0-417241edffdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284261956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4284261956
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4215418301
Short name T267
Test name
Test status
Simulation time 1510137348 ps
CPU time 18.89 seconds
Started Aug 06 04:44:15 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 220052 kb
Host smart-d0cf16ce-9067-4f85-b640-799fba0e18e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215418301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4215418301
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1383506711
Short name T98
Test name
Test status
Simulation time 782968775 ps
CPU time 10.04 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:44:19 PM PDT 24
Peak memory 219944 kb
Host smart-15356e6c-0cf5-49f9-aac3-57e3bdc952be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383506711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1383506711
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2860594403
Short name T248
Test name
Test status
Simulation time 546188250 ps
CPU time 23.62 seconds
Started Aug 06 04:44:07 PM PDT 24
Finished Aug 06 04:44:31 PM PDT 24
Peak memory 219848 kb
Host smart-df70c72c-8552-4d9f-812d-bda44184d985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860594403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2860594403
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3451153347
Short name T212
Test name
Test status
Simulation time 988568730 ps
CPU time 10.03 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:20 PM PDT 24
Peak memory 218996 kb
Host smart-143fad6f-c84d-47e7-b2c3-32c5090a5951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451153347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3451153347
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3977970850
Short name T206
Test name
Test status
Simulation time 11216313509 ps
CPU time 217.73 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:47:47 PM PDT 24
Peak memory 225036 kb
Host smart-45f4661b-7536-4a6e-aafa-be787a79e6f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977970850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3977970850
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.693276826
Short name T232
Test name
Test status
Simulation time 1374783098 ps
CPU time 19.74 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 220068 kb
Host smart-be1019fc-47a7-4d8b-9c24-86f1f3b6bdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693276826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.693276826
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1832545206
Short name T231
Test name
Test status
Simulation time 267647546 ps
CPU time 11.94 seconds
Started Aug 06 04:44:07 PM PDT 24
Finished Aug 06 04:44:19 PM PDT 24
Peak memory 220024 kb
Host smart-4d9bde6c-94ea-4b5b-ba8e-24340a87850c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832545206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1832545206
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3495953080
Short name T54
Test name
Test status
Simulation time 2100250888 ps
CPU time 44.72 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:58 PM PDT 24
Peak memory 220852 kb
Host smart-4f915201-9a8a-413f-b650-0e9541b1bd2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495953080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3495953080
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1256311235
Short name T297
Test name
Test status
Simulation time 690005464 ps
CPU time 8.54 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:19 PM PDT 24
Peak memory 219048 kb
Host smart-ff70f32d-c455-41ec-bd1e-10bcb9924813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256311235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1256311235
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.137617497
Short name T190
Test name
Test status
Simulation time 12098167989 ps
CPU time 218 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:47:51 PM PDT 24
Peak memory 242460 kb
Host smart-e32ea8a9-4816-43af-b25a-b7a73e2b94ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137617497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.137617497
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.154079146
Short name T43
Test name
Test status
Simulation time 332340886 ps
CPU time 19.41 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:44:28 PM PDT 24
Peak memory 219992 kb
Host smart-2fe7c620-c859-4bc6-872d-726df6d433fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154079146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.154079146
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.731207746
Short name T140
Test name
Test status
Simulation time 676591064 ps
CPU time 10.71 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 220076 kb
Host smart-9dab70e9-3a34-40fb-8513-bfef7d73d1fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731207746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.731207746
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.144227815
Short name T170
Test name
Test status
Simulation time 269112449 ps
CPU time 11.33 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:24 PM PDT 24
Peak memory 219876 kb
Host smart-058274cb-b640-4de9-8b57-ae852031a9e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144227815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.144227815
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.874468341
Short name T46
Test name
Test status
Simulation time 24578836100 ps
CPU time 958.61 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 05:00:12 PM PDT 24
Peak memory 233364 kb
Host smart-8e33ee3f-815e-40fd-9c47-12a3fc5ae720
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874468341 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.874468341
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2792854759
Short name T307
Test name
Test status
Simulation time 332596740 ps
CPU time 8.4 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 219020 kb
Host smart-37c7a488-0420-419e-99c3-444a8359fcd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792854759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2792854759
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.856676842
Short name T19
Test name
Test status
Simulation time 12244953382 ps
CPU time 251.48 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:48:25 PM PDT 24
Peak memory 239808 kb
Host smart-1eacdbe6-fb5a-4139-93be-a74b93cbf769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856676842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.856676842
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1912623894
Short name T299
Test name
Test status
Simulation time 1505728286 ps
CPU time 18.73 seconds
Started Aug 06 04:44:08 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 220000 kb
Host smart-65b9314c-23d8-4fd0-8699-754728651c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912623894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1912623894
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2364288692
Short name T222
Test name
Test status
Simulation time 260566935 ps
CPU time 11.7 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:44:23 PM PDT 24
Peak memory 219960 kb
Host smart-4af1047f-d89c-4b9c-9530-218754e9ac95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364288692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2364288692
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2125432262
Short name T186
Test name
Test status
Simulation time 1120417272 ps
CPU time 15.72 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 219924 kb
Host smart-04bd7f0d-5e15-4765-91aa-052999049ed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125432262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2125432262
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3304114062
Short name T159
Test name
Test status
Simulation time 174591943 ps
CPU time 8.16 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:21 PM PDT 24
Peak memory 219064 kb
Host smart-2828e8ea-d823-4f6e-a1c1-eba5962e2cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304114062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3304114062
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2808693660
Short name T227
Test name
Test status
Simulation time 10229667633 ps
CPU time 187.44 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:47:20 PM PDT 24
Peak memory 231416 kb
Host smart-1addca52-a323-4d46-aff7-682d2746c07c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808693660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2808693660
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3030105118
Short name T143
Test name
Test status
Simulation time 348195947 ps
CPU time 19.22 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 220028 kb
Host smart-cae6a625-b591-4562-bce0-b801ebfb4568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030105118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3030105118
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1230364085
Short name T153
Test name
Test status
Simulation time 758590622 ps
CPU time 10.25 seconds
Started Aug 06 04:44:08 PM PDT 24
Finished Aug 06 04:44:19 PM PDT 24
Peak memory 219980 kb
Host smart-7f61d4f2-8b06-4c56-80fc-3a021121c8e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230364085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1230364085
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3519267087
Short name T238
Test name
Test status
Simulation time 201308492 ps
CPU time 14.57 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 219956 kb
Host smart-9aacb413-4fb5-4aa3-a010-c412cddf846c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519267087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3519267087
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1350663407
Short name T68
Test name
Test status
Simulation time 505870535 ps
CPU time 10.01 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:23 PM PDT 24
Peak memory 219032 kb
Host smart-c9191165-be1c-42d8-a589-60808305c348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350663407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1350663407
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1292765804
Short name T275
Test name
Test status
Simulation time 2842636918 ps
CPU time 152.95 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:46:46 PM PDT 24
Peak memory 220168 kb
Host smart-1a7897c1-49c2-4973-b30b-a0760774c153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292765804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1292765804
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3864674734
Short name T213
Test name
Test status
Simulation time 333321391 ps
CPU time 19.7 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 220000 kb
Host smart-4a57a2ef-d3ae-4adb-a046-973cc595684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864674734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3864674734
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3475495042
Short name T245
Test name
Test status
Simulation time 351118114 ps
CPU time 10.24 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 220060 kb
Host smart-0c3a08c3-eb59-486a-8481-761864045029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475495042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3475495042
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1015672162
Short name T33
Test name
Test status
Simulation time 2309726485 ps
CPU time 34.94 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:45 PM PDT 24
Peak memory 219996 kb
Host smart-c6e8b697-5d2e-4d3f-8754-6537498210d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015672162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1015672162
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2377056952
Short name T182
Test name
Test status
Simulation time 254772372 ps
CPU time 9.93 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:20 PM PDT 24
Peak memory 218972 kb
Host smart-1253eeb1-1497-4238-9ab9-f90497b0f3d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377056952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2377056952
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2331477500
Short name T36
Test name
Test status
Simulation time 33836557024 ps
CPU time 336.65 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:49:48 PM PDT 24
Peak memory 227168 kb
Host smart-1cc5de67-eb57-488a-889f-6bf8df7f9227
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331477500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2331477500
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2813688519
Short name T314
Test name
Test status
Simulation time 1320805973 ps
CPU time 19.3 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:32 PM PDT 24
Peak memory 219944 kb
Host smart-94502845-a61b-451e-b46d-0ed9c6b5ff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813688519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2813688519
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.201572182
Short name T156
Test name
Test status
Simulation time 2108329757 ps
CPU time 16.74 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:48 PM PDT 24
Peak memory 219360 kb
Host smart-86c4308a-ad56-4217-8295-3b28fdfe976a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201572182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.201572182
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.348852557
Short name T184
Test name
Test status
Simulation time 806506213 ps
CPU time 39.92 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:44:51 PM PDT 24
Peak memory 219868 kb
Host smart-7b48e707-e537-44ce-b7ae-323fee87bb4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348852557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.348852557
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1710694398
Short name T264
Test name
Test status
Simulation time 986691667 ps
CPU time 14.89 seconds
Started Aug 06 04:43:49 PM PDT 24
Finished Aug 06 04:44:04 PM PDT 24
Peak memory 218948 kb
Host smart-c79d1f0f-3690-4a23-8a74-f3f77187df64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710694398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1710694398
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.315766353
Short name T167
Test name
Test status
Simulation time 3589514340 ps
CPU time 139.08 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:46:01 PM PDT 24
Peak memory 220240 kb
Host smart-f62ccdc0-9ae8-4cc6-abf2-5f5cc26cd98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315766353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.315766353
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3883595145
Short name T272
Test name
Test status
Simulation time 2250584801 ps
CPU time 22.76 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:44:00 PM PDT 24
Peak memory 220096 kb
Host smart-719f79d7-5caf-4f06-bcc6-33e8b00f1dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883595145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3883595145
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3888658330
Short name T154
Test name
Test status
Simulation time 917901625 ps
CPU time 12.25 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:07 PM PDT 24
Peak memory 219996 kb
Host smart-b082a1fd-3ce3-43c4-b983-a556cea3bafa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888658330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3888658330
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1904920450
Short name T122
Test name
Test status
Simulation time 737664441 ps
CPU time 10.06 seconds
Started Aug 06 04:43:49 PM PDT 24
Finished Aug 06 04:43:59 PM PDT 24
Peak memory 219956 kb
Host smart-323221f5-5b6b-4e00-89e0-025ebd68a7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904920450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1904920450
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.190496871
Short name T114
Test name
Test status
Simulation time 208386446 ps
CPU time 14.78 seconds
Started Aug 06 04:43:45 PM PDT 24
Finished Aug 06 04:44:00 PM PDT 24
Peak memory 219896 kb
Host smart-d4931f1a-4223-48f4-83e7-2ad4f69c1e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190496871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.190496871
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1560486617
Short name T67
Test name
Test status
Simulation time 691463814 ps
CPU time 8.21 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:19 PM PDT 24
Peak memory 218976 kb
Host smart-b4b701f7-67e9-400b-9b6e-42f2e9e11e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560486617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1560486617
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2078039322
Short name T208
Test name
Test status
Simulation time 5554319186 ps
CPU time 170.46 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:47:04 PM PDT 24
Peak memory 242552 kb
Host smart-0851397e-12f8-4a32-ad94-836b75724279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078039322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2078039322
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1885905252
Short name T145
Test name
Test status
Simulation time 1010564848 ps
CPU time 23.07 seconds
Started Aug 06 04:44:15 PM PDT 24
Finished Aug 06 04:44:38 PM PDT 24
Peak memory 219980 kb
Host smart-77f92f8f-7bfb-48cf-87aa-5599aadf4540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885905252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1885905252
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2545689189
Short name T225
Test name
Test status
Simulation time 183829107 ps
CPU time 10.22 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:44:21 PM PDT 24
Peak memory 219956 kb
Host smart-e98caf00-900d-4c2a-a5de-97d8ff602cd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545689189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2545689189
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4154747475
Short name T282
Test name
Test status
Simulation time 3423893142 ps
CPU time 43.67 seconds
Started Aug 06 04:44:08 PM PDT 24
Finished Aug 06 04:44:52 PM PDT 24
Peak memory 220084 kb
Host smart-17868db9-7ed6-4cdc-8abf-01ae81231c47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154747475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4154747475
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2240935218
Short name T50
Test name
Test status
Simulation time 101797273624 ps
CPU time 5489.73 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 06:15:45 PM PDT 24
Peak memory 236548 kb
Host smart-4cc372e9-b55b-4b72-9878-e00cfdb7f9a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240935218 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2240935218
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.9263843
Short name T10
Test name
Test status
Simulation time 248851080 ps
CPU time 10.2 seconds
Started Aug 06 04:44:08 PM PDT 24
Finished Aug 06 04:44:18 PM PDT 24
Peak memory 219108 kb
Host smart-101d0b0a-ee67-4442-b0f9-abc8ccd52abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9263843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.9263843
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1843887041
Short name T3
Test name
Test status
Simulation time 7997690236 ps
CPU time 360.77 seconds
Started Aug 06 04:44:28 PM PDT 24
Finished Aug 06 04:50:29 PM PDT 24
Peak memory 226512 kb
Host smart-1dfd6164-e890-4170-a973-e7a4ff784179
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843887041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1843887041
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3343782444
Short name T155
Test name
Test status
Simulation time 1833334777 ps
CPU time 22.62 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:35 PM PDT 24
Peak memory 219976 kb
Host smart-aa8c8cc1-5fc1-4728-87b0-937faf89c015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343782444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3343782444
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.912718070
Short name T148
Test name
Test status
Simulation time 759940488 ps
CPU time 10 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:27 PM PDT 24
Peak memory 219932 kb
Host smart-c9eef4a5-574f-4cfa-99f3-8521f87d7e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912718070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.912718070
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.952900039
Short name T18
Test name
Test status
Simulation time 370462984 ps
CPU time 10.75 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:25 PM PDT 24
Peak memory 219856 kb
Host smart-63065603-0b39-4ee5-a8f7-43da1f6c6c00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952900039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.952900039
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.385689852
Short name T262
Test name
Test status
Simulation time 171395688 ps
CPU time 8.58 seconds
Started Aug 06 04:44:18 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 219180 kb
Host smart-1e7a4160-d395-4d53-9fd0-b628927431b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385689852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.385689852
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2866044917
Short name T199
Test name
Test status
Simulation time 9894588298 ps
CPU time 220.63 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:47:53 PM PDT 24
Peak memory 238600 kb
Host smart-e2e5b0fb-547d-432b-b916-7ff9c1c18752
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866044917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2866044917
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4199958930
Short name T204
Test name
Test status
Simulation time 679276485 ps
CPU time 19.42 seconds
Started Aug 06 04:44:15 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 219952 kb
Host smart-3c3a27ba-8762-4b7e-951a-9b2c3040e6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199958930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4199958930
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1436265250
Short name T306
Test name
Test status
Simulation time 275101674 ps
CPU time 11.68 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:28 PM PDT 24
Peak memory 219988 kb
Host smart-6819bdae-2577-4e6f-8e38-6d22cdae2226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436265250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1436265250
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4104773680
Short name T189
Test name
Test status
Simulation time 559360555 ps
CPU time 32.06 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:44:41 PM PDT 24
Peak memory 219868 kb
Host smart-f4dfa428-321c-408b-a8c4-47eb476e72d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104773680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4104773680
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3782668724
Short name T263
Test name
Test status
Simulation time 505978741 ps
CPU time 10.17 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 219044 kb
Host smart-c4ecf07a-b749-4820-b080-1ee3272756df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782668724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3782668724
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2200688069
Short name T317
Test name
Test status
Simulation time 2158430806 ps
CPU time 119.8 seconds
Started Aug 06 04:44:22 PM PDT 24
Finished Aug 06 04:46:22 PM PDT 24
Peak memory 235532 kb
Host smart-6eca0c81-c0a6-4006-b3fd-3096bb1aefcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200688069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2200688069
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.98841878
Short name T207
Test name
Test status
Simulation time 2065371872 ps
CPU time 23.35 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:55 PM PDT 24
Peak memory 219956 kb
Host smart-04501f7d-0696-441f-9140-24997fee10a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98841878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.98841878
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.855258457
Short name T149
Test name
Test status
Simulation time 182143132 ps
CPU time 9.98 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:20 PM PDT 24
Peak memory 220012 kb
Host smart-2ec62803-d00f-423c-9fa9-59461f26059c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855258457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.855258457
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3280056854
Short name T274
Test name
Test status
Simulation time 548304157 ps
CPU time 37.34 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:53 PM PDT 24
Peak memory 219916 kb
Host smart-825e75b6-ac49-4c07-80f1-50ca094b860b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280056854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3280056854
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1767867209
Short name T126
Test name
Test status
Simulation time 636708749 ps
CPU time 8.38 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:21 PM PDT 24
Peak memory 219068 kb
Host smart-c028f3bc-19ca-456e-bdc9-5d476beeedf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767867209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1767867209
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1590962329
Short name T249
Test name
Test status
Simulation time 5053213965 ps
CPU time 263.86 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:48:34 PM PDT 24
Peak memory 237308 kb
Host smart-5954a6b3-cb01-4d9a-9ea4-1b9e3efe5be6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590962329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1590962329
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1383810493
Short name T123
Test name
Test status
Simulation time 1011209603 ps
CPU time 22.92 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:36 PM PDT 24
Peak memory 219884 kb
Host smart-5d85da60-b389-4d24-baa2-eaa652a55f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383810493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1383810493
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3132515428
Short name T292
Test name
Test status
Simulation time 384400909 ps
CPU time 10.3 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:23 PM PDT 24
Peak memory 219912 kb
Host smart-5e305d70-57d6-426b-a34a-cddb7f440c84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132515428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3132515428
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3577569413
Short name T179
Test name
Test status
Simulation time 564436347 ps
CPU time 36.72 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:47 PM PDT 24
Peak memory 219876 kb
Host smart-b455a516-96a6-4bee-bb53-9bb5084c5675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577569413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3577569413
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1973618367
Short name T198
Test name
Test status
Simulation time 661564635 ps
CPU time 8.16 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:22 PM PDT 24
Peak memory 219080 kb
Host smart-2154b8be-1464-4f1d-a3ae-612a1cc13efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973618367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1973618367
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.538949882
Short name T39
Test name
Test status
Simulation time 34133761258 ps
CPU time 399.45 seconds
Started Aug 06 04:44:22 PM PDT 24
Finished Aug 06 04:51:02 PM PDT 24
Peak memory 235528 kb
Host smart-2935c30f-44c4-4d4e-b5bc-0147cd165731
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538949882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.538949882
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1388191077
Short name T139
Test name
Test status
Simulation time 2216086180 ps
CPU time 18.69 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 220100 kb
Host smart-4f6f76a7-23b0-4b81-b2a6-fd4698dcf8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388191077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1388191077
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1403096340
Short name T121
Test name
Test status
Simulation time 229050718 ps
CPU time 9.91 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:20 PM PDT 24
Peak memory 219988 kb
Host smart-4ed54520-f386-4a71-bdc2-56252c1651b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403096340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1403096340
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3942774192
Short name T62
Test name
Test status
Simulation time 531016959 ps
CPU time 27.28 seconds
Started Aug 06 04:44:15 PM PDT 24
Finished Aug 06 04:44:42 PM PDT 24
Peak memory 219884 kb
Host smart-35a05437-5ccc-4e98-9bd2-9c4ecd547e8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942774192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3942774192
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.686888532
Short name T30
Test name
Test status
Simulation time 16654098783 ps
CPU time 1666.56 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 05:12:03 PM PDT 24
Peak memory 236544 kb
Host smart-814ba6fa-c7a4-4613-bc9e-a81c317e2afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686888532 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.686888532
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2230293005
Short name T117
Test name
Test status
Simulation time 476972430 ps
CPU time 9.9 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 219068 kb
Host smart-c0dfaaab-daa0-4458-b46b-33ea1f360984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230293005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2230293005
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1325536799
Short name T57
Test name
Test status
Simulation time 4320994390 ps
CPU time 228.64 seconds
Started Aug 06 04:44:15 PM PDT 24
Finished Aug 06 04:48:04 PM PDT 24
Peak memory 238620 kb
Host smart-56412ac2-5e0f-4ace-aa03-7d43c815899a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325536799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1325536799
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3520347019
Short name T115
Test name
Test status
Simulation time 333402596 ps
CPU time 18.9 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 219912 kb
Host smart-a6b0f0fb-1f20-4053-8240-a695e102be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520347019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3520347019
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1930240832
Short name T266
Test name
Test status
Simulation time 180343824 ps
CPU time 10.59 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:27 PM PDT 24
Peak memory 219956 kb
Host smart-ef0299b0-b6d1-438f-b02c-403f0bbc075a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930240832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1930240832
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2296030631
Short name T295
Test name
Test status
Simulation time 1739576199 ps
CPU time 33.95 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:48 PM PDT 24
Peak memory 219948 kb
Host smart-c075117f-b4a4-4ba3-bd37-941f976de7e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296030631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2296030631
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2067450027
Short name T16
Test name
Test status
Simulation time 197783916767 ps
CPU time 784.24 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:57:14 PM PDT 24
Peak memory 236616 kb
Host smart-402b0a72-4869-4150-8cda-095be459a6cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067450027 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2067450027
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4059582844
Short name T144
Test name
Test status
Simulation time 692163332 ps
CPU time 8.22 seconds
Started Aug 06 04:44:18 PM PDT 24
Finished Aug 06 04:44:27 PM PDT 24
Peak memory 219144 kb
Host smart-11974979-18ad-490c-acbc-63c4315c5098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059582844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4059582844
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4075733363
Short name T41
Test name
Test status
Simulation time 78715155323 ps
CPU time 222.89 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:47:54 PM PDT 24
Peak memory 218920 kb
Host smart-a4bf38c6-1419-408b-ac9f-d728e940a40c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075733363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4075733363
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.108534615
Short name T25
Test name
Test status
Simulation time 502953661 ps
CPU time 23.1 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:44:55 PM PDT 24
Peak memory 220076 kb
Host smart-76d7e804-dc20-4671-a554-4452a559f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108534615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.108534615
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3543280269
Short name T174
Test name
Test status
Simulation time 270068791 ps
CPU time 12.52 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 219932 kb
Host smart-ede8fe2d-5408-458b-8a69-98274c7b1950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543280269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3543280269
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.285811998
Short name T181
Test name
Test status
Simulation time 1505066910 ps
CPU time 28.29 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:44 PM PDT 24
Peak memory 219928 kb
Host smart-5c9a431e-0f9b-42e6-a9e1-993b6881cc83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285811998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.285811998
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.164044675
Short name T47
Test name
Test status
Simulation time 118356275601 ps
CPU time 841.58 seconds
Started Aug 06 04:44:18 PM PDT 24
Finished Aug 06 04:58:19 PM PDT 24
Peak memory 238248 kb
Host smart-d77735a0-e7a2-4672-bd69-c122b6725f10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164044675 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.164044675
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3377389761
Short name T188
Test name
Test status
Simulation time 94999029465 ps
CPU time 474.18 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:52:21 PM PDT 24
Peak memory 235840 kb
Host smart-9591bfa0-f0c2-41f4-b928-8ce1bcd79c9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377389761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3377389761
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3910007387
Short name T146
Test name
Test status
Simulation time 1379073349 ps
CPU time 18.97 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:44:46 PM PDT 24
Peak memory 219984 kb
Host smart-015ab576-ca70-4d68-956e-0476eab2fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910007387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3910007387
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1822227417
Short name T13
Test name
Test status
Simulation time 806617892 ps
CPU time 10.73 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:25 PM PDT 24
Peak memory 219984 kb
Host smart-ae9cae35-47c8-4cc4-8be8-d17acf798c0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822227417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1822227417
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2859943104
Short name T313
Test name
Test status
Simulation time 1476480366 ps
CPU time 38.49 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:52 PM PDT 24
Peak memory 220556 kb
Host smart-89a0b990-5ada-499e-99e8-a45f7414bc29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859943104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2859943104
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.236225542
Short name T257
Test name
Test status
Simulation time 1244283691 ps
CPU time 10.2 seconds
Started Aug 06 04:44:28 PM PDT 24
Finished Aug 06 04:44:38 PM PDT 24
Peak memory 218388 kb
Host smart-ab8cfe02-03a9-4262-a6b0-1ebdaa502546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236225542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.236225542
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2486574817
Short name T216
Test name
Test status
Simulation time 9775975584 ps
CPU time 265.29 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:48:38 PM PDT 24
Peak memory 242264 kb
Host smart-1a67ef57-6135-4516-88a8-0785a6f7e33c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486574817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2486574817
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3438040321
Short name T280
Test name
Test status
Simulation time 671154283 ps
CPU time 22.84 seconds
Started Aug 06 04:44:15 PM PDT 24
Finished Aug 06 04:44:38 PM PDT 24
Peak memory 219944 kb
Host smart-3ee52232-282d-4c60-a21b-e60c885fa400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438040321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3438040321
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1525546732
Short name T175
Test name
Test status
Simulation time 368576709 ps
CPU time 10.52 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:25 PM PDT 24
Peak memory 219984 kb
Host smart-9848d599-c530-4805-a982-c5cb34a53fdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525546732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1525546732
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1315495603
Short name T265
Test name
Test status
Simulation time 1231403426 ps
CPU time 18.34 seconds
Started Aug 06 04:44:21 PM PDT 24
Finished Aug 06 04:44:39 PM PDT 24
Peak memory 219888 kb
Host smart-3dad6469-aef9-49cb-81fa-851aee2fe762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315495603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1315495603
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2173188384
Short name T193
Test name
Test status
Simulation time 171142968 ps
CPU time 8.27 seconds
Started Aug 06 04:43:39 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 218960 kb
Host smart-0d7711d0-0136-4124-a6ce-e027f20e7f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173188384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2173188384
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1109495679
Short name T301
Test name
Test status
Simulation time 21408433803 ps
CPU time 273.91 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:48:11 PM PDT 24
Peak memory 219756 kb
Host smart-93491c2b-8ed9-4493-b43e-6a5d102ebca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109495679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1109495679
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1783017502
Short name T31
Test name
Test status
Simulation time 496593456 ps
CPU time 22.78 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 219980 kb
Host smart-4665e55e-8114-4a20-be24-882375cf0f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783017502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1783017502
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.15163204
Short name T289
Test name
Test status
Simulation time 176132568 ps
CPU time 10.5 seconds
Started Aug 06 04:43:50 PM PDT 24
Finished Aug 06 04:44:01 PM PDT 24
Peak memory 219944 kb
Host smart-b26b270e-4d72-460b-b455-754af92ef122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15163204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.15163204
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2179468187
Short name T217
Test name
Test status
Simulation time 2073470758 ps
CPU time 18.1 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:56 PM PDT 24
Peak memory 220028 kb
Host smart-c6ed8d63-137b-4462-af25-e5f293d46939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179468187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2179468187
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3235061985
Short name T202
Test name
Test status
Simulation time 181240186 ps
CPU time 13.62 seconds
Started Aug 06 04:43:44 PM PDT 24
Finished Aug 06 04:43:57 PM PDT 24
Peak memory 219508 kb
Host smart-c235e4bc-50fe-4dad-ad98-6cd4674e8204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235061985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3235061985
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2377881007
Short name T15
Test name
Test status
Simulation time 35040235111 ps
CPU time 9390.98 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 07:20:04 PM PDT 24
Peak memory 234400 kb
Host smart-e0efc945-46e0-42f5-866e-d8f6eb9dac4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377881007 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2377881007
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.60344748
Short name T135
Test name
Test status
Simulation time 346072425 ps
CPU time 8.62 seconds
Started Aug 06 04:43:59 PM PDT 24
Finished Aug 06 04:44:08 PM PDT 24
Peak memory 218964 kb
Host smart-8e21f011-c6cf-4dc3-909c-1df78e5f1e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60344748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.60344748
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2347951391
Short name T281
Test name
Test status
Simulation time 21311197254 ps
CPU time 410.95 seconds
Started Aug 06 04:43:31 PM PDT 24
Finished Aug 06 04:50:22 PM PDT 24
Peak memory 220304 kb
Host smart-699def9b-4022-45d2-a39a-f7dc80b50527
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347951391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2347951391
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1999809670
Short name T152
Test name
Test status
Simulation time 1378409433 ps
CPU time 19.42 seconds
Started Aug 06 04:43:46 PM PDT 24
Finished Aug 06 04:44:05 PM PDT 24
Peak memory 219956 kb
Host smart-39d4dab6-d6e7-42e8-bdd0-f434121c738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999809670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1999809670
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.78727147
Short name T158
Test name
Test status
Simulation time 3200090074 ps
CPU time 12.03 seconds
Started Aug 06 04:43:27 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 220152 kb
Host smart-c90c5778-afa0-4910-b47f-adb97335263a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78727147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.78727147
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3654108993
Short name T79
Test name
Test status
Simulation time 1007902962 ps
CPU time 11.5 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:49 PM PDT 24
Peak memory 219924 kb
Host smart-40475c9b-f584-4fc1-9906-c35b077211aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654108993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3654108993
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3608516365
Short name T233
Test name
Test status
Simulation time 2167692104 ps
CPU time 34.01 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:44:11 PM PDT 24
Peak memory 220036 kb
Host smart-2646e6b7-4b1e-412d-ad94-fa1eea49842f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608516365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3608516365
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.175096351
Short name T243
Test name
Test status
Simulation time 252216039 ps
CPU time 10.14 seconds
Started Aug 06 04:43:46 PM PDT 24
Finished Aug 06 04:43:56 PM PDT 24
Peak memory 218972 kb
Host smart-329ab04a-808b-473b-8fca-377773228d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175096351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.175096351
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3922915165
Short name T247
Test name
Test status
Simulation time 11586407567 ps
CPU time 183.83 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:46:42 PM PDT 24
Peak memory 239500 kb
Host smart-f1b8f378-fe8a-49cc-8ac2-5f95e958beb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922915165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3922915165
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3894868898
Short name T142
Test name
Test status
Simulation time 2064152125 ps
CPU time 22.35 seconds
Started Aug 06 04:43:33 PM PDT 24
Finished Aug 06 04:43:55 PM PDT 24
Peak memory 219976 kb
Host smart-b7be05b7-e54c-4cc7-96f8-b2f30e95abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894868898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3894868898
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3779757105
Short name T256
Test name
Test status
Simulation time 706619334 ps
CPU time 10.77 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 219976 kb
Host smart-a24a3681-bfb6-48e4-9c79-c62eb3419c66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779757105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3779757105
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1849977485
Short name T224
Test name
Test status
Simulation time 994493377 ps
CPU time 16.11 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:54 PM PDT 24
Peak memory 219812 kb
Host smart-f22376e4-5e7d-466c-8894-58f300bc5627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849977485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1849977485
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4271283997
Short name T312
Test name
Test status
Simulation time 4045390032 ps
CPU time 25.3 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:44:07 PM PDT 24
Peak memory 219912 kb
Host smart-956417a8-181f-4a3e-a840-960ad99b5b8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271283997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4271283997
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2060161437
Short name T66
Test name
Test status
Simulation time 250282462 ps
CPU time 9.81 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:47 PM PDT 24
Peak memory 218860 kb
Host smart-8965dc43-f867-4d0d-b4b4-ac6c9e7c5c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060161437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2060161437
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1558596016
Short name T287
Test name
Test status
Simulation time 9987711874 ps
CPU time 224.76 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:47:28 PM PDT 24
Peak memory 229860 kb
Host smart-552a4e3e-4152-489f-bb82-4d806a2a6488
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558596016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1558596016
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.609095563
Short name T163
Test name
Test status
Simulation time 345581169 ps
CPU time 19.33 seconds
Started Aug 06 04:43:58 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 220028 kb
Host smart-d50a8a74-f044-45ca-a9d8-0eade4d953a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609095563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.609095563
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3539490705
Short name T111
Test name
Test status
Simulation time 9938170924 ps
CPU time 17.07 seconds
Started Aug 06 04:43:55 PM PDT 24
Finished Aug 06 04:44:12 PM PDT 24
Peak memory 220084 kb
Host smart-79b9a6ee-eaea-411b-9571-514206356960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539490705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3539490705
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.554372853
Short name T128
Test name
Test status
Simulation time 2450051413 ps
CPU time 10.21 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:47 PM PDT 24
Peak memory 220040 kb
Host smart-8e14eb77-afb2-4e82-a57e-49ba2ed8cebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554372853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.554372853
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2119267531
Short name T244
Test name
Test status
Simulation time 1590184035 ps
CPU time 27.43 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:44:08 PM PDT 24
Peak memory 219836 kb
Host smart-66093d48-e708-4e02-b866-2ab3b7950dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119267531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2119267531
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2453955699
Short name T55
Test name
Test status
Simulation time 1027539713 ps
CPU time 10.1 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:43:54 PM PDT 24
Peak memory 219048 kb
Host smart-685252a8-13b5-4c09-b850-15e627837515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453955699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2453955699
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2778417309
Short name T220
Test name
Test status
Simulation time 3382371237 ps
CPU time 213.21 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:47:13 PM PDT 24
Peak memory 235080 kb
Host smart-3b8073a1-69c4-4ce6-9e7a-dc13bd21a573
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778417309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2778417309
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2188850210
Short name T125
Test name
Test status
Simulation time 1270258722 ps
CPU time 19.09 seconds
Started Aug 06 04:43:44 PM PDT 24
Finished Aug 06 04:44:03 PM PDT 24
Peak memory 220044 kb
Host smart-d3115313-3b69-4fff-bae5-e28fcb27640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188850210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2188850210
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3676771876
Short name T97
Test name
Test status
Simulation time 687388180 ps
CPU time 11 seconds
Started Aug 06 04:43:56 PM PDT 24
Finished Aug 06 04:44:07 PM PDT 24
Peak memory 219932 kb
Host smart-c54a0bf0-dc3f-4f1a-89fd-d24662ac8404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676771876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3676771876
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2060386381
Short name T278
Test name
Test status
Simulation time 1434531777 ps
CPU time 12.27 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:44:07 PM PDT 24
Peak memory 219936 kb
Host smart-6556d207-f33e-46da-a88b-873f06024759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060386381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2060386381
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1946914141
Short name T151
Test name
Test status
Simulation time 3034717370 ps
CPU time 26.52 seconds
Started Aug 06 04:44:03 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 220004 kb
Host smart-f652d8c5-654e-4f6d-a290-2e926b0ed035
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946914141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1946914141
Directory /workspace/9.rom_ctrl_stress_all/latest
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