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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 96.89 91.99 97.68 100.00 98.28 97.45 98.14


Total test records in report: 406
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T292 /workspace/coverage/default/22.rom_ctrl_alert_test.1669970275 Aug 07 04:55:06 PM PDT 24 Aug 07 04:55:15 PM PDT 24 718264774 ps
T293 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3920431 Aug 07 04:55:14 PM PDT 24 Aug 07 04:55:25 PM PDT 24 1682401761 ps
T294 /workspace/coverage/default/38.rom_ctrl_alert_test.3256272511 Aug 07 04:55:30 PM PDT 24 Aug 07 04:55:38 PM PDT 24 167613666 ps
T295 /workspace/coverage/default/39.rom_ctrl_alert_test.2415342125 Aug 07 04:55:32 PM PDT 24 Aug 07 04:55:42 PM PDT 24 995058401 ps
T296 /workspace/coverage/default/20.rom_ctrl_alert_test.3845979764 Aug 07 04:55:20 PM PDT 24 Aug 07 04:55:30 PM PDT 24 254524844 ps
T297 /workspace/coverage/default/25.rom_ctrl_stress_all.2224908071 Aug 07 04:55:03 PM PDT 24 Aug 07 04:55:39 PM PDT 24 313890411 ps
T298 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1703338353 Aug 07 04:54:59 PM PDT 24 Aug 07 04:55:18 PM PDT 24 340622090 ps
T299 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1114496511 Aug 07 04:55:38 PM PDT 24 Aug 07 04:57:28 PM PDT 24 7170583269 ps
T300 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2597265883 Aug 07 04:54:40 PM PDT 24 Aug 07 04:54:51 PM PDT 24 356943650 ps
T301 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3217535350 Aug 07 04:54:58 PM PDT 24 Aug 07 05:07:54 PM PDT 24 91888865566 ps
T302 /workspace/coverage/default/27.rom_ctrl_stress_all.961355432 Aug 07 04:55:35 PM PDT 24 Aug 07 04:55:47 PM PDT 24 856288364 ps
T303 /workspace/coverage/default/8.rom_ctrl_stress_all.3582678244 Aug 07 04:55:01 PM PDT 24 Aug 07 04:55:35 PM PDT 24 250557531 ps
T304 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1755131477 Aug 07 04:55:08 PM PDT 24 Aug 07 04:55:30 PM PDT 24 1897440856 ps
T305 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.308552874 Aug 07 04:55:03 PM PDT 24 Aug 07 04:55:15 PM PDT 24 1817448574 ps
T306 /workspace/coverage/default/29.rom_ctrl_alert_test.2073968645 Aug 07 04:55:22 PM PDT 24 Aug 07 04:55:37 PM PDT 24 4279719790 ps
T307 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.742015602 Aug 07 04:55:02 PM PDT 24 Aug 07 05:10:43 PM PDT 24 26761871978 ps
T308 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.60771306 Aug 07 04:55:03 PM PDT 24 Aug 07 04:59:02 PM PDT 24 14520672005 ps
T309 /workspace/coverage/default/38.rom_ctrl_stress_all.2972040917 Aug 07 04:55:03 PM PDT 24 Aug 07 04:55:21 PM PDT 24 777171737 ps
T310 /workspace/coverage/default/36.rom_ctrl_stress_all.2356743945 Aug 07 04:55:15 PM PDT 24 Aug 07 04:55:59 PM PDT 24 3589605691 ps
T311 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.991486617 Aug 07 04:55:05 PM PDT 24 Aug 07 04:55:17 PM PDT 24 536438184 ps
T312 /workspace/coverage/default/44.rom_ctrl_alert_test.1204083807 Aug 07 04:55:34 PM PDT 24 Aug 07 04:55:43 PM PDT 24 689344051 ps
T33 /workspace/coverage/default/2.rom_ctrl_sec_cm.164175635 Aug 07 04:54:56 PM PDT 24 Aug 07 04:58:43 PM PDT 24 752162827 ps
T313 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3313314741 Aug 07 04:55:39 PM PDT 24 Aug 07 04:55:57 PM PDT 24 1374983734 ps
T314 /workspace/coverage/default/2.rom_ctrl_smoke.3809260845 Aug 07 04:54:59 PM PDT 24 Aug 07 04:55:11 PM PDT 24 553065866 ps
T315 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3826865921 Aug 07 04:55:08 PM PDT 24 Aug 07 05:33:35 PM PDT 24 251417987482 ps
T316 /workspace/coverage/default/40.rom_ctrl_stress_all.1392610909 Aug 07 04:55:28 PM PDT 24 Aug 07 04:56:16 PM PDT 24 11399208101 ps
T317 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2099584159 Aug 07 04:55:47 PM PDT 24 Aug 07 05:00:20 PM PDT 24 7739887319 ps
T318 /workspace/coverage/default/17.rom_ctrl_stress_all.3460549378 Aug 07 04:55:12 PM PDT 24 Aug 07 04:55:43 PM PDT 24 547193671 ps
T58 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.668534457 Aug 07 04:55:09 PM PDT 24 Aug 07 04:57:53 PM PDT 24 451038656 ps
T61 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1129625498 Aug 07 04:55:13 PM PDT 24 Aug 07 04:55:25 PM PDT 24 603077891 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2842154290 Aug 07 04:54:59 PM PDT 24 Aug 07 04:55:07 PM PDT 24 332163350 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3413469592 Aug 07 04:54:50 PM PDT 24 Aug 07 04:55:00 PM PDT 24 1125151256 ps
T319 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3852533435 Aug 07 04:54:49 PM PDT 24 Aug 07 04:55:03 PM PDT 24 167792349 ps
T320 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1237042024 Aug 07 04:55:43 PM PDT 24 Aug 07 04:55:55 PM PDT 24 614735101 ps
T65 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1580076500 Aug 07 04:55:08 PM PDT 24 Aug 07 04:55:17 PM PDT 24 616334531 ps
T95 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3229895318 Aug 07 04:55:01 PM PDT 24 Aug 07 04:55:16 PM PDT 24 1017450893 ps
T96 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3793346204 Aug 07 04:55:16 PM PDT 24 Aug 07 04:55:24 PM PDT 24 242357573 ps
T59 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1007480006 Aug 07 04:55:36 PM PDT 24 Aug 07 04:58:16 PM PDT 24 2323626925 ps
T60 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2830505438 Aug 07 04:54:52 PM PDT 24 Aug 07 04:57:31 PM PDT 24 366094385 ps
T321 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1046735492 Aug 07 04:55:02 PM PDT 24 Aug 07 04:55:10 PM PDT 24 378922065 ps
T322 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1682571189 Aug 07 04:55:38 PM PDT 24 Aug 07 04:55:47 PM PDT 24 689037800 ps
T323 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1665805362 Aug 07 04:54:59 PM PDT 24 Aug 07 04:55:10 PM PDT 24 845528954 ps
T66 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1260456459 Aug 07 04:55:30 PM PDT 24 Aug 07 04:55:40 PM PDT 24 261233677 ps
T324 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.246858062 Aug 07 04:54:54 PM PDT 24 Aug 07 04:55:04 PM PDT 24 513835647 ps
T325 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4282530032 Aug 07 04:54:42 PM PDT 24 Aug 07 04:54:51 PM PDT 24 751903759 ps
T326 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3755502657 Aug 07 04:55:29 PM PDT 24 Aug 07 04:55:41 PM PDT 24 751769487 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.109509459 Aug 07 04:55:26 PM PDT 24 Aug 07 04:55:34 PM PDT 24 175635686 ps
T68 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3029512071 Aug 07 04:55:28 PM PDT 24 Aug 07 04:55:38 PM PDT 24 254333300 ps
T69 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.900751126 Aug 07 04:55:07 PM PDT 24 Aug 07 04:55:15 PM PDT 24 172527899 ps
T70 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.183447057 Aug 07 04:55:01 PM PDT 24 Aug 07 04:55:10 PM PDT 24 663949562 ps
T71 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3601190120 Aug 07 04:55:37 PM PDT 24 Aug 07 04:55:47 PM PDT 24 251287254 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1660859184 Aug 07 04:54:56 PM PDT 24 Aug 07 04:55:06 PM PDT 24 1773229811 ps
T90 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3085675960 Aug 07 04:55:27 PM PDT 24 Aug 07 04:55:37 PM PDT 24 253182886 ps
T327 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3039884999 Aug 07 04:55:25 PM PDT 24 Aug 07 04:55:35 PM PDT 24 1298793495 ps
T328 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.426267472 Aug 07 04:54:46 PM PDT 24 Aug 07 04:54:56 PM PDT 24 1241263557 ps
T91 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.858044384 Aug 07 04:55:06 PM PDT 24 Aug 07 04:55:18 PM PDT 24 1716900823 ps
T329 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4152663591 Aug 07 04:54:56 PM PDT 24 Aug 07 04:55:06 PM PDT 24 497791502 ps
T330 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4097983112 Aug 07 04:54:59 PM PDT 24 Aug 07 04:55:12 PM PDT 24 346733867 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2356791567 Aug 07 04:55:30 PM PDT 24 Aug 07 04:55:44 PM PDT 24 253253085 ps
T331 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4184320300 Aug 07 04:55:04 PM PDT 24 Aug 07 04:55:17 PM PDT 24 4927801530 ps
T93 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3888154004 Aug 07 04:54:49 PM PDT 24 Aug 07 04:54:59 PM PDT 24 1027040115 ps
T332 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3139704934 Aug 07 04:54:58 PM PDT 24 Aug 07 04:55:13 PM PDT 24 986437319 ps
T333 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4052774550 Aug 07 04:55:04 PM PDT 24 Aug 07 04:55:11 PM PDT 24 687857406 ps
T334 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1417967326 Aug 07 04:55:14 PM PDT 24 Aug 07 04:55:32 PM PDT 24 262421233 ps
T335 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2039960828 Aug 07 04:55:01 PM PDT 24 Aug 07 04:55:09 PM PDT 24 1037710413 ps
T336 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3405756353 Aug 07 04:55:02 PM PDT 24 Aug 07 04:55:21 PM PDT 24 2041089540 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3367622917 Aug 07 04:54:51 PM PDT 24 Aug 07 04:57:30 PM PDT 24 4438816944 ps
T337 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.324427622 Aug 07 04:54:50 PM PDT 24 Aug 07 04:55:01 PM PDT 24 1035505267 ps
T338 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2526370536 Aug 07 04:55:26 PM PDT 24 Aug 07 04:55:41 PM PDT 24 181749468 ps
T107 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1198954032 Aug 07 04:55:25 PM PDT 24 Aug 07 04:56:47 PM PDT 24 637414357 ps
T339 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1045459455 Aug 07 04:55:03 PM PDT 24 Aug 07 04:55:11 PM PDT 24 171027217 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3685159461 Aug 07 04:55:08 PM PDT 24 Aug 07 04:56:31 PM PDT 24 647883933 ps
T340 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2526184322 Aug 07 04:55:37 PM PDT 24 Aug 07 04:55:45 PM PDT 24 333099090 ps
T111 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1795047953 Aug 07 04:55:03 PM PDT 24 Aug 07 04:56:28 PM PDT 24 340873953 ps
T118 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2819375770 Aug 07 04:55:18 PM PDT 24 Aug 07 04:56:41 PM PDT 24 710307341 ps
T341 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2246930673 Aug 07 04:55:39 PM PDT 24 Aug 07 04:55:52 PM PDT 24 171077728 ps
T342 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2019866028 Aug 07 04:54:48 PM PDT 24 Aug 07 04:55:01 PM PDT 24 222481607 ps
T343 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2872180968 Aug 07 04:55:36 PM PDT 24 Aug 07 04:55:45 PM PDT 24 1124213059 ps
T344 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1368566410 Aug 07 04:55:06 PM PDT 24 Aug 07 04:55:16 PM PDT 24 995301163 ps
T345 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1538406604 Aug 07 04:55:29 PM PDT 24 Aug 07 04:55:42 PM PDT 24 338739161 ps
T346 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1095575612 Aug 07 04:55:04 PM PDT 24 Aug 07 04:55:19 PM PDT 24 1000977783 ps
T347 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2520157049 Aug 07 04:55:32 PM PDT 24 Aug 07 04:55:40 PM PDT 24 2060088160 ps
T348 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.742416360 Aug 07 04:54:57 PM PDT 24 Aug 07 04:55:08 PM PDT 24 273226174 ps
T349 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2508655938 Aug 07 04:55:02 PM PDT 24 Aug 07 04:55:12 PM PDT 24 260217398 ps
T108 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2025121781 Aug 07 04:55:02 PM PDT 24 Aug 07 04:56:24 PM PDT 24 614408802 ps
T350 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1531519942 Aug 07 04:55:05 PM PDT 24 Aug 07 04:55:44 PM PDT 24 2760787731 ps
T351 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3192000994 Aug 07 04:55:03 PM PDT 24 Aug 07 04:55:18 PM PDT 24 253775944 ps
T352 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.641089845 Aug 07 04:55:37 PM PDT 24 Aug 07 04:55:45 PM PDT 24 340506229 ps
T353 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1865129263 Aug 07 04:55:08 PM PDT 24 Aug 07 04:55:22 PM PDT 24 249696001 ps
T115 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.406580998 Aug 07 04:55:09 PM PDT 24 Aug 07 04:56:29 PM PDT 24 953188092 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2989786020 Aug 07 04:55:02 PM PDT 24 Aug 07 04:55:19 PM PDT 24 1787603224 ps
T354 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1880738508 Aug 07 04:54:58 PM PDT 24 Aug 07 04:55:07 PM PDT 24 2609805367 ps
T355 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.348597941 Aug 07 04:54:45 PM PDT 24 Aug 07 04:55:01 PM PDT 24 1037695378 ps
T356 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.155307793 Aug 07 04:55:07 PM PDT 24 Aug 07 04:55:15 PM PDT 24 823116437 ps
T357 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2111440360 Aug 07 04:54:56 PM PDT 24 Aug 07 04:55:11 PM PDT 24 1032072959 ps
T358 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3365966637 Aug 07 04:55:19 PM PDT 24 Aug 07 04:55:33 PM PDT 24 2068754486 ps
T359 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2563078758 Aug 07 04:55:43 PM PDT 24 Aug 07 04:55:54 PM PDT 24 374590670 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3850176851 Aug 07 04:55:00 PM PDT 24 Aug 07 04:56:22 PM PDT 24 641403313 ps
T360 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3996270376 Aug 07 04:55:11 PM PDT 24 Aug 07 04:55:21 PM PDT 24 1029284773 ps
T361 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.136146133 Aug 07 04:55:17 PM PDT 24 Aug 07 04:55:31 PM PDT 24 774929608 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2172515388 Aug 07 04:54:44 PM PDT 24 Aug 07 04:54:56 PM PDT 24 1041321590 ps
T363 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2094121237 Aug 07 04:54:46 PM PDT 24 Aug 07 04:54:57 PM PDT 24 322362927 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4280916140 Aug 07 04:55:03 PM PDT 24 Aug 07 04:55:15 PM PDT 24 351756268 ps
T365 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.546551370 Aug 07 04:55:21 PM PDT 24 Aug 07 04:55:29 PM PDT 24 414290208 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1089877891 Aug 07 04:55:25 PM PDT 24 Aug 07 04:55:36 PM PDT 24 983711751 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1927290423 Aug 07 04:54:42 PM PDT 24 Aug 07 04:54:52 PM PDT 24 2255027314 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4109517412 Aug 07 04:54:56 PM PDT 24 Aug 07 04:55:06 PM PDT 24 1034001331 ps
T369 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2760028525 Aug 07 04:55:36 PM PDT 24 Aug 07 04:55:45 PM PDT 24 1032684748 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4191226551 Aug 07 04:54:56 PM PDT 24 Aug 07 04:57:30 PM PDT 24 619171578 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.832332315 Aug 07 04:55:40 PM PDT 24 Aug 07 04:57:00 PM PDT 24 3261538810 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.625328497 Aug 07 04:54:50 PM PDT 24 Aug 07 04:54:58 PM PDT 24 167645646 ps
T117 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.704935454 Aug 07 04:55:07 PM PDT 24 Aug 07 04:57:43 PM PDT 24 1453578276 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1988461818 Aug 07 04:54:59 PM PDT 24 Aug 07 04:55:08 PM PDT 24 302377621 ps
T372 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1000887394 Aug 07 04:55:11 PM PDT 24 Aug 07 04:55:21 PM PDT 24 511349262 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2491288973 Aug 07 04:54:57 PM PDT 24 Aug 07 04:55:09 PM PDT 24 696057751 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2448497399 Aug 07 04:55:09 PM PDT 24 Aug 07 04:55:19 PM PDT 24 3534568103 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.90887737 Aug 07 04:54:57 PM PDT 24 Aug 07 04:55:06 PM PDT 24 1030694717 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3671118722 Aug 07 04:54:54 PM PDT 24 Aug 07 04:55:05 PM PDT 24 167511427 ps
T376 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2806751445 Aug 07 04:55:19 PM PDT 24 Aug 07 04:55:33 PM PDT 24 2010850275 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2589523130 Aug 07 04:54:32 PM PDT 24 Aug 07 04:55:11 PM PDT 24 3123781608 ps
T110 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3791551155 Aug 07 04:54:50 PM PDT 24 Aug 07 04:57:21 PM PDT 24 1365715800 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2415576551 Aug 07 04:54:53 PM PDT 24 Aug 07 04:55:06 PM PDT 24 524348659 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1937835583 Aug 07 04:55:06 PM PDT 24 Aug 07 04:55:43 PM PDT 24 722891949 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3831750485 Aug 07 04:55:13 PM PDT 24 Aug 07 04:55:23 PM PDT 24 263018182 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3397602320 Aug 07 04:54:45 PM PDT 24 Aug 07 04:54:53 PM PDT 24 248604239 ps
T382 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.164488582 Aug 07 04:55:04 PM PDT 24 Aug 07 04:55:13 PM PDT 24 179654179 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1429052246 Aug 07 04:55:21 PM PDT 24 Aug 07 04:56:43 PM PDT 24 323202372 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.118048498 Aug 07 04:54:54 PM PDT 24 Aug 07 04:55:03 PM PDT 24 1030667892 ps
T82 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.846166379 Aug 07 04:55:04 PM PDT 24 Aug 07 04:55:12 PM PDT 24 517662555 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2835326414 Aug 07 04:55:18 PM PDT 24 Aug 07 04:55:29 PM PDT 24 546010753 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3949392498 Aug 07 04:54:56 PM PDT 24 Aug 07 04:55:04 PM PDT 24 174709656 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.313766594 Aug 07 04:55:23 PM PDT 24 Aug 07 04:55:32 PM PDT 24 167496734 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2611776282 Aug 07 04:54:57 PM PDT 24 Aug 07 04:55:06 PM PDT 24 174612509 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3850962712 Aug 07 04:55:17 PM PDT 24 Aug 07 04:55:32 PM PDT 24 1044017707 ps
T116 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1592127770 Aug 07 04:55:31 PM PDT 24 Aug 07 04:58:07 PM PDT 24 635960923 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.644427439 Aug 07 04:54:48 PM PDT 24 Aug 07 04:54:58 PM PDT 24 437289524 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1424613175 Aug 07 04:55:03 PM PDT 24 Aug 07 04:56:27 PM PDT 24 456484148 ps
T390 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3493019833 Aug 07 04:55:29 PM PDT 24 Aug 07 04:55:42 PM PDT 24 1029555963 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1557838320 Aug 07 04:55:12 PM PDT 24 Aug 07 04:55:37 PM PDT 24 1033430170 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.779230658 Aug 07 04:55:02 PM PDT 24 Aug 07 04:55:12 PM PDT 24 990367542 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.794270840 Aug 07 04:54:46 PM PDT 24 Aug 07 04:54:57 PM PDT 24 710270925 ps
T394 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1540663983 Aug 07 04:55:01 PM PDT 24 Aug 07 04:55:11 PM PDT 24 193980424 ps
T395 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4196865386 Aug 07 04:55:05 PM PDT 24 Aug 07 04:55:14 PM PDT 24 284287834 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.412177023 Aug 07 04:54:44 PM PDT 24 Aug 07 04:54:54 PM PDT 24 3518036586 ps
T397 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.988269406 Aug 07 04:55:44 PM PDT 24 Aug 07 04:55:56 PM PDT 24 320778583 ps
T398 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3521757724 Aug 07 04:55:17 PM PDT 24 Aug 07 04:55:28 PM PDT 24 170734574 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2761223512 Aug 07 04:55:40 PM PDT 24 Aug 07 04:55:52 PM PDT 24 231342393 ps
T400 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.116239508 Aug 07 04:54:59 PM PDT 24 Aug 07 04:55:09 PM PDT 24 1767045277 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2741497404 Aug 07 04:54:58 PM PDT 24 Aug 07 04:55:13 PM PDT 24 704099429 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3392111097 Aug 07 04:55:08 PM PDT 24 Aug 07 04:55:16 PM PDT 24 405299662 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.170003952 Aug 07 04:55:34 PM PDT 24 Aug 07 04:58:09 PM PDT 24 381403827 ps
T403 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2164751860 Aug 07 04:55:19 PM PDT 24 Aug 07 04:55:29 PM PDT 24 1177735950 ps
T404 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2618451349 Aug 07 04:55:18 PM PDT 24 Aug 07 04:55:29 PM PDT 24 276294305 ps
T114 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.943545346 Aug 07 04:55:07 PM PDT 24 Aug 07 04:57:43 PM PDT 24 1625977466 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.793628312 Aug 07 04:54:59 PM PDT 24 Aug 07 04:55:12 PM PDT 24 258553376 ps
T406 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1730936562 Aug 07 04:55:19 PM PDT 24 Aug 07 04:55:29 PM PDT 24 545576070 ps

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.211058564
Short name T3
Test name
Test status
Simulation time 162972517727 ps
CPU time 477.62 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 05:03:24 PM PDT 24
Peak memory 240460 kb
Host smart-5e393351-7283-4208-b780-529af925bef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211058564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.211058564
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.307771195
Short name T12
Test name
Test status
Simulation time 127267459566 ps
CPU time 8974.02 seconds
Started Aug 07 04:55:33 PM PDT 24
Finished Aug 07 07:25:08 PM PDT 24
Peak memory 238040 kb
Host smart-6392aa0f-43c8-4912-b876-4ed0819d83ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307771195 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.307771195
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.330917911
Short name T43
Test name
Test status
Simulation time 19084057186 ps
CPU time 354.11 seconds
Started Aug 07 04:55:30 PM PDT 24
Finished Aug 07 05:01:25 PM PDT 24
Peak memory 239304 kb
Host smart-f4715d68-f9c3-4dec-a420-e33197d2368e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330917911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.330917911
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1007480006
Short name T59
Test name
Test status
Simulation time 2323626925 ps
CPU time 159.32 seconds
Started Aug 07 04:55:36 PM PDT 24
Finished Aug 07 04:58:16 PM PDT 24
Peak memory 214764 kb
Host smart-56560d67-181a-485e-84df-85958c25d2a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007480006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1007480006
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.453172
Short name T5
Test name
Test status
Simulation time 1641733393 ps
CPU time 42.18 seconds
Started Aug 07 04:54:48 PM PDT 24
Finished Aug 07 04:55:31 PM PDT 24
Peak memory 220040 kb
Host smart-7f9b32be-0d2c-49b6-b56d-e199da34c2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.rom_ctrl_stress_all.453172
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.865146110
Short name T24
Test name
Test status
Simulation time 1665707946 ps
CPU time 222.9 seconds
Started Aug 07 04:54:43 PM PDT 24
Finished Aug 07 04:58:26 PM PDT 24
Peak memory 239828 kb
Host smart-3b9f6c77-029c-496e-8a99-724e878fc0be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865146110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.865146110
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2842154290
Short name T62
Test name
Test status
Simulation time 332163350 ps
CPU time 8.03 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:07 PM PDT 24
Peak memory 211516 kb
Host smart-d9c29e25-7409-48c0-b60e-76576085f46c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842154290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2842154290
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.943545346
Short name T114
Test name
Test status
Simulation time 1625977466 ps
CPU time 156.33 seconds
Started Aug 07 04:55:07 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 214772 kb
Host smart-9ce0abe3-ce45-46e7-bbc7-ee2a02cdc846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943545346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.943545346
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1021290954
Short name T146
Test name
Test status
Simulation time 497895135 ps
CPU time 9.89 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:13 PM PDT 24
Peak memory 219188 kb
Host smart-83dfab9b-b2f1-41e8-a336-b995f68413b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021290954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1021290954
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.64058382
Short name T1
Test name
Test status
Simulation time 4109883485 ps
CPU time 22.75 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 220152 kb
Host smart-a2c678ec-acdf-4b9f-a583-67abde48a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64058382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.64058382
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2589948866
Short name T131
Test name
Test status
Simulation time 1033049257 ps
CPU time 22.74 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:25 PM PDT 24
Peak memory 220068 kb
Host smart-2729a1e1-c8c9-4428-aae7-059ed7fa369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589948866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2589948866
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1592127770
Short name T116
Test name
Test status
Simulation time 635960923 ps
CPU time 156.16 seconds
Started Aug 07 04:55:31 PM PDT 24
Finished Aug 07 04:58:07 PM PDT 24
Peak memory 219452 kb
Host smart-162d002e-9130-4626-a9a9-4423e0258aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592127770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1592127770
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2506913231
Short name T17
Test name
Test status
Simulation time 106590435464 ps
CPU time 1130.48 seconds
Started Aug 07 04:55:13 PM PDT 24
Finished Aug 07 05:14:03 PM PDT 24
Peak memory 236240 kb
Host smart-b1759368-4854-4603-8312-ba95eefc3303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506913231 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2506913231
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3007726268
Short name T15
Test name
Test status
Simulation time 20346414689 ps
CPU time 760.56 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 05:07:47 PM PDT 24
Peak memory 229872 kb
Host smart-38e307b2-776e-4544-8151-ca4100bb2de5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007726268 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3007726268
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.668534457
Short name T58
Test name
Test status
Simulation time 451038656 ps
CPU time 158.35 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:57:53 PM PDT 24
Peak memory 214936 kb
Host smart-2c68bf27-dc7b-40a3-a2fe-817e2e91ee04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668534457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.668534457
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4191226551
Short name T112
Test name
Test status
Simulation time 619171578 ps
CPU time 153.97 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:57:30 PM PDT 24
Peak memory 215584 kb
Host smart-6f98e755-ef3e-4767-bf2c-612a535bc4fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191226551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4191226551
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.170003952
Short name T402
Test name
Test status
Simulation time 381403827 ps
CPU time 154.74 seconds
Started Aug 07 04:55:34 PM PDT 24
Finished Aug 07 04:58:09 PM PDT 24
Peak memory 219360 kb
Host smart-0101b4cb-dc2d-491e-825a-d596f961881c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170003952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.170003952
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.289548364
Short name T141
Test name
Test status
Simulation time 704697613 ps
CPU time 11 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 220072 kb
Host smart-65575ccd-aa05-45ed-bfa4-5705bc087258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289548364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.289548364
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2823173176
Short name T78
Test name
Test status
Simulation time 779256060 ps
CPU time 46.17 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:48 PM PDT 24
Peak memory 220656 kb
Host smart-bc92376a-3d63-420b-84b1-e7c8edaf81af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823173176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2823173176
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3888154004
Short name T93
Test name
Test status
Simulation time 1027040115 ps
CPU time 9.94 seconds
Started Aug 07 04:54:49 PM PDT 24
Finished Aug 07 04:54:59 PM PDT 24
Peak memory 211908 kb
Host smart-57dc926a-fa4f-4907-b740-317a1bdc2626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888154004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3888154004
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3601190120
Short name T71
Test name
Test status
Simulation time 251287254 ps
CPU time 10.42 seconds
Started Aug 07 04:55:37 PM PDT 24
Finished Aug 07 04:55:47 PM PDT 24
Peak memory 211396 kb
Host smart-0e264fc9-4c31-4430-8752-bdb3cdd2e946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601190120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3601190120
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1573198464
Short name T40
Test name
Test status
Simulation time 714129530 ps
CPU time 10.36 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 219968 kb
Host smart-c978b768-9822-4b09-a1b9-347ef618175d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573198464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1573198464
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.625328497
Short name T370
Test name
Test status
Simulation time 167645646 ps
CPU time 8.14 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:54:58 PM PDT 24
Peak memory 211148 kb
Host smart-6283287b-ac84-4ae9-8773-edc8bbe7ff65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625328497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.625328497
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.644427439
Short name T389
Test name
Test status
Simulation time 437289524 ps
CPU time 10.04 seconds
Started Aug 07 04:54:48 PM PDT 24
Finished Aug 07 04:54:58 PM PDT 24
Peak memory 211420 kb
Host smart-e6b8e17a-c1b4-46fd-bd34-88a115c62ea2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644427439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.644427439
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2415576551
Short name T378
Test name
Test status
Simulation time 524348659 ps
CPU time 13.46 seconds
Started Aug 07 04:54:53 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 212320 kb
Host smart-2c06b535-d86a-4331-a4c2-b2807d2ac398
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415576551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2415576551
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2094121237
Short name T363
Test name
Test status
Simulation time 322362927 ps
CPU time 10.66 seconds
Started Aug 07 04:54:46 PM PDT 24
Finished Aug 07 04:54:57 PM PDT 24
Peak memory 217220 kb
Host smart-71ea5237-41b0-4991-ad48-9a5ea44248bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094121237 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2094121237
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3397602320
Short name T381
Test name
Test status
Simulation time 248604239 ps
CPU time 8.34 seconds
Started Aug 07 04:54:45 PM PDT 24
Finished Aug 07 04:54:53 PM PDT 24
Peak memory 211636 kb
Host smart-a42ddf99-8ee9-40f1-9a99-d5ddc801f569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397602320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3397602320
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.794270840
Short name T393
Test name
Test status
Simulation time 710270925 ps
CPU time 10.09 seconds
Started Aug 07 04:54:46 PM PDT 24
Finished Aug 07 04:54:57 PM PDT 24
Peak memory 211128 kb
Host smart-1289d5b7-25b6-41cd-8e1d-e68ce37bc7df
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794270840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.794270840
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4282530032
Short name T325
Test name
Test status
Simulation time 751903759 ps
CPU time 8.04 seconds
Started Aug 07 04:54:42 PM PDT 24
Finished Aug 07 04:54:51 PM PDT 24
Peak memory 211056 kb
Host smart-b6e8e53c-54e4-498b-b160-e6c092facce8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282530032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4282530032
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1988461818
Short name T371
Test name
Test status
Simulation time 302377621 ps
CPU time 8.31 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:08 PM PDT 24
Peak memory 211824 kb
Host smart-59aca9e4-9844-48a5-818f-8125c0589804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988461818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1988461818
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3405756353
Short name T336
Test name
Test status
Simulation time 2041089540 ps
CPU time 19.12 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:21 PM PDT 24
Peak memory 219152 kb
Host smart-6c402365-8d88-4f3f-a8dd-a46683e820a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405756353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3405756353
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3367622917
Short name T104
Test name
Test status
Simulation time 4438816944 ps
CPU time 158.42 seconds
Started Aug 07 04:54:51 PM PDT 24
Finished Aug 07 04:57:30 PM PDT 24
Peak memory 215032 kb
Host smart-ec23e4c8-9306-40cb-8344-e9dee2df7ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367622917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3367622917
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.90887737
Short name T81
Test name
Test status
Simulation time 1030694717 ps
CPU time 9.75 seconds
Started Aug 07 04:54:57 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 211324 kb
Host smart-b1d1193f-1f24-4a0b-8bdc-90fc98cc2ebd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90887737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasi
ng.90887737
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.412177023
Short name T396
Test name
Test status
Simulation time 3518036586 ps
CPU time 10.03 seconds
Started Aug 07 04:54:44 PM PDT 24
Finished Aug 07 04:54:54 PM PDT 24
Peak memory 211236 kb
Host smart-c90e2e83-819f-496b-90d5-126abbd1f145
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412177023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.412177023
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2491288973
Short name T373
Test name
Test status
Simulation time 696057751 ps
CPU time 11.96 seconds
Started Aug 07 04:54:57 PM PDT 24
Finished Aug 07 04:55:09 PM PDT 24
Peak memory 211492 kb
Host smart-f2ca18b3-fe69-41ed-8186-42afcdb6d673
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491288973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2491288973
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.246858062
Short name T324
Test name
Test status
Simulation time 513835647 ps
CPU time 10.23 seconds
Started Aug 07 04:54:54 PM PDT 24
Finished Aug 07 04:55:04 PM PDT 24
Peak memory 216760 kb
Host smart-3c8af080-704d-4a2e-836a-3adf531e4bbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246858062 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.246858062
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.426267472
Short name T328
Test name
Test status
Simulation time 1241263557 ps
CPU time 9.75 seconds
Started Aug 07 04:54:46 PM PDT 24
Finished Aug 07 04:54:56 PM PDT 24
Peak memory 211768 kb
Host smart-7e01458d-3e39-4f76-b139-8129edd01efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426267472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.426267472
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4109517412
Short name T368
Test name
Test status
Simulation time 1034001331 ps
CPU time 9.77 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 211160 kb
Host smart-f6704f7d-5662-4488-86c5-49d9f7c886a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109517412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4109517412
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1927290423
Short name T367
Test name
Test status
Simulation time 2255027314 ps
CPU time 9.87 seconds
Started Aug 07 04:54:42 PM PDT 24
Finished Aug 07 04:54:52 PM PDT 24
Peak memory 211124 kb
Host smart-39b1aed8-dbbe-4613-94fa-9833003b9c3f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927290423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1927290423
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2589523130
Short name T377
Test name
Test status
Simulation time 3123781608 ps
CPU time 38.31 seconds
Started Aug 07 04:54:32 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 214384 kb
Host smart-3c033acd-4ba7-4620-a2ec-b348e1886c41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589523130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2589523130
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2019866028
Short name T342
Test name
Test status
Simulation time 222481607 ps
CPU time 12.84 seconds
Started Aug 07 04:54:48 PM PDT 24
Finished Aug 07 04:55:01 PM PDT 24
Peak memory 219092 kb
Host smart-62ccdd87-0556-4415-bdfc-b3d2136384e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019866028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2019866028
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3791551155
Short name T110
Test name
Test status
Simulation time 1365715800 ps
CPU time 151.34 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:57:21 PM PDT 24
Peak memory 219436 kb
Host smart-4320163f-8fcb-49ef-80f3-35a9bec5bd8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791551155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3791551155
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1540663983
Short name T394
Test name
Test status
Simulation time 193980424 ps
CPU time 9.71 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 218220 kb
Host smart-482c00d3-347a-49a4-bfb1-87dfc7cffa3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540663983 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1540663983
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3039884999
Short name T327
Test name
Test status
Simulation time 1298793495 ps
CPU time 9.88 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:55:35 PM PDT 24
Peak memory 211184 kb
Host smart-73f1813b-4a13-4df2-a8d3-d02aa4795d51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039884999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3039884999
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.779230658
Short name T392
Test name
Test status
Simulation time 990367542 ps
CPU time 9.8 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 211520 kb
Host smart-b183ae88-a81c-4d71-96cd-a1ae52a753e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779230658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.779230658
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1557838320
Short name T391
Test name
Test status
Simulation time 1033430170 ps
CPU time 14.58 seconds
Started Aug 07 04:55:12 PM PDT 24
Finished Aug 07 04:55:37 PM PDT 24
Peak memory 218336 kb
Host smart-f73a1293-0b28-4dc0-9e22-4cb8e67a1782
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557838320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1557838320
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1045459455
Short name T339
Test name
Test status
Simulation time 171027217 ps
CPU time 8.27 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 216304 kb
Host smart-c50532f4-dcb1-4699-8e83-e9e0fef8914e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045459455 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1045459455
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2039960828
Short name T335
Test name
Test status
Simulation time 1037710413 ps
CPU time 8.02 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:09 PM PDT 24
Peak memory 211308 kb
Host smart-f26a6cd3-eed2-4ba9-a20f-fe76dad2a392
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039960828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2039960828
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1368566410
Short name T344
Test name
Test status
Simulation time 995301163 ps
CPU time 9.89 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 04:55:16 PM PDT 24
Peak memory 212180 kb
Host smart-d395cd85-5153-4997-a653-5fd1496a8f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368566410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1368566410
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2761223512
Short name T399
Test name
Test status
Simulation time 231342393 ps
CPU time 11.28 seconds
Started Aug 07 04:55:40 PM PDT 24
Finished Aug 07 04:55:52 PM PDT 24
Peak memory 218160 kb
Host smart-0699cb70-124b-4c94-9309-d7000fab91e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761223512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2761223512
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1089877891
Short name T366
Test name
Test status
Simulation time 983711751 ps
CPU time 10.38 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:55:36 PM PDT 24
Peak memory 215912 kb
Host smart-01a1faa1-053f-459f-be7d-3a1b734d4190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089877891 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1089877891
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.313766594
Short name T386
Test name
Test status
Simulation time 167496734 ps
CPU time 8.17 seconds
Started Aug 07 04:55:23 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 211236 kb
Host smart-e3172767-f428-4675-9340-66161fea44b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313766594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.313766594
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3850962712
Short name T388
Test name
Test status
Simulation time 1044017707 ps
CPU time 14.86 seconds
Started Aug 07 04:55:17 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 213236 kb
Host smart-0e1aa37f-166b-48c6-9bf9-4c386b0c5639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850962712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3850962712
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3365966637
Short name T358
Test name
Test status
Simulation time 2068754486 ps
CPU time 13.35 seconds
Started Aug 07 04:55:19 PM PDT 24
Finished Aug 07 04:55:33 PM PDT 24
Peak memory 218028 kb
Host smart-f35f4257-d0c7-41e8-92d8-0ee41b07de92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365966637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3365966637
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2618451349
Short name T404
Test name
Test status
Simulation time 276294305 ps
CPU time 10.96 seconds
Started Aug 07 04:55:18 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 217588 kb
Host smart-85b2c367-c690-4039-832b-ec632a6ccab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618451349 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2618451349
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4196865386
Short name T395
Test name
Test status
Simulation time 284287834 ps
CPU time 9.75 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:14 PM PDT 24
Peak memory 211164 kb
Host smart-5934cf8b-c196-41e0-9328-dfdd4da9629b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196865386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4196865386
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2448497399
Short name T374
Test name
Test status
Simulation time 3534568103 ps
CPU time 9.78 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:55:19 PM PDT 24
Peak memory 211764 kb
Host smart-6d2097d6-21fc-47b6-9b0c-2f24b58489d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448497399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2448497399
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.136146133
Short name T361
Test name
Test status
Simulation time 774929608 ps
CPU time 14.51 seconds
Started Aug 07 04:55:17 PM PDT 24
Finished Aug 07 04:55:31 PM PDT 24
Peak memory 218100 kb
Host smart-8f3bab90-f43c-486b-a72b-9c8eee4ab3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136146133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.136146133
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3685159461
Short name T103
Test name
Test status
Simulation time 647883933 ps
CPU time 82.44 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:56:31 PM PDT 24
Peak memory 214076 kb
Host smart-44a24f25-00af-4fcd-b8bb-5a1e6e37e496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685159461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3685159461
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1682571189
Short name T322
Test name
Test status
Simulation time 689037800 ps
CPU time 8.87 seconds
Started Aug 07 04:55:38 PM PDT 24
Finished Aug 07 04:55:47 PM PDT 24
Peak memory 216676 kb
Host smart-924c6ffa-756b-4b21-a7e2-b0ade989ade0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682571189 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1682571189
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1580076500
Short name T65
Test name
Test status
Simulation time 616334531 ps
CPU time 7.96 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:17 PM PDT 24
Peak memory 211516 kb
Host smart-f64d40fe-e38f-466d-9042-f937696aebff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580076500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1580076500
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2520157049
Short name T347
Test name
Test status
Simulation time 2060088160 ps
CPU time 8.38 seconds
Started Aug 07 04:55:32 PM PDT 24
Finished Aug 07 04:55:40 PM PDT 24
Peak memory 212056 kb
Host smart-e92af5b7-7e01-4134-be34-d0ee9ef85eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520157049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2520157049
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1417967326
Short name T334
Test name
Test status
Simulation time 262421233 ps
CPU time 14.96 seconds
Started Aug 07 04:55:14 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 218132 kb
Host smart-6c984e87-2f33-4e55-a24d-bf708e7ef285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417967326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1417967326
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.406580998
Short name T115
Test name
Test status
Simulation time 953188092 ps
CPU time 79.79 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:56:29 PM PDT 24
Peak memory 212980 kb
Host smart-922820ca-f625-451f-a5ef-18b1286027fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406580998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.406580998
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2835326414
Short name T384
Test name
Test status
Simulation time 546010753 ps
CPU time 10.78 seconds
Started Aug 07 04:55:18 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 217216 kb
Host smart-f765be93-33ab-4b9f-a65b-5901c50d5815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835326414 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2835326414
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3392111097
Short name T401
Test name
Test status
Simulation time 405299662 ps
CPU time 7.82 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:16 PM PDT 24
Peak memory 211404 kb
Host smart-9bc90ee5-5dff-4184-9b59-64e27f1ad83d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392111097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3392111097
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3085675960
Short name T90
Test name
Test status
Simulation time 253182886 ps
CPU time 10.03 seconds
Started Aug 07 04:55:27 PM PDT 24
Finished Aug 07 04:55:37 PM PDT 24
Peak memory 211720 kb
Host smart-2c2697c7-12b2-42df-b45e-bb5168753458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085675960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3085675960
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3521757724
Short name T398
Test name
Test status
Simulation time 170734574 ps
CPU time 10.76 seconds
Started Aug 07 04:55:17 PM PDT 24
Finished Aug 07 04:55:28 PM PDT 24
Peak memory 217988 kb
Host smart-17841842-d586-4e1c-a25d-f24d4a7d8212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521757724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3521757724
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.704935454
Short name T117
Test name
Test status
Simulation time 1453578276 ps
CPU time 155.08 seconds
Started Aug 07 04:55:07 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 214740 kb
Host smart-01ee58b5-89f6-4493-8d61-7904ee79c051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704935454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.704935454
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2164751860
Short name T403
Test name
Test status
Simulation time 1177735950 ps
CPU time 10.23 seconds
Started Aug 07 04:55:19 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 217064 kb
Host smart-2b7d9396-026f-405f-a1ed-f80b51eb20df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164751860 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2164751860
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2760028525
Short name T369
Test name
Test status
Simulation time 1032684748 ps
CPU time 9.31 seconds
Started Aug 07 04:55:36 PM PDT 24
Finished Aug 07 04:55:45 PM PDT 24
Peak memory 211376 kb
Host smart-4d502f1a-4a8a-4773-9857-23c49f12783d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760028525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2760028525
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4052774550
Short name T333
Test name
Test status
Simulation time 687857406 ps
CPU time 7.73 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 211876 kb
Host smart-222b89d1-8b63-4914-8768-5cf49281b6e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052774550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4052774550
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1538406604
Short name T345
Test name
Test status
Simulation time 338739161 ps
CPU time 12.35 seconds
Started Aug 07 04:55:29 PM PDT 24
Finished Aug 07 04:55:42 PM PDT 24
Peak memory 218000 kb
Host smart-cf9c4a38-b72c-4fa4-8a04-dd1a69180e60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538406604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1538406604
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2819375770
Short name T118
Test name
Test status
Simulation time 710307341 ps
CPU time 82.73 seconds
Started Aug 07 04:55:18 PM PDT 24
Finished Aug 07 04:56:41 PM PDT 24
Peak memory 219400 kb
Host smart-30de7898-578e-431f-b6e0-76ba37e96cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819375770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2819375770
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2526370536
Short name T338
Test name
Test status
Simulation time 181749468 ps
CPU time 9 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 04:55:41 PM PDT 24
Peak memory 216112 kb
Host smart-abf22266-63e2-4f97-92c4-17f625b3dbf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526370536 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2526370536
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2526184322
Short name T340
Test name
Test status
Simulation time 333099090 ps
CPU time 7.88 seconds
Started Aug 07 04:55:37 PM PDT 24
Finished Aug 07 04:55:45 PM PDT 24
Peak memory 211384 kb
Host smart-d119bc7e-ef04-40c1-9286-26307fb092ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526184322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2526184322
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1531519942
Short name T350
Test name
Test status
Simulation time 2760787731 ps
CPU time 38.84 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:44 PM PDT 24
Peak memory 214400 kb
Host smart-6422ad70-abc3-44c3-b057-969c5b4678f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531519942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1531519942
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.109509459
Short name T67
Test name
Test status
Simulation time 175635686 ps
CPU time 7.95 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 04:55:34 PM PDT 24
Peak memory 211892 kb
Host smart-0919520d-35d2-4205-99d5-a2ea493c7caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109509459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.109509459
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1237042024
Short name T320
Test name
Test status
Simulation time 614735101 ps
CPU time 11.23 seconds
Started Aug 07 04:55:43 PM PDT 24
Finished Aug 07 04:55:55 PM PDT 24
Peak memory 217932 kb
Host smart-9bbded85-4f8a-4ba5-b9a0-c15f1e4bced1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237042024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1237042024
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.832332315
Short name T105
Test name
Test status
Simulation time 3261538810 ps
CPU time 80.02 seconds
Started Aug 07 04:55:40 PM PDT 24
Finished Aug 07 04:57:00 PM PDT 24
Peak memory 214424 kb
Host smart-3369b572-d3de-4f38-b823-1528a18025e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832332315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.832332315
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.164488582
Short name T382
Test name
Test status
Simulation time 179654179 ps
CPU time 8.82 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:13 PM PDT 24
Peak memory 217584 kb
Host smart-bc9590fc-97f1-40fb-a0f5-af640052adc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164488582 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.164488582
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2872180968
Short name T343
Test name
Test status
Simulation time 1124213059 ps
CPU time 9.53 seconds
Started Aug 07 04:55:36 PM PDT 24
Finished Aug 07 04:55:45 PM PDT 24
Peak memory 211552 kb
Host smart-9d92561c-0576-4658-b365-b787b853457f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872180968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2872180968
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2356791567
Short name T92
Test name
Test status
Simulation time 253253085 ps
CPU time 13.2 seconds
Started Aug 07 04:55:30 PM PDT 24
Finished Aug 07 04:55:44 PM PDT 24
Peak memory 213088 kb
Host smart-844d4472-5e27-40be-872f-3cce4d0df379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356791567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2356791567
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3493019833
Short name T390
Test name
Test status
Simulation time 1029555963 ps
CPU time 12.34 seconds
Started Aug 07 04:55:29 PM PDT 24
Finished Aug 07 04:55:42 PM PDT 24
Peak memory 218832 kb
Host smart-b477406c-d1ca-477c-a108-325e193bf819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493019833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3493019833
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1198954032
Short name T107
Test name
Test status
Simulation time 637414357 ps
CPU time 82.31 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:56:47 PM PDT 24
Peak memory 214444 kb
Host smart-954a7c1d-4722-4b90-80e1-fa15d252eb16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198954032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1198954032
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2563078758
Short name T359
Test name
Test status
Simulation time 374590670 ps
CPU time 10.64 seconds
Started Aug 07 04:55:43 PM PDT 24
Finished Aug 07 04:55:54 PM PDT 24
Peak memory 217844 kb
Host smart-3709419d-5a39-4c76-b510-5f404331730d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563078758 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2563078758
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.641089845
Short name T352
Test name
Test status
Simulation time 340506229 ps
CPU time 8.09 seconds
Started Aug 07 04:55:37 PM PDT 24
Finished Aug 07 04:55:45 PM PDT 24
Peak memory 211956 kb
Host smart-fe9c63da-3400-484a-8c63-7730dd4cd18c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641089845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.641089845
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.988269406
Short name T397
Test name
Test status
Simulation time 320778583 ps
CPU time 11.66 seconds
Started Aug 07 04:55:44 PM PDT 24
Finished Aug 07 04:55:56 PM PDT 24
Peak memory 217844 kb
Host smart-5bbf69e6-14ad-4694-a2a1-fd4bdedd10aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988269406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.988269406
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1660859184
Short name T72
Test name
Test status
Simulation time 1773229811 ps
CPU time 9.93 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 211204 kb
Host smart-ed72f54c-df28-410a-b527-33beebc815d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660859184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1660859184
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3229895318
Short name T95
Test name
Test status
Simulation time 1017450893 ps
CPU time 14.58 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:16 PM PDT 24
Peak memory 211164 kb
Host smart-18257d96-f9ed-447c-b5c8-f2be9e5b78d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229895318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3229895318
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4280916140
Short name T364
Test name
Test status
Simulation time 351756268 ps
CPU time 11.86 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 212160 kb
Host smart-a58e5675-b60d-439f-a0ec-f4542e3871ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280916140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4280916140
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1880738508
Short name T354
Test name
Test status
Simulation time 2609805367 ps
CPU time 9.04 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:55:07 PM PDT 24
Peak memory 217396 kb
Host smart-effd2cc5-7d52-411e-b7ec-b32d86eb73f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880738508 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1880738508
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3413469592
Short name T64
Test name
Test status
Simulation time 1125151256 ps
CPU time 9.87 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:55:00 PM PDT 24
Peak memory 211588 kb
Host smart-e342e1d5-e903-4e47-8b1c-89e9ec16c8de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413469592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3413469592
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2611776282
Short name T387
Test name
Test status
Simulation time 174612509 ps
CPU time 8.13 seconds
Started Aug 07 04:54:57 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 211112 kb
Host smart-60d945bf-29d7-4ec2-90eb-83c900367aca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611776282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2611776282
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.118048498
Short name T383
Test name
Test status
Simulation time 1030667892 ps
CPU time 8.02 seconds
Started Aug 07 04:54:54 PM PDT 24
Finished Aug 07 04:55:03 PM PDT 24
Peak memory 211136 kb
Host smart-d6e2ea17-6d92-49ff-a9ce-6e87c44eb802
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118048498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
118048498
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.858044384
Short name T91
Test name
Test status
Simulation time 1716900823 ps
CPU time 11.89 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 213156 kb
Host smart-fc9dc217-2e3d-4dc2-abc5-80ae3fbec22a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858044384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.858044384
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3671118722
Short name T375
Test name
Test status
Simulation time 167511427 ps
CPU time 11 seconds
Started Aug 07 04:54:54 PM PDT 24
Finished Aug 07 04:55:05 PM PDT 24
Peak memory 217784 kb
Host smart-c2fba065-f76e-4aac-9c9c-cb43483126ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671118722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3671118722
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3850176851
Short name T109
Test name
Test status
Simulation time 641403313 ps
CPU time 81.71 seconds
Started Aug 07 04:55:00 PM PDT 24
Finished Aug 07 04:56:22 PM PDT 24
Peak memory 214328 kb
Host smart-1942bdd2-2611-4b32-b965-cac2126625c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850176851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3850176851
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3949392498
Short name T385
Test name
Test status
Simulation time 174709656 ps
CPU time 8.36 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:55:04 PM PDT 24
Peak memory 211180 kb
Host smart-25a6b423-58df-4fcc-b606-237017760a6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949392498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3949392498
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.324427622
Short name T337
Test name
Test status
Simulation time 1035505267 ps
CPU time 10.21 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:55:01 PM PDT 24
Peak memory 211164 kb
Host smart-7d339770-fb17-4912-845b-62d6c7ac6910
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324427622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.324427622
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2741497404
Short name T83
Test name
Test status
Simulation time 704099429 ps
CPU time 14.96 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:55:13 PM PDT 24
Peak memory 212724 kb
Host smart-159f3dac-de20-4668-b989-2ce9550ee2c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741497404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2741497404
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2172515388
Short name T362
Test name
Test status
Simulation time 1041321590 ps
CPU time 11.13 seconds
Started Aug 07 04:54:44 PM PDT 24
Finished Aug 07 04:54:56 PM PDT 24
Peak memory 217876 kb
Host smart-7f908b7f-2632-496e-bac1-d0d71e5dd31e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172515388 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2172515388
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2508655938
Short name T349
Test name
Test status
Simulation time 260217398 ps
CPU time 10.02 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 211184 kb
Host smart-de7adaed-4ff5-4660-90b9-5531561b4a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508655938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2508655938
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3852533435
Short name T319
Test name
Test status
Simulation time 167792349 ps
CPU time 8.21 seconds
Started Aug 07 04:54:49 PM PDT 24
Finished Aug 07 04:55:03 PM PDT 24
Peak memory 211092 kb
Host smart-4244424b-9c60-452c-87ce-8aa303838f6b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852533435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3852533435
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4152663591
Short name T329
Test name
Test status
Simulation time 497791502 ps
CPU time 9.9 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 211116 kb
Host smart-cef87fc3-996e-44dd-b52b-45e40267b36d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152663591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4152663591
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2111440360
Short name T357
Test name
Test status
Simulation time 1032072959 ps
CPU time 14.14 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 213112 kb
Host smart-ae8515fc-54b1-4a68-8242-630256244003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111440360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2111440360
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.793628312
Short name T405
Test name
Test status
Simulation time 258553376 ps
CPU time 12.74 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 219100 kb
Host smart-1ed22827-be5a-4e40-b3fe-7d2ab3f125b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793628312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.793628312
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1046735492
Short name T321
Test name
Test status
Simulation time 378922065 ps
CPU time 8.4 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 211192 kb
Host smart-05d70674-8ef5-43e5-a70d-894e75f675d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046735492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1046735492
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2989786020
Short name T80
Test name
Test status
Simulation time 1787603224 ps
CPU time 16.83 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:19 PM PDT 24
Peak memory 212720 kb
Host smart-69a2f5a6-386f-4cdb-a563-ac0538da914b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989786020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2989786020
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1665805362
Short name T323
Test name
Test status
Simulation time 845528954 ps
CPU time 10.91 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 218064 kb
Host smart-ca98923e-004e-4d89-be4c-350d6104686c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665805362 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1665805362
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3996270376
Short name T360
Test name
Test status
Simulation time 1029284773 ps
CPU time 9.77 seconds
Started Aug 07 04:55:11 PM PDT 24
Finished Aug 07 04:55:21 PM PDT 24
Peak memory 211332 kb
Host smart-e75fe93a-c8f3-42e4-a380-850816573091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996270376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3996270376
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1095575612
Short name T346
Test name
Test status
Simulation time 1000977783 ps
CPU time 14.62 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:19 PM PDT 24
Peak memory 211132 kb
Host smart-02b0d1dc-e34f-4ddb-b741-9b79db6aa9ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095575612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1095575612
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.348597941
Short name T355
Test name
Test status
Simulation time 1037695378 ps
CPU time 9.85 seconds
Started Aug 07 04:54:45 PM PDT 24
Finished Aug 07 04:55:01 PM PDT 24
Peak memory 211172 kb
Host smart-4fd32eae-3e59-4682-9a1f-3d727f22e549
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348597941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
348597941
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.900751126
Short name T69
Test name
Test status
Simulation time 172527899 ps
CPU time 8.15 seconds
Started Aug 07 04:55:07 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 211856 kb
Host smart-09f57d84-e346-4257-8bb7-447eda5a3c62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900751126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.900751126
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2246930673
Short name T341
Test name
Test status
Simulation time 171077728 ps
CPU time 12.85 seconds
Started Aug 07 04:55:39 PM PDT 24
Finished Aug 07 04:55:52 PM PDT 24
Peak memory 218220 kb
Host smart-fcf85ca0-c712-4626-88d4-10b54598f390
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246930673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2246930673
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1730936562
Short name T406
Test name
Test status
Simulation time 545576070 ps
CPU time 10.17 seconds
Started Aug 07 04:55:19 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 217128 kb
Host smart-7d91e723-9f32-4b15-8d4a-0003fcf4f93d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730936562 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1730936562
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.846166379
Short name T82
Test name
Test status
Simulation time 517662555 ps
CPU time 8.28 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 211384 kb
Host smart-5e47a932-e62d-4489-af8c-9cc7808e94ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846166379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.846166379
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.116239508
Short name T400
Test name
Test status
Simulation time 1767045277 ps
CPU time 9.82 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:09 PM PDT 24
Peak memory 212028 kb
Host smart-9d182805-82e4-4837-89b6-9b918cf6a48e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116239508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.116239508
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4097983112
Short name T330
Test name
Test status
Simulation time 346733867 ps
CPU time 12.47 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 219260 kb
Host smart-a7a42963-d659-48b9-a6e5-66bd2d8879e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097983112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4097983112
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2830505438
Short name T60
Test name
Test status
Simulation time 366094385 ps
CPU time 159.33 seconds
Started Aug 07 04:54:52 PM PDT 24
Finished Aug 07 04:57:31 PM PDT 24
Peak memory 214736 kb
Host smart-76f7a937-a7dc-46c4-8a41-b7261625ada4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830505438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2830505438
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.155307793
Short name T356
Test name
Test status
Simulation time 823116437 ps
CPU time 8.72 seconds
Started Aug 07 04:55:07 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 216728 kb
Host smart-8e0f8675-0a5f-4bdf-a878-2784e63d2d4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155307793 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.155307793
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3793346204
Short name T96
Test name
Test status
Simulation time 242357573 ps
CPU time 8.18 seconds
Started Aug 07 04:55:16 PM PDT 24
Finished Aug 07 04:55:24 PM PDT 24
Peak memory 211816 kb
Host smart-4c01dcff-0ca4-4796-b788-d47a9f28360d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793346204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3793346204
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1000887394
Short name T372
Test name
Test status
Simulation time 511349262 ps
CPU time 9.88 seconds
Started Aug 07 04:55:11 PM PDT 24
Finished Aug 07 04:55:21 PM PDT 24
Peak memory 211780 kb
Host smart-9c5d43ac-117c-4ce5-858f-6f3c803d44d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000887394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1000887394
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4184320300
Short name T331
Test name
Test status
Simulation time 4927801530 ps
CPU time 13.17 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:17 PM PDT 24
Peak memory 218392 kb
Host smart-f09fa0b6-e9bf-41c5-ab0e-063b15aa1eed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184320300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4184320300
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1795047953
Short name T111
Test name
Test status
Simulation time 340873953 ps
CPU time 84.54 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:56:28 PM PDT 24
Peak memory 219448 kb
Host smart-28ee28ab-efe1-4ac6-9dcf-d882155dadf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795047953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1795047953
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.546551370
Short name T365
Test name
Test status
Simulation time 414290208 ps
CPU time 8.3 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 214476 kb
Host smart-84599634-9431-4642-9236-26a2042a410b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546551370 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.546551370
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3831750485
Short name T380
Test name
Test status
Simulation time 263018182 ps
CPU time 9.88 seconds
Started Aug 07 04:55:13 PM PDT 24
Finished Aug 07 04:55:23 PM PDT 24
Peak memory 211744 kb
Host smart-8bd93403-af1b-4057-aeb6-b97667ae50d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831750485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3831750485
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1129625498
Short name T61
Test name
Test status
Simulation time 603077891 ps
CPU time 11.47 seconds
Started Aug 07 04:55:13 PM PDT 24
Finished Aug 07 04:55:25 PM PDT 24
Peak memory 213000 kb
Host smart-e7984dc5-2745-400e-9d5f-b4318c01a2e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129625498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1129625498
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1865129263
Short name T353
Test name
Test status
Simulation time 249696001 ps
CPU time 13.77 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:22 PM PDT 24
Peak memory 219360 kb
Host smart-3c24be33-fbd8-401d-898e-60334b1e1eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865129263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1865129263
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2025121781
Short name T108
Test name
Test status
Simulation time 614408802 ps
CPU time 82.1 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:56:24 PM PDT 24
Peak memory 214356 kb
Host smart-c7a22f0a-1274-4cff-b8dd-83d1821b4bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025121781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2025121781
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.742416360
Short name T348
Test name
Test status
Simulation time 273226174 ps
CPU time 10.21 seconds
Started Aug 07 04:54:57 PM PDT 24
Finished Aug 07 04:55:08 PM PDT 24
Peak memory 219436 kb
Host smart-a166e61a-b335-4450-8eb1-6f538e148769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742416360 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.742416360
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3139704934
Short name T332
Test name
Test status
Simulation time 986437319 ps
CPU time 14.8 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:55:13 PM PDT 24
Peak memory 211580 kb
Host smart-0afd3ef3-e676-4836-99f6-788094da4607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139704934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3139704934
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1937835583
Short name T379
Test name
Test status
Simulation time 722891949 ps
CPU time 37.36 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 04:55:43 PM PDT 24
Peak memory 214500 kb
Host smart-412f7b46-08d0-4f59-9f8d-42bb97b2e9d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937835583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1937835583
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1260456459
Short name T66
Test name
Test status
Simulation time 261233677 ps
CPU time 9.85 seconds
Started Aug 07 04:55:30 PM PDT 24
Finished Aug 07 04:55:40 PM PDT 24
Peak memory 211992 kb
Host smart-21457550-7562-4685-ba56-87ac8fec19d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260456459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1260456459
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3192000994
Short name T351
Test name
Test status
Simulation time 253775944 ps
CPU time 14.51 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 218160 kb
Host smart-e48dc87c-a7e9-4607-91c3-0c313eb79bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192000994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3192000994
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1429052246
Short name T106
Test name
Test status
Simulation time 323202372 ps
CPU time 81.34 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 04:56:43 PM PDT 24
Peak memory 213212 kb
Host smart-821cab06-0c28-4630-8081-af5125a64055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429052246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1429052246
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2806751445
Short name T376
Test name
Test status
Simulation time 2010850275 ps
CPU time 14.38 seconds
Started Aug 07 04:55:19 PM PDT 24
Finished Aug 07 04:55:33 PM PDT 24
Peak memory 213800 kb
Host smart-cde17e41-aee1-485d-be8d-20c297ef983b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806751445 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2806751445
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.183447057
Short name T70
Test name
Test status
Simulation time 663949562 ps
CPU time 7.89 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 211400 kb
Host smart-6c89d961-7a28-4620-8685-4f73930bea42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183447057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.183447057
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3029512071
Short name T68
Test name
Test status
Simulation time 254333300 ps
CPU time 9.56 seconds
Started Aug 07 04:55:28 PM PDT 24
Finished Aug 07 04:55:38 PM PDT 24
Peak memory 211908 kb
Host smart-acd59965-5017-417a-81c6-e15865429470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029512071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3029512071
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3755502657
Short name T326
Test name
Test status
Simulation time 751769487 ps
CPU time 12.28 seconds
Started Aug 07 04:55:29 PM PDT 24
Finished Aug 07 04:55:41 PM PDT 24
Peak memory 217988 kb
Host smart-7392ea39-a5c6-4d82-bdf9-44b466c8bd04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755502657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3755502657
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1424613175
Short name T113
Test name
Test status
Simulation time 456484148 ps
CPU time 83.77 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:56:27 PM PDT 24
Peak memory 219408 kb
Host smart-c7de4293-a029-4b25-9992-25c17df132bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424613175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1424613175
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3283270931
Short name T242
Test name
Test status
Simulation time 689356257 ps
CPU time 8.27 seconds
Started Aug 07 04:54:39 PM PDT 24
Finished Aug 07 04:54:48 PM PDT 24
Peak memory 219140 kb
Host smart-85c2dd80-56d5-4e39-9a22-5d74591b4481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283270931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3283270931
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3189845172
Short name T2
Test name
Test status
Simulation time 22769933335 ps
CPU time 303.53 seconds
Started Aug 07 04:54:48 PM PDT 24
Finished Aug 07 04:59:52 PM PDT 24
Peak memory 229840 kb
Host smart-e43f3088-9dd9-40e6-a8df-d5d849cadef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189845172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3189845172
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3710402750
Short name T251
Test name
Test status
Simulation time 349825457 ps
CPU time 19.47 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 219964 kb
Host smart-c6ad90d5-1f56-4637-b2e7-cdd9e69662ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710402750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3710402750
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2597265883
Short name T300
Test name
Test status
Simulation time 356943650 ps
CPU time 10.8 seconds
Started Aug 07 04:54:40 PM PDT 24
Finished Aug 07 04:54:51 PM PDT 24
Peak memory 220040 kb
Host smart-a739ab32-8dc5-445a-8962-44ee9e7500a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597265883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2597265883
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1101837606
Short name T162
Test name
Test status
Simulation time 272024658 ps
CPU time 12.02 seconds
Started Aug 07 04:54:55 PM PDT 24
Finished Aug 07 04:55:07 PM PDT 24
Peak memory 219932 kb
Host smart-8862dde9-adb0-4cb7-8a8e-bcac72a1e7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101837606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1101837606
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3789000737
Short name T246
Test name
Test status
Simulation time 578468940 ps
CPU time 21.26 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 219924 kb
Host smart-97742e2a-e9ba-4ef6-9b66-ca58b380a8f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789000737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3789000737
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4293523866
Short name T6
Test name
Test status
Simulation time 916781648 ps
CPU time 9.99 seconds
Started Aug 07 04:54:57 PM PDT 24
Finished Aug 07 04:55:07 PM PDT 24
Peak memory 219000 kb
Host smart-22ae267e-80b0-479b-ba62-2158cc92ff26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293523866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4293523866
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1216983689
Short name T194
Test name
Test status
Simulation time 14969297848 ps
CPU time 282.38 seconds
Started Aug 07 04:54:45 PM PDT 24
Finished Aug 07 04:59:28 PM PDT 24
Peak memory 243040 kb
Host smart-730a0abf-36bc-4a7e-a102-2894360c85eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216983689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1216983689
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.528547977
Short name T195
Test name
Test status
Simulation time 692797665 ps
CPU time 19.01 seconds
Started Aug 07 04:55:07 PM PDT 24
Finished Aug 07 04:55:27 PM PDT 24
Peak memory 219956 kb
Host smart-6f5e85a0-5ba2-477e-aeb8-3e4aee073ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528547977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.528547977
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2511123378
Short name T149
Test name
Test status
Simulation time 690009683 ps
CPU time 10.3 seconds
Started Aug 07 04:54:55 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 219980 kb
Host smart-fbbcce6e-e70b-4db4-a3ac-673d9e81d795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511123378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2511123378
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3898716185
Short name T25
Test name
Test status
Simulation time 325062779 ps
CPU time 119.99 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:56:51 PM PDT 24
Peak memory 236080 kb
Host smart-2e635ca2-aeeb-40e1-a985-46412b29190e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898716185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3898716185
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.246257409
Short name T18
Test name
Test status
Simulation time 2877095015 ps
CPU time 12.16 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:14 PM PDT 24
Peak memory 220088 kb
Host smart-ea09a93d-8daf-40b1-80db-29e4f0b58d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246257409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.246257409
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3762929347
Short name T270
Test name
Test status
Simulation time 2111631484 ps
CPU time 32.11 seconds
Started Aug 07 04:54:51 PM PDT 24
Finished Aug 07 04:55:23 PM PDT 24
Peak memory 219924 kb
Host smart-427e2844-bc50-4a8d-bf5f-b1b9ebfe3df8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762929347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3762929347
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3217535350
Short name T301
Test name
Test status
Simulation time 91888865566 ps
CPU time 776.24 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 05:07:54 PM PDT 24
Peak memory 236316 kb
Host smart-28b842f8-f05a-4dcf-bd5c-c7d15d2409e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217535350 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3217535350
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4056664480
Short name T254
Test name
Test status
Simulation time 517398186 ps
CPU time 10.03 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:55:08 PM PDT 24
Peak memory 219068 kb
Host smart-455782c5-1130-4a9f-b7c8-a9e46fda5842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056664480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4056664480
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1990029232
Short name T8
Test name
Test status
Simulation time 3185483560 ps
CPU time 146.78 seconds
Started Aug 07 04:54:52 PM PDT 24
Finished Aug 07 04:57:19 PM PDT 24
Peak memory 220292 kb
Host smart-4832a370-75dd-4595-8c46-98f0d0321b21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990029232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1990029232
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2517318346
Short name T84
Test name
Test status
Simulation time 506103407 ps
CPU time 22.51 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 219912 kb
Host smart-1dd94245-7aa3-4989-9c9d-044f8786ec8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517318346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2517318346
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3256308779
Short name T241
Test name
Test status
Simulation time 273382526 ps
CPU time 12.31 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 220004 kb
Host smart-c260c557-9554-498d-8ca1-2aaf14fa7603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256308779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3256308779
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2211422031
Short name T75
Test name
Test status
Simulation time 804552144 ps
CPU time 41.8 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:44 PM PDT 24
Peak memory 219916 kb
Host smart-c781d4fb-d664-4faf-aa13-0b5602e8fd23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211422031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2211422031
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2740682497
Short name T28
Test name
Test status
Simulation time 1079815251 ps
CPU time 10.09 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 219160 kb
Host smart-4e4554dd-b899-4d8f-9335-e1289cfcace9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740682497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2740682497
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3278245084
Short name T46
Test name
Test status
Simulation time 4144549577 ps
CPU time 176.06 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 230536 kb
Host smart-a97d7d70-3596-4621-957e-9c49b51a9eb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278245084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3278245084
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2313733420
Short name T49
Test name
Test status
Simulation time 518591889 ps
CPU time 22.91 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:31 PM PDT 24
Peak memory 220040 kb
Host smart-0ce27498-0128-4a5c-8433-b0bbdaf9873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313733420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2313733420
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3041969269
Short name T19
Test name
Test status
Simulation time 794181477 ps
CPU time 35 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:34 PM PDT 24
Peak memory 219900 kb
Host smart-0530eed6-bfb5-4be3-b5a3-6a42cb2913bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041969269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3041969269
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.402044334
Short name T53
Test name
Test status
Simulation time 20085177205 ps
CPU time 814.11 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 05:08:55 PM PDT 24
Peak memory 232460 kb
Host smart-9fd675cb-328e-451d-b9cf-555b916f1106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402044334 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.402044334
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1866421034
Short name T288
Test name
Test status
Simulation time 749985117 ps
CPU time 8.23 seconds
Started Aug 07 04:55:16 PM PDT 24
Finished Aug 07 04:55:24 PM PDT 24
Peak memory 219016 kb
Host smart-f8d86e3f-e595-4ba8-b3ca-e7ef82771516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866421034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1866421034
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.904056108
Short name T171
Test name
Test status
Simulation time 24806226965 ps
CPU time 396.09 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 05:01:38 PM PDT 24
Peak memory 239600 kb
Host smart-28ead458-a346-42a2-a3c2-73f46033da6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904056108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.904056108
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1755131477
Short name T304
Test name
Test status
Simulation time 1897440856 ps
CPU time 22.1 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:30 PM PDT 24
Peak memory 220016 kb
Host smart-d09b906e-d0e3-4ec2-b643-e5ea686990b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755131477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1755131477
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2514690416
Short name T184
Test name
Test status
Simulation time 340176722 ps
CPU time 12.08 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 219876 kb
Host smart-87628707-38f0-4495-81b8-615aaf34f6cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514690416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2514690416
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3973814383
Short name T238
Test name
Test status
Simulation time 1491214962 ps
CPU time 38.37 seconds
Started Aug 07 04:55:42 PM PDT 24
Finished Aug 07 04:56:20 PM PDT 24
Peak memory 220000 kb
Host smart-38b8e614-6e91-4725-84d4-c769e8c77319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973814383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3973814383
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3312399891
Short name T236
Test name
Test status
Simulation time 496929997 ps
CPU time 9.79 seconds
Started Aug 07 04:55:19 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 219020 kb
Host smart-462d76a8-2196-4d86-9d38-0cf948520206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312399891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3312399891
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.226208485
Short name T272
Test name
Test status
Simulation time 9933516408 ps
CPU time 186.03 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:58:11 PM PDT 24
Peak memory 240948 kb
Host smart-88a5f027-1d19-4f6c-aa29-8a5ee000ef92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226208485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.226208485
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3273810242
Short name T124
Test name
Test status
Simulation time 676783584 ps
CPU time 19.64 seconds
Started Aug 07 04:54:55 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 219344 kb
Host smart-4bc36bf0-beee-4a9c-8213-74f34ea89eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273810242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3273810242
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.991486617
Short name T311
Test name
Test status
Simulation time 536438184 ps
CPU time 11.8 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:17 PM PDT 24
Peak memory 220064 kb
Host smart-49ba23a3-222c-4966-8807-d8bf5d841915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991486617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.991486617
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1217268871
Short name T227
Test name
Test status
Simulation time 504617778 ps
CPU time 23.76 seconds
Started Aug 07 04:55:11 PM PDT 24
Finished Aug 07 04:55:35 PM PDT 24
Peak memory 219932 kb
Host smart-21727016-cfa2-4927-b115-a8e4800f5acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217268871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1217268871
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.4237277991
Short name T87
Test name
Test status
Simulation time 692048491 ps
CPU time 8.02 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 04:55:34 PM PDT 24
Peak memory 219076 kb
Host smart-fe124011-b1a2-404a-b79b-ae6878b3775a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237277991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4237277991
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3418419939
Short name T154
Test name
Test status
Simulation time 6198804649 ps
CPU time 303.3 seconds
Started Aug 07 04:55:16 PM PDT 24
Finished Aug 07 05:00:20 PM PDT 24
Peak memory 235624 kb
Host smart-f2ed9072-2758-4bba-b9a2-17341d0076be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418419939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3418419939
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1852278430
Short name T122
Test name
Test status
Simulation time 346415437 ps
CPU time 19.56 seconds
Started Aug 07 04:55:15 PM PDT 24
Finished Aug 07 04:55:34 PM PDT 24
Peak memory 219920 kb
Host smart-3ba57843-d9d2-46a7-a733-dcbf42180d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852278430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1852278430
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.611550775
Short name T278
Test name
Test status
Simulation time 728429707 ps
CPU time 10.46 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:55:08 PM PDT 24
Peak memory 219944 kb
Host smart-5cad52bf-0cc5-428a-b8fe-67893a768a08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611550775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.611550775
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3302149913
Short name T85
Test name
Test status
Simulation time 4322092949 ps
CPU time 49.61 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:54 PM PDT 24
Peak memory 220052 kb
Host smart-22b779d4-4c84-40e4-b2d9-dd13d689e189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302149913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3302149913
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.4211703952
Short name T245
Test name
Test status
Simulation time 29608061215 ps
CPU time 8032.83 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 07:09:20 PM PDT 24
Peak memory 232144 kb
Host smart-e0d6081f-5914-42ab-8bcb-629c9b303832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211703952 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.4211703952
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2304756042
Short name T286
Test name
Test status
Simulation time 339266589 ps
CPU time 8.17 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 219068 kb
Host smart-b1cbed88-e4c8-45f0-92ce-2fbc0e7ea968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304756042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2304756042
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1147138394
Short name T280
Test name
Test status
Simulation time 5071783632 ps
CPU time 277.9 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:59:41 PM PDT 24
Peak memory 245488 kb
Host smart-bd4b123f-3606-476f-9da4-beb82ed90a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147138394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1147138394
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1195464525
Short name T253
Test name
Test status
Simulation time 1014383495 ps
CPU time 22.7 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:28 PM PDT 24
Peak memory 219984 kb
Host smart-a0d39ffb-cc41-4597-9246-bdae81776211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195464525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1195464525
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1074801176
Short name T226
Test name
Test status
Simulation time 1349950303 ps
CPU time 11.7 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:16 PM PDT 24
Peak memory 219988 kb
Host smart-d76e9059-2d4a-447e-8b24-b0f385cb3a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074801176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1074801176
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.730841903
Short name T205
Test name
Test status
Simulation time 1259690737 ps
CPU time 18.79 seconds
Started Aug 07 04:55:20 PM PDT 24
Finished Aug 07 04:55:39 PM PDT 24
Peak memory 219920 kb
Host smart-9664b0fd-f790-482e-8d44-86cf275ac39f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730841903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.730841903
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1599872306
Short name T234
Test name
Test status
Simulation time 1379132037 ps
CPU time 7.97 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:09 PM PDT 24
Peak memory 218960 kb
Host smart-06f4419b-910f-4bb2-9950-236ed59c5501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599872306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1599872306
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1564572057
Short name T174
Test name
Test status
Simulation time 11792649983 ps
CPU time 342.75 seconds
Started Aug 07 04:55:32 PM PDT 24
Finished Aug 07 05:01:15 PM PDT 24
Peak memory 241104 kb
Host smart-b3e6e715-f214-4a55-8aa4-c22d5e496972
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564572057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1564572057
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.487984355
Short name T22
Test name
Test status
Simulation time 1321311758 ps
CPU time 19.99 seconds
Started Aug 07 04:55:14 PM PDT 24
Finished Aug 07 04:55:34 PM PDT 24
Peak memory 220072 kb
Host smart-a98a4abd-4ca6-47bb-b883-0249acedb170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487984355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.487984355
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1372464904
Short name T248
Test name
Test status
Simulation time 258970021 ps
CPU time 12.12 seconds
Started Aug 07 04:55:28 PM PDT 24
Finished Aug 07 04:55:40 PM PDT 24
Peak memory 219960 kb
Host smart-6d73476c-69b1-43be-8938-e66cf9742aee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372464904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1372464904
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4095813475
Short name T73
Test name
Test status
Simulation time 560442535 ps
CPU time 35.84 seconds
Started Aug 07 04:55:39 PM PDT 24
Finished Aug 07 04:56:15 PM PDT 24
Peak memory 220044 kb
Host smart-5f018eaf-0eed-41c3-ac80-37146ff9e73f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095813475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4095813475
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3074880271
Short name T247
Test name
Test status
Simulation time 167415164 ps
CPU time 8.27 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 219076 kb
Host smart-865fe0ff-889d-4cb7-8f04-c9dabdf58789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074880271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3074880271
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.167317858
Short name T132
Test name
Test status
Simulation time 5664004178 ps
CPU time 278.53 seconds
Started Aug 07 04:55:19 PM PDT 24
Finished Aug 07 04:59:58 PM PDT 24
Peak memory 220244 kb
Host smart-8acd6293-8578-473c-91c1-a001a652916c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167317858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.167317858
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3541677669
Short name T269
Test name
Test status
Simulation time 5518225823 ps
CPU time 23.04 seconds
Started Aug 07 04:54:54 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 220092 kb
Host smart-01fd57b7-7500-4f20-a57c-e296a927c69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541677669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3541677669
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3860291662
Short name T197
Test name
Test status
Simulation time 649898798 ps
CPU time 10.41 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:14 PM PDT 24
Peak memory 219948 kb
Host smart-2ad205b7-f026-4dbc-8573-7f007edc5340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860291662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3860291662
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3460549378
Short name T318
Test name
Test status
Simulation time 547193671 ps
CPU time 30.3 seconds
Started Aug 07 04:55:12 PM PDT 24
Finished Aug 07 04:55:43 PM PDT 24
Peak memory 219952 kb
Host smart-f61fc0c6-a918-4445-b19a-778e05535b1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460549378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3460549378
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3383010200
Short name T148
Test name
Test status
Simulation time 1841089321 ps
CPU time 8.43 seconds
Started Aug 07 04:55:12 PM PDT 24
Finished Aug 07 04:55:21 PM PDT 24
Peak memory 219008 kb
Host smart-a0ebedd0-3c93-45a8-976a-79f7107c5594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383010200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3383010200
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2577958681
Short name T217
Test name
Test status
Simulation time 16370401737 ps
CPU time 259.19 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 240572 kb
Host smart-2cf23630-189c-4780-85bd-c9a424f61ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577958681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2577958681
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2769350174
Short name T267
Test name
Test status
Simulation time 6201813143 ps
CPU time 22.94 seconds
Started Aug 07 04:55:14 PM PDT 24
Finished Aug 07 04:55:37 PM PDT 24
Peak memory 220184 kb
Host smart-1f88ad1a-4998-45d6-abf3-6e2f256e8282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769350174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2769350174
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.540223636
Short name T35
Test name
Test status
Simulation time 1042962527 ps
CPU time 12.28 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 219984 kb
Host smart-f3bc3f0c-c552-45f7-8bee-21bc7878c262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540223636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.540223636
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3401582518
Short name T77
Test name
Test status
Simulation time 408129163 ps
CPU time 14.57 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:55:13 PM PDT 24
Peak memory 219924 kb
Host smart-8f780540-9c52-42c9-ab28-584e246206f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401582518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3401582518
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2181129158
Short name T42
Test name
Test status
Simulation time 1460348583 ps
CPU time 10.53 seconds
Started Aug 07 04:55:24 PM PDT 24
Finished Aug 07 04:55:34 PM PDT 24
Peak memory 219036 kb
Host smart-34be9166-3ffa-4a89-8453-755b62d340bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181129158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2181129158
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4080406282
Short name T14
Test name
Test status
Simulation time 13871106425 ps
CPU time 188.04 seconds
Started Aug 07 04:55:16 PM PDT 24
Finished Aug 07 04:58:25 PM PDT 24
Peak memory 234324 kb
Host smart-61cbf9a5-f428-4790-a148-01761ad308c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080406282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4080406282
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2676131096
Short name T203
Test name
Test status
Simulation time 953575877 ps
CPU time 22.58 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:26 PM PDT 24
Peak memory 219988 kb
Host smart-e2ece3f0-e514-4b6a-864e-d8b90a04a9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676131096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2676131096
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3333532020
Short name T225
Test name
Test status
Simulation time 184026849 ps
CPU time 10.1 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 219968 kb
Host smart-d8271031-682d-4624-94e9-7a327eeee403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333532020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3333532020
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3707972381
Short name T224
Test name
Test status
Simulation time 1108018068 ps
CPU time 12.59 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:55:21 PM PDT 24
Peak memory 219292 kb
Host smart-1184de9d-1324-420f-b907-e376c6128687
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707972381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3707972381
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.671559023
Short name T223
Test name
Test status
Simulation time 882061229 ps
CPU time 10.05 seconds
Started Aug 07 04:54:47 PM PDT 24
Finished Aug 07 04:54:58 PM PDT 24
Peak memory 219144 kb
Host smart-3484039d-603f-439d-a596-4ff91e67ed21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671559023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.671559023
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2732153056
Short name T20
Test name
Test status
Simulation time 4160049040 ps
CPU time 142.57 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:57:13 PM PDT 24
Peak memory 230412 kb
Host smart-c5a87d2c-2692-431a-b364-665f4ea24e70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732153056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2732153056
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1506904214
Short name T192
Test name
Test status
Simulation time 518844795 ps
CPU time 23.04 seconds
Started Aug 07 04:54:54 PM PDT 24
Finished Aug 07 04:55:17 PM PDT 24
Peak memory 219992 kb
Host smart-e3d8072e-3fdd-415e-b949-f5a0c3c160ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506904214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1506904214
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2246773873
Short name T89
Test name
Test status
Simulation time 19880366218 ps
CPU time 16.05 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:19 PM PDT 24
Peak memory 219988 kb
Host smart-58dfe0ab-d55b-44c7-bef4-8fed6af61736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2246773873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2246773873
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.164175635
Short name T33
Test name
Test status
Simulation time 752162827 ps
CPU time 227.43 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 234432 kb
Host smart-e843a53d-a320-462b-b33a-2ddcdfa62ff8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164175635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.164175635
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3809260845
Short name T314
Test name
Test status
Simulation time 553065866 ps
CPU time 12.33 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 220016 kb
Host smart-0c76e6f1-7b2d-4742-815c-16559396e35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809260845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3809260845
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2929231249
Short name T57
Test name
Test status
Simulation time 754225400 ps
CPU time 17.28 seconds
Started Aug 07 04:54:54 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 219708 kb
Host smart-07e036e3-3902-44c1-a66d-fc1b4801253a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929231249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2929231249
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2603803869
Short name T55
Test name
Test status
Simulation time 21966814833 ps
CPU time 5212.34 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 06:21:55 PM PDT 24
Peak memory 229832 kb
Host smart-3ebc3643-dd47-4121-a60d-00aaccc0a379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603803869 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2603803869
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3845979764
Short name T296
Test name
Test status
Simulation time 254524844 ps
CPU time 10.28 seconds
Started Aug 07 04:55:20 PM PDT 24
Finished Aug 07 04:55:30 PM PDT 24
Peak memory 219076 kb
Host smart-672c538e-508b-4113-997e-8cb667fd0eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845979764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3845979764
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.60771306
Short name T308
Test name
Test status
Simulation time 14520672005 ps
CPU time 238.41 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 244812 kb
Host smart-7df05336-bb38-474f-ba73-09286d062f83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60771306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_co
rrupt_sig_fatal_chk.60771306
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2039050742
Short name T259
Test name
Test status
Simulation time 512848032 ps
CPU time 22.47 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:24 PM PDT 24
Peak memory 219996 kb
Host smart-1597baa5-9831-4176-8830-d94c174552e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039050742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2039050742
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1497427820
Short name T98
Test name
Test status
Simulation time 1073688894 ps
CPU time 12.21 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:16 PM PDT 24
Peak memory 220044 kb
Host smart-400788da-b83d-455a-8ede-3f6044a67aa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497427820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1497427820
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4106959731
Short name T213
Test name
Test status
Simulation time 992470053 ps
CPU time 9.76 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 04:55:16 PM PDT 24
Peak memory 219856 kb
Host smart-6a628130-ff1f-4ecd-a15c-67136b725273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106959731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4106959731
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3940518051
Short name T23
Test name
Test status
Simulation time 3936121380 ps
CPU time 232.75 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 04:58:59 PM PDT 24
Peak memory 230348 kb
Host smart-dd051d09-d780-45a5-8249-577e0671ea8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940518051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3940518051
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.401389924
Short name T240
Test name
Test status
Simulation time 664150289 ps
CPU time 19.42 seconds
Started Aug 07 04:55:29 PM PDT 24
Finished Aug 07 04:55:48 PM PDT 24
Peak memory 220016 kb
Host smart-ebecc15d-011c-49c3-808a-6863bcf1ca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401389924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.401389924
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1214352823
Short name T143
Test name
Test status
Simulation time 188531241 ps
CPU time 10.64 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 220088 kb
Host smart-03fafd17-3cab-425f-bb6a-4ca59edf349e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214352823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1214352823
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3648547336
Short name T198
Test name
Test status
Simulation time 344987380 ps
CPU time 19.7 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:25 PM PDT 24
Peak memory 219872 kb
Host smart-e02fdd81-c8c4-4854-97c7-8afd522b6f4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648547336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3648547336
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4027045773
Short name T52
Test name
Test status
Simulation time 100887609352 ps
CPU time 5470.1 seconds
Started Aug 07 04:55:34 PM PDT 24
Finished Aug 07 06:26:44 PM PDT 24
Peak memory 234916 kb
Host smart-905851af-1e78-4678-96cd-67eb5c624c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027045773 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4027045773
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1669970275
Short name T292
Test name
Test status
Simulation time 718264774 ps
CPU time 8.51 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 218968 kb
Host smart-c1a7b911-d252-4ec8-95ec-ba9221d85674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669970275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1669970275
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4086811552
Short name T209
Test name
Test status
Simulation time 5792385495 ps
CPU time 314.91 seconds
Started Aug 07 04:55:32 PM PDT 24
Finished Aug 07 05:00:47 PM PDT 24
Peak memory 228804 kb
Host smart-f306f1de-9906-4336-a178-41a0e5f30d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086811552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4086811552
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.392357690
Short name T206
Test name
Test status
Simulation time 689303829 ps
CPU time 19.6 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 04:55:41 PM PDT 24
Peak memory 219936 kb
Host smart-2f3f54e7-1ccb-4b74-9935-b12b4ec25ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392357690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.392357690
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3783680340
Short name T158
Test name
Test status
Simulation time 469403925 ps
CPU time 10.23 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 219960 kb
Host smart-f0e91689-a296-4f9e-855e-468d8dbdc2f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783680340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3783680340
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3456047018
Short name T290
Test name
Test status
Simulation time 1309365897 ps
CPU time 34.17 seconds
Started Aug 07 04:55:10 PM PDT 24
Finished Aug 07 04:55:44 PM PDT 24
Peak memory 219936 kb
Host smart-44bb9b94-4256-4f08-849b-dd7adcd55f79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456047018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3456047018
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.35254313
Short name T229
Test name
Test status
Simulation time 826230342 ps
CPU time 8.3 seconds
Started Aug 07 04:55:15 PM PDT 24
Finished Aug 07 04:55:24 PM PDT 24
Peak memory 219116 kb
Host smart-5a7ed381-21e2-4fd0-af9e-27858f434db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35254313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.35254313
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.410638183
Short name T263
Test name
Test status
Simulation time 13428309829 ps
CPU time 353.4 seconds
Started Aug 07 04:55:13 PM PDT 24
Finished Aug 07 05:01:06 PM PDT 24
Peak memory 218884 kb
Host smart-e28832df-b4d8-4d62-8e02-a845655e95e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410638183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.410638183
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1703338353
Short name T298
Test name
Test status
Simulation time 340622090 ps
CPU time 19.4 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 219952 kb
Host smart-22ae8135-dab1-41c3-917c-498b72c4692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703338353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1703338353
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.985249818
Short name T237
Test name
Test status
Simulation time 261748478 ps
CPU time 12.36 seconds
Started Aug 07 04:55:16 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 220012 kb
Host smart-569db904-3e16-486e-b937-d069ede7af9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985249818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.985249818
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2354464270
Short name T128
Test name
Test status
Simulation time 389506153 ps
CPU time 20.74 seconds
Started Aug 07 04:55:18 PM PDT 24
Finished Aug 07 04:55:39 PM PDT 24
Peak memory 219916 kb
Host smart-c81549d9-8a4e-469a-a1ef-cb2654f94a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354464270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2354464270
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3826865921
Short name T315
Test name
Test status
Simulation time 251417987482 ps
CPU time 2306.64 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 05:33:35 PM PDT 24
Peak memory 244796 kb
Host smart-cdf790ae-8509-45d6-b2c1-450704738804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826865921 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3826865921
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2113186525
Short name T179
Test name
Test status
Simulation time 248639957 ps
CPU time 9.81 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:55:08 PM PDT 24
Peak memory 218948 kb
Host smart-b80976c4-becf-44cd-847c-1a3ba279e05a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113186525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2113186525
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2085470344
Short name T186
Test name
Test status
Simulation time 29873173389 ps
CPU time 300.97 seconds
Started Aug 07 04:55:11 PM PDT 24
Finished Aug 07 05:00:12 PM PDT 24
Peak memory 239764 kb
Host smart-65af0612-799b-4501-86f3-c5e9fef20c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085470344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2085470344
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2375218520
Short name T157
Test name
Test status
Simulation time 1242678968 ps
CPU time 10.21 seconds
Started Aug 07 04:55:20 PM PDT 24
Finished Aug 07 04:55:31 PM PDT 24
Peak memory 219960 kb
Host smart-a6038392-8a34-44a8-a420-482fb49747f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375218520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2375218520
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2569009861
Short name T100
Test name
Test status
Simulation time 531606276 ps
CPU time 23.68 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 219936 kb
Host smart-eabb6add-e9fd-4a3d-9688-43bdab484516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569009861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2569009861
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.532543991
Short name T151
Test name
Test status
Simulation time 257973214 ps
CPU time 10.13 seconds
Started Aug 07 04:55:22 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 218960 kb
Host smart-693f5db8-c078-4d08-b0ed-29936b7810c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532543991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.532543991
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.948497480
Short name T231
Test name
Test status
Simulation time 3001982318 ps
CPU time 161.55 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:57:45 PM PDT 24
Peak memory 220016 kb
Host smart-163983e8-2915-4d45-8c69-71ff97feb329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948497480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.948497480
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1645999720
Short name T123
Test name
Test status
Simulation time 347503055 ps
CPU time 19.31 seconds
Started Aug 07 04:55:24 PM PDT 24
Finished Aug 07 04:55:43 PM PDT 24
Peak memory 219944 kb
Host smart-857665b6-6289-4cab-aea2-ca1546590771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645999720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1645999720
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3608758366
Short name T165
Test name
Test status
Simulation time 753610678 ps
CPU time 10.45 seconds
Started Aug 07 04:55:17 PM PDT 24
Finished Aug 07 04:55:28 PM PDT 24
Peak memory 219956 kb
Host smart-3b477e9b-d8c6-4a7d-9061-955fcdd3669a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608758366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3608758366
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2224908071
Short name T297
Test name
Test status
Simulation time 313890411 ps
CPU time 31.23 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:39 PM PDT 24
Peak memory 220060 kb
Host smart-87da9fc5-8610-47b1-b714-92b8670005b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224908071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2224908071
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1654623120
Short name T220
Test name
Test status
Simulation time 4114589007 ps
CPU time 14.73 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 219060 kb
Host smart-8c17200d-a782-4dfd-b801-5cc5fc859edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654623120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1654623120
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2697214128
Short name T193
Test name
Test status
Simulation time 1353790992 ps
CPU time 121.46 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:57:26 PM PDT 24
Peak memory 241532 kb
Host smart-f6f5f657-0cba-48f7-bd33-4f53b45db89b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697214128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2697214128
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4196131239
Short name T10
Test name
Test status
Simulation time 2479490948 ps
CPU time 23.14 seconds
Started Aug 07 04:55:16 PM PDT 24
Finished Aug 07 04:55:39 PM PDT 24
Peak memory 220048 kb
Host smart-8e4648c2-eb02-49ac-a6c8-5d7e9887eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196131239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4196131239
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1716892756
Short name T38
Test name
Test status
Simulation time 1075912853 ps
CPU time 12 seconds
Started Aug 07 04:55:16 PM PDT 24
Finished Aug 07 04:55:28 PM PDT 24
Peak memory 219944 kb
Host smart-f42a1ba1-2b05-4140-8313-dc783ffdf530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1716892756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1716892756
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3551993573
Short name T257
Test name
Test status
Simulation time 1111924017 ps
CPU time 19.91 seconds
Started Aug 07 04:55:31 PM PDT 24
Finished Aug 07 04:55:51 PM PDT 24
Peak memory 220020 kb
Host smart-09991bae-b515-41a5-8646-ac834b9d7a28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551993573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3551993573
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4015299324
Short name T30
Test name
Test status
Simulation time 1035984949 ps
CPU time 9.92 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 04:55:31 PM PDT 24
Peak memory 219120 kb
Host smart-d41be2cd-bccc-4956-a6a1-e53845bf853a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015299324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4015299324
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.255340458
Short name T235
Test name
Test status
Simulation time 777103238 ps
CPU time 22.78 seconds
Started Aug 07 04:55:43 PM PDT 24
Finished Aug 07 04:56:06 PM PDT 24
Peak memory 220012 kb
Host smart-b5f55f65-b89b-439e-b5ef-8776f9cf928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255340458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.255340458
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3766107267
Short name T139
Test name
Test status
Simulation time 303120626 ps
CPU time 10.27 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 04:55:37 PM PDT 24
Peak memory 219960 kb
Host smart-d7d5d67c-f7b7-4dcb-b9ef-8e3b82e52ac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3766107267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3766107267
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.961355432
Short name T302
Test name
Test status
Simulation time 856288364 ps
CPU time 11.47 seconds
Started Aug 07 04:55:35 PM PDT 24
Finished Aug 07 04:55:47 PM PDT 24
Peak memory 219936 kb
Host smart-0918d5f3-9bc8-4f59-a42a-f216c196ccd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961355432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.961355432
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1020607929
Short name T102
Test name
Test status
Simulation time 110887650380 ps
CPU time 2099.6 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 05:30:06 PM PDT 24
Peak memory 244844 kb
Host smart-5ca305ed-d005-4268-b7c0-34aca50e864e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020607929 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1020607929
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.63344010
Short name T232
Test name
Test status
Simulation time 174221380 ps
CPU time 8.22 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 218968 kb
Host smart-f25d4748-1f14-4027-ab10-f852ad426b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63344010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.63344010
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1114496511
Short name T299
Test name
Test status
Simulation time 7170583269 ps
CPU time 109.07 seconds
Started Aug 07 04:55:38 PM PDT 24
Finished Aug 07 04:57:28 PM PDT 24
Peak memory 220296 kb
Host smart-3674009d-51bb-4c00-9332-086e09ca48f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114496511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1114496511
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1077991085
Short name T101
Test name
Test status
Simulation time 182682164 ps
CPU time 10.22 seconds
Started Aug 07 04:55:07 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 219972 kb
Host smart-00901f64-9339-4a30-ad40-b6c89a04160e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077991085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1077991085
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1130727000
Short name T266
Test name
Test status
Simulation time 35588136444 ps
CPU time 1355.69 seconds
Started Aug 07 04:55:35 PM PDT 24
Finished Aug 07 05:18:10 PM PDT 24
Peak memory 236588 kb
Host smart-e8caf630-800e-48e6-ac04-9369b247b5d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130727000 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1130727000
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2073968645
Short name T306
Test name
Test status
Simulation time 4279719790 ps
CPU time 15.23 seconds
Started Aug 07 04:55:22 PM PDT 24
Finished Aug 07 04:55:37 PM PDT 24
Peak memory 219160 kb
Host smart-b79e44f2-8dc4-40ba-abe2-8e35410648f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073968645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2073968645
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4134241379
Short name T282
Test name
Test status
Simulation time 4848729046 ps
CPU time 138.1 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:57:27 PM PDT 24
Peak memory 225392 kb
Host smart-e764f784-9168-47a9-8e1e-994c8b7d5f3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134241379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4134241379
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3729143968
Short name T273
Test name
Test status
Simulation time 2750287304 ps
CPU time 22.88 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:31 PM PDT 24
Peak memory 220112 kb
Host smart-e7dafd23-4201-47a7-9cb5-01b4972c438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729143968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3729143968
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.859332730
Short name T126
Test name
Test status
Simulation time 259064320 ps
CPU time 12.03 seconds
Started Aug 07 04:55:06 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 219976 kb
Host smart-cfaa3c1c-3d57-4036-9bf5-2eef70b80c18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859332730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.859332730
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.773603234
Short name T261
Test name
Test status
Simulation time 1472075178 ps
CPU time 24.03 seconds
Started Aug 07 04:55:10 PM PDT 24
Finished Aug 07 04:55:34 PM PDT 24
Peak memory 219964 kb
Host smart-963785ad-e8dc-4110-b1e0-5a5a892edd0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773603234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.773603234
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3259272376
Short name T164
Test name
Test status
Simulation time 752879552 ps
CPU time 8.48 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 218924 kb
Host smart-f8f7faa5-59b7-4aee-a04a-05b174f642e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259272376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3259272376
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3785693037
Short name T21
Test name
Test status
Simulation time 12030893335 ps
CPU time 234.79 seconds
Started Aug 07 04:54:46 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 241420 kb
Host smart-018dc499-bc4d-4225-9de1-8ad1a2078469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785693037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3785693037
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2966408125
Short name T274
Test name
Test status
Simulation time 4943627407 ps
CPU time 23.29 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 220172 kb
Host smart-ca3a1800-ced2-4ddb-aafc-ec9724a22f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966408125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2966408125
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1934634396
Short name T138
Test name
Test status
Simulation time 261495737 ps
CPU time 11.95 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 219924 kb
Host smart-fe12e454-e47a-424a-bfbe-1850fb172cae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934634396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1934634396
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1980473595
Short name T26
Test name
Test status
Simulation time 3380008901 ps
CPU time 225.65 seconds
Started Aug 07 04:55:13 PM PDT 24
Finished Aug 07 04:58:59 PM PDT 24
Peak memory 238816 kb
Host smart-76996903-3d0f-4755-920f-001b744e0542
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980473595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1980473595
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.728047949
Short name T129
Test name
Test status
Simulation time 2311466665 ps
CPU time 12.22 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:55:08 PM PDT 24
Peak memory 220040 kb
Host smart-7558f57e-00b3-40c4-996f-fbbcf9634929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728047949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.728047949
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4276682874
Short name T137
Test name
Test status
Simulation time 3352024279 ps
CPU time 223.98 seconds
Started Aug 07 04:55:17 PM PDT 24
Finished Aug 07 04:59:01 PM PDT 24
Peak memory 225652 kb
Host smart-78e3c341-c72e-4237-994d-2fbebab7bf51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276682874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4276682874
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2457002236
Short name T276
Test name
Test status
Simulation time 347872870 ps
CPU time 19.72 seconds
Started Aug 07 04:55:08 PM PDT 24
Finished Aug 07 04:55:28 PM PDT 24
Peak memory 219984 kb
Host smart-333f1187-7ea6-47b2-a0c8-62ff5b9125b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457002236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2457002236
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1951624511
Short name T196
Test name
Test status
Simulation time 859461387 ps
CPU time 10.22 seconds
Started Aug 07 04:55:19 PM PDT 24
Finished Aug 07 04:55:30 PM PDT 24
Peak memory 219924 kb
Host smart-0df3bd85-0000-408f-a304-74941da54c01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951624511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1951624511
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2324518508
Short name T56
Test name
Test status
Simulation time 2175622534 ps
CPU time 40.45 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:56:05 PM PDT 24
Peak memory 220144 kb
Host smart-b7e8c9ac-2980-41bd-ba0f-dfc3945ed052
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324518508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2324518508
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.20601969
Short name T222
Test name
Test status
Simulation time 174160647 ps
CPU time 8.56 seconds
Started Aug 07 04:55:30 PM PDT 24
Finished Aug 07 04:55:39 PM PDT 24
Peak memory 219088 kb
Host smart-c6533d05-cd1d-4e16-8b4d-5616b5049e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20601969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.20601969
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1357210383
Short name T285
Test name
Test status
Simulation time 2048442899 ps
CPU time 160.41 seconds
Started Aug 07 04:55:18 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 238436 kb
Host smart-34130c53-b8f2-498e-8c38-a0a81eb1e119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357210383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1357210383
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1198925773
Short name T130
Test name
Test status
Simulation time 1323452383 ps
CPU time 19.66 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 04:55:41 PM PDT 24
Peak memory 219972 kb
Host smart-ed11c81f-afba-40c6-87a5-7177ad6a18b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198925773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1198925773
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.232737059
Short name T212
Test name
Test status
Simulation time 350258125 ps
CPU time 12.05 seconds
Started Aug 07 04:55:10 PM PDT 24
Finished Aug 07 04:55:23 PM PDT 24
Peak memory 220004 kb
Host smart-9eec4b36-db6c-4d01-b5a5-cdcffb471d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232737059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.232737059
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.697978807
Short name T189
Test name
Test status
Simulation time 1469580566 ps
CPU time 38.11 seconds
Started Aug 07 04:55:34 PM PDT 24
Finished Aug 07 04:56:12 PM PDT 24
Peak memory 219920 kb
Host smart-cab85e01-3c4e-4a26-8f00-aa155ae53c0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697978807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.697978807
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1372664360
Short name T27
Test name
Test status
Simulation time 971635569 ps
CPU time 8.52 seconds
Started Aug 07 04:55:33 PM PDT 24
Finished Aug 07 04:55:42 PM PDT 24
Peak memory 219144 kb
Host smart-805e14ef-6f2c-49f6-b805-a337bbdd8461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372664360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1372664360
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2099584159
Short name T317
Test name
Test status
Simulation time 7739887319 ps
CPU time 272.69 seconds
Started Aug 07 04:55:47 PM PDT 24
Finished Aug 07 05:00:20 PM PDT 24
Peak memory 238484 kb
Host smart-3773334e-ec66-4e9a-bb05-18fc2787a067
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099584159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2099584159
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3460809002
Short name T160
Test name
Test status
Simulation time 348221676 ps
CPU time 19.56 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:55:28 PM PDT 24
Peak memory 220032 kb
Host smart-a57c0e18-4354-462e-a09d-1f5d7eae8cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460809002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3460809002
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.386277527
Short name T88
Test name
Test status
Simulation time 1012956057 ps
CPU time 16.63 seconds
Started Aug 07 04:55:13 PM PDT 24
Finished Aug 07 04:55:30 PM PDT 24
Peak memory 220004 kb
Host smart-038efe25-3ad4-4587-8728-5199a849b604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386277527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.386277527
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1434229882
Short name T99
Test name
Test status
Simulation time 773964353 ps
CPU time 37.63 seconds
Started Aug 07 04:55:35 PM PDT 24
Finished Aug 07 04:56:12 PM PDT 24
Peak memory 219948 kb
Host smart-50c1999e-227e-46aa-a1aa-8d95493fc75d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434229882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1434229882
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.379792732
Short name T63
Test name
Test status
Simulation time 257181344 ps
CPU time 10.01 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:12 PM PDT 24
Peak memory 219108 kb
Host smart-6c833a79-a7c9-4265-8534-1d9a7b99fb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379792732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.379792732
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2027806567
Short name T136
Test name
Test status
Simulation time 30441156258 ps
CPU time 345.43 seconds
Started Aug 07 04:55:11 PM PDT 24
Finished Aug 07 05:00:56 PM PDT 24
Peak memory 229384 kb
Host smart-70dcf821-4c1c-4f08-bb65-f550babe2826
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027806567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2027806567
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3313314741
Short name T313
Test name
Test status
Simulation time 1374983734 ps
CPU time 18.62 seconds
Started Aug 07 04:55:39 PM PDT 24
Finished Aug 07 04:55:57 PM PDT 24
Peak memory 219916 kb
Host smart-15ab1bde-8351-4483-acf4-a5e2c45c46ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313314741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3313314741
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.973938636
Short name T173
Test name
Test status
Simulation time 554810465 ps
CPU time 33.91 seconds
Started Aug 07 04:55:32 PM PDT 24
Finished Aug 07 04:56:06 PM PDT 24
Peak memory 219996 kb
Host smart-3f741896-ae61-4b81-9664-a67d1548e2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973938636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.973938636
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3608040203
Short name T191
Test name
Test status
Simulation time 175058840 ps
CPU time 8.49 seconds
Started Aug 07 04:55:39 PM PDT 24
Finished Aug 07 04:55:48 PM PDT 24
Peak memory 219008 kb
Host smart-66faca75-671b-42f2-838d-e8b2717b7ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608040203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3608040203
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2234311863
Short name T187
Test name
Test status
Simulation time 4871153278 ps
CPU time 237.45 seconds
Started Aug 07 04:55:45 PM PDT 24
Finished Aug 07 04:59:43 PM PDT 24
Peak memory 220216 kb
Host smart-598a1879-edfb-4a4c-adec-46c0bbe5fcf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234311863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2234311863
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3008521457
Short name T260
Test name
Test status
Simulation time 1742267785 ps
CPU time 19.03 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:22 PM PDT 24
Peak memory 219952 kb
Host smart-9e37bae8-7838-4f2b-9857-48f2df89337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008521457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3008521457
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1068700089
Short name T250
Test name
Test status
Simulation time 3637041982 ps
CPU time 11.58 seconds
Started Aug 07 04:55:40 PM PDT 24
Finished Aug 07 04:55:52 PM PDT 24
Peak memory 220056 kb
Host smart-a3d4f888-8d2c-4561-8c73-48cc533ffbce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068700089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1068700089
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1223328371
Short name T289
Test name
Test status
Simulation time 207452841 ps
CPU time 20.95 seconds
Started Aug 07 04:55:30 PM PDT 24
Finished Aug 07 04:55:51 PM PDT 24
Peak memory 219736 kb
Host smart-73a8270d-3b67-4379-a096-178d6b64eba0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223328371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1223328371
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.502759930
Short name T145
Test name
Test status
Simulation time 2009451394 ps
CPU time 14.67 seconds
Started Aug 07 04:55:30 PM PDT 24
Finished Aug 07 04:55:44 PM PDT 24
Peak memory 219064 kb
Host smart-c1ed6a12-2b63-4d3a-8c84-e6d46915407e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502759930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.502759930
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.220801132
Short name T252
Test name
Test status
Simulation time 1301693881 ps
CPU time 23.02 seconds
Started Aug 07 04:55:27 PM PDT 24
Finished Aug 07 04:55:51 PM PDT 24
Peak memory 219956 kb
Host smart-6762f175-f820-45ab-9157-f0476eda85de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220801132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.220801132
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3920431
Short name T293
Test name
Test status
Simulation time 1682401761 ps
CPU time 11.64 seconds
Started Aug 07 04:55:14 PM PDT 24
Finished Aug 07 04:55:25 PM PDT 24
Peak memory 219976 kb
Host smart-39870898-abc6-4d0a-8cd2-cc4c8f9380f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3920431
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2007494198
Short name T249
Test name
Test status
Simulation time 829739140 ps
CPU time 13.86 seconds
Started Aug 07 04:55:34 PM PDT 24
Finished Aug 07 04:55:48 PM PDT 24
Peak memory 220020 kb
Host smart-513ccdbc-5340-473b-b87e-eb998634287f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007494198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2007494198
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4175885361
Short name T86
Test name
Test status
Simulation time 661989103 ps
CPU time 8.48 seconds
Started Aug 07 04:55:15 PM PDT 24
Finished Aug 07 04:55:23 PM PDT 24
Peak memory 219184 kb
Host smart-1dd1dc73-9fca-4a17-9067-45a6a809dc02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175885361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4175885361
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1782448199
Short name T7
Test name
Test status
Simulation time 3043447247 ps
CPU time 194.15 seconds
Started Aug 07 04:55:14 PM PDT 24
Finished Aug 07 04:58:28 PM PDT 24
Peak memory 234776 kb
Host smart-3d3e1f93-c27b-4bbd-87d8-d820ddaf16e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782448199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1782448199
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4062472507
Short name T155
Test name
Test status
Simulation time 1376812847 ps
CPU time 19.47 seconds
Started Aug 07 04:55:27 PM PDT 24
Finished Aug 07 04:55:46 PM PDT 24
Peak memory 219992 kb
Host smart-4975b072-622e-442e-894d-6649bdabceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062472507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4062472507
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2117645957
Short name T94
Test name
Test status
Simulation time 538351022 ps
CPU time 12.29 seconds
Started Aug 07 04:55:36 PM PDT 24
Finished Aug 07 04:55:49 PM PDT 24
Peak memory 219948 kb
Host smart-e20e2102-2f28-4798-aeac-556f3ae96fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117645957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2117645957
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2356743945
Short name T310
Test name
Test status
Simulation time 3589605691 ps
CPU time 41.26 seconds
Started Aug 07 04:55:15 PM PDT 24
Finished Aug 07 04:55:59 PM PDT 24
Peak memory 221228 kb
Host smart-04e05eec-7ed5-41c7-9cb6-3707aba5b74c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356743945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2356743945
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.115584179
Short name T202
Test name
Test status
Simulation time 114566892855 ps
CPU time 1039.82 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 05:12:23 PM PDT 24
Peak memory 238688 kb
Host smart-9dad6bf8-d59e-4c5d-bda7-0e09f4b7cf35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115584179 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.115584179
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2100953089
Short name T204
Test name
Test status
Simulation time 687608170 ps
CPU time 8.15 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 219092 kb
Host smart-3a5edfc6-fd91-4db4-b505-659e57db55c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100953089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2100953089
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2431724039
Short name T11
Test name
Test status
Simulation time 692258830 ps
CPU time 19.33 seconds
Started Aug 07 04:55:28 PM PDT 24
Finished Aug 07 04:55:48 PM PDT 24
Peak memory 220052 kb
Host smart-e590ca12-5b88-4d10-a38d-6d8e0ece5192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431724039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2431724039
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3165354396
Short name T180
Test name
Test status
Simulation time 178809566 ps
CPU time 10.44 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:55:35 PM PDT 24
Peak memory 220024 kb
Host smart-5e5218d6-e4a4-4df0-8dcd-982600f2ae90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165354396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3165354396
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1057972555
Short name T176
Test name
Test status
Simulation time 567720722 ps
CPU time 28.56 seconds
Started Aug 07 04:55:24 PM PDT 24
Finished Aug 07 04:55:53 PM PDT 24
Peak memory 219924 kb
Host smart-180713df-9254-4f33-9926-ee61007659e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057972555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1057972555
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.4014669490
Short name T51
Test name
Test status
Simulation time 19504303421 ps
CPU time 7842.47 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 07:05:46 PM PDT 24
Peak memory 230344 kb
Host smart-fcf12b5d-51c0-441a-bc58-ab237f76a785
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014669490 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.4014669490
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3256272511
Short name T294
Test name
Test status
Simulation time 167613666 ps
CPU time 8.34 seconds
Started Aug 07 04:55:30 PM PDT 24
Finished Aug 07 04:55:38 PM PDT 24
Peak memory 218996 kb
Host smart-6909bb13-155c-4ce5-b289-cd8de161cdc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256272511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3256272511
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1094274334
Short name T211
Test name
Test status
Simulation time 10662333172 ps
CPU time 145.64 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:57:35 PM PDT 24
Peak memory 237456 kb
Host smart-42bd8f09-2ee8-4343-841b-50d79e57b125
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094274334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1094274334
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.258208096
Short name T190
Test name
Test status
Simulation time 4510952260 ps
CPU time 22.66 seconds
Started Aug 07 04:55:09 PM PDT 24
Finished Aug 07 04:55:31 PM PDT 24
Peak memory 220124 kb
Host smart-bb323aac-4e29-40e5-83b7-f7a678ac009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258208096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.258208096
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2738079557
Short name T120
Test name
Test status
Simulation time 364226270 ps
CPU time 10.48 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:14 PM PDT 24
Peak memory 219984 kb
Host smart-6212e74c-c3fb-4565-a643-850bf0d50e51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738079557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2738079557
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2972040917
Short name T309
Test name
Test status
Simulation time 777171737 ps
CPU time 17.39 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:21 PM PDT 24
Peak memory 219876 kb
Host smart-51238583-b6d0-44bf-8e48-c6b70dc48006
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972040917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2972040917
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2415342125
Short name T295
Test name
Test status
Simulation time 995058401 ps
CPU time 10.18 seconds
Started Aug 07 04:55:32 PM PDT 24
Finished Aug 07 04:55:42 PM PDT 24
Peak memory 219040 kb
Host smart-f4d3b16e-6b71-40a4-aceb-0288a999a01c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415342125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2415342125
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2989800742
Short name T150
Test name
Test status
Simulation time 38284712497 ps
CPU time 222.06 seconds
Started Aug 07 04:55:12 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 229072 kb
Host smart-75d08581-304f-47d0-a03c-035132560849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989800742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2989800742
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2309226772
Short name T127
Test name
Test status
Simulation time 522972627 ps
CPU time 22.96 seconds
Started Aug 07 04:55:22 PM PDT 24
Finished Aug 07 04:55:45 PM PDT 24
Peak memory 219940 kb
Host smart-3f1c76c1-54b1-4b99-8ca1-d5f9d434144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309226772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2309226772
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2112384787
Short name T166
Test name
Test status
Simulation time 273096156 ps
CPU time 12.19 seconds
Started Aug 07 04:55:11 PM PDT 24
Finished Aug 07 04:55:23 PM PDT 24
Peak memory 220044 kb
Host smart-bb9bff33-1b0e-4d62-93b2-1da7cedf2871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112384787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2112384787
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3333969479
Short name T13
Test name
Test status
Simulation time 1497786129 ps
CPU time 24.8 seconds
Started Aug 07 04:55:30 PM PDT 24
Finished Aug 07 04:55:55 PM PDT 24
Peak memory 219932 kb
Host smart-87031f5f-bed2-4427-b140-d6be7eb19c7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333969479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3333969479
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3922979159
Short name T258
Test name
Test status
Simulation time 719434134 ps
CPU time 8.62 seconds
Started Aug 07 04:54:56 PM PDT 24
Finished Aug 07 04:55:05 PM PDT 24
Peak memory 219036 kb
Host smart-85ebde67-a6f4-465a-b105-658dbd078e53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922979159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3922979159
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1787153142
Short name T134
Test name
Test status
Simulation time 18120225798 ps
CPU time 304.96 seconds
Started Aug 07 04:54:52 PM PDT 24
Finished Aug 07 04:59:57 PM PDT 24
Peak memory 234096 kb
Host smart-9d9dcad3-3ec4-41a1-b067-840cadf2827b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787153142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1787153142
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2487410881
Short name T268
Test name
Test status
Simulation time 2060899147 ps
CPU time 23.02 seconds
Started Aug 07 04:54:52 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 219940 kb
Host smart-e58d421a-8b9b-4138-8245-ca5e2378decc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487410881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2487410881
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.884014944
Short name T156
Test name
Test status
Simulation time 2168623493 ps
CPU time 10.55 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:14 PM PDT 24
Peak memory 220120 kb
Host smart-835b4fad-dbfe-460b-be2b-0ffade87f654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884014944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.884014944
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.708737377
Short name T32
Test name
Test status
Simulation time 602634886 ps
CPU time 119.56 seconds
Started Aug 07 04:54:49 PM PDT 24
Finished Aug 07 04:56:49 PM PDT 24
Peak memory 239036 kb
Host smart-508f41f0-3d74-43bf-987c-0c5afd9089ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708737377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.708737377
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2438023990
Short name T9
Test name
Test status
Simulation time 3031283007 ps
CPU time 18.15 seconds
Started Aug 07 04:54:50 PM PDT 24
Finished Aug 07 04:55:09 PM PDT 24
Peak memory 220052 kb
Host smart-30857401-0b1d-4796-a8a3-7b724f0a242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438023990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2438023990
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.322349559
Short name T177
Test name
Test status
Simulation time 633169657 ps
CPU time 21.27 seconds
Started Aug 07 04:54:44 PM PDT 24
Finished Aug 07 04:55:06 PM PDT 24
Peak memory 219908 kb
Host smart-bd501241-cae9-4424-b250-44b27c7e00a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322349559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.322349559
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1535373449
Short name T133
Test name
Test status
Simulation time 590228080 ps
CPU time 8.36 seconds
Started Aug 07 04:55:29 PM PDT 24
Finished Aug 07 04:55:37 PM PDT 24
Peak memory 218904 kb
Host smart-2f89f845-c654-4251-a051-00b6e0e044b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535373449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1535373449
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.63546796
Short name T214
Test name
Test status
Simulation time 14774500289 ps
CPU time 263.47 seconds
Started Aug 07 04:55:19 PM PDT 24
Finished Aug 07 04:59:42 PM PDT 24
Peak memory 226700 kb
Host smart-19aaee4a-c0f9-4b69-9fe2-82fbdfc70334
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63546796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_co
rrupt_sig_fatal_chk.63546796
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.331880690
Short name T185
Test name
Test status
Simulation time 565073042 ps
CPU time 22.67 seconds
Started Aug 07 04:55:27 PM PDT 24
Finished Aug 07 04:55:50 PM PDT 24
Peak memory 220024 kb
Host smart-187ff5ae-4ec3-4013-8139-3107ef9c5150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331880690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.331880690
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.275999303
Short name T201
Test name
Test status
Simulation time 269324561 ps
CPU time 12.19 seconds
Started Aug 07 04:55:23 PM PDT 24
Finished Aug 07 04:55:35 PM PDT 24
Peak memory 219944 kb
Host smart-b76b3b63-07a2-479c-b78c-9c2e50f08b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275999303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.275999303
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1392610909
Short name T316
Test name
Test status
Simulation time 11399208101 ps
CPU time 47.86 seconds
Started Aug 07 04:55:28 PM PDT 24
Finished Aug 07 04:56:16 PM PDT 24
Peak memory 220384 kb
Host smart-4162c3c1-1949-4616-a1a0-8bc4f7f7f78c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392610909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1392610909
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1513168694
Short name T215
Test name
Test status
Simulation time 989474299 ps
CPU time 9.57 seconds
Started Aug 07 04:55:41 PM PDT 24
Finished Aug 07 04:55:50 PM PDT 24
Peak memory 218932 kb
Host smart-99e1f2d8-0a15-4168-9444-b7787d400509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513168694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1513168694
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4013783348
Short name T45
Test name
Test status
Simulation time 6270716092 ps
CPU time 215.11 seconds
Started Aug 07 04:55:41 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 220244 kb
Host smart-e9fe2d18-a2a8-4281-a150-b88a5d64234e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013783348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4013783348
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1358543889
Short name T275
Test name
Test status
Simulation time 332274923 ps
CPU time 19.44 seconds
Started Aug 07 04:55:22 PM PDT 24
Finished Aug 07 04:55:42 PM PDT 24
Peak memory 219996 kb
Host smart-83740f0f-7b47-48ca-a67d-7a6c6536fff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358543889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1358543889
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2282159313
Short name T233
Test name
Test status
Simulation time 686552479 ps
CPU time 10.08 seconds
Started Aug 07 04:55:21 PM PDT 24
Finished Aug 07 04:55:31 PM PDT 24
Peak memory 220000 kb
Host smart-119001cb-80ca-473a-8b7e-4c16837e90bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282159313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2282159313
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2036471444
Short name T239
Test name
Test status
Simulation time 290603733 ps
CPU time 16.72 seconds
Started Aug 07 04:55:40 PM PDT 24
Finished Aug 07 04:55:57 PM PDT 24
Peak memory 220016 kb
Host smart-0a3727af-9ec3-4557-b51b-d98c47f69631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036471444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2036471444
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3405719727
Short name T230
Test name
Test status
Simulation time 249928512 ps
CPU time 10.33 seconds
Started Aug 07 04:55:29 PM PDT 24
Finished Aug 07 04:55:40 PM PDT 24
Peak memory 218956 kb
Host smart-3fdd6522-3857-4579-abfe-12787f03063a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405719727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3405719727
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.969384434
Short name T283
Test name
Test status
Simulation time 5953626482 ps
CPU time 308.59 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 05:00:35 PM PDT 24
Peak memory 228972 kb
Host smart-438a3c00-4346-4583-bbdd-9250bfd0d058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969384434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.969384434
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3678423780
Short name T125
Test name
Test status
Simulation time 516100366 ps
CPU time 22.87 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 04:55:49 PM PDT 24
Peak memory 219324 kb
Host smart-d426b5a8-e4ec-4eba-800f-4efc430ea1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678423780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3678423780
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2488676954
Short name T243
Test name
Test status
Simulation time 361745812 ps
CPU time 10.18 seconds
Started Aug 07 04:55:07 PM PDT 24
Finished Aug 07 04:55:17 PM PDT 24
Peak memory 220064 kb
Host smart-433bdf55-8dce-4e25-9fd5-9c2c532e918b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488676954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2488676954
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.624470382
Short name T34
Test name
Test status
Simulation time 7111713561 ps
CPU time 38.81 seconds
Started Aug 07 04:55:40 PM PDT 24
Finished Aug 07 04:56:19 PM PDT 24
Peak memory 220032 kb
Host smart-6b8405dc-adbe-4e40-9a35-62acfecc674d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624470382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.624470382
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1252049511
Short name T188
Test name
Test status
Simulation time 254474386 ps
CPU time 10.15 seconds
Started Aug 07 04:55:32 PM PDT 24
Finished Aug 07 04:55:42 PM PDT 24
Peak memory 219092 kb
Host smart-75b4d756-d5fd-40a5-893e-c52f5f2303d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252049511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1252049511
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4221798168
Short name T244
Test name
Test status
Simulation time 4874324219 ps
CPU time 164.17 seconds
Started Aug 07 04:55:24 PM PDT 24
Finished Aug 07 04:58:08 PM PDT 24
Peak memory 220252 kb
Host smart-6b9fe89e-29a3-4430-aa6d-1bab6ab689f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221798168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4221798168
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3843507195
Short name T135
Test name
Test status
Simulation time 4713628625 ps
CPU time 19.27 seconds
Started Aug 07 04:55:14 PM PDT 24
Finished Aug 07 04:55:37 PM PDT 24
Peak memory 220068 kb
Host smart-28044124-8f39-47bf-88d0-e97e2d0e32dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843507195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3843507195
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2539083132
Short name T169
Test name
Test status
Simulation time 1523132095 ps
CPU time 11.96 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:17 PM PDT 24
Peak memory 219944 kb
Host smart-547a557f-5ee7-405b-adbe-0039baf04d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539083132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2539083132
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1246236932
Short name T41
Test name
Test status
Simulation time 1154744749 ps
CPU time 18.93 seconds
Started Aug 07 04:55:05 PM PDT 24
Finished Aug 07 04:55:24 PM PDT 24
Peak memory 219984 kb
Host smart-57b9806c-05ff-4882-b8e0-a054464407cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246236932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1246236932
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1204083807
Short name T312
Test name
Test status
Simulation time 689344051 ps
CPU time 8.38 seconds
Started Aug 07 04:55:34 PM PDT 24
Finished Aug 07 04:55:43 PM PDT 24
Peak memory 219172 kb
Host smart-e031fd68-2a6c-4d7e-aa2e-5444062f69c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204083807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1204083807
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3814092631
Short name T219
Test name
Test status
Simulation time 17003562277 ps
CPU time 246.4 seconds
Started Aug 07 04:55:24 PM PDT 24
Finished Aug 07 04:59:30 PM PDT 24
Peak memory 219228 kb
Host smart-754d8fc8-e260-46ec-b52a-981c98b3e37f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814092631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3814092631
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2826825656
Short name T31
Test name
Test status
Simulation time 346405077 ps
CPU time 19.39 seconds
Started Aug 07 04:55:36 PM PDT 24
Finished Aug 07 04:55:56 PM PDT 24
Peak memory 219976 kb
Host smart-c4ee6e3a-f2c7-415c-bc90-353d8dede7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826825656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2826825656
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2555061223
Short name T97
Test name
Test status
Simulation time 180112801 ps
CPU time 10.75 seconds
Started Aug 07 04:55:36 PM PDT 24
Finished Aug 07 04:55:47 PM PDT 24
Peak memory 219984 kb
Host smart-17869ab3-b989-44a4-9903-31fb6c3b0813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555061223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2555061223
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.431556715
Short name T291
Test name
Test status
Simulation time 1397796338 ps
CPU time 20.7 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:55:46 PM PDT 24
Peak memory 220240 kb
Host smart-93fff47c-23cd-4652-b508-eca32ecb22e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431556715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.431556715
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4294797100
Short name T159
Test name
Test status
Simulation time 174761698 ps
CPU time 8.45 seconds
Started Aug 07 04:55:37 PM PDT 24
Finished Aug 07 04:55:46 PM PDT 24
Peak memory 219040 kb
Host smart-dad26a5a-d2cd-416b-91fa-f41aa0b7d3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294797100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4294797100
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1065212504
Short name T208
Test name
Test status
Simulation time 21841103196 ps
CPU time 231.98 seconds
Started Aug 07 04:55:49 PM PDT 24
Finished Aug 07 04:59:41 PM PDT 24
Peak memory 234548 kb
Host smart-7278abfc-de41-4934-b093-97b57cd85ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065212504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1065212504
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2705239526
Short name T284
Test name
Test status
Simulation time 3094992945 ps
CPU time 22.69 seconds
Started Aug 07 04:55:41 PM PDT 24
Finished Aug 07 04:56:03 PM PDT 24
Peak memory 220148 kb
Host smart-c5ddcf5a-ef62-435c-8792-1c0ee3f60116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705239526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2705239526
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1152563316
Short name T265
Test name
Test status
Simulation time 304990837 ps
CPU time 12.24 seconds
Started Aug 07 04:55:20 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 219980 kb
Host smart-20f24e49-6f7b-412a-a536-621ffe233736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152563316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1152563316
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3004344692
Short name T256
Test name
Test status
Simulation time 2142746372 ps
CPU time 26.65 seconds
Started Aug 07 04:55:37 PM PDT 24
Finished Aug 07 04:56:04 PM PDT 24
Peak memory 219964 kb
Host smart-fd2339a0-abb2-4a10-911d-dfd874fd996a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004344692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3004344692
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.719192653
Short name T50
Test name
Test status
Simulation time 110503560714 ps
CPU time 1148.79 seconds
Started Aug 07 04:55:28 PM PDT 24
Finished Aug 07 05:14:38 PM PDT 24
Peak memory 239208 kb
Host smart-b33d5856-fc40-4dae-b802-ce7b02e7d327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719192653 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.719192653
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3510494230
Short name T199
Test name
Test status
Simulation time 248872075 ps
CPU time 9.9 seconds
Started Aug 07 04:55:28 PM PDT 24
Finished Aug 07 04:55:38 PM PDT 24
Peak memory 218984 kb
Host smart-94301873-79e6-46cb-8ebe-40a0444c03c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510494230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3510494230
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3257262840
Short name T255
Test name
Test status
Simulation time 3932341911 ps
CPU time 208.48 seconds
Started Aug 07 04:55:38 PM PDT 24
Finished Aug 07 04:59:07 PM PDT 24
Peak memory 237228 kb
Host smart-22026d0f-6ba7-4a9c-b8eb-8e5202c01620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257262840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3257262840
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1306442897
Short name T168
Test name
Test status
Simulation time 636244306 ps
CPU time 19.58 seconds
Started Aug 07 04:55:39 PM PDT 24
Finished Aug 07 04:55:59 PM PDT 24
Peak memory 220064 kb
Host smart-c03b741b-669e-407b-9790-13f4e9c012f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306442897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1306442897
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1756485786
Short name T121
Test name
Test status
Simulation time 269000972 ps
CPU time 12.19 seconds
Started Aug 07 04:55:27 PM PDT 24
Finished Aug 07 04:55:40 PM PDT 24
Peak memory 219928 kb
Host smart-20e8faf5-da6b-4607-b531-00a083032f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756485786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1756485786
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.23072055
Short name T39
Test name
Test status
Simulation time 404898778 ps
CPU time 25.51 seconds
Started Aug 07 04:55:22 PM PDT 24
Finished Aug 07 04:55:48 PM PDT 24
Peak memory 219920 kb
Host smart-0d71a2ba-ad2c-4ece-b4f0-8a07853781fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23072055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.23072055
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1105721144
Short name T54
Test name
Test status
Simulation time 33501307044 ps
CPU time 5244.83 seconds
Started Aug 07 04:55:40 PM PDT 24
Finished Aug 07 06:23:05 PM PDT 24
Peak memory 228664 kb
Host smart-400b8d85-6c8b-47ff-8a9d-a35b895e58f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105721144 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1105721144
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2549790141
Short name T178
Test name
Test status
Simulation time 786121884 ps
CPU time 8.18 seconds
Started Aug 07 04:55:38 PM PDT 24
Finished Aug 07 04:55:46 PM PDT 24
Peak memory 218740 kb
Host smart-05a1541f-950c-491d-a8a0-1881691404a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549790141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2549790141
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.993958073
Short name T44
Test name
Test status
Simulation time 15811091268 ps
CPU time 236.43 seconds
Started Aug 07 04:55:22 PM PDT 24
Finished Aug 07 04:59:18 PM PDT 24
Peak memory 240128 kb
Host smart-5b4c5960-0881-477b-8d75-e9bcc7ed5057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993958073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.993958073
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.530452657
Short name T37
Test name
Test status
Simulation time 534947073 ps
CPU time 12.23 seconds
Started Aug 07 04:55:26 PM PDT 24
Finished Aug 07 04:55:39 PM PDT 24
Peak memory 220076 kb
Host smart-6dc33de4-5880-41a2-8c20-25f896ee805c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530452657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.530452657
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.176453340
Short name T271
Test name
Test status
Simulation time 507120690 ps
CPU time 23.23 seconds
Started Aug 07 04:55:23 PM PDT 24
Finished Aug 07 04:55:46 PM PDT 24
Peak memory 219916 kb
Host smart-74ff245b-91f3-4786-820c-d2c91ad8eabd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176453340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.176453340
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1690377081
Short name T16
Test name
Test status
Simulation time 78973145980 ps
CPU time 7022.43 seconds
Started Aug 07 04:55:12 PM PDT 24
Finished Aug 07 06:52:15 PM PDT 24
Peak memory 232872 kb
Host smart-bad7edc3-acf0-4ec6-b0de-bd0cf6f14445
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690377081 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1690377081
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1403438781
Short name T142
Test name
Test status
Simulation time 249494808 ps
CPU time 10.33 seconds
Started Aug 07 04:55:41 PM PDT 24
Finished Aug 07 04:55:51 PM PDT 24
Peak memory 219040 kb
Host smart-c371996f-de07-416f-8131-97bf58718dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403438781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1403438781
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1290305538
Short name T287
Test name
Test status
Simulation time 13424598844 ps
CPU time 155.02 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 237360 kb
Host smart-66c27c34-6c3d-4c25-905d-7c1cbd667de2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290305538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1290305538
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1531828624
Short name T153
Test name
Test status
Simulation time 377674277 ps
CPU time 19.3 seconds
Started Aug 07 04:55:31 PM PDT 24
Finished Aug 07 04:55:50 PM PDT 24
Peak memory 219976 kb
Host smart-90285285-5b95-4959-b9ed-5a0d0c7225e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531828624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1531828624
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2795634131
Short name T167
Test name
Test status
Simulation time 184737770 ps
CPU time 10.28 seconds
Started Aug 07 04:55:25 PM PDT 24
Finished Aug 07 04:55:35 PM PDT 24
Peak memory 220060 kb
Host smart-4a4a88f4-6b15-44a5-981f-015db91ea9a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2795634131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2795634131
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3996808889
Short name T47
Test name
Test status
Simulation time 271664641 ps
CPU time 15.79 seconds
Started Aug 07 04:55:29 PM PDT 24
Finished Aug 07 04:55:45 PM PDT 24
Peak memory 219944 kb
Host smart-c01af9b8-241e-4a67-95d3-6a86fb837357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996808889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3996808889
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.49356986
Short name T281
Test name
Test status
Simulation time 256905172 ps
CPU time 10.06 seconds
Started Aug 07 04:55:34 PM PDT 24
Finished Aug 07 04:55:45 PM PDT 24
Peak memory 219012 kb
Host smart-8d70aa9b-2df9-446e-9b00-725384dc9e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49356986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.49356986
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1333835095
Short name T175
Test name
Test status
Simulation time 6785383770 ps
CPU time 167.36 seconds
Started Aug 07 04:55:35 PM PDT 24
Finished Aug 07 04:58:22 PM PDT 24
Peak memory 234484 kb
Host smart-e078d9cf-3da4-4b0e-ae45-6fdaec3f7332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333835095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1333835095
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3893569337
Short name T36
Test name
Test status
Simulation time 344418836 ps
CPU time 19.41 seconds
Started Aug 07 04:55:31 PM PDT 24
Finished Aug 07 04:55:51 PM PDT 24
Peak memory 220076 kb
Host smart-e4047a50-d5b3-4b26-a6f0-0c4d6b641f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893569337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3893569337
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3466578912
Short name T163
Test name
Test status
Simulation time 4317253593 ps
CPU time 12.43 seconds
Started Aug 07 04:55:41 PM PDT 24
Finished Aug 07 04:55:54 PM PDT 24
Peak memory 220088 kb
Host smart-73f52652-e7bc-4420-bb04-51e9961d9092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466578912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3466578912
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3418416899
Short name T79
Test name
Test status
Simulation time 1827372645 ps
CPU time 32.82 seconds
Started Aug 07 04:55:40 PM PDT 24
Finished Aug 07 04:56:13 PM PDT 24
Peak memory 219956 kb
Host smart-96193feb-848e-4107-9f8a-ea0737093d28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418416899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3418416899
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2689041362
Short name T172
Test name
Test status
Simulation time 267277419 ps
CPU time 9.91 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 218508 kb
Host smart-bf58c065-061e-42ee-a607-63c30872bc88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689041362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2689041362
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2540429444
Short name T207
Test name
Test status
Simulation time 8409883742 ps
CPU time 224.83 seconds
Started Aug 07 04:54:55 PM PDT 24
Finished Aug 07 04:58:40 PM PDT 24
Peak memory 242692 kb
Host smart-e955d348-7975-47e1-9fcf-ac13805ac16b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540429444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2540429444
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.466669012
Short name T140
Test name
Test status
Simulation time 2750149922 ps
CPU time 19.5 seconds
Started Aug 07 04:55:07 PM PDT 24
Finished Aug 07 04:55:27 PM PDT 24
Peak memory 220060 kb
Host smart-6426ce49-11d0-400d-95af-52e24e3d2132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466669012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.466669012
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1426690552
Short name T4
Test name
Test status
Simulation time 471959910 ps
CPU time 10.29 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 220284 kb
Host smart-ffdadf72-7214-4be5-a838-08dd69c09ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426690552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1426690552
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3720377676
Short name T76
Test name
Test status
Simulation time 273666487 ps
CPU time 12.56 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:14 PM PDT 24
Peak memory 219988 kb
Host smart-d91fab6c-b3d3-4236-b2c0-8b520f8d829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720377676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3720377676
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1091723525
Short name T74
Test name
Test status
Simulation time 1024755541 ps
CPU time 36.06 seconds
Started Aug 07 04:54:53 PM PDT 24
Finished Aug 07 04:55:29 PM PDT 24
Peak memory 219920 kb
Host smart-b3b7a7d0-5adf-47d3-a048-ce2430cb255a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091723525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1091723525
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.742015602
Short name T307
Test name
Test status
Simulation time 26761871978 ps
CPU time 940.69 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 05:10:43 PM PDT 24
Peak memory 233076 kb
Host smart-65fd0dbd-7d09-4ca4-be5f-5fb6da37fd5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742015602 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.742015602
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3634176887
Short name T200
Test name
Test status
Simulation time 2475109758 ps
CPU time 10.09 seconds
Started Aug 07 04:55:04 PM PDT 24
Finished Aug 07 04:55:14 PM PDT 24
Peak memory 219184 kb
Host smart-172e200b-9c97-4449-be4b-a87f7324c3c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634176887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3634176887
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.433845594
Short name T210
Test name
Test status
Simulation time 4841136550 ps
CPU time 170.44 seconds
Started Aug 07 04:55:22 PM PDT 24
Finished Aug 07 04:58:13 PM PDT 24
Peak memory 220252 kb
Host smart-a26c4673-3b01-43bb-a248-8280f57cd839
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433845594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.433845594
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.673293308
Short name T181
Test name
Test status
Simulation time 1084280523 ps
CPU time 10.61 seconds
Started Aug 07 04:54:54 PM PDT 24
Finished Aug 07 04:55:05 PM PDT 24
Peak memory 219956 kb
Host smart-85e56e95-fd94-4115-a134-5fc4a6a50dc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673293308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.673293308
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3571784641
Short name T221
Test name
Test status
Simulation time 8309331250 ps
CPU time 17.9 seconds
Started Aug 07 04:55:10 PM PDT 24
Finished Aug 07 04:55:28 PM PDT 24
Peak memory 220096 kb
Host smart-7f08c2fe-d5a9-40f7-a350-2e5089807897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571784641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3571784641
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.587362241
Short name T279
Test name
Test status
Simulation time 871812998 ps
CPU time 14.04 seconds
Started Aug 07 04:54:48 PM PDT 24
Finished Aug 07 04:55:03 PM PDT 24
Peak memory 219900 kb
Host smart-b63e1f0c-4b4e-46f1-87af-6c2af71bd832
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587362241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.587362241
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1350664679
Short name T147
Test name
Test status
Simulation time 994122412 ps
CPU time 9.76 seconds
Started Aug 07 04:55:10 PM PDT 24
Finished Aug 07 04:55:20 PM PDT 24
Peak memory 219064 kb
Host smart-e6599a12-2410-4f6d-ba71-e1e764e510d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350664679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1350664679
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2702222164
Short name T218
Test name
Test status
Simulation time 45177751765 ps
CPU time 215.51 seconds
Started Aug 07 04:54:51 PM PDT 24
Finished Aug 07 04:58:26 PM PDT 24
Peak memory 240080 kb
Host smart-1a79b58b-25a2-4274-a07f-31e3ea4f0965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702222164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2702222164
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1113037939
Short name T228
Test name
Test status
Simulation time 507475814 ps
CPU time 22.69 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:25 PM PDT 24
Peak memory 219992 kb
Host smart-d81237a8-19c6-4491-a463-157b5c54cf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113037939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1113037939
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3025351577
Short name T182
Test name
Test status
Simulation time 788426742 ps
CPU time 10.52 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:14 PM PDT 24
Peak memory 220060 kb
Host smart-c0717acc-b520-4aa8-83af-737238ba9cbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025351577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3025351577
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3832498439
Short name T264
Test name
Test status
Simulation time 1076964027 ps
CPU time 12.03 seconds
Started Aug 07 04:55:13 PM PDT 24
Finished Aug 07 04:55:25 PM PDT 24
Peak memory 219872 kb
Host smart-b76eb1c4-0930-48b7-80ea-005b396d6c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832498439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3832498439
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2973943618
Short name T144
Test name
Test status
Simulation time 688273304 ps
CPU time 17.22 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:18 PM PDT 24
Peak memory 219896 kb
Host smart-002ab74e-501f-438c-9273-d9926f64069b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973943618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2973943618
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.10696088
Short name T152
Test name
Test status
Simulation time 827916504 ps
CPU time 8.23 seconds
Started Aug 07 04:54:46 PM PDT 24
Finished Aug 07 04:54:55 PM PDT 24
Peak memory 218976 kb
Host smart-4af1c49d-2736-488c-9297-0282e9f24154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10696088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.10696088
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1053009033
Short name T216
Test name
Test status
Simulation time 7983511942 ps
CPU time 267.75 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:59:26 PM PDT 24
Peak memory 244232 kb
Host smart-9deebfba-ac3b-4d5b-9169-f5cc08675f06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053009033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1053009033
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.232281237
Short name T183
Test name
Test status
Simulation time 1010953344 ps
CPU time 22.48 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:25 PM PDT 24
Peak memory 220000 kb
Host smart-1d399c24-a56d-49f4-8d23-f405b7dd4851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232281237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.232281237
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.308552874
Short name T305
Test name
Test status
Simulation time 1817448574 ps
CPU time 11.88 seconds
Started Aug 07 04:55:03 PM PDT 24
Finished Aug 07 04:55:15 PM PDT 24
Peak memory 220068 kb
Host smart-1634d7e3-9980-4290-9942-5d75571903f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308552874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.308552874
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2465333084
Short name T161
Test name
Test status
Simulation time 181723110 ps
CPU time 10.21 seconds
Started Aug 07 04:55:24 PM PDT 24
Finished Aug 07 04:55:35 PM PDT 24
Peak memory 219996 kb
Host smart-2677864c-a749-4c42-841b-5bb6b7459139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465333084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2465333084
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3582678244
Short name T303
Test name
Test status
Simulation time 250557531 ps
CPU time 28.91 seconds
Started Aug 07 04:55:01 PM PDT 24
Finished Aug 07 04:55:35 PM PDT 24
Peak memory 219992 kb
Host smart-d0f801c5-608d-406d-aed4-b3c7b7381ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582678244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3582678244
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3478722217
Short name T29
Test name
Test status
Simulation time 167675991 ps
CPU time 8.22 seconds
Started Aug 07 04:55:02 PM PDT 24
Finished Aug 07 04:55:10 PM PDT 24
Peak memory 219004 kb
Host smart-57b0c711-b77b-4590-adc6-8675047112b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478722217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3478722217
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2678151838
Short name T119
Test name
Test status
Simulation time 2530040064 ps
CPU time 198.7 seconds
Started Aug 07 04:54:58 PM PDT 24
Finished Aug 07 04:58:17 PM PDT 24
Peak memory 234512 kb
Host smart-4aa2ac77-017e-48ca-a7f9-96370150ee04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678151838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2678151838
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.718254946
Short name T48
Test name
Test status
Simulation time 1013320478 ps
CPU time 22.02 seconds
Started Aug 07 04:55:10 PM PDT 24
Finished Aug 07 04:55:32 PM PDT 24
Peak memory 219944 kb
Host smart-7cf5a627-644f-4786-beac-61c16540d136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718254946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.718254946
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2201180854
Short name T262
Test name
Test status
Simulation time 1040836214 ps
CPU time 12.5 seconds
Started Aug 07 04:54:52 PM PDT 24
Finished Aug 07 04:55:04 PM PDT 24
Peak memory 220028 kb
Host smart-b2341b65-b0ae-477a-a540-34323c59175b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201180854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2201180854
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2353601079
Short name T277
Test name
Test status
Simulation time 180844447 ps
CPU time 10.2 seconds
Started Aug 07 04:54:59 PM PDT 24
Finished Aug 07 04:55:09 PM PDT 24
Peak memory 219948 kb
Host smart-7395bbd8-1e94-49bb-8aa1-3e7db921f681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353601079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2353601079
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2905288996
Short name T170
Test name
Test status
Simulation time 2098311699 ps
CPU time 47.03 seconds
Started Aug 07 04:55:15 PM PDT 24
Finished Aug 07 04:56:02 PM PDT 24
Peak memory 220060 kb
Host smart-ba9a4a82-0c63-4a1d-be1c-ada094ac79d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905288996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2905288996
Directory /workspace/9.rom_ctrl_stress_all/latest
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