Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2004774

1

T1

7

T2

6

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	524434	1			T1	32		T2	6		T6	3
values[0x0]	757932	1			T7	30620		T13	26395		T15	50038
values[0x1]	784816	1			T7	31523		T13	27111		T15	51958

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33781	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2033401

1

T1

26

T2

6

T6

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8126	1			T7	337		T13	287		T118	3
valid_sources[0x01]	7607	1			T1	3		T7	307		T13	268
valid_sources[0x02]	8716	1			T7	339		T16	4		T57	3
valid_sources[0x03]	7703	1			T7	350		T13	301		T17	3
valid_sources[0x04]	8606	1			T7	299		T13	248		T14	1
valid_sources[0x05]	7900	1			T7	345		T13	287		T14	3
valid_sources[0x06]	7172	1			T7	293		T13	284		T118	1
valid_sources[0x07]	7220	1			T7	371		T13	297		T103	1
valid_sources[0x08]	6860	1			T7	293		T8	37		T16	1
valid_sources[0x09]	7126	1			T7	319		T13	228		T14	3
valid_sources[0x0a]	7686	1			T7	342		T9	1		T10	21
valid_sources[0x0b]	7066	1			T7	350		T13	278		T14	1
valid_sources[0x0c]	8641	1			T7	314		T16	2		T13	260
valid_sources[0x0d]	7430	1			T7	326		T13	278		T14	2
valid_sources[0x0e]	8237	1			T7	352		T19	5		T13	269
valid_sources[0x0f]	7442	1			T7	333		T13	277		T17	1
valid_sources[0x10]	8870	1			T7	298		T16	8		T13	304
valid_sources[0x11]	7366	1			T7	310		T13	308		T14	3
valid_sources[0x12]	7541	1			T6	1		T7	343		T13	250
valid_sources[0x13]	8294	1			T1	7		T7	306		T13	311
valid_sources[0x14]	8914	1			T7	283		T13	273		T103	1
valid_sources[0x15]	7037	1			T7	332		T13	269		T14	3
valid_sources[0x16]	7348	1			T7	331		T8	20		T13	256
valid_sources[0x17]	8740	1			T7	344		T13	251		T14	1
valid_sources[0x18]	6957	1			T7	330		T13	262		T14	1
valid_sources[0x19]	8790	1			T7	320		T8	16		T13	282
valid_sources[0x1a]	10025	1			T7	316		T13	301		T14	2
valid_sources[0x1b]	7599	1			T7	290		T13	272		T14	4
valid_sources[0x1c]	8603	1			T7	300		T10	1		T13	252
valid_sources[0x1d]	9275	1			T7	381		T20	1		T16	1
valid_sources[0x1e]	7465	1			T7	325		T13	289		T14	1
valid_sources[0x1f]	9055	1			T1	1		T7	316		T13	286
valid_sources[0x20]	7988	1			T7	319		T13	236		T119	1
valid_sources[0x21]	7380	1			T7	324		T13	288		T118	1
valid_sources[0x22]	8245	1			T7	336		T16	2		T13	261
valid_sources[0x23]	7437	1			T7	300		T13	274		T17	2
valid_sources[0x24]	10687	1			T6	1		T7	310		T13	283
valid_sources[0x25]	7698	1			T7	321		T16	2		T13	245
valid_sources[0x26]	7598	1			T7	370		T13	290		T14	2
valid_sources[0x27]	6615	1			T7	315		T16	4		T57	2
valid_sources[0x28]	9669	1			T7	400		T8	66		T16	10
valid_sources[0x29]	9242	1			T7	315		T13	288		T14	2
valid_sources[0x2a]	8066	1			T7	313		T13	251		T14	3
valid_sources[0x2b]	9276	1			T7	325		T16	2		T13	283
valid_sources[0x2c]	9950	1			T1	3		T7	360		T13	299
valid_sources[0x2d]	7490	1			T7	362		T13	282		T14	1
valid_sources[0x2e]	8328	1			T7	365		T13	284		T118	2
valid_sources[0x2f]	9077	1			T7	337		T16	3		T13	288
valid_sources[0x30]	9390	1			T7	309		T13	254		T14	3
valid_sources[0x31]	8092	1			T7	291		T13	249		T14	2
valid_sources[0x32]	8959	1			T7	308		T13	247		T14	6
valid_sources[0x33]	7895	1			T7	300		T13	260		T103	3
valid_sources[0x34]	7488	1			T7	292		T13	258		T103	1
valid_sources[0x35]	6735	1			T1	2		T7	341		T13	322
valid_sources[0x36]	7226	1			T7	289		T10	3		T16	2
valid_sources[0x37]	8480	1			T7	330		T13	271		T17	1
valid_sources[0x38]	7664	1			T7	303		T13	291		T14	3
valid_sources[0x39]	9048	1			T7	281		T13	267		T14	1
valid_sources[0x3a]	7216	1			T7	308		T13	281		T118	1
valid_sources[0x3b]	7113	1			T7	291		T13	293		T14	1
valid_sources[0x3c]	7783	1			T7	296		T13	271		T17	2
valid_sources[0x3d]	8178	1			T7	335		T38	3		T13	287
valid_sources[0x3e]	9985	1			T7	305		T13	274		T118	1
valid_sources[0x3f]	7129	1			T7	296		T13	277		T14	2
valid_sources[0x40]	7739	1			T7	295		T57	1		T13	281
valid_sources[0x41]	8422	1			T7	326		T13	305		T14	2
valid_sources[0x42]	9229	1			T7	339		T13	253		T14	4
valid_sources[0x43]	8667	1			T7	300		T13	274		T14	1
valid_sources[0x44]	7628	1			T1	1		T7	325		T13	280
valid_sources[0x45]	9898	1			T7	295		T13	253		T14	1
valid_sources[0x46]	10355	1			T7	307		T13	330		T14	5
valid_sources[0x47]	7509	1			T7	303		T16	1		T13	290
valid_sources[0x48]	8982	1			T7	324		T13	276		T17	3
valid_sources[0x49]	7003	1			T7	280		T13	273		T118	2
valid_sources[0x4a]	7265	1			T7	305		T13	296		T118	4
valid_sources[0x4b]	7785	1			T7	315		T13	306		T14	2
valid_sources[0x4c]	8168	1			T7	272		T13	224		T118	3
valid_sources[0x4d]	9695	1			T7	322		T13	279		T73	1
valid_sources[0x4e]	8840	1			T7	338		T13	279		T118	2
valid_sources[0x4f]	7732	1			T1	1		T7	306		T13	288
valid_sources[0x50]	8519	1			T7	339		T13	312		T118	3
valid_sources[0x51]	7369	1			T7	322		T13	289		T14	1
valid_sources[0x52]	7524	1			T7	315		T13	277		T118	1
valid_sources[0x53]	7989	1			T7	309		T20	2		T13	282
valid_sources[0x54]	7875	1			T7	329		T13	226		T120	1
valid_sources[0x55]	8451	1			T7	327		T13	287		T14	3
valid_sources[0x56]	7961	1			T7	331		T13	240		T14	2
valid_sources[0x57]	8123	1			T7	300		T13	280		T14	1
valid_sources[0x58]	6730	1			T7	315		T13	299		T14	2
valid_sources[0x59]	7673	1			T7	311		T13	307		T14	3
valid_sources[0x5a]	9033	1			T7	311		T13	314		T118	3
valid_sources[0x5b]	9008	1			T7	332		T16	3		T13	257
valid_sources[0x5c]	7470	1			T7	315		T57	4		T13	277
valid_sources[0x5d]	6872	1			T7	292		T13	324		T103	1
valid_sources[0x5e]	7939	1			T7	305		T16	4		T13	287
valid_sources[0x5f]	7355	1			T7	385		T13	259		T118	1
valid_sources[0x60]	7227	1			T7	366		T13	235		T118	1
valid_sources[0x61]	8209	1			T1	1		T7	324		T13	265
valid_sources[0x62]	8159	1			T7	351		T13	287		T14	1
valid_sources[0x63]	11172	1			T7	314		T16	1		T13	311
valid_sources[0x64]	6833	1			T7	319		T13	293		T118	4
valid_sources[0x65]	7552	1			T7	315		T13	287		T118	1
valid_sources[0x66]	8073	1			T7	266		T13	266		T118	3
valid_sources[0x67]	9384	1			T7	313		T13	275		T118	2
valid_sources[0x68]	7454	1			T7	323		T102	26		T13	243
valid_sources[0x69]	8245	1			T1	4		T7	310		T19	1
valid_sources[0x6a]	8233	1			T7	350		T13	296		T73	1
valid_sources[0x6b]	6956	1			T7	334		T13	302		T118	2
valid_sources[0x6c]	8463	1			T7	332		T13	241		T75	25
valid_sources[0x6d]	7786	1			T7	287		T13	286		T118	2
valid_sources[0x6e]	7426	1			T7	313		T16	1		T13	271
valid_sources[0x6f]	7656	1			T7	344		T13	264		T14	1
valid_sources[0x70]	7288	1			T1	1		T7	371		T13	302
valid_sources[0x71]	7023	1			T7	327		T13	296		T14	1
valid_sources[0x72]	7577	1			T7	324		T13	295		T118	1
valid_sources[0x73]	7853	1			T7	326		T16	1		T13	270
valid_sources[0x74]	9368	1			T7	315		T16	9		T13	274
valid_sources[0x75]	7361	1			T7	281		T16	9		T13	314
valid_sources[0x76]	7466	1			T7	317		T13	283		T14	3
valid_sources[0x77]	7753	1			T7	318		T13	320		T14	5
valid_sources[0x78]	8932	1			T7	321		T13	294		T14	2
valid_sources[0x79]	8947	1			T7	353		T13	299		T14	2
valid_sources[0x7a]	7363	1			T7	300		T13	250		T14	1
valid_sources[0x7b]	7036	1			T7	354		T57	3		T13	248
valid_sources[0x7c]	9150	1			T7	296		T13	296		T14	2
valid_sources[0x7d]	7828	1			T7	319		T13	281		T14	1
valid_sources[0x7e]	7283	1			T7	336		T13	294		T103	1
valid_sources[0x7f]	8769	1			T7	415		T57	2		T13	283
valid_sources[0x80]	7995	1			T7	343		T16	1		T13	295

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

502830

1

T1

7

T2

6

T6

3

values[0x0]

all_enables

biggest_size

751373

1

T7

30363

T13

26174

T15

49593

values[0x1]

all_enables

biggest_size

750571

1

T7

30099

T13

25963

T15

49719

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	143621	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1531596

1

T1

6

T2

20

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	413657	1			T1	16		T2	41		T4	1
values[0x0]	584551	1			T3	2		T5	1		T7	24111
values[0x1]	677009	1			T3	7		T5	2		T7	28180

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62636	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1612581

1

T1

8

T2

24

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6429	1			T7	288		T13	254		T121	1
valid_sources[0x01]	6498	1			T7	338		T13	227		T15	575
valid_sources[0x02]	6531	1			T7	284		T11	1		T13	226
valid_sources[0x03]	6216	1			T7	265		T16	1		T13	241
valid_sources[0x04]	6879	1			T6	2		T7	313		T16	1
valid_sources[0x05]	6980	1			T7	255		T13	216		T45	1
valid_sources[0x06]	6138	1			T7	309		T16	1		T13	254
valid_sources[0x07]	6668	1			T7	254		T9	1		T16	1
valid_sources[0x08]	7167	1			T5	3		T7	253		T16	1
valid_sources[0x09]	6282	1			T7	245		T13	214		T15	301
valid_sources[0x0a]	6961	1			T7	228		T38	1		T13	253
valid_sources[0x0b]	5862	1			T1	1		T7	287		T11	1
valid_sources[0x0c]	6766	1			T7	225		T13	269		T17	1
valid_sources[0x0d]	6567	1			T7	263		T13	249		T45	4
valid_sources[0x0e]	6568	1			T1	1		T7	259		T16	1
valid_sources[0x0f]	6083	1			T7	217		T13	220		T17	1
valid_sources[0x10]	6603	1			T7	213		T11	1		T19	3
valid_sources[0x11]	7208	1			T7	270		T16	1		T13	238
valid_sources[0x12]	6025	1			T7	289		T9	1		T13	206
valid_sources[0x13]	6789	1			T7	311		T13	230		T117	1
valid_sources[0x14]	6615	1			T7	278		T13	214		T15	656
valid_sources[0x15]	6565	1			T7	262		T13	269		T15	782
valid_sources[0x16]	6879	1			T7	241		T13	233		T44	1
valid_sources[0x17]	6191	1			T7	262		T13	261		T15	635
valid_sources[0x18]	5953	1			T7	236		T11	1		T13	234
valid_sources[0x19]	6991	1			T7	209		T13	223		T78	4
valid_sources[0x1a]	6733	1			T7	242		T11	2		T16	1
valid_sources[0x1b]	6617	1			T7	326		T9	1		T13	202
valid_sources[0x1c]	6555	1			T7	229		T13	267		T15	581
valid_sources[0x1d]	6176	1			T7	294		T11	1		T13	217
valid_sources[0x1e]	6629	1			T7	262		T38	1		T39	1
valid_sources[0x1f]	6088	1			T7	275		T13	226		T122	1
valid_sources[0x20]	6834	1			T7	298		T13	267		T123	3
valid_sources[0x21]	6631	1			T7	260		T13	228		T40	1
valid_sources[0x22]	6404	1			T7	265		T16	1		T39	2
valid_sources[0x23]	6152	1			T7	220		T13	236		T15	403
valid_sources[0x24]	6629	1			T7	226		T13	236		T122	2
valid_sources[0x25]	6855	1			T7	247		T39	1		T13	187
valid_sources[0x26]	6463	1			T7	250		T13	242		T17	1
valid_sources[0x27]	6223	1			T7	267		T13	247		T17	1
valid_sources[0x28]	6313	1			T1	2		T7	277		T9	1
valid_sources[0x29]	6212	1			T7	283		T13	229		T15	276
valid_sources[0x2a]	7121	1			T7	285		T39	1		T13	247
valid_sources[0x2b]	7206	1			T7	256		T9	1		T16	1
valid_sources[0x2c]	6060	1			T6	3		T7	270		T13	242
valid_sources[0x2d]	7110	1			T7	325		T13	227		T61	2
valid_sources[0x2e]	6430	1			T7	281		T13	253		T122	1
valid_sources[0x2f]	5967	1			T7	304		T9	1		T13	228
valid_sources[0x30]	6588	1			T3	9		T7	270		T13	227
valid_sources[0x31]	6336	1			T7	294		T39	2		T13	240
valid_sources[0x32]	7016	1			T1	1		T7	256		T16	1
valid_sources[0x33]	6281	1			T7	293		T13	235		T17	1
valid_sources[0x34]	6362	1			T7	244		T16	1		T13	233
valid_sources[0x35]	7282	1			T7	263		T39	1		T13	230
valid_sources[0x36]	7451	1			T7	239		T13	232		T117	1
valid_sources[0x37]	6184	1			T7	294		T11	2		T13	245
valid_sources[0x38]	7658	1			T7	249		T13	258		T123	3
valid_sources[0x39]	7723	1			T7	272		T16	1		T13	249
valid_sources[0x3a]	6303	1			T7	246		T13	212		T78	1
valid_sources[0x3b]	7335	1			T7	331		T13	232		T15	887
valid_sources[0x3c]	6093	1			T6	2		T7	307		T13	216
valid_sources[0x3d]	6418	1			T7	260		T13	244		T61	1
valid_sources[0x3e]	6740	1			T1	1		T7	244		T13	236
valid_sources[0x3f]	7094	1			T7	260		T13	265		T15	964
valid_sources[0x40]	5854	1			T7	304		T9	1		T39	1
valid_sources[0x41]	6266	1			T7	318		T16	1		T13	243
valid_sources[0x42]	7410	1			T7	261		T11	4		T13	237
valid_sources[0x43]	5899	1			T6	6		T7	343		T11	1
valid_sources[0x44]	6409	1			T7	303		T12	6		T13	209
valid_sources[0x45]	7206	1			T7	323		T9	1		T16	1
valid_sources[0x46]	7024	1			T7	318		T13	208		T78	1
valid_sources[0x47]	5830	1			T7	275		T13	226		T15	249
valid_sources[0x48]	5767	1			T7	312		T13	243		T77	1
valid_sources[0x49]	7388	1			T7	320		T13	263		T74	2
valid_sources[0x4a]	6187	1			T7	336		T16	1		T13	220
valid_sources[0x4b]	6552	1			T7	253		T13	238		T44	1
valid_sources[0x4c]	6174	1			T1	1		T7	298		T13	208
valid_sources[0x4d]	6844	1			T7	304		T16	1		T39	1
valid_sources[0x4e]	6230	1			T7	264		T19	11		T39	1
valid_sources[0x4f]	6739	1			T7	223		T16	1		T13	205
valid_sources[0x50]	6418	1			T7	204		T13	231		T78	1
valid_sources[0x51]	6383	1			T7	235		T38	1		T13	231
valid_sources[0x52]	6160	1			T7	279		T13	219		T40	1
valid_sources[0x53]	7920	1			T6	3		T7	320		T16	1
valid_sources[0x54]	5811	1			T1	1		T7	259		T16	1
valid_sources[0x55]	5957	1			T7	216		T13	206		T122	1
valid_sources[0x56]	6112	1			T4	1		T7	256		T11	3
valid_sources[0x57]	5971	1			T7	298		T11	2		T13	249
valid_sources[0x58]	6142	1			T7	267		T13	232		T15	312
valid_sources[0x59]	6060	1			T7	239		T16	1		T13	237
valid_sources[0x5a]	6831	1			T7	261		T13	207		T17	1
valid_sources[0x5b]	6554	1			T7	269		T12	1		T13	252
valid_sources[0x5c]	6334	1			T7	232		T11	1		T13	234
valid_sources[0x5d]	6133	1			T7	224		T39	2		T13	235
valid_sources[0x5e]	6746	1			T7	290		T13	214		T122	1
valid_sources[0x5f]	6205	1			T7	253		T13	276		T124	1
valid_sources[0x60]	7133	1			T7	239		T13	245		T122	2
valid_sources[0x61]	5242	1			T7	276		T13	212		T77	1
valid_sources[0x62]	6889	1			T6	2		T7	221		T19	13
valid_sources[0x63]	6050	1			T7	268		T13	212		T17	1
valid_sources[0x64]	6491	1			T7	286		T13	248		T17	1
valid_sources[0x65]	6743	1			T7	239		T16	1		T13	227
valid_sources[0x66]	6407	1			T7	291		T13	223		T122	1
valid_sources[0x67]	6594	1			T7	298		T13	246		T15	352
valid_sources[0x68]	7016	1			T7	336		T13	262		T17	1
valid_sources[0x69]	6130	1			T7	233		T38	1		T13	237
valid_sources[0x6a]	6615	1			T1	1		T7	283		T13	240
valid_sources[0x6b]	6496	1			T7	281		T13	203		T17	1
valid_sources[0x6c]	6280	1			T7	218		T13	204		T120	3
valid_sources[0x6d]	7041	1			T7	274		T13	255		T78	1
valid_sources[0x6e]	6333	1			T7	244		T38	1		T13	242
valid_sources[0x6f]	6383	1			T7	238		T16	1		T13	204
valid_sources[0x70]	6599	1			T7	234		T11	2		T16	1
valid_sources[0x71]	6753	1			T7	265		T13	250		T15	563
valid_sources[0x72]	7143	1			T7	265		T13	252		T17	1
valid_sources[0x73]	6504	1			T7	268		T57	4		T39	1
valid_sources[0x74]	6381	1			T7	266		T16	1		T13	225
valid_sources[0x75]	6050	1			T7	303		T57	4		T13	224
valid_sources[0x76]	6127	1			T7	278		T13	243		T62	1
valid_sources[0x77]	6871	1			T7	272		T38	1		T13	266
valid_sources[0x78]	6746	1			T7	266		T11	2		T16	1
valid_sources[0x79]	6783	1			T7	309		T13	220		T78	1
valid_sources[0x7a]	6401	1			T7	274		T39	1		T13	228
valid_sources[0x7b]	6025	1			T7	304		T13	230		T40	1
valid_sources[0x7c]	6985	1			T7	247		T13	245		T15	475
valid_sources[0x7d]	5814	1			T7	333		T13	229		T40	2
valid_sources[0x7e]	6788	1			T7	326		T13	258		T44	1
valid_sources[0x7f]	7008	1			T7	319		T9	1		T13	242
valid_sources[0x80]	5946	1			T7	277		T57	1		T13	212

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

385527

1

T1

6

T2

20

T6

21

values[0x0]

all_enables

biggest_size

572939

1

T5

1

T7

23636

T24

4

values[0x1]

all_enables

biggest_size

573130

1

T7

23603

T13

20756

T61

1