Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3645567

1

T1

25

T7

148799

T8

188

full_word

2338386

1

T1

7

T2

4

T6

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5983633	1			T1	32		T2	4		T6	2
auto[TlIntgErrCmd]	98	1			T54	2		T55	3		T56	7
auto[TlIntgErrData]	114	1			T54	4		T55	5		T56	5
auto[TlIntgErrBoth]	108	1			T54	4		T55	2		T56	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

929731

1

T1

32

T2

4

T6

2

auto[1]

5054222

1

T7

205598

T13

173982

T15

339171

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	378202	1			T1	25		T7	15259		T8	188
auto[TlIntgErrNone]	partial	auto[1]	3267069	1			T7	133540		T13	112032		T15	220629
auto[TlIntgErrNone]	full_word	auto[0]	551383	1			T1	7		T2	4		T6	2
auto[TlIntgErrNone]	full_word	auto[1]	1786979	1			T7	72058		T13	61950		T15	118542
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T55	1		T56	2		T107	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T54	2		T55	2		T56	5
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T108	1		T109	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T54	3		T55	3		T56	3
auto[TlIntgErrData]	partial	auto[1]	47	1			T55	2		T56	1		T107	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T54	1		T111	2		T112	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T56	1		T107	2		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T54	2		T55	1		T56	4
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T54	1		T56	4		T107	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T54	1		T55	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T114	1		T108	1		T109	1