Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_kmac_cg	100.00	1	100	1	64	64

---

Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_kmac_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00

Variables for Group Instance rom_ctrl_kmac_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_kmac_done	3	0	3	100.00	100	1	1	0
cp_kmac_ready	4	0	4	100.00	100	1	1	0

Summary for Variable cp_kmac_done

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_kmac_done

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
kmac_first	354	1			T2	3		T3	1		T5	1
same_cycle	5	1			T44	1		T45	1		T46	1
rom_first	1171	1			T1	1		T2	25		T4	2

---

Summary for Variable cp_kmac_ready

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_kmac_ready

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stall_repeat	13891652	1			T1	75057		T2	115370		T4	8180
stall_long	1287243	1			T1	9000		T116	224411		T63	8967
stall_1	6549591	1			T1	1481		T2	231308		T4	16353
zero_delay_5	11645901	1			T2	29086		T3	16372		T4	2078