Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2562775

1

T3

7

T4

3

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	665002	1			T3	66		T4	3		T5	44
values[0x0]	968818	1			T12	10372		T14	10528		T15	19765
values[0x1]	1003152	1			T12	10831		T14	10687		T15	20579

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2596216

1

T3

43

T4

3

T5

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9364	1			T12	126		T14	123		T15	206
valid_sources[0x01]	9563	1			T11	1		T12	97		T14	114
valid_sources[0x02]	9416	1			T11	1		T12	123		T58	5
valid_sources[0x03]	10399	1			T3	2		T66	1		T67	1
valid_sources[0x04]	9571	1			T20	2		T68	2		T11	4
valid_sources[0x05]	10407	1			T20	1		T11	3		T12	100
valid_sources[0x06]	9830	1			T11	2		T12	103		T59	1
valid_sources[0x07]	10342	1			T67	1		T11	2		T12	136
valid_sources[0x08]	11025	1			T11	4		T12	132		T58	7
valid_sources[0x09]	10770	1			T12	119		T59	1		T14	123
valid_sources[0x0a]	10765	1			T13	1		T12	102		T59	1
valid_sources[0x0b]	10602	1			T11	1		T12	101		T14	98
valid_sources[0x0c]	10311	1			T20	1		T12	107		T14	113
valid_sources[0x0d]	11842	1			T12	107		T14	129		T15	169
valid_sources[0x0e]	8478	1			T5	4		T11	3		T12	104
valid_sources[0x0f]	9319	1			T13	1		T12	132		T59	1
valid_sources[0x10]	10407	1			T11	1		T12	117		T14	118
valid_sources[0x11]	10867	1			T11	1		T12	97		T14	110
valid_sources[0x12]	11247	1			T11	1		T12	108		T59	1
valid_sources[0x13]	10759	1			T67	1		T11	1		T12	125
valid_sources[0x14]	10587	1			T66	1		T11	1		T12	131
valid_sources[0x15]	11195	1			T3	1		T5	6		T11	2
valid_sources[0x16]	10491	1			T11	3		T12	111		T14	142
valid_sources[0x17]	11164	1			T67	2		T11	1		T12	98
valid_sources[0x18]	10009	1			T66	1		T12	110		T14	96
valid_sources[0x19]	10471	1			T3	2		T11	2		T12	111
valid_sources[0x1a]	11015	1			T5	2		T11	1		T12	99
valid_sources[0x1b]	10032	1			T11	2		T12	118		T14	133
valid_sources[0x1c]	9947	1			T20	2		T12	119		T14	102
valid_sources[0x1d]	9636	1			T11	3		T12	115		T14	90
valid_sources[0x1e]	10987	1			T7	24		T11	1		T12	104
valid_sources[0x1f]	8590	1			T11	2		T12	106		T59	2
valid_sources[0x20]	11033	1			T20	1		T11	1		T12	104
valid_sources[0x21]	9561	1			T20	3		T11	1		T12	90
valid_sources[0x22]	11123	1			T11	1		T12	134		T59	2
valid_sources[0x23]	9832	1			T68	3		T11	1		T12	110
valid_sources[0x24]	12386	1			T3	1		T11	3		T12	134
valid_sources[0x25]	10030	1			T3	2		T11	2		T12	130
valid_sources[0x26]	9869	1			T3	1		T12	115		T14	116
valid_sources[0x27]	8588	1			T3	1		T66	1		T11	1
valid_sources[0x28]	9226	1			T3	1		T11	1		T12	96
valid_sources[0x29]	10484	1			T9	1		T66	1		T67	1
valid_sources[0x2a]	10821	1			T9	1		T11	3		T12	94
valid_sources[0x2b]	9435	1			T11	2		T12	98		T59	2
valid_sources[0x2c]	9667	1			T12	102		T58	5		T14	104
valid_sources[0x2d]	9135	1			T67	2		T11	3		T12	124
valid_sources[0x2e]	9930	1			T11	3		T12	143		T14	115
valid_sources[0x2f]	10975	1			T5	2		T13	3		T66	1
valid_sources[0x30]	10026	1			T11	3		T12	103		T14	120
valid_sources[0x31]	9306	1			T3	1		T67	4		T11	2
valid_sources[0x32]	10772	1			T9	1		T11	2		T12	81
valid_sources[0x33]	10382	1			T13	3		T11	3		T12	104
valid_sources[0x34]	11501	1			T3	1		T9	1		T11	2
valid_sources[0x35]	11139	1			T11	2		T12	94		T59	1
valid_sources[0x36]	10426	1			T12	114		T14	109		T15	254
valid_sources[0x37]	9752	1			T9	1		T11	3		T12	95
valid_sources[0x38]	10620	1			T3	1		T12	111		T14	124
valid_sources[0x39]	10992	1			T11	6		T12	125		T14	124
valid_sources[0x3a]	10114	1			T3	1		T66	1		T11	4
valid_sources[0x3b]	10520	1			T3	1		T66	1		T11	4
valid_sources[0x3c]	9647	1			T11	2		T12	125		T14	104
valid_sources[0x3d]	9845	1			T12	103		T58	2		T59	2
valid_sources[0x3e]	9504	1			T12	111		T14	75		T15	207
valid_sources[0x3f]	12921	1			T11	1		T12	101		T58	2
valid_sources[0x40]	10278	1			T3	1		T11	2		T12	109
valid_sources[0x41]	10462	1			T3	1		T11	1		T12	112
valid_sources[0x42]	9836	1			T20	3		T12	122		T14	82
valid_sources[0x43]	9105	1			T12	121		T14	122		T15	274
valid_sources[0x44]	9816	1			T12	112		T14	108		T15	198
valid_sources[0x45]	10096	1			T3	1		T20	2		T11	1
valid_sources[0x46]	9417	1			T8	14		T67	2		T11	1
valid_sources[0x47]	10672	1			T12	121		T14	122		T15	186
valid_sources[0x48]	9112	1			T20	2		T11	2		T12	121
valid_sources[0x49]	11082	1			T3	1		T11	1		T12	104
valid_sources[0x4a]	9833	1			T11	1		T12	133		T14	99
valid_sources[0x4b]	10548	1			T3	1		T67	2		T11	1
valid_sources[0x4c]	9736	1			T3	1		T20	1		T12	103
valid_sources[0x4d]	10222	1			T3	1		T12	107		T14	94
valid_sources[0x4e]	10592	1			T3	1		T20	1		T11	3
valid_sources[0x4f]	9523	1			T11	3		T12	107		T14	121
valid_sources[0x50]	9187	1			T68	3		T11	1		T12	124
valid_sources[0x51]	8713	1			T3	1		T66	1		T11	1
valid_sources[0x52]	10056	1			T11	1		T12	125		T14	96
valid_sources[0x53]	10244	1			T12	99		T57	31		T58	2
valid_sources[0x54]	8661	1			T11	1		T12	101		T14	106
valid_sources[0x55]	10917	1			T3	1		T20	4		T12	106
valid_sources[0x56]	12965	1			T11	1		T12	97		T14	109
valid_sources[0x57]	11230	1			T5	4		T11	1		T12	98
valid_sources[0x58]	10276	1			T12	123		T14	110		T15	217
valid_sources[0x59]	9928	1			T3	1		T67	1		T68	3
valid_sources[0x5a]	12243	1			T11	2		T12	141		T58	1
valid_sources[0x5b]	10232	1			T12	134		T59	1		T14	100
valid_sources[0x5c]	9682	1			T20	2		T11	2		T12	121
valid_sources[0x5d]	11762	1			T68	4		T11	1		T12	120
valid_sources[0x5e]	11240	1			T11	2		T12	111		T59	1
valid_sources[0x5f]	10271	1			T3	1		T12	101		T14	120
valid_sources[0x60]	10627	1			T3	1		T11	1		T12	103
valid_sources[0x61]	9644	1			T5	1		T9	1		T20	4
valid_sources[0x62]	10732	1			T20	2		T11	1		T12	122
valid_sources[0x63]	9938	1			T66	1		T11	3		T12	114
valid_sources[0x64]	11081	1			T20	3		T11	2		T12	121
valid_sources[0x65]	10511	1			T11	2		T12	115		T14	113
valid_sources[0x66]	9194	1			T67	2		T12	121		T14	116
valid_sources[0x67]	11062	1			T20	4		T11	1		T12	110
valid_sources[0x68]	10586	1			T20	4		T11	1		T12	103
valid_sources[0x69]	10044	1			T3	1		T5	1		T11	2
valid_sources[0x6a]	10262	1			T20	3		T66	3		T11	1
valid_sources[0x6b]	12336	1			T11	1		T12	113		T14	123
valid_sources[0x6c]	11226	1			T3	1		T66	1		T11	2
valid_sources[0x6d]	11511	1			T11	1		T12	102		T58	2
valid_sources[0x6e]	10680	1			T20	3		T11	1		T12	114
valid_sources[0x6f]	10459	1			T66	1		T11	4		T12	95
valid_sources[0x70]	9733	1			T13	3		T11	2		T12	114
valid_sources[0x71]	9901	1			T20	1		T11	3		T12	130
valid_sources[0x72]	11153	1			T66	1		T68	1		T11	1
valid_sources[0x73]	9510	1			T13	1		T67	1		T11	1
valid_sources[0x74]	10768	1			T67	2		T11	2		T12	112
valid_sources[0x75]	10297	1			T66	1		T11	1		T12	125
valid_sources[0x76]	8988	1			T11	1		T12	133		T59	2
valid_sources[0x77]	10016	1			T3	1		T66	2		T11	1
valid_sources[0x78]	9976	1			T11	3		T12	102		T14	103
valid_sources[0x79]	10602	1			T20	4		T11	1		T12	138
valid_sources[0x7a]	11009	1			T3	1		T11	1		T12	99
valid_sources[0x7b]	10577	1			T13	2		T20	1		T12	90
valid_sources[0x7c]	9264	1			T20	4		T11	1		T12	123
valid_sources[0x7d]	10211	1			T11	1		T12	120		T14	111
valid_sources[0x7e]	9817	1			T20	5		T66	1		T11	1
valid_sources[0x7f]	12135	1			T9	1		T11	1		T12	116
valid_sources[0x80]	9812	1			T3	2		T9	2		T66	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

643301

1

T3

7

T4

3

T5

1

values[0x0]

all_enables

biggest_size

960215

1

T12

10274

T14

10440

T15

19605

values[0x1]

all_enables

biggest_size

959259

1

T12

10377

T14

10172

T15

19686

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1958257

1

T1

1

T2

1

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	525251	1			T2	1		T3	32		T4	32
values[0x0]	749696	1			T1	3		T10	2		T21	4
values[0x1]	865063	1			T1	1		T21	4		T71	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	78792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2061218

1

T1

1

T2

1

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9074	1			T12	200		T14	123		T15	198
valid_sources[0x01]	8817	1			T12	5		T40	1		T14	99
valid_sources[0x02]	8931	1			T6	1		T12	296		T39	1
valid_sources[0x03]	7918	1			T18	3		T12	10		T14	110
valid_sources[0x04]	8150	1			T6	2		T13	1		T12	3
valid_sources[0x05]	9014	1			T19	1		T67	32		T12	246
valid_sources[0x06]	8509	1			T12	145		T14	103		T15	189
valid_sources[0x07]	9070	1			T19	2		T12	133		T58	1
valid_sources[0x08]	8081	1			T12	4		T40	1		T14	104
valid_sources[0x09]	8332	1			T12	318		T58	1		T14	100
valid_sources[0x0a]	8526	1			T12	94		T14	100		T15	204
valid_sources[0x0b]	7878	1			T68	1		T12	57		T14	86
valid_sources[0x0c]	8139	1			T12	64		T14	81		T15	177
valid_sources[0x0d]	8725	1			T12	104		T14	74		T15	159
valid_sources[0x0e]	7793	1			T18	1		T12	94		T40	1
valid_sources[0x0f]	9147	1			T13	1		T12	200		T39	4
valid_sources[0x10]	8041	1			T12	5		T14	99		T15	175
valid_sources[0x11]	8493	1			T12	587		T14	88		T15	207
valid_sources[0x12]	7828	1			T68	1		T12	70		T58	1
valid_sources[0x13]	8369	1			T12	181		T14	94		T15	208
valid_sources[0x14]	7612	1			T12	8		T58	1		T14	86
valid_sources[0x15]	8297	1			T68	4		T12	5		T14	105
valid_sources[0x16]	7872	1			T12	191		T14	83		T15	199
valid_sources[0x17]	7956	1			T7	3		T12	105		T40	1
valid_sources[0x18]	8267	1			T68	1		T12	5		T58	2
valid_sources[0x19]	7917	1			T12	245		T14	80		T15	189
valid_sources[0x1a]	8673	1			T68	2		T12	97		T14	105
valid_sources[0x1b]	7995	1			T12	78		T14	106		T15	196
valid_sources[0x1c]	8326	1			T18	1		T12	5		T14	89
valid_sources[0x1d]	8271	1			T12	6		T14	88		T15	174
valid_sources[0x1e]	7629	1			T7	1		T12	3		T14	96
valid_sources[0x1f]	8400	1			T6	1		T12	312		T14	115
valid_sources[0x20]	7992	1			T7	1		T12	116		T40	1
valid_sources[0x21]	8708	1			T12	5		T58	1		T14	81
valid_sources[0x22]	7674	1			T12	6		T14	89		T15	198
valid_sources[0x23]	9022	1			T12	3		T14	106		T15	181
valid_sources[0x24]	7990	1			T12	45		T14	92		T15	193
valid_sources[0x25]	7688	1			T12	20		T14	99		T15	170
valid_sources[0x26]	7702	1			T18	2		T12	66		T14	98
valid_sources[0x27]	7928	1			T6	2		T7	1		T68	1
valid_sources[0x28]	8676	1			T12	6		T58	1		T14	88
valid_sources[0x29]	8648	1			T19	1		T12	16		T14	86
valid_sources[0x2a]	8010	1			T12	187		T58	1		T14	90
valid_sources[0x2b]	8741	1			T7	1		T12	123		T58	1
valid_sources[0x2c]	9079	1			T12	45		T14	101		T15	151
valid_sources[0x2d]	8361	1			T12	96		T14	108		T15	183
valid_sources[0x2e]	8400	1			T5	1		T6	2		T12	5
valid_sources[0x2f]	8774	1			T12	61		T14	101		T15	213
valid_sources[0x30]	8678	1			T12	8		T14	112		T15	169
valid_sources[0x31]	8667	1			T12	10		T58	1		T14	104
valid_sources[0x32]	8525	1			T7	1		T12	180		T14	98
valid_sources[0x33]	8230	1			T12	77		T14	103		T15	192
valid_sources[0x34]	7987	1			T12	245		T14	91		T15	160
valid_sources[0x35]	8102	1			T4	2		T7	1		T66	4
valid_sources[0x36]	8222	1			T7	1		T12	141		T14	86
valid_sources[0x37]	8687	1			T5	1		T12	301		T14	101
valid_sources[0x38]	8749	1			T13	2		T12	8		T14	109
valid_sources[0x39]	8233	1			T12	193		T14	84		T15	184
valid_sources[0x3a]	8320	1			T6	1		T12	10		T14	85
valid_sources[0x3b]	8435	1			T12	3		T14	82		T15	186
valid_sources[0x3c]	8528	1			T7	1		T12	243		T14	99
valid_sources[0x3d]	8094	1			T7	2		T18	1		T12	10
valid_sources[0x3e]	8225	1			T1	1		T12	20		T58	1
valid_sources[0x3f]	8207	1			T12	1		T61	1		T14	89
valid_sources[0x40]	8340	1			T6	3		T12	114		T14	87
valid_sources[0x41]	8917	1			T68	1		T12	445		T14	92
valid_sources[0x42]	7790	1			T68	1		T18	1		T12	4
valid_sources[0x43]	8402	1			T12	7		T14	84		T15	195
valid_sources[0x44]	8576	1			T19	1		T12	202		T58	1
valid_sources[0x45]	8087	1			T71	19		T12	94		T14	104
valid_sources[0x46]	8001	1			T10	2		T12	16		T14	89
valid_sources[0x47]	8158	1			T12	156		T40	1		T14	81
valid_sources[0x48]	8006	1			T1	1		T4	1		T12	121
valid_sources[0x49]	8727	1			T19	2		T12	108		T14	111
valid_sources[0x4a]	9244	1			T4	3		T12	73		T14	85
valid_sources[0x4b]	8278	1			T12	58		T14	91		T15	173
valid_sources[0x4c]	8929	1			T12	189		T14	72		T15	184
valid_sources[0x4d]	8604	1			T12	139		T14	76		T15	186
valid_sources[0x4e]	8014	1			T12	94		T14	101		T15	187
valid_sources[0x4f]	7819	1			T4	2		T12	3		T58	1
valid_sources[0x50]	8339	1			T19	1		T12	181		T14	103
valid_sources[0x51]	8523	1			T12	32		T14	88		T15	174
valid_sources[0x52]	8158	1			T12	3		T14	84		T15	191
valid_sources[0x53]	8030	1			T18	1		T12	167		T14	94
valid_sources[0x54]	9102	1			T4	1		T12	322		T14	91
valid_sources[0x55]	8387	1			T6	1		T7	1		T12	50
valid_sources[0x56]	8183	1			T7	1		T12	182		T14	101
valid_sources[0x57]	9352	1			T13	1		T12	6		T40	1
valid_sources[0x58]	7676	1			T4	2		T66	7		T12	6
valid_sources[0x59]	8045	1			T12	11		T14	85		T15	178
valid_sources[0x5a]	8021	1			T12	93		T58	1		T14	82
valid_sources[0x5b]	8247	1			T12	2		T40	2		T14	90
valid_sources[0x5c]	8904	1			T12	424		T14	96		T15	171
valid_sources[0x5d]	8215	1			T7	1		T12	5		T14	86
valid_sources[0x5e]	8572	1			T3	19		T18	1		T12	228
valid_sources[0x5f]	7805	1			T12	249		T14	90		T15	185
valid_sources[0x60]	7714	1			T12	10		T14	101		T15	178
valid_sources[0x61]	9310	1			T12	297		T14	89		T15	184
valid_sources[0x62]	8359	1			T4	1		T12	12		T14	90
valid_sources[0x63]	8625	1			T12	235		T39	1		T14	93
valid_sources[0x64]	8229	1			T12	13		T14	88		T15	181
valid_sources[0x65]	7810	1			T13	1		T12	19		T14	104
valid_sources[0x66]	8121	1			T5	2		T12	173		T14	75
valid_sources[0x67]	8818	1			T12	100		T14	98		T15	170
valid_sources[0x68]	9903	1			T9	22		T18	1		T12	519
valid_sources[0x69]	7947	1			T5	4		T18	1		T12	6
valid_sources[0x6a]	8205	1			T7	1		T12	14		T39	10
valid_sources[0x6b]	8993	1			T12	103		T14	108		T15	181
valid_sources[0x6c]	8730	1			T4	7		T19	2		T12	6
valid_sources[0x6d]	8460	1			T12	11		T14	89		T15	219
valid_sources[0x6e]	8503	1			T12	456		T14	87		T15	151
valid_sources[0x6f]	7927	1			T18	1		T12	50		T58	1
valid_sources[0x70]	8350	1			T4	1		T12	4		T14	83
valid_sources[0x71]	8816	1			T1	1		T68	1		T12	3
valid_sources[0x72]	9114	1			T12	19		T14	86		T15	175
valid_sources[0x73]	7813	1			T12	148		T14	92		T15	157
valid_sources[0x74]	8441	1			T19	1		T18	2		T12	123
valid_sources[0x75]	8309	1			T13	2		T18	1		T12	104
valid_sources[0x76]	8918	1			T68	2		T12	358		T14	86
valid_sources[0x77]	8804	1			T68	1		T12	13		T40	1
valid_sources[0x78]	7843	1			T12	352		T14	102		T15	201
valid_sources[0x79]	8821	1			T7	1		T13	1		T12	145
valid_sources[0x7a]	8321	1			T12	220		T40	1		T14	80
valid_sources[0x7b]	8654	1			T18	1		T12	236		T14	85
valid_sources[0x7c]	8666	1			T5	2		T12	14		T14	94
valid_sources[0x7d]	8265	1			T12	400		T14	105		T15	218
valid_sources[0x7e]	8343	1			T68	1		T12	11		T58	1
valid_sources[0x7f]	8768	1			T6	1		T12	71		T14	94
valid_sources[0x80]	8385	1			T68	1		T12	16		T14	87

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

490623

1

T2

1

T3

16

T4

17

values[0x0]

all_enables

biggest_size

734893

1

T1

1

T71

1

T12

9391

values[0x1]

all_enables

biggest_size

732741

1

T21

1

T71

3

T12

9075