Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4660579

1

T3

59

T5

43

T7

85

full_word

2992278

1

T3

7

T4

2

T5

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7652557	1			T3	66		T4	2		T5	44
auto[TlIntgErrCmd]	93	1			T63	4		T64	5		T65	4
auto[TlIntgErrData]	104	1			T63	5		T64	9		T65	10
auto[TlIntgErrBoth]	103	1			T63	1		T64	6		T65	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1182989

1

T3

66

T4

2

T5

44

auto[1]

6469868

1

T12

68761

T14

73546

T15

129131

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	477728	1			T3	59		T5	43		T7	85
auto[TlIntgErrNone]	partial	auto[1]	4182571	1			T12	44187		T14	48712		T15	82630
auto[TlIntgErrNone]	full_word	auto[0]	705135	1			T3	7		T4	2		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	2287123	1			T12	24574		T14	24834		T15	46501
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T63	1		T65	2		T120	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T63	3		T64	4		T65	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T64	1		T65	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T119	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T63	2		T64	3		T65	3
auto[TlIntgErrData]	partial	auto[1]	55	1			T63	3		T64	6		T65	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T65	1		T116	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T65	1		T117	2		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T64	4		T65	3		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T63	1		T64	1		T65	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T118	1		T122	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T64	1		T117	1		T123	1