Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2195361

1

T2

24

T5

114

T6

67

full_word

1370465

1

T2

1

T5

11

T6

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3565516	1			T2	25		T5	125		T6	71
auto[TlIntgErrCmd]	108	1			T64	9		T65	11		T66	4
auto[TlIntgErrData]	100	1			T64	6		T65	6		T66	4
auto[TlIntgErrBoth]	102	1			T64	5		T65	3		T66	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

555412

1

T2

25

T5

125

T6

71

auto[1]

3010414

1

T13

214693

T16

710875

T17

219859

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	231387	1			T2	24		T5	114		T6	67
auto[TlIntgErrNone]	partial	auto[1]	1963686	1			T13	138949		T16	460564		T17	143926
auto[TlIntgErrNone]	full_word	auto[0]	323881	1			T2	1		T5	11		T6	4
auto[TlIntgErrNone]	full_word	auto[1]	1046562	1			T13	75744		T16	250311		T17	75933
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T64	3		T65	4		T66	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T64	5		T65	4		T66	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T64	1		T65	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T65	2		T131	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T64	6		T65	1		T126	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T65	4		T66	3		T126	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T65	1		T66	1		T123	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T126	1		T129	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T64	3		T65	1		T126	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T64	2		T65	2		T66	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T127	1		T133	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T129	1		T131	1		-	-