Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2526282

1

T4

270

T7

83726

T11

106

full_word

1623030

1

T1

6

T3

4

T4

33

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4149032	1			T1	6		T3	4		T4	303
auto[TlIntgErrCmd]	89	1			T53	7		T54	7		T55	4
auto[TlIntgErrData]	80	1			T53	4		T54	4		T55	6
auto[TlIntgErrBoth]	111	1			T53	9		T54	9		T55	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

654016

1

T1

6

T3

4

T4

303

auto[1]

3495296

1

T7

116000

T13

521878

T14

72677

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	269504	1			T4	270		T7	8628		T11	106
auto[TlIntgErrNone]	partial	auto[1]	2256522	1			T7	75098		T13	333380		T14	48155
auto[TlIntgErrNone]	full_word	auto[0]	384394	1			T1	6		T3	4		T4	33
auto[TlIntgErrNone]	full_word	auto[1]	1238612	1			T7	40902		T13	188498		T14	24522
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T53	1		T55	1		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T53	5		T54	6		T55	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T113	1		T118	1		T115	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T53	1		T54	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T53	2		T54	3		T55	3
auto[TlIntgErrData]	partial	auto[1]	33	1			T53	2		T54	1		T55	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T55	1		T120	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T113	1		T121	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T53	3		T54	4		T55	4
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T53	5		T54	3		T55	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T53	1		T54	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T54	1		T116	1		T123	1