Unified Coverage Report :: Module :: prim_generic_rom

Module : prim_generic_rom

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	66.67				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic	88.89	66.67				100.00	100.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	66.67				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	66.67				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_rom

	Line No.	Total	Covered	Percent
TOTAL		3	2	66.67
CONT_ASSIGN	22	1	0	0.00
ALWAYS	27	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' or '../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	0	1
27	1	1
28	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_rom

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	27	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' or '../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	27	if (req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_rom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
noXOnCsI	83654402	83654402	0	0

noXOnCsI

Name	Attempts	Real Successes	Failures	Incomplete
Total	83654402	83654402	0	0
T1	182270	182270	0	0
T2	33145	33145	0	0
T3	993252	993252	0	0
T4	99200	99200	0	0
T5	16502	16502	0	0
T6	180697	180697	0	0
T7	215686	215686	0	0
T8	27164	27164	0	0
T9	16748	16748	0	0
T10	16731	16731	0	0