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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.89 91.85 97.68 100.00 98.28 97.45 98.37


Total test records in report: 410
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T32 /workspace/coverage/default/0.rom_ctrl_sec_cm.1517498215 Aug 12 06:19:09 PM PDT 24 Aug 12 06:21:13 PM PDT 24 4325969113 ps
T308 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1884923718 Aug 12 06:19:37 PM PDT 24 Aug 12 06:19:57 PM PDT 24 346424065 ps
T309 /workspace/coverage/default/5.rom_ctrl_alert_test.2403120637 Aug 12 06:19:17 PM PDT 24 Aug 12 06:19:27 PM PDT 24 272590919 ps
T310 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2100798727 Aug 12 06:19:47 PM PDT 24 Aug 12 06:19:59 PM PDT 24 508547258 ps
T311 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3538100320 Aug 12 06:19:23 PM PDT 24 Aug 12 06:19:36 PM PDT 24 266922059 ps
T312 /workspace/coverage/default/31.rom_ctrl_stress_all.1104098933 Aug 12 06:19:39 PM PDT 24 Aug 12 06:19:59 PM PDT 24 1362080257 ps
T313 /workspace/coverage/default/10.rom_ctrl_alert_test.2066162343 Aug 12 06:19:21 PM PDT 24 Aug 12 06:19:29 PM PDT 24 180481773 ps
T314 /workspace/coverage/default/12.rom_ctrl_alert_test.3196343779 Aug 12 06:19:20 PM PDT 24 Aug 12 06:19:31 PM PDT 24 256775205 ps
T315 /workspace/coverage/default/25.rom_ctrl_alert_test.3271719773 Aug 12 06:19:39 PM PDT 24 Aug 12 06:19:47 PM PDT 24 663311615 ps
T316 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2577227590 Aug 12 06:19:26 PM PDT 24 Aug 12 06:26:11 PM PDT 24 29630825650 ps
T317 /workspace/coverage/default/30.rom_ctrl_alert_test.3715209633 Aug 12 06:19:45 PM PDT 24 Aug 12 06:19:54 PM PDT 24 172624191 ps
T318 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1816875254 Aug 12 06:19:54 PM PDT 24 Aug 12 06:24:53 PM PDT 24 24814582023 ps
T319 /workspace/coverage/default/11.rom_ctrl_stress_all.1147595267 Aug 12 06:19:17 PM PDT 24 Aug 12 06:19:42 PM PDT 24 1101053552 ps
T320 /workspace/coverage/default/36.rom_ctrl_stress_all.3762184124 Aug 12 06:19:43 PM PDT 24 Aug 12 06:20:12 PM PDT 24 532833155 ps
T321 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4251597304 Aug 12 06:19:50 PM PDT 24 Aug 12 06:20:02 PM PDT 24 551447405 ps
T27 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.548151902 Aug 12 05:03:40 PM PDT 24 Aug 12 05:06:15 PM PDT 24 379969922 ps
T72 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2668112299 Aug 12 05:03:31 PM PDT 24 Aug 12 05:03:44 PM PDT 24 721671583 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.398631673 Aug 12 05:03:17 PM PDT 24 Aug 12 05:03:31 PM PDT 24 1418629345 ps
T120 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2767310699 Aug 12 05:03:08 PM PDT 24 Aug 12 05:03:16 PM PDT 24 333595596 ps
T114 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2210537517 Aug 12 05:03:09 PM PDT 24 Aug 12 05:03:17 PM PDT 24 260334564 ps
T322 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2670322310 Aug 12 05:03:09 PM PDT 24 Aug 12 05:03:19 PM PDT 24 993176383 ps
T323 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2767598248 Aug 12 05:03:06 PM PDT 24 Aug 12 05:03:16 PM PDT 24 506214143 ps
T84 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2655099284 Aug 12 05:03:27 PM PDT 24 Aug 12 05:03:42 PM PDT 24 3946307152 ps
T85 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.968941779 Aug 12 05:03:29 PM PDT 24 Aug 12 05:04:14 PM PDT 24 1029636545 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.800828814 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:17 PM PDT 24 293404756 ps
T28 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1033133930 Aug 12 05:03:18 PM PDT 24 Aug 12 05:03:29 PM PDT 24 763101311 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.965740501 Aug 12 05:03:27 PM PDT 24 Aug 12 05:03:35 PM PDT 24 331621470 ps
T54 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2988879123 Aug 12 05:03:05 PM PDT 24 Aug 12 05:04:29 PM PDT 24 1297313518 ps
T55 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1714103649 Aug 12 05:03:29 PM PDT 24 Aug 12 05:04:53 PM PDT 24 288667235 ps
T324 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1921198641 Aug 12 05:03:12 PM PDT 24 Aug 12 05:03:23 PM PDT 24 593350160 ps
T56 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2271594377 Aug 12 05:03:09 PM PDT 24 Aug 12 05:05:46 PM PDT 24 1208999062 ps
T121 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4243667706 Aug 12 05:03:14 PM PDT 24 Aug 12 05:03:32 PM PDT 24 3139156895 ps
T87 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3900217554 Aug 12 05:03:16 PM PDT 24 Aug 12 05:03:54 PM PDT 24 3131536804 ps
T57 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4140489376 Aug 12 05:03:14 PM PDT 24 Aug 12 05:05:48 PM PDT 24 775193539 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3955948166 Aug 12 05:03:05 PM PDT 24 Aug 12 05:03:17 PM PDT 24 763326961 ps
T53 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.120607648 Aug 12 05:03:06 PM PDT 24 Aug 12 05:03:20 PM PDT 24 1123357068 ps
T58 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1271502410 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:17 PM PDT 24 723843270 ps
T325 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.833768921 Aug 12 05:03:16 PM PDT 24 Aug 12 05:03:24 PM PDT 24 176030310 ps
T59 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3722434421 Aug 12 05:03:25 PM PDT 24 Aug 12 05:03:39 PM PDT 24 516613652 ps
T326 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3866595856 Aug 12 05:03:10 PM PDT 24 Aug 12 05:04:07 PM PDT 24 3208668821 ps
T89 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.723030070 Aug 12 05:03:12 PM PDT 24 Aug 12 05:03:56 PM PDT 24 2026422933 ps
T327 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3508069276 Aug 12 05:03:11 PM PDT 24 Aug 12 05:03:20 PM PDT 24 171172914 ps
T74 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2160545443 Aug 12 05:03:31 PM PDT 24 Aug 12 05:03:40 PM PDT 24 194648835 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.390138865 Aug 12 05:03:36 PM PDT 24 Aug 12 05:06:18 PM PDT 24 491862057 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1958030295 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:16 PM PDT 24 766770372 ps
T83 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.893137224 Aug 12 05:03:27 PM PDT 24 Aug 12 05:03:38 PM PDT 24 1062423718 ps
T116 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2826797603 Aug 12 05:03:24 PM PDT 24 Aug 12 05:03:33 PM PDT 24 168253524 ps
T328 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2959537165 Aug 12 05:03:26 PM PDT 24 Aug 12 05:03:42 PM PDT 24 2024700011 ps
T329 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3198005112 Aug 12 05:03:16 PM PDT 24 Aug 12 05:03:30 PM PDT 24 506814521 ps
T124 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2892117049 Aug 12 05:03:13 PM PDT 24 Aug 12 05:05:44 PM PDT 24 2131798759 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3971934638 Aug 12 05:03:16 PM PDT 24 Aug 12 05:04:14 PM PDT 24 1501612584 ps
T330 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4123688806 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:19 PM PDT 24 1030574555 ps
T331 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2068007930 Aug 12 05:03:24 PM PDT 24 Aug 12 05:03:39 PM PDT 24 250055181 ps
T332 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3459149193 Aug 12 05:03:11 PM PDT 24 Aug 12 05:03:19 PM PDT 24 175002738 ps
T117 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2547842714 Aug 12 05:03:27 PM PDT 24 Aug 12 05:03:38 PM PDT 24 517067296 ps
T122 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2560103097 Aug 12 05:03:13 PM PDT 24 Aug 12 05:05:55 PM PDT 24 1146041479 ps
T91 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3844271210 Aug 12 05:03:15 PM PDT 24 Aug 12 05:03:52 PM PDT 24 2857382227 ps
T92 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3990815996 Aug 12 05:03:27 PM PDT 24 Aug 12 05:03:37 PM PDT 24 254823256 ps
T118 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.26811269 Aug 12 05:03:12 PM PDT 24 Aug 12 05:03:21 PM PDT 24 436500163 ps
T119 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1353311765 Aug 12 05:03:27 PM PDT 24 Aug 12 05:03:37 PM PDT 24 339652215 ps
T333 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.564796850 Aug 12 05:03:12 PM PDT 24 Aug 12 05:03:48 PM PDT 24 1089800590 ps
T334 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.219161344 Aug 12 05:03:20 PM PDT 24 Aug 12 05:03:32 PM PDT 24 662147215 ps
T335 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3596575837 Aug 12 05:03:14 PM PDT 24 Aug 12 05:03:24 PM PDT 24 252019653 ps
T131 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4167239587 Aug 12 05:03:26 PM PDT 24 Aug 12 05:04:57 PM PDT 24 409268562 ps
T336 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3894232654 Aug 12 05:03:25 PM PDT 24 Aug 12 05:03:35 PM PDT 24 987412820 ps
T337 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3230412571 Aug 12 05:03:22 PM PDT 24 Aug 12 05:03:36 PM PDT 24 1029835902 ps
T338 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3194197134 Aug 12 05:03:26 PM PDT 24 Aug 12 05:03:36 PM PDT 24 514979861 ps
T339 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2285477490 Aug 12 05:03:32 PM PDT 24 Aug 12 05:03:42 PM PDT 24 264127433 ps
T340 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1456533251 Aug 12 05:03:06 PM PDT 24 Aug 12 05:03:15 PM PDT 24 249733882 ps
T93 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2075442146 Aug 12 05:03:17 PM PDT 24 Aug 12 05:03:28 PM PDT 24 990302240 ps
T341 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.505385283 Aug 12 05:03:28 PM PDT 24 Aug 12 05:03:36 PM PDT 24 176133602 ps
T342 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.40048325 Aug 12 05:03:14 PM PDT 24 Aug 12 05:03:28 PM PDT 24 262104329 ps
T125 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3688892683 Aug 12 05:03:18 PM PDT 24 Aug 12 05:05:52 PM PDT 24 1543169350 ps
T343 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1370938962 Aug 12 05:03:34 PM PDT 24 Aug 12 05:03:48 PM PDT 24 995312950 ps
T123 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1094066006 Aug 12 05:03:08 PM PDT 24 Aug 12 05:05:44 PM PDT 24 478225825 ps
T98 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2881727700 Aug 12 05:03:27 PM PDT 24 Aug 12 05:03:42 PM PDT 24 990598478 ps
T99 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1700187549 Aug 12 05:03:29 PM PDT 24 Aug 12 05:04:35 PM PDT 24 10171626585 ps
T344 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2630583709 Aug 12 05:03:17 PM PDT 24 Aug 12 05:03:31 PM PDT 24 250645882 ps
T345 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.331483962 Aug 12 05:03:12 PM PDT 24 Aug 12 05:03:23 PM PDT 24 1076905771 ps
T346 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3352324766 Aug 12 05:03:21 PM PDT 24 Aug 12 05:03:30 PM PDT 24 887547379 ps
T347 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3710128804 Aug 12 05:03:08 PM PDT 24 Aug 12 05:03:25 PM PDT 24 252288032 ps
T348 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.857574473 Aug 12 05:03:35 PM PDT 24 Aug 12 05:04:31 PM PDT 24 1116469142 ps
T349 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.276871905 Aug 12 05:03:38 PM PDT 24 Aug 12 05:03:47 PM PDT 24 541247820 ps
T350 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1998325477 Aug 12 05:03:33 PM PDT 24 Aug 12 05:03:43 PM PDT 24 1002088503 ps
T351 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1053019075 Aug 12 05:03:26 PM PDT 24 Aug 12 05:03:40 PM PDT 24 269363368 ps
T352 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3480372133 Aug 12 05:03:25 PM PDT 24 Aug 12 05:04:22 PM PDT 24 2357765718 ps
T353 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.204407986 Aug 12 05:03:27 PM PDT 24 Aug 12 05:03:41 PM PDT 24 1124435225 ps
T354 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2997436510 Aug 12 05:03:29 PM PDT 24 Aug 12 05:03:40 PM PDT 24 988998041 ps
T355 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1219657973 Aug 12 05:03:09 PM PDT 24 Aug 12 05:03:19 PM PDT 24 476098355 ps
T356 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3840783349 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:23 PM PDT 24 845558026 ps
T357 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2867681845 Aug 12 05:03:08 PM PDT 24 Aug 12 05:04:05 PM PDT 24 2117194730 ps
T358 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1345183207 Aug 12 05:03:28 PM PDT 24 Aug 12 05:03:43 PM PDT 24 2740381429 ps
T359 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3051237872 Aug 12 05:03:13 PM PDT 24 Aug 12 05:03:23 PM PDT 24 2466047665 ps
T360 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.776877863 Aug 12 05:03:30 PM PDT 24 Aug 12 05:04:08 PM PDT 24 2768857647 ps
T361 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3348519732 Aug 12 05:03:02 PM PDT 24 Aug 12 05:03:11 PM PDT 24 244782209 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1698882373 Aug 12 05:03:06 PM PDT 24 Aug 12 05:03:17 PM PDT 24 255889986 ps
T363 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4158998409 Aug 12 05:03:20 PM PDT 24 Aug 12 05:03:30 PM PDT 24 1656320971 ps
T364 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.562045736 Aug 12 05:03:12 PM PDT 24 Aug 12 05:03:22 PM PDT 24 2747947443 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.737230006 Aug 12 05:03:25 PM PDT 24 Aug 12 05:04:32 PM PDT 24 6920334581 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3585128891 Aug 12 05:03:09 PM PDT 24 Aug 12 05:03:17 PM PDT 24 1037357523 ps
T130 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4067338790 Aug 12 05:03:11 PM PDT 24 Aug 12 05:05:49 PM PDT 24 614860484 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3591836830 Aug 12 05:03:10 PM PDT 24 Aug 12 05:03:20 PM PDT 24 249747836 ps
T367 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3215254217 Aug 12 05:03:36 PM PDT 24 Aug 12 05:03:50 PM PDT 24 856612530 ps
T127 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3468518357 Aug 12 05:03:31 PM PDT 24 Aug 12 05:04:57 PM PDT 24 390494752 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2098858222 Aug 12 05:03:08 PM PDT 24 Aug 12 05:03:19 PM PDT 24 660922978 ps
T369 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.587564445 Aug 12 05:03:31 PM PDT 24 Aug 12 05:03:41 PM PDT 24 509453485 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3676895524 Aug 12 05:03:15 PM PDT 24 Aug 12 05:03:25 PM PDT 24 263342652 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.290996656 Aug 12 05:03:12 PM PDT 24 Aug 12 05:03:29 PM PDT 24 2093084399 ps
T370 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.267289339 Aug 12 05:03:24 PM PDT 24 Aug 12 05:03:35 PM PDT 24 1028944394 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2281656763 Aug 12 05:03:13 PM PDT 24 Aug 12 05:04:33 PM PDT 24 519225969 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.254308866 Aug 12 05:03:19 PM PDT 24 Aug 12 05:03:33 PM PDT 24 256780641 ps
T133 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4273033009 Aug 12 05:03:40 PM PDT 24 Aug 12 05:06:16 PM PDT 24 441688772 ps
T373 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1714249407 Aug 12 05:03:14 PM PDT 24 Aug 12 05:03:25 PM PDT 24 1057248702 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3769425410 Aug 12 05:03:23 PM PDT 24 Aug 12 05:04:02 PM PDT 24 2870632436 ps
T103 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2660839855 Aug 12 05:03:13 PM PDT 24 Aug 12 05:04:19 PM PDT 24 1521329888 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1346187745 Aug 12 05:03:09 PM PDT 24 Aug 12 05:03:22 PM PDT 24 268624682 ps
T128 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2329797680 Aug 12 05:03:22 PM PDT 24 Aug 12 05:06:02 PM PDT 24 2479358649 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3165507077 Aug 12 05:03:26 PM PDT 24 Aug 12 05:03:35 PM PDT 24 175633166 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1816962197 Aug 12 05:03:06 PM PDT 24 Aug 12 05:03:18 PM PDT 24 167478871 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1804532661 Aug 12 05:03:03 PM PDT 24 Aug 12 05:03:13 PM PDT 24 991779707 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1060549522 Aug 12 05:03:24 PM PDT 24 Aug 12 05:03:37 PM PDT 24 664274374 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1735268961 Aug 12 05:03:20 PM PDT 24 Aug 12 05:03:34 PM PDT 24 250757731 ps
T126 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1118517935 Aug 12 05:03:22 PM PDT 24 Aug 12 05:04:45 PM PDT 24 1189366134 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3442234037 Aug 12 05:03:32 PM PDT 24 Aug 12 05:03:42 PM PDT 24 994507581 ps
T382 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2474160072 Aug 12 05:03:26 PM PDT 24 Aug 12 05:03:35 PM PDT 24 261061553 ps
T383 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3756647876 Aug 12 05:03:11 PM PDT 24 Aug 12 05:03:23 PM PDT 24 282115802 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.629222812 Aug 12 05:03:15 PM PDT 24 Aug 12 05:04:35 PM PDT 24 470271360 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.201439932 Aug 12 05:03:11 PM PDT 24 Aug 12 05:03:21 PM PDT 24 670566844 ps
T129 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3879074824 Aug 12 05:03:28 PM PDT 24 Aug 12 05:06:04 PM PDT 24 1548006892 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.897816820 Aug 12 05:03:22 PM PDT 24 Aug 12 05:03:36 PM PDT 24 1124972694 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.483512736 Aug 12 05:03:08 PM PDT 24 Aug 12 05:03:18 PM PDT 24 1078705818 ps
T388 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3642612546 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:20 PM PDT 24 174574294 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2530735983 Aug 12 05:03:23 PM PDT 24 Aug 12 05:03:33 PM PDT 24 1075126052 ps
T390 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.906659848 Aug 12 05:03:29 PM PDT 24 Aug 12 05:03:38 PM PDT 24 663533848 ps
T391 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1365222855 Aug 12 05:03:36 PM PDT 24 Aug 12 05:03:47 PM PDT 24 1526380206 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.37245248 Aug 12 05:03:31 PM PDT 24 Aug 12 05:03:41 PM PDT 24 501038535 ps
T393 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1305228134 Aug 12 05:03:25 PM PDT 24 Aug 12 05:03:40 PM PDT 24 997389399 ps
T394 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.651459268 Aug 12 05:03:09 PM PDT 24 Aug 12 05:03:18 PM PDT 24 170064742 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.949192754 Aug 12 05:03:24 PM PDT 24 Aug 12 05:03:33 PM PDT 24 167519360 ps
T395 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3513611274 Aug 12 05:03:11 PM PDT 24 Aug 12 05:03:21 PM PDT 24 265688325 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2990352119 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:20 PM PDT 24 519724679 ps
T397 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4068939384 Aug 12 05:03:14 PM PDT 24 Aug 12 05:03:23 PM PDT 24 183734123 ps
T108 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2581499589 Aug 12 05:03:30 PM PDT 24 Aug 12 05:03:38 PM PDT 24 174837964 ps
T398 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.274937515 Aug 12 05:03:29 PM PDT 24 Aug 12 05:05:05 PM PDT 24 21993805544 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3098340756 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:15 PM PDT 24 1831799222 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1035037431 Aug 12 05:03:05 PM PDT 24 Aug 12 05:03:19 PM PDT 24 991438059 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.482734282 Aug 12 05:03:07 PM PDT 24 Aug 12 05:03:15 PM PDT 24 692233813 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3712335832 Aug 12 05:03:30 PM PDT 24 Aug 12 05:04:15 PM PDT 24 4239623233 ps
T106 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2276665764 Aug 12 05:03:09 PM PDT 24 Aug 12 05:04:15 PM PDT 24 1531455664 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3664287068 Aug 12 05:03:08 PM PDT 24 Aug 12 05:03:18 PM PDT 24 293698385 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2387633243 Aug 12 05:03:08 PM PDT 24 Aug 12 05:03:19 PM PDT 24 260581395 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2628292302 Aug 12 05:03:24 PM PDT 24 Aug 12 05:03:33 PM PDT 24 182709519 ps
T405 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1664639159 Aug 12 05:03:09 PM PDT 24 Aug 12 05:03:21 PM PDT 24 171444659 ps
T107 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3940025092 Aug 12 05:03:28 PM PDT 24 Aug 12 05:03:37 PM PDT 24 689295528 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2726031020 Aug 12 05:03:28 PM PDT 24 Aug 12 05:04:13 PM PDT 24 1073132594 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3792008953 Aug 12 05:03:23 PM PDT 24 Aug 12 05:03:33 PM PDT 24 255931784 ps
T408 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1544057057 Aug 12 05:03:11 PM PDT 24 Aug 12 05:03:27 PM PDT 24 1046749364 ps
T132 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2899929225 Aug 12 05:03:29 PM PDT 24 Aug 12 05:06:09 PM PDT 24 524694200 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4175110031 Aug 12 05:03:08 PM PDT 24 Aug 12 05:03:53 PM PDT 24 4073624041 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2793544225 Aug 12 05:03:15 PM PDT 24 Aug 12 05:03:25 PM PDT 24 650623925 ps

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4156870101
Short name T3
Test name
Test status
Simulation time 48456391539 ps
CPU time 365.63 seconds
Started Aug 12 06:19:52 PM PDT 24
Finished Aug 12 06:25:58 PM PDT 24
Peak memory 239532 kb
Host smart-e0ff7e1a-31dc-44bb-82f8-c55b84445b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156870101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4156870101
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3236275411
Short name T15
Test name
Test status
Simulation time 4476530714 ps
CPU time 182.73 seconds
Started Aug 12 06:19:27 PM PDT 24
Finished Aug 12 06:22:30 PM PDT 24
Peak memory 233784 kb
Host smart-d81ece14-af69-4cea-ae80-9307a8fc7663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236275411 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3236275411
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2224560513
Short name T2
Test name
Test status
Simulation time 3617963876 ps
CPU time 12.37 seconds
Started Aug 12 06:19:08 PM PDT 24
Finished Aug 12 06:19:21 PM PDT 24
Peak memory 219380 kb
Host smart-f7e1c222-73ed-4130-9778-45dc420c966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224560513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2224560513
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2080246560
Short name T34
Test name
Test status
Simulation time 647772027 ps
CPU time 10.83 seconds
Started Aug 12 06:19:39 PM PDT 24
Finished Aug 12 06:19:51 PM PDT 24
Peak memory 219348 kb
Host smart-7bab086b-85c2-4e67-8d0f-dcade06941a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080246560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2080246560
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3368590257
Short name T22
Test name
Test status
Simulation time 15544407671 ps
CPU time 247.85 seconds
Started Aug 12 06:19:38 PM PDT 24
Finished Aug 12 06:23:46 PM PDT 24
Peak memory 219696 kb
Host smart-4658b845-5ebb-457e-9878-adda4a72b850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368590257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3368590257
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.23991622
Short name T7
Test name
Test status
Simulation time 175234541 ps
CPU time 8.35 seconds
Started Aug 12 06:19:37 PM PDT 24
Finished Aug 12 06:19:46 PM PDT 24
Peak memory 218792 kb
Host smart-55e24837-4370-4823-b279-0311ce81fb84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23991622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.23991622
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.548151902
Short name T27
Test name
Test status
Simulation time 379969922 ps
CPU time 154.66 seconds
Started Aug 12 05:03:40 PM PDT 24
Finished Aug 12 05:06:15 PM PDT 24
Peak memory 219120 kb
Host smart-d144afad-676b-4f47-a6b9-fc27a5e60f93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548151902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.548151902
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3181313512
Short name T14
Test name
Test status
Simulation time 806753861 ps
CPU time 40.24 seconds
Started Aug 12 06:19:26 PM PDT 24
Finished Aug 12 06:20:06 PM PDT 24
Peak memory 219252 kb
Host smart-17bf3620-48fd-4243-8a7d-61b843339f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181313512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3181313512
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.207218946
Short name T215
Test name
Test status
Simulation time 379741567 ps
CPU time 20.64 seconds
Started Aug 12 06:19:46 PM PDT 24
Finished Aug 12 06:20:07 PM PDT 24
Peak memory 219320 kb
Host smart-be19f5da-9193-414c-bda5-1e5be63cf43a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207218946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.207218946
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1028998797
Short name T38
Test name
Test status
Simulation time 4955088437 ps
CPU time 16.64 seconds
Started Aug 12 06:19:28 PM PDT 24
Finished Aug 12 06:19:45 PM PDT 24
Peak memory 219436 kb
Host smart-02520489-f3e9-4a7e-a78f-e15a2eff863e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028998797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1028998797
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.220973008
Short name T24
Test name
Test status
Simulation time 1230825338 ps
CPU time 248.86 seconds
Started Aug 12 06:19:16 PM PDT 24
Finished Aug 12 06:23:25 PM PDT 24
Peak memory 239636 kb
Host smart-c2189e2c-a7b0-400c-9990-505a8aa7bb4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220973008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.220973008
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2660839855
Short name T103
Test name
Test status
Simulation time 1521329888 ps
CPU time 65.34 seconds
Started Aug 12 05:03:13 PM PDT 24
Finished Aug 12 05:04:19 PM PDT 24
Peak memory 215248 kb
Host smart-70fea269-0a7f-43d5-a410-aa69dd6fec71
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660839855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2660839855
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3824758953
Short name T12
Test name
Test status
Simulation time 300303621 ps
CPU time 11.96 seconds
Started Aug 12 06:19:16 PM PDT 24
Finished Aug 12 06:19:28 PM PDT 24
Peak memory 219256 kb
Host smart-e9bb60e7-c9ad-424d-bacb-50005a44cfcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824758953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3824758953
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2899929225
Short name T132
Test name
Test status
Simulation time 524694200 ps
CPU time 159.15 seconds
Started Aug 12 05:03:29 PM PDT 24
Finished Aug 12 05:06:09 PM PDT 24
Peak memory 215788 kb
Host smart-a61a8a81-9ab2-4502-8b2c-7ba726af4367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899929225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2899929225
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1946529807
Short name T41
Test name
Test status
Simulation time 1319180255 ps
CPU time 19.23 seconds
Started Aug 12 06:19:56 PM PDT 24
Finished Aug 12 06:20:15 PM PDT 24
Peak memory 219440 kb
Host smart-8bec4cd1-ecd7-4768-85d4-ba0b7a7fdb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946529807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1946529807
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.698246151
Short name T199
Test name
Test status
Simulation time 4940953096 ps
CPU time 22.89 seconds
Started Aug 12 06:19:10 PM PDT 24
Finished Aug 12 06:19:33 PM PDT 24
Peak memory 219540 kb
Host smart-dea1c677-1179-4970-81aa-28fdd12e91d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698246151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.698246151
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3468518357
Short name T127
Test name
Test status
Simulation time 390494752 ps
CPU time 86.34 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:04:57 PM PDT 24
Peak memory 214044 kb
Host smart-6f6bd6e0-33b7-464b-a9a6-cb0015ea334b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468518357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3468518357
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3688892683
Short name T125
Test name
Test status
Simulation time 1543169350 ps
CPU time 154.26 seconds
Started Aug 12 05:03:18 PM PDT 24
Finished Aug 12 05:05:52 PM PDT 24
Peak memory 219100 kb
Host smart-fd29f2b6-50ad-4932-9182-9638da9358b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688892683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3688892683
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1053395921
Short name T94
Test name
Test status
Simulation time 414995551 ps
CPU time 28.84 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:20:12 PM PDT 24
Peak memory 219368 kb
Host smart-c51a7a58-0b2a-4b27-80b3-ffc7bd5aca55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053395921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1053395921
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.968941779
Short name T85
Test name
Test status
Simulation time 1029636545 ps
CPU time 44.01 seconds
Started Aug 12 05:03:29 PM PDT 24
Finished Aug 12 05:04:14 PM PDT 24
Peak memory 214440 kb
Host smart-ae14a134-7a4d-42d8-b152-79d10f50153c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968941779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.968941779
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2988879123
Short name T54
Test name
Test status
Simulation time 1297313518 ps
CPU time 83.87 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:04:29 PM PDT 24
Peak memory 214172 kb
Host smart-de082264-ab06-47c2-b03f-a87fecf3c123
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988879123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2988879123
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2893234337
Short name T109
Test name
Test status
Simulation time 357800286 ps
CPU time 10.25 seconds
Started Aug 12 06:19:26 PM PDT 24
Finished Aug 12 06:19:36 PM PDT 24
Peak memory 219344 kb
Host smart-2834cd0a-fb79-44c1-8998-ae80ec92927a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893234337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2893234337
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.876778973
Short name T165
Test name
Test status
Simulation time 11954490319 ps
CPU time 205.17 seconds
Started Aug 12 06:19:27 PM PDT 24
Finished Aug 12 06:22:53 PM PDT 24
Peak memory 230420 kb
Host smart-5ec75cef-6dcf-4ee8-bb0e-e888b60505b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876778973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.876778973
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.147470213
Short name T13
Test name
Test status
Simulation time 348503763 ps
CPU time 24.53 seconds
Started Aug 12 06:19:08 PM PDT 24
Finished Aug 12 06:19:33 PM PDT 24
Peak memory 219336 kb
Host smart-1ddb68bf-ce7d-4e47-8a0c-30e0da1ddd82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147470213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.147470213
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4217551602
Short name T176
Test name
Test status
Simulation time 15035594221 ps
CPU time 247.69 seconds
Started Aug 12 06:19:27 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 226400 kb
Host smart-f30bfb7f-85ca-4f0a-ae76-21414073168d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217551602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4217551602
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.949192754
Short name T105
Test name
Test status
Simulation time 167519360 ps
CPU time 8.12 seconds
Started Aug 12 05:03:24 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 211000 kb
Host smart-9f37939d-6ec4-46e7-87bd-bbda11d4c915
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949192754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.949192754
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2767310699
Short name T120
Test name
Test status
Simulation time 333595596 ps
CPU time 8.33 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:16 PM PDT 24
Peak memory 210980 kb
Host smart-9946bd5d-6d36-4bc3-9a43-ac06d08362d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767310699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2767310699
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3955948166
Short name T88
Test name
Test status
Simulation time 763326961 ps
CPU time 12.02 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:17 PM PDT 24
Peak memory 211272 kb
Host smart-01f493c5-59c6-4364-908f-3984719bc922
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955948166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3955948166
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.483512736
Short name T387
Test name
Test status
Simulation time 1078705818 ps
CPU time 10.21 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:18 PM PDT 24
Peak memory 216956 kb
Host smart-c8260438-08e0-4e75-b459-b08f83292416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483512736 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.483512736
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2387633243
Short name T104
Test name
Test status
Simulation time 260581395 ps
CPU time 9.8 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:19 PM PDT 24
Peak memory 211664 kb
Host smart-11fd2eb2-187b-4ebc-83cc-8815f9f620a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387633243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2387633243
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3508069276
Short name T327
Test name
Test status
Simulation time 171172914 ps
CPU time 8.17 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:03:20 PM PDT 24
Peak memory 210776 kb
Host smart-3777baae-0540-4951-8c54-a69fa78d531f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508069276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3508069276
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1804532661
Short name T378
Test name
Test status
Simulation time 991779707 ps
CPU time 9.67 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:13 PM PDT 24
Peak memory 210812 kb
Host smart-5e433d03-2544-4bb3-9495-047d561ab48f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804532661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1804532661
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4175110031
Short name T409
Test name
Test status
Simulation time 4073624041 ps
CPU time 44.68 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:53 PM PDT 24
Peak memory 215108 kb
Host smart-43bd8020-6008-4729-af4c-13e9034fcc28
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175110031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4175110031
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2210537517
Short name T114
Test name
Test status
Simulation time 260334564 ps
CPU time 8.26 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:03:17 PM PDT 24
Peak memory 211512 kb
Host smart-6694f022-64aa-4e93-958d-d183d0e5531a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210537517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2210537517
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1735268961
Short name T380
Test name
Test status
Simulation time 250757731 ps
CPU time 13.03 seconds
Started Aug 12 05:03:20 PM PDT 24
Finished Aug 12 05:03:34 PM PDT 24
Peak memory 217432 kb
Host smart-fccb12fb-f35d-476c-8936-ef3196ff05d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735268961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1735268961
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4067338790
Short name T130
Test name
Test status
Simulation time 614860484 ps
CPU time 157.24 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:05:49 PM PDT 24
Peak memory 214584 kb
Host smart-280a9067-1976-449c-85c0-cf6f16fd2f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067338790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4067338790
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.800828814
Short name T86
Test name
Test status
Simulation time 293404756 ps
CPU time 10.06 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:17 PM PDT 24
Peak memory 211308 kb
Host smart-9e5bf843-c029-47fa-972c-b09786fa7cb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800828814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.800828814
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3792008953
Short name T407
Test name
Test status
Simulation time 255931784 ps
CPU time 10.22 seconds
Started Aug 12 05:03:23 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 211084 kb
Host smart-4e3811fa-632f-4f46-9d65-4b26546b08a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792008953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3792008953
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3710128804
Short name T347
Test name
Test status
Simulation time 252288032 ps
CPU time 17.15 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:25 PM PDT 24
Peak memory 212196 kb
Host smart-f3a30051-3f44-47e2-9d97-b5cac66f37e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710128804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3710128804
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1271502410
Short name T58
Test name
Test status
Simulation time 723843270 ps
CPU time 9.25 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:17 PM PDT 24
Peak memory 217400 kb
Host smart-9012356c-64b9-41f3-a4e0-0cf2e39d2ad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271502410 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1271502410
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2990352119
Short name T396
Test name
Test status
Simulation time 519724679 ps
CPU time 9.97 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:20 PM PDT 24
Peak memory 211136 kb
Host smart-b8bcbd18-d663-49a4-ac2a-c405fcbec99d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990352119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2990352119
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2997436510
Short name T354
Test name
Test status
Simulation time 988998041 ps
CPU time 10.01 seconds
Started Aug 12 05:03:29 PM PDT 24
Finished Aug 12 05:03:40 PM PDT 24
Peak memory 210828 kb
Host smart-a19faa0c-2f78-4033-ac05-298c66a20dd2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997436510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2997436510
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1456533251
Short name T340
Test name
Test status
Simulation time 249733882 ps
CPU time 9.67 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:15 PM PDT 24
Peak memory 210872 kb
Host smart-228df7e8-967e-4f3e-810e-da5aa38ece6b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456533251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1456533251
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2276665764
Short name T106
Test name
Test status
Simulation time 1531455664 ps
CPU time 65.78 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:04:15 PM PDT 24
Peak memory 214168 kb
Host smart-19ec9af4-2d42-4545-ada7-aaca3dc8075e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276665764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2276665764
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.482734282
Short name T401
Test name
Test status
Simulation time 692233813 ps
CPU time 8.23 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:15 PM PDT 24
Peak memory 211836 kb
Host smart-c00bbe55-515b-478d-b486-cb1c969f59ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482734282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.482734282
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1346187745
Short name T375
Test name
Test status
Simulation time 268624682 ps
CPU time 12.27 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:03:22 PM PDT 24
Peak memory 217704 kb
Host smart-95f3a5a6-2a97-40a2-8713-a6ec8c327dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346187745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1346187745
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1998325477
Short name T350
Test name
Test status
Simulation time 1002088503 ps
CPU time 10.25 seconds
Started Aug 12 05:03:33 PM PDT 24
Finished Aug 12 05:03:43 PM PDT 24
Peak memory 216024 kb
Host smart-a7c9e3f5-ad71-4aef-aa46-5f67e1e7d888
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998325477 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1998325477
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.833768921
Short name T325
Test name
Test status
Simulation time 176030310 ps
CPU time 8.52 seconds
Started Aug 12 05:03:16 PM PDT 24
Finished Aug 12 05:03:24 PM PDT 24
Peak memory 211504 kb
Host smart-0b324e55-6be5-4c4d-a002-2b653e6ea70b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833768921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.833768921
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.274937515
Short name T398
Test name
Test status
Simulation time 21993805544 ps
CPU time 95.1 seconds
Started Aug 12 05:03:29 PM PDT 24
Finished Aug 12 05:05:05 PM PDT 24
Peak memory 216188 kb
Host smart-b887d699-9f62-48ce-a492-25ceef0ef0b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274937515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.274937515
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.906659848
Short name T390
Test name
Test status
Simulation time 663533848 ps
CPU time 8.4 seconds
Started Aug 12 05:03:29 PM PDT 24
Finished Aug 12 05:03:38 PM PDT 24
Peak memory 210220 kb
Host smart-93df1540-2db3-4793-9d29-bb6ec7d2e088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906659848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.906659848
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3215254217
Short name T367
Test name
Test status
Simulation time 856612530 ps
CPU time 13.48 seconds
Started Aug 12 05:03:36 PM PDT 24
Finished Aug 12 05:03:50 PM PDT 24
Peak memory 218656 kb
Host smart-5f64e5b0-1fdf-46f6-8000-e7c3f89d1e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215254217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3215254217
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2329797680
Short name T128
Test name
Test status
Simulation time 2479358649 ps
CPU time 159.82 seconds
Started Aug 12 05:03:22 PM PDT 24
Finished Aug 12 05:06:02 PM PDT 24
Peak memory 214560 kb
Host smart-7d03def3-3916-48f2-8b6c-a42bbf1903c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329797680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2329797680
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4068939384
Short name T397
Test name
Test status
Simulation time 183734123 ps
CPU time 8.61 seconds
Started Aug 12 05:03:14 PM PDT 24
Finished Aug 12 05:03:23 PM PDT 24
Peak memory 215748 kb
Host smart-a2c1a29b-eed0-4e15-8622-6b1d4dcc7b43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068939384 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4068939384
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2530735983
Short name T389
Test name
Test status
Simulation time 1075126052 ps
CPU time 9.85 seconds
Started Aug 12 05:03:23 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 211060 kb
Host smart-799c8db7-9099-459f-9c96-106ceb630b08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530735983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2530735983
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3480372133
Short name T352
Test name
Test status
Simulation time 2357765718 ps
CPU time 57.08 seconds
Started Aug 12 05:03:25 PM PDT 24
Finished Aug 12 05:04:22 PM PDT 24
Peak memory 216256 kb
Host smart-de0c5a60-c5a4-40e5-89a7-9e763f4eab89
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480372133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3480372133
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3051237872
Short name T359
Test name
Test status
Simulation time 2466047665 ps
CPU time 9.81 seconds
Started Aug 12 05:03:13 PM PDT 24
Finished Aug 12 05:03:23 PM PDT 24
Peak memory 211692 kb
Host smart-f49c56bc-f09d-4915-bac6-2359912b9766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051237872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3051237872
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2068007930
Short name T331
Test name
Test status
Simulation time 250055181 ps
CPU time 15.22 seconds
Started Aug 12 05:03:24 PM PDT 24
Finished Aug 12 05:03:39 PM PDT 24
Peak memory 217816 kb
Host smart-74ca668a-de74-4309-973e-5e86e3b0aa3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068007930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2068007930
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4167239587
Short name T131
Test name
Test status
Simulation time 409268562 ps
CPU time 85.8 seconds
Started Aug 12 05:03:26 PM PDT 24
Finished Aug 12 05:04:57 PM PDT 24
Peak memory 213956 kb
Host smart-2bab48c4-c4bc-41f9-adbd-bc276b7bc72e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167239587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4167239587
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2793544225
Short name T410
Test name
Test status
Simulation time 650623925 ps
CPU time 9.37 seconds
Started Aug 12 05:03:15 PM PDT 24
Finished Aug 12 05:03:25 PM PDT 24
Peak memory 217456 kb
Host smart-63a8dc51-5a1c-4c1e-831f-6fd2f3feae6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793544225 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2793544225
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2581499589
Short name T108
Test name
Test status
Simulation time 174837964 ps
CPU time 8.34 seconds
Started Aug 12 05:03:30 PM PDT 24
Finished Aug 12 05:03:38 PM PDT 24
Peak memory 211228 kb
Host smart-5906f3b0-0df1-4e8a-9d0e-abefb441d04f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581499589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2581499589
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.505385283
Short name T341
Test name
Test status
Simulation time 176133602 ps
CPU time 8.21 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:03:36 PM PDT 24
Peak memory 211992 kb
Host smart-6d7f64bf-3b97-4b02-b458-f7bf50fb45ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505385283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.505385283
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.204407986
Short name T353
Test name
Test status
Simulation time 1124435225 ps
CPU time 13.69 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:41 PM PDT 24
Peak memory 217756 kb
Host smart-4d594231-75a1-4f73-921c-f8165adbb136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204407986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.204407986
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.267289339
Short name T370
Test name
Test status
Simulation time 1028944394 ps
CPU time 10.64 seconds
Started Aug 12 05:03:24 PM PDT 24
Finished Aug 12 05:03:35 PM PDT 24
Peak memory 216068 kb
Host smart-24ec16f7-fd2f-4f39-98e3-ea0d713a074e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267289339 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.267289339
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4158998409
Short name T363
Test name
Test status
Simulation time 1656320971 ps
CPU time 9.94 seconds
Started Aug 12 05:03:20 PM PDT 24
Finished Aug 12 05:03:30 PM PDT 24
Peak memory 211320 kb
Host smart-c0667088-4e10-4bf3-b412-23371b9f1137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158998409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4158998409
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.737230006
Short name T100
Test name
Test status
Simulation time 6920334581 ps
CPU time 66.86 seconds
Started Aug 12 05:03:25 PM PDT 24
Finished Aug 12 05:04:32 PM PDT 24
Peak memory 215240 kb
Host smart-39a4c4f2-c5ad-41c4-884e-f36d73cd2c0e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737230006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.737230006
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.897816820
Short name T386
Test name
Test status
Simulation time 1124972694 ps
CPU time 14.48 seconds
Started Aug 12 05:03:22 PM PDT 24
Finished Aug 12 05:03:36 PM PDT 24
Peak memory 212888 kb
Host smart-2f77fcd0-c079-4b2d-9850-8fcc81b7e40b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897816820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.897816820
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.219161344
Short name T334
Test name
Test status
Simulation time 662147215 ps
CPU time 11.07 seconds
Started Aug 12 05:03:20 PM PDT 24
Finished Aug 12 05:03:32 PM PDT 24
Peak memory 218668 kb
Host smart-1ab70958-d3cc-4eeb-bf9c-fa43a3c46da1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219161344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.219161344
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.390138865
Short name T81
Test name
Test status
Simulation time 491862057 ps
CPU time 161.48 seconds
Started Aug 12 05:03:36 PM PDT 24
Finished Aug 12 05:06:18 PM PDT 24
Peak memory 214556 kb
Host smart-da9f8ecf-5b0c-4b7b-9957-20074398e2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390138865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.390138865
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1033133930
Short name T28
Test name
Test status
Simulation time 763101311 ps
CPU time 10.31 seconds
Started Aug 12 05:03:18 PM PDT 24
Finished Aug 12 05:03:29 PM PDT 24
Peak memory 218176 kb
Host smart-cccaef87-f70c-449e-a49f-c7b8b0579987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033133930 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1033133930
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3940025092
Short name T107
Test name
Test status
Simulation time 689295528 ps
CPU time 8.03 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:03:37 PM PDT 24
Peak memory 211024 kb
Host smart-304cc613-7f07-4bfd-bd07-99ced74fa18f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940025092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3940025092
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2726031020
Short name T406
Test name
Test status
Simulation time 1073132594 ps
CPU time 44.73 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:04:13 PM PDT 24
Peak memory 214272 kb
Host smart-136c7a44-d045-4a5d-aa6d-e935860d745f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726031020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2726031020
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3990815996
Short name T92
Test name
Test status
Simulation time 254823256 ps
CPU time 10.05 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:37 PM PDT 24
Peak memory 211664 kb
Host smart-196438c8-a0de-4517-9b2c-a2235d87b096
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990815996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3990815996
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3198005112
Short name T329
Test name
Test status
Simulation time 506814521 ps
CPU time 13.69 seconds
Started Aug 12 05:03:16 PM PDT 24
Finished Aug 12 05:03:30 PM PDT 24
Peak memory 217600 kb
Host smart-ecdb99e0-becf-4039-80af-379a37727f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198005112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3198005112
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1118517935
Short name T126
Test name
Test status
Simulation time 1189366134 ps
CPU time 82.9 seconds
Started Aug 12 05:03:22 PM PDT 24
Finished Aug 12 05:04:45 PM PDT 24
Peak memory 214148 kb
Host smart-4d0dae78-f0fd-4ecf-9177-a644867e5ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118517935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1118517935
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1365222855
Short name T391
Test name
Test status
Simulation time 1526380206 ps
CPU time 10.34 seconds
Started Aug 12 05:03:36 PM PDT 24
Finished Aug 12 05:03:47 PM PDT 24
Peak memory 216608 kb
Host smart-d608ef7d-39d4-4084-be15-017ebc958f22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365222855 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1365222855
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1353311765
Short name T119
Test name
Test status
Simulation time 339652215 ps
CPU time 10.08 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:37 PM PDT 24
Peak memory 210004 kb
Host smart-5b9b1c7b-bd15-4f5d-80ac-cde91794512c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353311765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1353311765
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3900217554
Short name T87
Test name
Test status
Simulation time 3131536804 ps
CPU time 37.23 seconds
Started Aug 12 05:03:16 PM PDT 24
Finished Aug 12 05:03:54 PM PDT 24
Peak memory 214176 kb
Host smart-bc31c1dc-4d56-4429-9022-1624ae747593
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900217554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3900217554
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2547842714
Short name T117
Test name
Test status
Simulation time 517067296 ps
CPU time 10.16 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:38 PM PDT 24
Peak memory 211636 kb
Host smart-a00ef4c0-55c7-42ff-a594-6221bc1e806c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547842714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2547842714
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1370938962
Short name T343
Test name
Test status
Simulation time 995312950 ps
CPU time 13.09 seconds
Started Aug 12 05:03:34 PM PDT 24
Finished Aug 12 05:03:48 PM PDT 24
Peak memory 217924 kb
Host smart-edc7db4e-a2f5-4465-8963-cb4dcb43a737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370938962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1370938962
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3879074824
Short name T129
Test name
Test status
Simulation time 1548006892 ps
CPU time 155.24 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:06:04 PM PDT 24
Peak memory 215468 kb
Host smart-93fdc9cc-2f53-4eaa-9d06-3f426bbeae3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879074824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3879074824
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.893137224
Short name T83
Test name
Test status
Simulation time 1062423718 ps
CPU time 10.34 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:38 PM PDT 24
Peak memory 216276 kb
Host smart-ae0a12f5-f2f1-4a3d-a80d-7eadb329a3f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893137224 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.893137224
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3194197134
Short name T338
Test name
Test status
Simulation time 514979861 ps
CPU time 10.05 seconds
Started Aug 12 05:03:26 PM PDT 24
Finished Aug 12 05:03:36 PM PDT 24
Peak memory 210988 kb
Host smart-38a48fb2-bf1a-40ca-b293-5527f545436a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194197134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3194197134
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3712335832
Short name T402
Test name
Test status
Simulation time 4239623233 ps
CPU time 45.27 seconds
Started Aug 12 05:03:30 PM PDT 24
Finished Aug 12 05:04:15 PM PDT 24
Peak memory 214236 kb
Host smart-022c84dc-9b05-4cd0-9b37-83408774c51b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712335832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3712335832
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2668112299
Short name T72
Test name
Test status
Simulation time 721671583 ps
CPU time 12.43 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:03:44 PM PDT 24
Peak memory 212876 kb
Host smart-f255ce09-51b3-4506-a097-dbfc8f43c1e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668112299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2668112299
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3722434421
Short name T59
Test name
Test status
Simulation time 516613652 ps
CPU time 13.67 seconds
Started Aug 12 05:03:25 PM PDT 24
Finished Aug 12 05:03:39 PM PDT 24
Peak memory 217788 kb
Host smart-b8aba84a-6286-4b51-ad85-636c469c7050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722434421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3722434421
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1714103649
Short name T55
Test name
Test status
Simulation time 288667235 ps
CPU time 84.08 seconds
Started Aug 12 05:03:29 PM PDT 24
Finished Aug 12 05:04:53 PM PDT 24
Peak memory 219128 kb
Host smart-ad74c41f-ea5f-45a5-9b2a-3cf2ee711337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714103649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1714103649
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2959537165
Short name T328
Test name
Test status
Simulation time 2024700011 ps
CPU time 16 seconds
Started Aug 12 05:03:26 PM PDT 24
Finished Aug 12 05:03:42 PM PDT 24
Peak memory 218416 kb
Host smart-d44322ad-3451-435c-b307-66b3ee18fe41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959537165 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2959537165
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3442234037
Short name T381
Test name
Test status
Simulation time 994507581 ps
CPU time 9.94 seconds
Started Aug 12 05:03:32 PM PDT 24
Finished Aug 12 05:03:42 PM PDT 24
Peak memory 211396 kb
Host smart-c4dc6c6f-5925-4bc4-b29e-458e10892a9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442234037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3442234037
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.776877863
Short name T360
Test name
Test status
Simulation time 2768857647 ps
CPU time 37.52 seconds
Started Aug 12 05:03:30 PM PDT 24
Finished Aug 12 05:04:08 PM PDT 24
Peak memory 214140 kb
Host smart-21edb963-3f28-434d-8496-9fc60ed1ebb1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776877863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.776877863
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.276871905
Short name T349
Test name
Test status
Simulation time 541247820 ps
CPU time 9.8 seconds
Started Aug 12 05:03:38 PM PDT 24
Finished Aug 12 05:03:47 PM PDT 24
Peak memory 211072 kb
Host smart-c96be848-fa04-4b83-8539-0c5010f2fd45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276871905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.276871905
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.254308866
Short name T372
Test name
Test status
Simulation time 256780641 ps
CPU time 14.11 seconds
Started Aug 12 05:03:19 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 217640 kb
Host smart-727a85dd-c596-4532-8fc9-a58f0d3aff05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254308866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.254308866
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4273033009
Short name T133
Test name
Test status
Simulation time 441688772 ps
CPU time 156.16 seconds
Started Aug 12 05:03:40 PM PDT 24
Finished Aug 12 05:06:16 PM PDT 24
Peak memory 214508 kb
Host smart-f759f155-a238-45b6-bf24-172a1d5e886a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273033009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4273033009
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2285477490
Short name T339
Test name
Test status
Simulation time 264127433 ps
CPU time 10.41 seconds
Started Aug 12 05:03:32 PM PDT 24
Finished Aug 12 05:03:42 PM PDT 24
Peak memory 215972 kb
Host smart-810add8c-c215-41ec-b4c1-2be99c51d179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285477490 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2285477490
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2474160072
Short name T382
Test name
Test status
Simulation time 261061553 ps
CPU time 9.43 seconds
Started Aug 12 05:03:26 PM PDT 24
Finished Aug 12 05:03:35 PM PDT 24
Peak memory 211020 kb
Host smart-db3e1dac-c38d-4ea1-8324-91de842fe8e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474160072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2474160072
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1700187549
Short name T99
Test name
Test status
Simulation time 10171626585 ps
CPU time 66.33 seconds
Started Aug 12 05:03:29 PM PDT 24
Finished Aug 12 05:04:35 PM PDT 24
Peak memory 216220 kb
Host smart-358f742d-be61-455e-b507-d21c5997d3bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700187549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1700187549
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.965740501
Short name T115
Test name
Test status
Simulation time 331621470 ps
CPU time 8.37 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:35 PM PDT 24
Peak memory 211880 kb
Host smart-8926bf12-0934-48ee-96a8-b88a48a4b924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965740501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.965740501
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1345183207
Short name T358
Test name
Test status
Simulation time 2740381429 ps
CPU time 14.11 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:03:43 PM PDT 24
Peak memory 217812 kb
Host smart-7886a754-295a-4bb5-bd3b-136c81020909
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345183207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1345183207
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.37245248
Short name T392
Test name
Test status
Simulation time 501038535 ps
CPU time 10.2 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:03:41 PM PDT 24
Peak memory 216520 kb
Host smart-9e4dd0c6-0353-490a-9632-aa79d49ed4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37245248 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.37245248
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1305228134
Short name T393
Test name
Test status
Simulation time 997389399 ps
CPU time 14.85 seconds
Started Aug 12 05:03:25 PM PDT 24
Finished Aug 12 05:03:40 PM PDT 24
Peak memory 211908 kb
Host smart-392205bf-8238-4029-b118-31724abb759e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305228134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1305228134
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.857574473
Short name T348
Test name
Test status
Simulation time 1116469142 ps
CPU time 56.25 seconds
Started Aug 12 05:03:35 PM PDT 24
Finished Aug 12 05:04:31 PM PDT 24
Peak memory 215524 kb
Host smart-ca9dbbc4-349c-419e-91af-d815b2be9d6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857574473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.857574473
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.587564445
Short name T369
Test name
Test status
Simulation time 509453485 ps
CPU time 9.73 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:03:41 PM PDT 24
Peak memory 211828 kb
Host smart-1eafb511-4dce-4adf-b186-8cca01858d49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587564445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.587564445
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1053019075
Short name T351
Test name
Test status
Simulation time 269363368 ps
CPU time 14.16 seconds
Started Aug 12 05:03:26 PM PDT 24
Finished Aug 12 05:03:40 PM PDT 24
Peak memory 217664 kb
Host smart-9c0666a7-73b4-4e44-b53d-2783540a6395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053019075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1053019075
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3348519732
Short name T361
Test name
Test status
Simulation time 244782209 ps
CPU time 8.36 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 211228 kb
Host smart-ea9c5d12-c704-4fb4-a1f8-07da7ba8e5da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348519732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3348519732
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3591836830
Short name T366
Test name
Test status
Simulation time 249747836 ps
CPU time 10.18 seconds
Started Aug 12 05:03:10 PM PDT 24
Finished Aug 12 05:03:20 PM PDT 24
Peak memory 211020 kb
Host smart-9172a527-c5d5-4b08-b183-fe45ef852029
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591836830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3591836830
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.290996656
Short name T102
Test name
Test status
Simulation time 2093084399 ps
CPU time 17.46 seconds
Started Aug 12 05:03:12 PM PDT 24
Finished Aug 12 05:03:29 PM PDT 24
Peak memory 212036 kb
Host smart-2f7cdb82-ae0f-4727-b7a2-b991732ba86a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290996656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.290996656
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1958030295
Short name T82
Test name
Test status
Simulation time 766770372 ps
CPU time 9.25 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:16 PM PDT 24
Peak memory 217488 kb
Host smart-ff5e9c0c-7c74-431a-8b98-f99eb0570c68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958030295 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1958030295
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1698882373
Short name T362
Test name
Test status
Simulation time 255889986 ps
CPU time 10.22 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:17 PM PDT 24
Peak memory 211304 kb
Host smart-68d20701-5e66-41f4-ab1d-607022b8d26c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698882373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1698882373
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3585128891
Short name T365
Test name
Test status
Simulation time 1037357523 ps
CPU time 8.3 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:03:17 PM PDT 24
Peak memory 210808 kb
Host smart-883164e1-76b2-4f6f-b1ba-13c564f2ff6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585128891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3585128891
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2670322310
Short name T322
Test name
Test status
Simulation time 993176383 ps
CPU time 9.64 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:03:19 PM PDT 24
Peak memory 210820 kb
Host smart-a2fac019-c837-4527-9b9f-f019c523544b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670322310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2670322310
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3971934638
Short name T90
Test name
Test status
Simulation time 1501612584 ps
CPU time 57.32 seconds
Started Aug 12 05:03:16 PM PDT 24
Finished Aug 12 05:04:14 PM PDT 24
Peak memory 215204 kb
Host smart-1df4f919-7fcf-4f7d-9512-ea88d5cb1c35
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971934638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3971934638
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.26811269
Short name T118
Test name
Test status
Simulation time 436500163 ps
CPU time 8.26 seconds
Started Aug 12 05:03:12 PM PDT 24
Finished Aug 12 05:03:21 PM PDT 24
Peak memory 211588 kb
Host smart-d06be0d4-1aa9-4749-aa2e-2c27a4702fd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26811269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_same_csr_outstanding.26811269
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1060549522
Short name T379
Test name
Test status
Simulation time 664274374 ps
CPU time 13.21 seconds
Started Aug 12 05:03:24 PM PDT 24
Finished Aug 12 05:03:37 PM PDT 24
Peak memory 217940 kb
Host smart-cadcd906-6306-478f-95b3-f7ace45f0c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060549522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1060549522
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1094066006
Short name T123
Test name
Test status
Simulation time 478225825 ps
CPU time 154.34 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:05:44 PM PDT 24
Peak memory 214552 kb
Host smart-fdbc6e97-7f9e-4461-a590-f50dc55c647c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094066006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1094066006
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1035037431
Short name T400
Test name
Test status
Simulation time 991438059 ps
CPU time 14.38 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:19 PM PDT 24
Peak memory 210972 kb
Host smart-21e4bb78-0f30-4e86-b35a-714aa27adc35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035037431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1035037431
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3098340756
Short name T399
Test name
Test status
Simulation time 1831799222 ps
CPU time 8.64 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:15 PM PDT 24
Peak memory 211188 kb
Host smart-328d0c0f-befa-4057-897e-b942777abbf5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098340756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3098340756
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3840783349
Short name T356
Test name
Test status
Simulation time 845558026 ps
CPU time 15.76 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:23 PM PDT 24
Peak memory 212540 kb
Host smart-58c0efda-70bc-48b9-83f4-2b76a0af67ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840783349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3840783349
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3352324766
Short name T346
Test name
Test status
Simulation time 887547379 ps
CPU time 8.94 seconds
Started Aug 12 05:03:21 PM PDT 24
Finished Aug 12 05:03:30 PM PDT 24
Peak memory 216332 kb
Host smart-c3e7e294-649a-45d6-b628-da87e59171e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352324766 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3352324766
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3165507077
Short name T376
Test name
Test status
Simulation time 175633166 ps
CPU time 8.22 seconds
Started Aug 12 05:03:26 PM PDT 24
Finished Aug 12 05:03:35 PM PDT 24
Peak memory 211692 kb
Host smart-b89666a8-f4d1-4680-8f5d-f1ae1e3c4fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165507077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3165507077
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3596575837
Short name T335
Test name
Test status
Simulation time 252019653 ps
CPU time 10 seconds
Started Aug 12 05:03:14 PM PDT 24
Finished Aug 12 05:03:24 PM PDT 24
Peak memory 210828 kb
Host smart-85b4c2dc-c830-4940-addd-cf3830d27b9a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596575837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3596575837
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3459149193
Short name T332
Test name
Test status
Simulation time 175002738 ps
CPU time 8.44 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:03:19 PM PDT 24
Peak memory 210904 kb
Host smart-c95d109b-48bd-4fac-a323-202353331884
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459149193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3459149193
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3769425410
Short name T374
Test name
Test status
Simulation time 2870632436 ps
CPU time 38.71 seconds
Started Aug 12 05:03:23 PM PDT 24
Finished Aug 12 05:04:02 PM PDT 24
Peak memory 214164 kb
Host smart-71b3feef-b4b9-43c2-9009-b9e5ac601fbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769425410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3769425410
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.398631673
Short name T73
Test name
Test status
Simulation time 1418629345 ps
CPU time 13.96 seconds
Started Aug 12 05:03:17 PM PDT 24
Finished Aug 12 05:03:31 PM PDT 24
Peak memory 212744 kb
Host smart-49361423-e87a-43f3-8b34-e3470c9e79fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398631673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.398631673
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4123688806
Short name T330
Test name
Test status
Simulation time 1030574555 ps
CPU time 11.54 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:19 PM PDT 24
Peak memory 217636 kb
Host smart-4e8237e4-ea1b-487a-a641-21a6740f5522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123688806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4123688806
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3676895524
Short name T101
Test name
Test status
Simulation time 263342652 ps
CPU time 9.79 seconds
Started Aug 12 05:03:15 PM PDT 24
Finished Aug 12 05:03:25 PM PDT 24
Peak memory 211128 kb
Host smart-82984602-8ab9-4afc-9d25-c0191b231ea0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676895524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3676895524
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1921198641
Short name T324
Test name
Test status
Simulation time 593350160 ps
CPU time 10.46 seconds
Started Aug 12 05:03:12 PM PDT 24
Finished Aug 12 05:03:23 PM PDT 24
Peak memory 211012 kb
Host smart-bf64ab01-ab3c-4bb5-b53a-24ef1cdf1d4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921198641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1921198641
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4243667706
Short name T121
Test name
Test status
Simulation time 3139156895 ps
CPU time 17.14 seconds
Started Aug 12 05:03:14 PM PDT 24
Finished Aug 12 05:03:32 PM PDT 24
Peak memory 212684 kb
Host smart-40e1c5da-6e30-4c6d-b617-45b6f5f84e83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243667706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4243667706
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2628292302
Short name T404
Test name
Test status
Simulation time 182709519 ps
CPU time 8.69 seconds
Started Aug 12 05:03:24 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 215320 kb
Host smart-39e24667-6651-4e65-8fab-d4d35c16d5e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628292302 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2628292302
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2655099284
Short name T84
Test name
Test status
Simulation time 3946307152 ps
CPU time 14.77 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:42 PM PDT 24
Peak memory 211704 kb
Host smart-c5734dae-fde1-4d59-a957-20f7a9cc82e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655099284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2655099284
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3664287068
Short name T403
Test name
Test status
Simulation time 293698385 ps
CPU time 9.57 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:18 PM PDT 24
Peak memory 210780 kb
Host smart-e4322541-687a-4969-bd06-ce33272d5c30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664287068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3664287068
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2767598248
Short name T323
Test name
Test status
Simulation time 506214143 ps
CPU time 9.74 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:16 PM PDT 24
Peak memory 210796 kb
Host smart-91332f76-451a-498b-9bd7-21d4e8635153
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767598248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2767598248
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2867681845
Short name T357
Test name
Test status
Simulation time 2117194730 ps
CPU time 56.65 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:04:05 PM PDT 24
Peak memory 215484 kb
Host smart-2b6df3cd-a29a-49a6-a7ba-4dd12c3c23a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867681845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2867681845
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1219657973
Short name T355
Test name
Test status
Simulation time 476098355 ps
CPU time 9.98 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:03:19 PM PDT 24
Peak memory 211832 kb
Host smart-bde319c4-8327-4cf9-8c02-21c83cce3747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219657973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1219657973
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1816962197
Short name T377
Test name
Test status
Simulation time 167478871 ps
CPU time 11.49 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:18 PM PDT 24
Peak memory 217456 kb
Host smart-cf2c4291-0993-40b6-89be-399a841a72d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816962197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1816962197
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.629222812
Short name T384
Test name
Test status
Simulation time 470271360 ps
CPU time 80.53 seconds
Started Aug 12 05:03:15 PM PDT 24
Finished Aug 12 05:04:35 PM PDT 24
Peak memory 213068 kb
Host smart-b41237b1-1ec8-4357-895d-f9f56bf16421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629222812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.629222812
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1544057057
Short name T408
Test name
Test status
Simulation time 1046749364 ps
CPU time 11.15 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:03:27 PM PDT 24
Peak memory 218036 kb
Host smart-663caa0b-cd48-4887-a232-858354e02239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544057057 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1544057057
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.562045736
Short name T364
Test name
Test status
Simulation time 2747947443 ps
CPU time 10.15 seconds
Started Aug 12 05:03:12 PM PDT 24
Finished Aug 12 05:03:22 PM PDT 24
Peak memory 211316 kb
Host smart-eb244043-8d66-4d74-8926-855850531069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562045736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.562045736
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3866595856
Short name T326
Test name
Test status
Simulation time 3208668821 ps
CPU time 56.36 seconds
Started Aug 12 05:03:10 PM PDT 24
Finished Aug 12 05:04:07 PM PDT 24
Peak memory 216200 kb
Host smart-2c3fea66-193d-48ba-b67f-b37f0f6c7ff5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866595856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3866595856
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3230412571
Short name T337
Test name
Test status
Simulation time 1029835902 ps
CPU time 13.98 seconds
Started Aug 12 05:03:22 PM PDT 24
Finished Aug 12 05:03:36 PM PDT 24
Peak memory 212804 kb
Host smart-0a84cf5e-873f-4660-934c-39e77310bc39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230412571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3230412571
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1664639159
Short name T405
Test name
Test status
Simulation time 171444659 ps
CPU time 11.37 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:03:21 PM PDT 24
Peak memory 218324 kb
Host smart-648c978b-c470-4a86-99e7-15a682bc7829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664639159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1664639159
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2281656763
Short name T371
Test name
Test status
Simulation time 519225969 ps
CPU time 80.14 seconds
Started Aug 12 05:03:13 PM PDT 24
Finished Aug 12 05:04:33 PM PDT 24
Peak memory 214084 kb
Host smart-1c1b8794-8071-4906-989f-548d9746bd2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281656763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2281656763
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.331483962
Short name T345
Test name
Test status
Simulation time 1076905771 ps
CPU time 10.59 seconds
Started Aug 12 05:03:12 PM PDT 24
Finished Aug 12 05:03:23 PM PDT 24
Peak memory 217808 kb
Host smart-43181d59-7b27-4a24-bc5e-3ec1799aff43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331483962 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.331483962
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3513611274
Short name T395
Test name
Test status
Simulation time 265688325 ps
CPU time 9.78 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:03:21 PM PDT 24
Peak memory 211104 kb
Host smart-1d0ed9e0-a34a-415f-91b5-057b323642b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513611274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3513611274
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3844271210
Short name T91
Test name
Test status
Simulation time 2857382227 ps
CPU time 37.16 seconds
Started Aug 12 05:03:15 PM PDT 24
Finished Aug 12 05:03:52 PM PDT 24
Peak memory 214244 kb
Host smart-2bd7cc8e-0009-435f-bfe5-627ae1347976
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844271210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3844271210
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.201439932
Short name T385
Test name
Test status
Simulation time 670566844 ps
CPU time 9.84 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:03:21 PM PDT 24
Peak memory 211548 kb
Host smart-29707a1f-6ec5-4888-9c7b-70dd9db3a50b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201439932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.201439932
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.120607648
Short name T53
Test name
Test status
Simulation time 1123357068 ps
CPU time 13.82 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:20 PM PDT 24
Peak memory 217844 kb
Host smart-d0a3b70a-bf33-4446-952f-5c6c1b8f7904
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120607648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.120607648
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4140489376
Short name T57
Test name
Test status
Simulation time 775193539 ps
CPU time 154.21 seconds
Started Aug 12 05:03:14 PM PDT 24
Finished Aug 12 05:05:48 PM PDT 24
Peak memory 214468 kb
Host smart-d90c4dc2-fda4-436e-88a2-0f38fc1a09d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140489376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4140489376
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3756647876
Short name T383
Test name
Test status
Simulation time 282115802 ps
CPU time 11.52 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:03:23 PM PDT 24
Peak memory 219160 kb
Host smart-8df4077e-e175-4445-b1c1-88d830603ba2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756647876 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3756647876
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2075442146
Short name T93
Test name
Test status
Simulation time 990302240 ps
CPU time 10.11 seconds
Started Aug 12 05:03:17 PM PDT 24
Finished Aug 12 05:03:28 PM PDT 24
Peak memory 211172 kb
Host smart-b835e4ff-6829-4327-9f1c-cca6d93c0896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075442146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2075442146
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3894232654
Short name T336
Test name
Test status
Simulation time 987412820 ps
CPU time 9.42 seconds
Started Aug 12 05:03:25 PM PDT 24
Finished Aug 12 05:03:35 PM PDT 24
Peak memory 211864 kb
Host smart-d84dae3e-e63a-4494-900c-55172c967aa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894232654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3894232654
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3642612546
Short name T388
Test name
Test status
Simulation time 174574294 ps
CPU time 12.85 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:20 PM PDT 24
Peak memory 217720 kb
Host smart-fd94dee4-8c3d-4f26-8146-89b4c26300d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642612546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3642612546
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2892117049
Short name T124
Test name
Test status
Simulation time 2131798759 ps
CPU time 151.46 seconds
Started Aug 12 05:03:13 PM PDT 24
Finished Aug 12 05:05:44 PM PDT 24
Peak memory 214436 kb
Host smart-16747723-7846-41b4-a730-c56990bbab8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892117049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2892117049
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1714249407
Short name T373
Test name
Test status
Simulation time 1057248702 ps
CPU time 10.18 seconds
Started Aug 12 05:03:14 PM PDT 24
Finished Aug 12 05:03:25 PM PDT 24
Peak memory 215280 kb
Host smart-9d0076b7-d349-40ad-86d3-4526d3515cc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714249407 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1714249407
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2881727700
Short name T98
Test name
Test status
Simulation time 990598478 ps
CPU time 15.04 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:42 PM PDT 24
Peak memory 210932 kb
Host smart-a7e58b81-58bb-488f-8f84-31cb65f338a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881727700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2881727700
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.723030070
Short name T89
Test name
Test status
Simulation time 2026422933 ps
CPU time 43.23 seconds
Started Aug 12 05:03:12 PM PDT 24
Finished Aug 12 05:03:56 PM PDT 24
Peak memory 214088 kb
Host smart-737842a5-0876-4b28-9c12-f80487f1733f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723030070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.723030070
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.651459268
Short name T394
Test name
Test status
Simulation time 170064742 ps
CPU time 8.38 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:03:18 PM PDT 24
Peak memory 211628 kb
Host smart-9758da75-95bb-43ad-b1f9-71926c6754e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651459268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.651459268
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2098858222
Short name T368
Test name
Test status
Simulation time 660922978 ps
CPU time 11.14 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:19 PM PDT 24
Peak memory 217692 kb
Host smart-566f3067-0199-46a7-9c71-7e368a49757d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098858222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2098858222
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2271594377
Short name T56
Test name
Test status
Simulation time 1208999062 ps
CPU time 156.32 seconds
Started Aug 12 05:03:09 PM PDT 24
Finished Aug 12 05:05:46 PM PDT 24
Peak memory 219124 kb
Host smart-42355d1b-ca6d-405f-bfec-9e5037ade429
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271594377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2271594377
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2160545443
Short name T74
Test name
Test status
Simulation time 194648835 ps
CPU time 9.34 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:03:40 PM PDT 24
Peak memory 217976 kb
Host smart-fd0c29cc-e8de-4c17-a7b4-e070e93eb4a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160545443 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2160545443
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2826797603
Short name T116
Test name
Test status
Simulation time 168253524 ps
CPU time 8.27 seconds
Started Aug 12 05:03:24 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 211276 kb
Host smart-f91c8e35-f1b2-40b5-b3dc-479f50588aba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826797603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2826797603
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.564796850
Short name T333
Test name
Test status
Simulation time 1089800590 ps
CPU time 36.06 seconds
Started Aug 12 05:03:12 PM PDT 24
Finished Aug 12 05:03:48 PM PDT 24
Peak memory 214092 kb
Host smart-3ad82ee5-df0c-4071-89b2-9f88ab74ccc4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564796850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.564796850
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.40048325
Short name T342
Test name
Test status
Simulation time 262104329 ps
CPU time 13.94 seconds
Started Aug 12 05:03:14 PM PDT 24
Finished Aug 12 05:03:28 PM PDT 24
Peak memory 211756 kb
Host smart-fc3c0298-965d-4a4d-ae57-204ec1217c82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40048325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctr
l_same_csr_outstanding.40048325
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2630583709
Short name T344
Test name
Test status
Simulation time 250645882 ps
CPU time 13.29 seconds
Started Aug 12 05:03:17 PM PDT 24
Finished Aug 12 05:03:31 PM PDT 24
Peak memory 217552 kb
Host smart-71ae4c88-f288-4d7f-a6ee-3028ff9ff600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630583709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2630583709
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2560103097
Short name T122
Test name
Test status
Simulation time 1146041479 ps
CPU time 161.15 seconds
Started Aug 12 05:03:13 PM PDT 24
Finished Aug 12 05:05:55 PM PDT 24
Peak memory 215584 kb
Host smart-02b6f0ae-d08d-4b03-84e3-e4d5c62fc502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560103097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2560103097
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1360068206
Short name T200
Test name
Test status
Simulation time 167735687 ps
CPU time 8.45 seconds
Started Aug 12 06:19:08 PM PDT 24
Finished Aug 12 06:19:17 PM PDT 24
Peak memory 218700 kb
Host smart-66bbbd96-32a5-45e9-bc9c-9e5fc1335c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360068206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1360068206
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.927897504
Short name T150
Test name
Test status
Simulation time 1939443203 ps
CPU time 124.24 seconds
Started Aug 12 06:19:09 PM PDT 24
Finished Aug 12 06:21:14 PM PDT 24
Peak memory 243280 kb
Host smart-716e4bc5-b80e-4ce4-8667-210bde3ad440
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927897504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.927897504
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3610589025
Short name T295
Test name
Test status
Simulation time 345712845 ps
CPU time 19.66 seconds
Started Aug 12 06:19:09 PM PDT 24
Finished Aug 12 06:19:28 PM PDT 24
Peak memory 219628 kb
Host smart-85efbacb-21d1-4839-a8e0-74fa55b75b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610589025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3610589025
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3588315342
Short name T214
Test name
Test status
Simulation time 1031850162 ps
CPU time 12.58 seconds
Started Aug 12 06:19:13 PM PDT 24
Finished Aug 12 06:19:25 PM PDT 24
Peak memory 219348 kb
Host smart-c385e4bd-f335-480f-9696-57935427018a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588315342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3588315342
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1517498215
Short name T32
Test name
Test status
Simulation time 4325969113 ps
CPU time 123.96 seconds
Started Aug 12 06:19:09 PM PDT 24
Finished Aug 12 06:21:13 PM PDT 24
Peak memory 239360 kb
Host smart-1bcb5fd9-e399-4404-bf22-52d13a7dc60b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517498215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1517498215
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.684895935
Short name T262
Test name
Test status
Simulation time 1186487446 ps
CPU time 12.13 seconds
Started Aug 12 06:19:08 PM PDT 24
Finished Aug 12 06:19:20 PM PDT 24
Peak memory 219292 kb
Host smart-5ffd08e6-79cc-4f10-9756-ea4023375fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684895935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.684895935
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1242617643
Short name T39
Test name
Test status
Simulation time 4274584749 ps
CPU time 15.26 seconds
Started Aug 12 06:19:09 PM PDT 24
Finished Aug 12 06:19:24 PM PDT 24
Peak memory 218504 kb
Host smart-48dfc132-c433-4b2b-8c7b-368ee86a8e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242617643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1242617643
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.444399070
Short name T160
Test name
Test status
Simulation time 3611322776 ps
CPU time 225.47 seconds
Started Aug 12 06:19:09 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 219648 kb
Host smart-9cb7161e-8329-4da4-9153-acae80c21062
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444399070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.444399070
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1819121065
Short name T305
Test name
Test status
Simulation time 217777532 ps
CPU time 10.79 seconds
Started Aug 12 06:19:09 PM PDT 24
Finished Aug 12 06:19:20 PM PDT 24
Peak memory 219368 kb
Host smart-a4fb4730-8467-4391-9e98-b4590a79d7a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819121065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1819121065
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.427336752
Short name T25
Test name
Test status
Simulation time 319861958 ps
CPU time 120.23 seconds
Started Aug 12 06:19:10 PM PDT 24
Finished Aug 12 06:21:10 PM PDT 24
Peak memory 237412 kb
Host smart-2b0bf19a-ae17-402e-848d-bc4cedd678cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427336752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.427336752
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3565576927
Short name T252
Test name
Test status
Simulation time 1986562160 ps
CPU time 16.86 seconds
Started Aug 12 06:19:13 PM PDT 24
Finished Aug 12 06:19:30 PM PDT 24
Peak memory 219372 kb
Host smart-ed0d5f47-a896-41f0-aff2-f07a7fe63471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565576927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3565576927
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1385217901
Short name T62
Test name
Test status
Simulation time 4283343560 ps
CPU time 48.17 seconds
Started Aug 12 06:19:08 PM PDT 24
Finished Aug 12 06:19:56 PM PDT 24
Peak memory 219376 kb
Host smart-db0b63b2-72cf-4f47-934d-1c0be14cb3ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385217901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1385217901
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2066162343
Short name T313
Test name
Test status
Simulation time 180481773 ps
CPU time 8.35 seconds
Started Aug 12 06:19:21 PM PDT 24
Finished Aug 12 06:19:29 PM PDT 24
Peak memory 218692 kb
Host smart-8cd77851-a885-410c-a856-47a9c6010c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066162343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2066162343
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4020771911
Short name T232
Test name
Test status
Simulation time 33939709963 ps
CPU time 161.42 seconds
Started Aug 12 06:19:17 PM PDT 24
Finished Aug 12 06:21:59 PM PDT 24
Peak memory 229784 kb
Host smart-e4fdade6-6a4c-40f6-a5b7-0a656a651296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020771911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4020771911
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1683600854
Short name T291
Test name
Test status
Simulation time 339193048 ps
CPU time 19.99 seconds
Started Aug 12 06:19:17 PM PDT 24
Finished Aug 12 06:19:37 PM PDT 24
Peak memory 219372 kb
Host smart-5d26a475-2740-4ddc-81e8-7e1eb17f46b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683600854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1683600854
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.178979598
Short name T135
Test name
Test status
Simulation time 268759982 ps
CPU time 12.12 seconds
Started Aug 12 06:19:19 PM PDT 24
Finished Aug 12 06:19:31 PM PDT 24
Peak memory 219116 kb
Host smart-80f220c8-545e-4536-a796-22ecbb1e926e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178979598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.178979598
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3130052783
Short name T223
Test name
Test status
Simulation time 1216260116 ps
CPU time 34.01 seconds
Started Aug 12 06:19:15 PM PDT 24
Finished Aug 12 06:19:49 PM PDT 24
Peak memory 219276 kb
Host smart-44ad35ef-a979-47c4-93b7-335ce7165885
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130052783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3130052783
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1942382565
Short name T276
Test name
Test status
Simulation time 173129913 ps
CPU time 8.35 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:34 PM PDT 24
Peak memory 218776 kb
Host smart-febf40c3-71be-43e2-a228-b1970c00e474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942382565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1942382565
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2087882618
Short name T278
Test name
Test status
Simulation time 35577137335 ps
CPU time 232.12 seconds
Started Aug 12 06:19:18 PM PDT 24
Finished Aug 12 06:23:10 PM PDT 24
Peak memory 237796 kb
Host smart-04e9e76c-ebe1-423b-a2fa-0047ab3c0f41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087882618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2087882618
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3601777613
Short name T203
Test name
Test status
Simulation time 2067051554 ps
CPU time 22.94 seconds
Started Aug 12 06:19:21 PM PDT 24
Finished Aug 12 06:19:44 PM PDT 24
Peak memory 219456 kb
Host smart-cfb52f52-1b70-44bb-b8dc-2603c0b34bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601777613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3601777613
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3935037826
Short name T251
Test name
Test status
Simulation time 721303538 ps
CPU time 10.3 seconds
Started Aug 12 06:19:21 PM PDT 24
Finished Aug 12 06:19:31 PM PDT 24
Peak memory 219316 kb
Host smart-b7f08237-a00b-45f2-9538-95e3add6cc8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935037826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3935037826
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1147595267
Short name T319
Test name
Test status
Simulation time 1101053552 ps
CPU time 24.82 seconds
Started Aug 12 06:19:17 PM PDT 24
Finished Aug 12 06:19:42 PM PDT 24
Peak memory 219300 kb
Host smart-f3e0b5ee-2961-4807-bc07-8c2b761d8a07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147595267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1147595267
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3196343779
Short name T314
Test name
Test status
Simulation time 256775205 ps
CPU time 10.54 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:31 PM PDT 24
Peak memory 218716 kb
Host smart-47d1243f-5790-45e3-819d-2d4f0869bea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196343779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3196343779
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.706046265
Short name T226
Test name
Test status
Simulation time 1455852388 ps
CPU time 22.17 seconds
Started Aug 12 06:19:24 PM PDT 24
Finished Aug 12 06:19:47 PM PDT 24
Peak memory 219484 kb
Host smart-65a8b95a-3b7d-4165-80e7-7feae58552c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706046265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.706046265
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.702858065
Short name T225
Test name
Test status
Simulation time 3210901225 ps
CPU time 12.4 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:19:38 PM PDT 24
Peak memory 219416 kb
Host smart-f4e7d638-d8ef-47eb-b244-9ef546ad88df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702858065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.702858065
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3168639856
Short name T255
Test name
Test status
Simulation time 4913249675 ps
CPU time 37.54 seconds
Started Aug 12 06:19:26 PM PDT 24
Finished Aug 12 06:20:04 PM PDT 24
Peak memory 219412 kb
Host smart-d87716c4-8797-4b48-a3c1-3bc5d24bf892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168639856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3168639856
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1597967806
Short name T235
Test name
Test status
Simulation time 249078529 ps
CPU time 9.99 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:19:36 PM PDT 24
Peak memory 218636 kb
Host smart-f2849dfb-f7b1-42ac-b3d6-36da1cead1d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597967806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1597967806
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3813658473
Short name T112
Test name
Test status
Simulation time 495271187 ps
CPU time 22.63 seconds
Started Aug 12 06:19:28 PM PDT 24
Finished Aug 12 06:19:50 PM PDT 24
Peak memory 219116 kb
Host smart-7a5dd617-6ae4-4284-8dd0-b35f1f461467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813658473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3813658473
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3285310285
Short name T274
Test name
Test status
Simulation time 1164233566 ps
CPU time 12.4 seconds
Started Aug 12 06:19:28 PM PDT 24
Finished Aug 12 06:19:40 PM PDT 24
Peak memory 218976 kb
Host smart-9cf76ab7-1a50-495a-8de8-5add16d75469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285310285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3285310285
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.766242996
Short name T96
Test name
Test status
Simulation time 300427864 ps
CPU time 16.34 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:19:41 PM PDT 24
Peak memory 219304 kb
Host smart-a64f29b0-9793-4e45-b689-7a09dcdbf613
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766242996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.766242996
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1857420943
Short name T151
Test name
Test status
Simulation time 988268788 ps
CPU time 10.05 seconds
Started Aug 12 06:19:31 PM PDT 24
Finished Aug 12 06:19:41 PM PDT 24
Peak memory 218696 kb
Host smart-16e4311f-04b9-46ee-84c9-12e92c752f34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857420943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1857420943
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3147794375
Short name T304
Test name
Test status
Simulation time 5637015778 ps
CPU time 150.3 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:21:56 PM PDT 24
Peak memory 229660 kb
Host smart-619e8a71-4369-4341-abd6-8c27d436f153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147794375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3147794375
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1599082528
Short name T221
Test name
Test status
Simulation time 497670615 ps
CPU time 23.09 seconds
Started Aug 12 06:19:24 PM PDT 24
Finished Aug 12 06:19:47 PM PDT 24
Peak memory 219456 kb
Host smart-d04f3bc5-fdea-4f17-aadd-b1ede243ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599082528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1599082528
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.404820467
Short name T63
Test name
Test status
Simulation time 1223581501 ps
CPU time 12.01 seconds
Started Aug 12 06:19:31 PM PDT 24
Finished Aug 12 06:19:43 PM PDT 24
Peak memory 219376 kb
Host smart-4f639ddf-c5bd-48d4-a486-fec4e7826ddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404820467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.404820467
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1048338315
Short name T211
Test name
Test status
Simulation time 952311757 ps
CPU time 9.78 seconds
Started Aug 12 06:19:29 PM PDT 24
Finished Aug 12 06:19:39 PM PDT 24
Peak memory 218756 kb
Host smart-b18b955f-8754-48c4-987a-ea1e0921e90a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048338315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1048338315
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2577227590
Short name T316
Test name
Test status
Simulation time 29630825650 ps
CPU time 403.95 seconds
Started Aug 12 06:19:26 PM PDT 24
Finished Aug 12 06:26:11 PM PDT 24
Peak memory 234908 kb
Host smart-5ba69905-b6ae-4449-8ae3-fc64835c83a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577227590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2577227590
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2808415506
Short name T286
Test name
Test status
Simulation time 689453486 ps
CPU time 19.24 seconds
Started Aug 12 06:19:28 PM PDT 24
Finished Aug 12 06:19:48 PM PDT 24
Peak memory 219504 kb
Host smart-e142eee7-0e28-470e-b437-dd6e6b84982c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808415506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2808415506
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1954691343
Short name T284
Test name
Test status
Simulation time 348818044 ps
CPU time 10.22 seconds
Started Aug 12 06:19:24 PM PDT 24
Finished Aug 12 06:19:35 PM PDT 24
Peak memory 219300 kb
Host smart-9dff936c-1ff8-41b3-b7bf-8661a7e93d7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954691343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1954691343
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1875725215
Short name T18
Test name
Test status
Simulation time 2138605131 ps
CPU time 26.67 seconds
Started Aug 12 06:19:26 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 219332 kb
Host smart-5646a502-25f3-4744-83e4-16b2d0041035
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875725215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1875725215
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.115400550
Short name T257
Test name
Test status
Simulation time 527249252 ps
CPU time 10.25 seconds
Started Aug 12 06:19:29 PM PDT 24
Finished Aug 12 06:19:40 PM PDT 24
Peak memory 218756 kb
Host smart-56cca97f-93b4-44d9-a507-dffac5bcc9ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115400550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.115400550
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.486946507
Short name T21
Test name
Test status
Simulation time 17748097342 ps
CPU time 236.58 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 239132 kb
Host smart-624f6a3d-8039-4e2c-a507-66a99150348b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486946507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.486946507
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2096714391
Short name T268
Test name
Test status
Simulation time 334022601 ps
CPU time 18.88 seconds
Started Aug 12 06:19:30 PM PDT 24
Finished Aug 12 06:19:49 PM PDT 24
Peak memory 219412 kb
Host smart-30fc7a55-a25b-46e0-a2d2-8fc2701e2039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096714391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2096714391
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.704544322
Short name T137
Test name
Test status
Simulation time 716194720 ps
CPU time 10.19 seconds
Started Aug 12 06:19:24 PM PDT 24
Finished Aug 12 06:19:34 PM PDT 24
Peak memory 219296 kb
Host smart-c10fa5f2-3e8c-44a7-90b2-63a321f273e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704544322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.704544322
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2299276305
Short name T157
Test name
Test status
Simulation time 3644724898 ps
CPU time 20.56 seconds
Started Aug 12 06:19:24 PM PDT 24
Finished Aug 12 06:19:44 PM PDT 24
Peak memory 219416 kb
Host smart-c63e5799-a932-4d71-a56c-0b49d10a02d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299276305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2299276305
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1225946325
Short name T172
Test name
Test status
Simulation time 506645212 ps
CPU time 9.98 seconds
Started Aug 12 06:19:31 PM PDT 24
Finished Aug 12 06:19:41 PM PDT 24
Peak memory 218768 kb
Host smart-e4fe04d3-7409-4968-8e90-cd7f53b7ffce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225946325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1225946325
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1753915223
Short name T20
Test name
Test status
Simulation time 3782193205 ps
CPU time 263.41 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:23:49 PM PDT 24
Peak memory 238836 kb
Host smart-03690bf0-4838-4585-be62-4fdd1738f5f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753915223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1753915223
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.444433498
Short name T48
Test name
Test status
Simulation time 499335870 ps
CPU time 22.82 seconds
Started Aug 12 06:19:26 PM PDT 24
Finished Aug 12 06:19:49 PM PDT 24
Peak memory 219492 kb
Host smart-71a0d7c5-6bd2-4b31-ae73-0563f2211837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444433498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.444433498
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3538100320
Short name T311
Test name
Test status
Simulation time 266922059 ps
CPU time 12.47 seconds
Started Aug 12 06:19:23 PM PDT 24
Finished Aug 12 06:19:36 PM PDT 24
Peak memory 219316 kb
Host smart-11d8f4c9-c61e-42ec-a4fb-3c9015977a77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538100320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3538100320
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2073289635
Short name T71
Test name
Test status
Simulation time 278938828 ps
CPU time 19.4 seconds
Started Aug 12 06:19:34 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 219344 kb
Host smart-6247c311-4882-4d8d-ba8b-4168b69aee28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073289635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2073289635
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3204688269
Short name T263
Test name
Test status
Simulation time 168152225 ps
CPU time 8.57 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:19:34 PM PDT 24
Peak memory 218840 kb
Host smart-b8740cbc-fb92-464e-b3fe-bcb848ea3689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204688269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3204688269
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1978756301
Short name T152
Test name
Test status
Simulation time 18142368557 ps
CPU time 282.22 seconds
Started Aug 12 06:19:23 PM PDT 24
Finished Aug 12 06:24:05 PM PDT 24
Peak memory 219696 kb
Host smart-5dc990bb-56f3-4e56-85f2-9241b2ffa862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978756301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1978756301
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1784955912
Short name T210
Test name
Test status
Simulation time 2544907473 ps
CPU time 19 seconds
Started Aug 12 06:19:29 PM PDT 24
Finished Aug 12 06:19:49 PM PDT 24
Peak memory 219444 kb
Host smart-b4a1c047-2e4b-49f3-a195-eaa7b218a5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784955912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1784955912
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3801499320
Short name T163
Test name
Test status
Simulation time 1737726543 ps
CPU time 18.09 seconds
Started Aug 12 06:19:29 PM PDT 24
Finished Aug 12 06:19:48 PM PDT 24
Peak memory 219312 kb
Host smart-343cab24-e3e6-425f-8e74-3c77b80fc9c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801499320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3801499320
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1920255741
Short name T69
Test name
Test status
Simulation time 517173748 ps
CPU time 10.41 seconds
Started Aug 12 06:19:27 PM PDT 24
Finished Aug 12 06:19:37 PM PDT 24
Peak memory 218804 kb
Host smart-a7037157-87fd-4a3d-a462-a8439a26aa27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920255741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1920255741
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.804925268
Short name T186
Test name
Test status
Simulation time 21746885081 ps
CPU time 290.59 seconds
Started Aug 12 06:19:31 PM PDT 24
Finished Aug 12 06:24:21 PM PDT 24
Peak memory 233884 kb
Host smart-f7fdb27b-3b78-40a5-934c-13c23a284875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804925268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.804925268
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3572412501
Short name T173
Test name
Test status
Simulation time 496966109 ps
CPU time 23.4 seconds
Started Aug 12 06:19:23 PM PDT 24
Finished Aug 12 06:19:46 PM PDT 24
Peak memory 219456 kb
Host smart-8a301048-86bf-4223-bbee-1578e929480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572412501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3572412501
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3963034969
Short name T234
Test name
Test status
Simulation time 1330156706 ps
CPU time 26.81 seconds
Started Aug 12 06:19:30 PM PDT 24
Finished Aug 12 06:19:57 PM PDT 24
Peak memory 219348 kb
Host smart-60f34b01-4161-4c08-a95c-204e335bd73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963034969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3963034969
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.299676078
Short name T191
Test name
Test status
Simulation time 786764696 ps
CPU time 8.33 seconds
Started Aug 12 06:19:10 PM PDT 24
Finished Aug 12 06:19:19 PM PDT 24
Peak memory 218516 kb
Host smart-c39eb2fe-672b-4c6c-945a-351ab430f640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299676078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.299676078
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.869263785
Short name T259
Test name
Test status
Simulation time 6327923808 ps
CPU time 276.88 seconds
Started Aug 12 06:19:10 PM PDT 24
Finished Aug 12 06:23:47 PM PDT 24
Peak memory 242172 kb
Host smart-66e046f1-fe3e-4f04-be52-8cf6c8a58f4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869263785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.869263785
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2755451019
Short name T207
Test name
Test status
Simulation time 1905031517 ps
CPU time 22.88 seconds
Started Aug 12 06:19:09 PM PDT 24
Finished Aug 12 06:19:32 PM PDT 24
Peak memory 219456 kb
Host smart-df8e4f8b-62d0-4c2c-afe2-a9410d039138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755451019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2755451019
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1552325914
Short name T138
Test name
Test status
Simulation time 875735121 ps
CPU time 10.85 seconds
Started Aug 12 06:19:10 PM PDT 24
Finished Aug 12 06:19:21 PM PDT 24
Peak memory 219340 kb
Host smart-0d02b9a9-8b59-4c88-8cf2-5b537de1954b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552325914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1552325914
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1931912644
Short name T26
Test name
Test status
Simulation time 884140993 ps
CPU time 119.82 seconds
Started Aug 12 06:19:11 PM PDT 24
Finished Aug 12 06:21:11 PM PDT 24
Peak memory 235248 kb
Host smart-7dfbcecb-86fe-4900-ae7c-beb631ed6b16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931912644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1931912644
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4176068690
Short name T273
Test name
Test status
Simulation time 1137632853 ps
CPU time 10.65 seconds
Started Aug 12 06:19:09 PM PDT 24
Finished Aug 12 06:19:20 PM PDT 24
Peak memory 219328 kb
Host smart-5563c330-e196-4b47-bc2f-53f07600e14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176068690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4176068690
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1044928370
Short name T145
Test name
Test status
Simulation time 1487624155 ps
CPU time 11.63 seconds
Started Aug 12 06:19:14 PM PDT 24
Finished Aug 12 06:19:26 PM PDT 24
Peak memory 219344 kb
Host smart-da688241-a3c7-4dca-b5aa-96b4e6a9858e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044928370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1044928370
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.676411157
Short name T195
Test name
Test status
Simulation time 1303046297 ps
CPU time 10.14 seconds
Started Aug 12 06:19:26 PM PDT 24
Finished Aug 12 06:19:37 PM PDT 24
Peak memory 218604 kb
Host smart-ef529f27-e661-42ea-9dc7-820cc21ee93b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676411157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.676411157
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2606088783
Short name T42
Test name
Test status
Simulation time 4031317372 ps
CPU time 240.27 seconds
Started Aug 12 06:19:24 PM PDT 24
Finished Aug 12 06:23:24 PM PDT 24
Peak memory 229052 kb
Host smart-6aa795cf-97fc-439a-b041-e635b579626e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606088783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2606088783
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4291769750
Short name T306
Test name
Test status
Simulation time 2060006674 ps
CPU time 22.74 seconds
Started Aug 12 06:19:24 PM PDT 24
Finished Aug 12 06:19:47 PM PDT 24
Peak memory 219436 kb
Host smart-8f0a212b-edd1-4475-9588-50e6bd233851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291769750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4291769750
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1245446755
Short name T136
Test name
Test status
Simulation time 308372681 ps
CPU time 10.11 seconds
Started Aug 12 06:19:39 PM PDT 24
Finished Aug 12 06:19:49 PM PDT 24
Peak memory 219352 kb
Host smart-196447ae-6623-4ab6-bade-db1efe9fc15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245446755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1245446755
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.829651145
Short name T301
Test name
Test status
Simulation time 3426017279 ps
CPU time 12.33 seconds
Started Aug 12 06:19:26 PM PDT 24
Finished Aug 12 06:19:39 PM PDT 24
Peak memory 219420 kb
Host smart-52a75e3b-b42b-456f-97b1-08c657b436e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829651145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.829651145
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1115768260
Short name T78
Test name
Test status
Simulation time 260522308 ps
CPU time 10.37 seconds
Started Aug 12 06:19:40 PM PDT 24
Finished Aug 12 06:19:50 PM PDT 24
Peak memory 218760 kb
Host smart-4872a662-4f55-402c-a386-b13684370f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115768260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1115768260
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1093312440
Short name T275
Test name
Test status
Simulation time 3852151014 ps
CPU time 215.77 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:23:19 PM PDT 24
Peak memory 236940 kb
Host smart-b74a67e1-1311-40e6-b726-4a156ec93170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093312440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1093312440
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.974153137
Short name T206
Test name
Test status
Simulation time 337686752 ps
CPU time 19.89 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:20:04 PM PDT 24
Peak memory 219432 kb
Host smart-8db8d2fc-a933-44ce-b091-4a949c1d5657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974153137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.974153137
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2496019733
Short name T240
Test name
Test status
Simulation time 514556848 ps
CPU time 11.91 seconds
Started Aug 12 06:19:31 PM PDT 24
Finished Aug 12 06:19:43 PM PDT 24
Peak memory 219400 kb
Host smart-398bea82-6f53-4085-8100-8c0467c6a2d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496019733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2496019733
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.579628215
Short name T192
Test name
Test status
Simulation time 3011563160 ps
CPU time 35.1 seconds
Started Aug 12 06:19:31 PM PDT 24
Finished Aug 12 06:20:06 PM PDT 24
Peak memory 219376 kb
Host smart-d900ac6b-8165-433c-a9d6-91a8f93b2ac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579628215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.579628215
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3345534504
Short name T189
Test name
Test status
Simulation time 508179197 ps
CPU time 9.94 seconds
Started Aug 12 06:19:37 PM PDT 24
Finished Aug 12 06:19:47 PM PDT 24
Peak memory 218736 kb
Host smart-7173221f-acad-4235-964e-1b92fbef2284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345534504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3345534504
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3013956557
Short name T246
Test name
Test status
Simulation time 346827877 ps
CPU time 19.27 seconds
Started Aug 12 06:19:40 PM PDT 24
Finished Aug 12 06:19:59 PM PDT 24
Peak memory 219452 kb
Host smart-a26d3c8a-3217-48fb-bed8-3181006d1675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013956557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3013956557
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2763637787
Short name T218
Test name
Test status
Simulation time 1054007301 ps
CPU time 12.37 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:19:57 PM PDT 24
Peak memory 219376 kb
Host smart-8f22e3f3-78ec-4805-a71c-8e6477c0eb85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763637787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2763637787
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.4128955242
Short name T16
Test name
Test status
Simulation time 2866390570 ps
CPU time 26.99 seconds
Started Aug 12 06:19:38 PM PDT 24
Finished Aug 12 06:20:05 PM PDT 24
Peak memory 219384 kb
Host smart-5298f2ff-b682-4be6-83ff-b4bf1da643b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128955242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.4128955242
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1306621759
Short name T249
Test name
Test status
Simulation time 993182239 ps
CPU time 10.25 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:19:54 PM PDT 24
Peak memory 218620 kb
Host smart-def440ef-a22a-4967-b538-fa29f7c60fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306621759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1306621759
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3798945304
Short name T36
Test name
Test status
Simulation time 13197096744 ps
CPU time 267.14 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:24:11 PM PDT 24
Peak memory 239776 kb
Host smart-39d1d8d6-3727-455b-a605-60bed6b6d23f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798945304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3798945304
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1884923718
Short name T308
Test name
Test status
Simulation time 346424065 ps
CPU time 19.7 seconds
Started Aug 12 06:19:37 PM PDT 24
Finished Aug 12 06:19:57 PM PDT 24
Peak memory 219632 kb
Host smart-bfa4e0af-92e4-4695-bd00-5a98c75eaaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884923718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1884923718
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2051335352
Short name T299
Test name
Test status
Simulation time 260495815 ps
CPU time 12.34 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:19:56 PM PDT 24
Peak memory 219348 kb
Host smart-90d70795-ff1a-423b-9428-dfa9c44e942b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051335352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2051335352
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3468540188
Short name T279
Test name
Test status
Simulation time 4080933391 ps
CPU time 31 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:20:15 PM PDT 24
Peak memory 219420 kb
Host smart-ac04046b-b6f6-4c78-b718-7910f4fb5d94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468540188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3468540188
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.60430901
Short name T228
Test name
Test status
Simulation time 1237066369 ps
CPU time 10.16 seconds
Started Aug 12 06:19:39 PM PDT 24
Finished Aug 12 06:19:49 PM PDT 24
Peak memory 218688 kb
Host smart-fcd3ddfb-7b19-478f-baea-a714e578adb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60430901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.60430901
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3143863337
Short name T264
Test name
Test status
Simulation time 9525085442 ps
CPU time 156.48 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 225540 kb
Host smart-e500400b-aa79-4302-a564-fe7699befbf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143863337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3143863337
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1497085980
Short name T164
Test name
Test status
Simulation time 524368486 ps
CPU time 22.83 seconds
Started Aug 12 06:19:40 PM PDT 24
Finished Aug 12 06:20:03 PM PDT 24
Peak memory 219396 kb
Host smart-559e4e47-9a6e-4414-90a4-11c3201d6b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497085980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1497085980
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.526252006
Short name T272
Test name
Test status
Simulation time 275339495 ps
CPU time 12.29 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 219332 kb
Host smart-875ea083-fe58-43fe-b02e-c083a93cb2e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526252006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.526252006
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.506443514
Short name T97
Test name
Test status
Simulation time 996856039 ps
CPU time 37.57 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:20:20 PM PDT 24
Peak memory 219324 kb
Host smart-bf8cd4e5-1957-42ae-a87d-8b08462533df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506443514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.506443514
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3271719773
Short name T315
Test name
Test status
Simulation time 663311615 ps
CPU time 8.21 seconds
Started Aug 12 06:19:39 PM PDT 24
Finished Aug 12 06:19:47 PM PDT 24
Peak memory 218744 kb
Host smart-c662f8f5-3269-4e13-885d-cd562ddee099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271719773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3271719773
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3637887608
Short name T167
Test name
Test status
Simulation time 5771868738 ps
CPU time 216.81 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:23:21 PM PDT 24
Peak memory 239256 kb
Host smart-3b489466-3672-4133-b37e-8edda0010b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637887608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3637887608
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2021993709
Short name T29
Test name
Test status
Simulation time 2552794896 ps
CPU time 19.61 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:20:03 PM PDT 24
Peak memory 219504 kb
Host smart-80206e54-3d8b-4405-b0cd-a61825034c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021993709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2021993709
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3884992906
Short name T245
Test name
Test status
Simulation time 664657482 ps
CPU time 10.32 seconds
Started Aug 12 06:19:40 PM PDT 24
Finished Aug 12 06:19:50 PM PDT 24
Peak memory 219292 kb
Host smart-714478af-0c1b-4deb-9834-558aa3210637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884992906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3884992906
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.433591168
Short name T166
Test name
Test status
Simulation time 776489531 ps
CPU time 11.1 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:19:52 PM PDT 24
Peak memory 219284 kb
Host smart-09fde744-fb22-44a5-bdf0-04bdb39f075a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433591168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.433591168
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3233695645
Short name T180
Test name
Test status
Simulation time 689194599 ps
CPU time 8.11 seconds
Started Aug 12 06:19:39 PM PDT 24
Finished Aug 12 06:19:47 PM PDT 24
Peak memory 218768 kb
Host smart-08d0fc03-bf8c-4c7d-9ec1-73c67d9c6b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233695645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3233695645
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2546547343
Short name T44
Test name
Test status
Simulation time 3651633604 ps
CPU time 149.24 seconds
Started Aug 12 06:19:40 PM PDT 24
Finished Aug 12 06:22:09 PM PDT 24
Peak memory 239824 kb
Host smart-ccbcf012-b041-4c90-96ba-05f89c5e486c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546547343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2546547343
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2895005343
Short name T155
Test name
Test status
Simulation time 680454828 ps
CPU time 19.39 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:20:00 PM PDT 24
Peak memory 219488 kb
Host smart-6fdb4575-9dd9-457a-b37b-7cd2648a9fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895005343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2895005343
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3066224819
Short name T198
Test name
Test status
Simulation time 1054417886 ps
CPU time 33.18 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:20:16 PM PDT 24
Peak memory 219360 kb
Host smart-e16dfa0d-acf7-46e4-b97d-217bfb277ee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066224819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3066224819
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1356051632
Short name T185
Test name
Test status
Simulation time 262422295 ps
CPU time 10.2 seconds
Started Aug 12 06:19:40 PM PDT 24
Finished Aug 12 06:19:50 PM PDT 24
Peak memory 218560 kb
Host smart-f91116d1-9d72-48b1-a841-4b70013e4c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356051632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1356051632
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3341385609
Short name T193
Test name
Test status
Simulation time 16262530539 ps
CPU time 168.37 seconds
Started Aug 12 06:19:38 PM PDT 24
Finished Aug 12 06:22:26 PM PDT 24
Peak memory 228984 kb
Host smart-0b39d0e6-a8a3-43bc-8b74-b7694a91abac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341385609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3341385609
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2183777381
Short name T242
Test name
Test status
Simulation time 1382846457 ps
CPU time 19.08 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:20:01 PM PDT 24
Peak memory 219456 kb
Host smart-b285b920-3de8-4d3c-a4d5-bddd3d9fd052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183777381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2183777381
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4251597304
Short name T321
Test name
Test status
Simulation time 551447405 ps
CPU time 12.8 seconds
Started Aug 12 06:19:50 PM PDT 24
Finished Aug 12 06:20:02 PM PDT 24
Peak memory 219344 kb
Host smart-0ed03492-adcb-4a16-93e2-070dd5b05681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251597304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4251597304
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1635934453
Short name T296
Test name
Test status
Simulation time 1048203353 ps
CPU time 50.19 seconds
Started Aug 12 06:19:39 PM PDT 24
Finished Aug 12 06:20:29 PM PDT 24
Peak memory 220044 kb
Host smart-2e5fb8e5-709a-450a-ae95-0dbfe33e9cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635934453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1635934453
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.833277023
Short name T271
Test name
Test status
Simulation time 9103124440 ps
CPU time 247.63 seconds
Started Aug 12 06:19:37 PM PDT 24
Finished Aug 12 06:23:45 PM PDT 24
Peak memory 238940 kb
Host smart-1b941b0f-02d8-451b-92b5-96990f45371a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833277023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.833277023
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.611841259
Short name T253
Test name
Test status
Simulation time 969522327 ps
CPU time 22.53 seconds
Started Aug 12 06:19:38 PM PDT 24
Finished Aug 12 06:20:01 PM PDT 24
Peak memory 219456 kb
Host smart-7a2767e9-b9b3-44f1-9681-6c0670fbb6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611841259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.611841259
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3023814955
Short name T134
Test name
Test status
Simulation time 258479781 ps
CPU time 11.8 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 219292 kb
Host smart-1bac3975-1838-4601-aa0c-0ddfefbc40d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023814955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3023814955
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2853676334
Short name T261
Test name
Test status
Simulation time 827208647 ps
CPU time 38.7 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:20:23 PM PDT 24
Peak memory 219312 kb
Host smart-ea21be6e-3c6a-4c4d-a790-5824b7696b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853676334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2853676334
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4236737986
Short name T1
Test name
Test status
Simulation time 505965086 ps
CPU time 10.11 seconds
Started Aug 12 06:19:40 PM PDT 24
Finished Aug 12 06:19:50 PM PDT 24
Peak memory 218768 kb
Host smart-2d2caace-a428-4610-983e-4b7ad22fe720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236737986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4236737986
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.281069264
Short name T303
Test name
Test status
Simulation time 4460925296 ps
CPU time 257.87 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:24:02 PM PDT 24
Peak memory 238468 kb
Host smart-85b4573e-b2d7-4d0b-9cec-0b2abfb53df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281069264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.281069264
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2808032997
Short name T9
Test name
Test status
Simulation time 2923464421 ps
CPU time 23.01 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:20:05 PM PDT 24
Peak memory 219528 kb
Host smart-dcfaad7b-521e-4939-9718-b65f7ad21754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808032997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2808032997
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.288997632
Short name T233
Test name
Test status
Simulation time 3624757613 ps
CPU time 12.86 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:19:54 PM PDT 24
Peak memory 219408 kb
Host smart-f5d56803-debf-4092-a13c-32c1a84c7243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288997632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.288997632
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4168223736
Short name T171
Test name
Test status
Simulation time 759763714 ps
CPU time 20.31 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:20:01 PM PDT 24
Peak memory 219320 kb
Host smart-52b5df44-704b-45f6-a3b4-e6a11cb5da93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168223736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4168223736
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1711992574
Short name T269
Test name
Test status
Simulation time 168108317 ps
CPU time 8.42 seconds
Started Aug 12 06:19:12 PM PDT 24
Finished Aug 12 06:19:21 PM PDT 24
Peak memory 218632 kb
Host smart-61fe778c-95e5-4b40-8aa9-6e0ae16acd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711992574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1711992574
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2292374433
Short name T46
Test name
Test status
Simulation time 24440998388 ps
CPU time 308.08 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:24:15 PM PDT 24
Peak memory 225728 kb
Host smart-35cc17fd-3962-4240-b6f3-2ec03bb384fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292374433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2292374433
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2637385267
Short name T224
Test name
Test status
Simulation time 502069814 ps
CPU time 22.59 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:30 PM PDT 24
Peak memory 219472 kb
Host smart-77158491-8d98-49a3-8643-8fc10c739e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637385267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2637385267
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2134071034
Short name T282
Test name
Test status
Simulation time 727505126 ps
CPU time 10.12 seconds
Started Aug 12 06:19:08 PM PDT 24
Finished Aug 12 06:19:19 PM PDT 24
Peak memory 219344 kb
Host smart-28b313e8-da02-4281-abf8-05d01ce5c085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134071034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2134071034
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4220203189
Short name T31
Test name
Test status
Simulation time 572801678 ps
CPU time 125.01 seconds
Started Aug 12 06:19:10 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 240040 kb
Host smart-1f34b8d8-6924-4763-850d-63edaa2bc103
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220203189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4220203189
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1006347102
Short name T60
Test name
Test status
Simulation time 5326349694 ps
CPU time 45.97 seconds
Started Aug 12 06:19:14 PM PDT 24
Finished Aug 12 06:20:00 PM PDT 24
Peak memory 220504 kb
Host smart-716d2774-f2af-4662-88ff-a7d65f0216ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006347102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1006347102
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3715209633
Short name T317
Test name
Test status
Simulation time 172624191 ps
CPU time 8.38 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:19:54 PM PDT 24
Peak memory 218388 kb
Host smart-3e9f32be-4869-4eb3-bde0-2fc845f8efb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715209633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3715209633
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2767769534
Short name T208
Test name
Test status
Simulation time 5259581934 ps
CPU time 321.93 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:25:04 PM PDT 24
Peak memory 240524 kb
Host smart-a3ab84fb-2ffa-4330-a768-23fc5f46673e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767769534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2767769534
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3004586731
Short name T169
Test name
Test status
Simulation time 336541698 ps
CPU time 19.09 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:07 PM PDT 24
Peak memory 219336 kb
Host smart-03879123-6303-4a1e-89e9-2e3d2ea87dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004586731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3004586731
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1536195786
Short name T254
Test name
Test status
Simulation time 761144262 ps
CPU time 10.17 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:19:55 PM PDT 24
Peak memory 219276 kb
Host smart-42127a89-1710-4fd8-834c-581474e1ffb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536195786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1536195786
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1266675263
Short name T147
Test name
Test status
Simulation time 400956030 ps
CPU time 28.42 seconds
Started Aug 12 06:19:46 PM PDT 24
Finished Aug 12 06:20:14 PM PDT 24
Peak memory 219352 kb
Host smart-341cbd26-34de-4b57-bff0-af0256a37807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266675263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1266675263
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3462973046
Short name T75
Test name
Test status
Simulation time 187906215 ps
CPU time 8.6 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:19:56 PM PDT 24
Peak memory 218612 kb
Host smart-9a9d9122-42d3-46bf-8a3f-1adeab0314c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462973046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3462973046
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2287609880
Short name T201
Test name
Test status
Simulation time 5916864825 ps
CPU time 336.4 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:25:21 PM PDT 24
Peak memory 219688 kb
Host smart-64db83f6-0990-46e3-9450-4d32e2f4857b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287609880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2287609880
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1131032372
Short name T239
Test name
Test status
Simulation time 411085788 ps
CPU time 19.49 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:07 PM PDT 24
Peak memory 219456 kb
Host smart-0054fa82-9290-42cc-812a-ab03f75b4cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131032372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1131032372
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2593960710
Short name T216
Test name
Test status
Simulation time 525988872 ps
CPU time 12.29 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:00 PM PDT 24
Peak memory 219400 kb
Host smart-444b5696-1c4c-4790-ab54-9246e182e170
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593960710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2593960710
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1104098933
Short name T312
Test name
Test status
Simulation time 1362080257 ps
CPU time 19.38 seconds
Started Aug 12 06:19:39 PM PDT 24
Finished Aug 12 06:19:59 PM PDT 24
Peak memory 219340 kb
Host smart-69fd4d09-52a4-4c92-b0ef-e46f49545c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104098933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1104098933
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.201858577
Short name T148
Test name
Test status
Simulation time 265461233 ps
CPU time 9.89 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:19:51 PM PDT 24
Peak memory 218560 kb
Host smart-ce282b02-6ec3-472d-aefe-54b1406b89a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201858577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.201858577
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.530195396
Short name T280
Test name
Test status
Simulation time 1321118199 ps
CPU time 19.07 seconds
Started Aug 12 06:19:51 PM PDT 24
Finished Aug 12 06:20:10 PM PDT 24
Peak memory 219376 kb
Host smart-675b59e2-630e-4393-8066-57225ba832f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530195396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.530195396
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.833262488
Short name T219
Test name
Test status
Simulation time 351354837 ps
CPU time 10.49 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 219336 kb
Host smart-0eae3a3f-c462-4b05-891b-d2a8d7406c7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833262488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.833262488
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2153494263
Short name T174
Test name
Test status
Simulation time 379811519 ps
CPU time 21.47 seconds
Started Aug 12 06:19:59 PM PDT 24
Finished Aug 12 06:20:21 PM PDT 24
Peak memory 219356 kb
Host smart-dfcf83b5-7605-4dad-91fb-e5bf1081465b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153494263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2153494263
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.983258939
Short name T66
Test name
Test status
Simulation time 1032319846 ps
CPU time 8.39 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:19:52 PM PDT 24
Peak memory 218588 kb
Host smart-fb5a8164-ef2b-4c79-98ff-f313ad13a174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983258939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.983258939
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.376959945
Short name T45
Test name
Test status
Simulation time 3130894294 ps
CPU time 225.99 seconds
Started Aug 12 06:19:46 PM PDT 24
Finished Aug 12 06:23:32 PM PDT 24
Peak memory 234496 kb
Host smart-c1ff7b68-7f33-475b-acba-b1f865d82287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376959945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.376959945
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3443192301
Short name T170
Test name
Test status
Simulation time 523979225 ps
CPU time 22.61 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:20:07 PM PDT 24
Peak memory 219496 kb
Host smart-40fd05f2-7389-4120-a3ff-66a65b9a949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443192301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3443192301
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3205375696
Short name T230
Test name
Test status
Simulation time 1714814370 ps
CPU time 12.16 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:19:55 PM PDT 24
Peak memory 219344 kb
Host smart-440aaf37-16cb-48bd-bef2-c148beeb955e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205375696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3205375696
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4266714231
Short name T194
Test name
Test status
Simulation time 250536854 ps
CPU time 9.86 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:19:55 PM PDT 24
Peak memory 218768 kb
Host smart-d5cffb7e-a872-41af-b434-79b6cb2d5039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266714231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4266714231
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2604016493
Short name T65
Test name
Test status
Simulation time 4312668306 ps
CPU time 290.73 seconds
Started Aug 12 06:19:53 PM PDT 24
Finished Aug 12 06:24:44 PM PDT 24
Peak memory 237760 kb
Host smart-dec3cf77-3aff-488e-a565-0aa1e9b2c253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604016493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2604016493
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.413861556
Short name T184
Test name
Test status
Simulation time 500929706 ps
CPU time 22.87 seconds
Started Aug 12 06:19:46 PM PDT 24
Finished Aug 12 06:20:09 PM PDT 24
Peak memory 219460 kb
Host smart-736b5e63-f4c3-4ac2-b854-f3214737d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413861556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.413861556
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2100798727
Short name T310
Test name
Test status
Simulation time 508547258 ps
CPU time 11.91 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:19:59 PM PDT 24
Peak memory 219304 kb
Host smart-30ddaaf2-7b7d-42ca-b013-f724104df088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100798727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2100798727
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.167382257
Short name T141
Test name
Test status
Simulation time 708130221 ps
CPU time 39.57 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:20:24 PM PDT 24
Peak memory 220008 kb
Host smart-bb0dfcdb-2d42-471e-8dae-29f867cfc10c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167382257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.167382257
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1283628300
Short name T76
Test name
Test status
Simulation time 1183039886 ps
CPU time 10.05 seconds
Started Aug 12 06:19:51 PM PDT 24
Finished Aug 12 06:20:01 PM PDT 24
Peak memory 218448 kb
Host smart-59a2308e-f5d7-46b3-b36d-c0e2a05c1290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283628300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1283628300
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3185323968
Short name T237
Test name
Test status
Simulation time 15398445941 ps
CPU time 263.51 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 240036 kb
Host smart-9f40b004-c013-47cd-bec0-01cd273220b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185323968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3185323968
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3028230346
Short name T47
Test name
Test status
Simulation time 395155435 ps
CPU time 19.06 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:20:03 PM PDT 24
Peak memory 219476 kb
Host smart-0e500173-588e-4a40-bf92-cddd19dc7d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028230346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3028230346
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4229170478
Short name T11
Test name
Test status
Simulation time 1140202941 ps
CPU time 10.27 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:19:55 PM PDT 24
Peak memory 219376 kb
Host smart-b6b0badb-cadf-4bf0-9107-d70b45703175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229170478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4229170478
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3524763985
Short name T10
Test name
Test status
Simulation time 562585140 ps
CPU time 16.71 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:20:00 PM PDT 24
Peak memory 219320 kb
Host smart-8669d84b-4686-4d16-acfa-ec70f814c65d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524763985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3524763985
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2902939135
Short name T292
Test name
Test status
Simulation time 252504676 ps
CPU time 10.02 seconds
Started Aug 12 06:19:39 PM PDT 24
Finished Aug 12 06:19:49 PM PDT 24
Peak memory 218544 kb
Host smart-eba7d170-cd10-4b20-8f70-c19d9b7122cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902939135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2902939135
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.458713974
Short name T244
Test name
Test status
Simulation time 5761393310 ps
CPU time 319.59 seconds
Started Aug 12 06:19:41 PM PDT 24
Finished Aug 12 06:25:01 PM PDT 24
Peak memory 239000 kb
Host smart-82441b8c-4d75-4184-a4bb-90d29d708e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458713974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.458713974
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3076988368
Short name T182
Test name
Test status
Simulation time 644666600 ps
CPU time 22.79 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:10 PM PDT 24
Peak memory 219360 kb
Host smart-40344a45-23a6-4693-9183-cfd1ed5de625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076988368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3076988368
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1875923816
Short name T294
Test name
Test status
Simulation time 183580543 ps
CPU time 10.56 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 219208 kb
Host smart-3384d39e-7247-4a96-ac56-8c9801e0fb24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1875923816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1875923816
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3762184124
Short name T320
Test name
Test status
Simulation time 532833155 ps
CPU time 27.92 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:20:12 PM PDT 24
Peak memory 219304 kb
Host smart-1ce39178-678a-4292-950a-53adbaf32abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762184124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3762184124
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2007446262
Short name T80
Test name
Test status
Simulation time 991615428 ps
CPU time 14.73 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:19:57 PM PDT 24
Peak memory 218608 kb
Host smart-ae3f172c-05be-431c-8018-6084f4e16a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007446262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2007446262
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.415466583
Short name T52
Test name
Test status
Simulation time 14637008895 ps
CPU time 216.16 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:23:19 PM PDT 24
Peak memory 237952 kb
Host smart-d44dc54e-f1c7-42da-999f-786afbb8c976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415466583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.415466583
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3365739167
Short name T183
Test name
Test status
Simulation time 497471732 ps
CPU time 22.54 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:20:07 PM PDT 24
Peak memory 219468 kb
Host smart-e27f8368-7956-4e8d-b24c-27637e84d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365739167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3365739167
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2202436155
Short name T139
Test name
Test status
Simulation time 594296015 ps
CPU time 11.71 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:19:55 PM PDT 24
Peak memory 219336 kb
Host smart-0a2f734e-dfb9-436e-896d-b5d34f6e4f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202436155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2202436155
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.467791284
Short name T149
Test name
Test status
Simulation time 11119394886 ps
CPU time 38.3 seconds
Started Aug 12 06:19:53 PM PDT 24
Finished Aug 12 06:20:32 PM PDT 24
Peak memory 219344 kb
Host smart-3356771f-713c-4b9d-a94f-c6b5ed4be177
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467791284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.467791284
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2847251238
Short name T307
Test name
Test status
Simulation time 916473712 ps
CPU time 9.82 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 218640 kb
Host smart-48e383b3-9d10-4214-ad11-7879b250bd2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847251238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2847251238
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1752507846
Short name T23
Test name
Test status
Simulation time 3278717285 ps
CPU time 214.6 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 240020 kb
Host smart-cbbcdf6a-f355-448b-917d-0859607398bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752507846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1752507846
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.850389078
Short name T209
Test name
Test status
Simulation time 1320116779 ps
CPU time 19.88 seconds
Started Aug 12 06:19:49 PM PDT 24
Finished Aug 12 06:20:09 PM PDT 24
Peak memory 219464 kb
Host smart-27404fdd-3191-40a0-a207-23e67c186d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850389078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.850389078
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1220224358
Short name T140
Test name
Test status
Simulation time 1419633435 ps
CPU time 11.95 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:00 PM PDT 24
Peak memory 219268 kb
Host smart-e0d38970-a04d-42ef-8c58-80fdd2e6d9ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220224358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1220224358
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.571652937
Short name T35
Test name
Test status
Simulation time 520498527 ps
CPU time 15.37 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:20:01 PM PDT 24
Peak memory 219024 kb
Host smart-39d61fca-2c55-41d1-81c9-30d97537cc3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571652937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.571652937
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3445638729
Short name T236
Test name
Test status
Simulation time 360352308 ps
CPU time 8.27 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:19:52 PM PDT 24
Peak memory 218600 kb
Host smart-06eec28a-53f4-4eb5-a504-f7caa3571f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445638729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3445638729
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.75092404
Short name T168
Test name
Test status
Simulation time 18738737692 ps
CPU time 180.88 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 219724 kb
Host smart-5e28f9d3-1dbd-4f17-9dd8-c854dcc6531a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75092404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_co
rrupt_sig_fatal_chk.75092404
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.983423539
Short name T260
Test name
Test status
Simulation time 509061031 ps
CPU time 23.13 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:20:08 PM PDT 24
Peak memory 219504 kb
Host smart-fe07f284-fec7-4561-af0d-ff0163193c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983423539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.983423539
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.330529472
Short name T266
Test name
Test status
Simulation time 1971597298 ps
CPU time 17.19 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:20:03 PM PDT 24
Peak memory 219020 kb
Host smart-62f2801a-9f7b-4e27-aaeb-f222e4ec11ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330529472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.330529472
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3521730872
Short name T283
Test name
Test status
Simulation time 299566336 ps
CPU time 27.21 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:20:09 PM PDT 24
Peak memory 219340 kb
Host smart-c2462461-b36f-4f74-9201-e0e7e756bc3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521730872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3521730872
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3172106948
Short name T79
Test name
Test status
Simulation time 991962855 ps
CPU time 10.18 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:31 PM PDT 24
Peak memory 218812 kb
Host smart-f907e5fd-35f9-413a-ba4f-df0de4cf4c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172106948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3172106948
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2790427368
Short name T229
Test name
Test status
Simulation time 14683236350 ps
CPU time 223.79 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 236372 kb
Host smart-0b7848a3-13c7-41a0-83e9-d4a900bddb3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790427368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2790427368
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2196737875
Short name T267
Test name
Test status
Simulation time 19778873778 ps
CPU time 32.74 seconds
Started Aug 12 06:19:14 PM PDT 24
Finished Aug 12 06:19:47 PM PDT 24
Peak memory 219500 kb
Host smart-4e09e2b6-f96e-4043-8a15-399bda901fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196737875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2196737875
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.625933638
Short name T227
Test name
Test status
Simulation time 7146677420 ps
CPU time 17.47 seconds
Started Aug 12 06:19:15 PM PDT 24
Finished Aug 12 06:19:33 PM PDT 24
Peak memory 219404 kb
Host smart-afe7d0b9-6d05-4328-85ec-7ef3cbde69b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625933638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.625933638
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1266065480
Short name T270
Test name
Test status
Simulation time 180599422 ps
CPU time 11.25 seconds
Started Aug 12 06:19:10 PM PDT 24
Finished Aug 12 06:19:22 PM PDT 24
Peak memory 219308 kb
Host smart-08378bbe-638c-42c3-8ae8-c6e715576e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266065480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1266065480
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4174292239
Short name T285
Test name
Test status
Simulation time 200455607 ps
CPU time 21.31 seconds
Started Aug 12 06:19:18 PM PDT 24
Finished Aug 12 06:19:40 PM PDT 24
Peak memory 219332 kb
Host smart-d0af379d-68e3-4932-9704-b81398fdc12f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174292239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4174292239
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2428548878
Short name T4
Test name
Test status
Simulation time 516562634 ps
CPU time 9.98 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 218764 kb
Host smart-bead6c33-68f1-4ff5-8093-b7929f5b9b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428548878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2428548878
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2763085989
Short name T187
Test name
Test status
Simulation time 3297055699 ps
CPU time 207.15 seconds
Started Aug 12 06:19:44 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 225480 kb
Host smart-7d637ab1-abcb-4d42-9f31-0d409acbb5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763085989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2763085989
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.38692742
Short name T241
Test name
Test status
Simulation time 517258310 ps
CPU time 22.75 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:20:05 PM PDT 24
Peak memory 219496 kb
Host smart-a7196c63-96e1-4f77-b329-724b1651e817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38692742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.38692742
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1052284170
Short name T143
Test name
Test status
Simulation time 329587247 ps
CPU time 10.42 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:19:57 PM PDT 24
Peak memory 219328 kb
Host smart-4a370174-82af-490d-8f09-9f78f1805a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052284170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1052284170
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.130223106
Short name T146
Test name
Test status
Simulation time 810491666 ps
CPU time 20.38 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:08 PM PDT 24
Peak memory 219300 kb
Host smart-14e3ac2e-c772-4b17-986a-ae910502f76c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130223106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.130223106
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1063470778
Short name T61
Test name
Test status
Simulation time 1031790428 ps
CPU time 10.07 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:19:53 PM PDT 24
Peak memory 218576 kb
Host smart-22a85a36-9f57-4289-8bf4-06d1d8ec0b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063470778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1063470778
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2421373907
Short name T153
Test name
Test status
Simulation time 17239786687 ps
CPU time 257.75 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:24:05 PM PDT 24
Peak memory 233692 kb
Host smart-18ee4dd4-2607-47f2-a73c-5f421f2debe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421373907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2421373907
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1780096626
Short name T64
Test name
Test status
Simulation time 662178240 ps
CPU time 19.46 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:20:05 PM PDT 24
Peak memory 219436 kb
Host smart-06cfd641-6d98-46f7-a504-342768909fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780096626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1780096626
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3371689755
Short name T300
Test name
Test status
Simulation time 1060643850 ps
CPU time 11.81 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:19:59 PM PDT 24
Peak memory 219268 kb
Host smart-f86ebf0f-8625-4028-8d40-2cf28529360d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371689755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3371689755
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2667427494
Short name T178
Test name
Test status
Simulation time 2119668109 ps
CPU time 30.23 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:18 PM PDT 24
Peak memory 219300 kb
Host smart-c45f014b-5103-4fd1-8595-d88120af231f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667427494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2667427494
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.190758843
Short name T293
Test name
Test status
Simulation time 339142418 ps
CPU time 8.03 seconds
Started Aug 12 06:19:48 PM PDT 24
Finished Aug 12 06:19:56 PM PDT 24
Peak memory 218292 kb
Host smart-fa0727de-a498-4721-a6e5-5e60b1f3913d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190758843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.190758843
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1452154269
Short name T162
Test name
Test status
Simulation time 4991670982 ps
CPU time 256.83 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:24:00 PM PDT 24
Peak memory 243192 kb
Host smart-ae4567c9-b22a-45aa-9c4c-ebd8e88c03f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452154269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1452154269
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4105056463
Short name T161
Test name
Test status
Simulation time 1010690542 ps
CPU time 23.41 seconds
Started Aug 12 06:19:50 PM PDT 24
Finished Aug 12 06:20:13 PM PDT 24
Peak memory 219460 kb
Host smart-3b2d7e85-52b6-444c-bc5a-e27bbb682a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105056463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4105056463
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.472616013
Short name T6
Test name
Test status
Simulation time 1071450413 ps
CPU time 11.83 seconds
Started Aug 12 06:19:43 PM PDT 24
Finished Aug 12 06:19:55 PM PDT 24
Peak memory 219376 kb
Host smart-b59c5fcd-70e7-48d0-b58d-12af06503cf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472616013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.472616013
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.279523607
Short name T17
Test name
Test status
Simulation time 531368757 ps
CPU time 26.18 seconds
Started Aug 12 06:19:42 PM PDT 24
Finished Aug 12 06:20:09 PM PDT 24
Peak memory 219324 kb
Host smart-e5fbdfcf-a7ba-4b14-82d6-f5f1490891f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279523607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.279523607
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1611366486
Short name T197
Test name
Test status
Simulation time 255843769 ps
CPU time 10.62 seconds
Started Aug 12 06:19:50 PM PDT 24
Finished Aug 12 06:20:01 PM PDT 24
Peak memory 218580 kb
Host smart-eebe8d0d-abc5-4b9f-ae28-b7b4f671b988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611366486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1611366486
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2141899592
Short name T156
Test name
Test status
Simulation time 4414319604 ps
CPU time 284.62 seconds
Started Aug 12 06:19:46 PM PDT 24
Finished Aug 12 06:24:31 PM PDT 24
Peak memory 240460 kb
Host smart-8792de59-d28c-4f56-a658-5cddb650ea27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141899592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2141899592
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4197989575
Short name T258
Test name
Test status
Simulation time 7848056205 ps
CPU time 33 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:20 PM PDT 24
Peak memory 219140 kb
Host smart-05d4ef26-1370-431c-855e-40e363d008a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197989575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4197989575
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1877698519
Short name T217
Test name
Test status
Simulation time 1602999265 ps
CPU time 12.29 seconds
Started Aug 12 06:19:58 PM PDT 24
Finished Aug 12 06:20:10 PM PDT 24
Peak memory 219316 kb
Host smart-b877f377-f5fe-4cd8-8414-1175e0503d72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1877698519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1877698519
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4260956030
Short name T287
Test name
Test status
Simulation time 1028820868 ps
CPU time 20.71 seconds
Started Aug 12 06:19:46 PM PDT 24
Finished Aug 12 06:20:07 PM PDT 24
Peak memory 219360 kb
Host smart-1c734a74-caea-400f-854d-88a8ed4de3b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260956030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4260956030
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2593641342
Short name T77
Test name
Test status
Simulation time 612419103 ps
CPU time 8.39 seconds
Started Aug 12 06:19:50 PM PDT 24
Finished Aug 12 06:19:59 PM PDT 24
Peak memory 218772 kb
Host smart-24a21f11-89db-40b8-8a8e-48225de49519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593641342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2593641342
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2906424713
Short name T289
Test name
Test status
Simulation time 10503760487 ps
CPU time 129.37 seconds
Started Aug 12 06:19:49 PM PDT 24
Finished Aug 12 06:21:59 PM PDT 24
Peak memory 218872 kb
Host smart-723a6214-e5d6-4832-83cf-d874f0a08952
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906424713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2906424713
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1239636926
Short name T248
Test name
Test status
Simulation time 340085127 ps
CPU time 19.44 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:06 PM PDT 24
Peak memory 219472 kb
Host smart-a65a9a29-32f2-477c-bb54-bc4e745d0246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239636926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1239636926
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.803514398
Short name T238
Test name
Test status
Simulation time 182937341 ps
CPU time 10.39 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:19:56 PM PDT 24
Peak memory 219336 kb
Host smart-f095c617-7bf0-4e0d-b82c-d3f51f7067a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803514398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.803514398
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3707449096
Short name T250
Test name
Test status
Simulation time 37196853996 ps
CPU time 57.64 seconds
Started Aug 12 06:19:49 PM PDT 24
Finished Aug 12 06:20:47 PM PDT 24
Peak memory 219748 kb
Host smart-2fe6b9e1-995f-4c26-87ed-55c4c1ac3d0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707449096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3707449096
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3945323296
Short name T40
Test name
Test status
Simulation time 319926885 ps
CPU time 8.38 seconds
Started Aug 12 06:19:51 PM PDT 24
Finished Aug 12 06:19:59 PM PDT 24
Peak memory 218580 kb
Host smart-5a781629-6afd-4480-8ce0-4ec3f3a559d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945323296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3945323296
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2971195849
Short name T290
Test name
Test status
Simulation time 3929852833 ps
CPU time 283.63 seconds
Started Aug 12 06:19:55 PM PDT 24
Finished Aug 12 06:24:38 PM PDT 24
Peak memory 240296 kb
Host smart-4df19f61-bf92-4dc8-883b-631654c681a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971195849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2971195849
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.191900257
Short name T158
Test name
Test status
Simulation time 2479022215 ps
CPU time 22.66 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:20:08 PM PDT 24
Peak memory 219440 kb
Host smart-a28a0c66-2854-4362-b92f-1b93312cda64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191900257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.191900257
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1914755910
Short name T247
Test name
Test status
Simulation time 4144563175 ps
CPU time 17.47 seconds
Started Aug 12 06:19:46 PM PDT 24
Finished Aug 12 06:20:04 PM PDT 24
Peak memory 219416 kb
Host smart-6968200c-596d-4a2e-84d8-02c88322f027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914755910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1914755910
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2521440024
Short name T302
Test name
Test status
Simulation time 1473886973 ps
CPU time 31.26 seconds
Started Aug 12 06:19:48 PM PDT 24
Finished Aug 12 06:20:20 PM PDT 24
Peak memory 219292 kb
Host smart-827452e3-57b4-4b8d-a619-0e1af7e539d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521440024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2521440024
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2232659166
Short name T243
Test name
Test status
Simulation time 332904259 ps
CPU time 8.26 seconds
Started Aug 12 06:19:46 PM PDT 24
Finished Aug 12 06:19:54 PM PDT 24
Peak memory 218564 kb
Host smart-ffb16ac4-483c-4581-8084-f546044fbca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232659166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2232659166
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1816875254
Short name T318
Test name
Test status
Simulation time 24814582023 ps
CPU time 298.79 seconds
Started Aug 12 06:19:54 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 238868 kb
Host smart-4a2c72a5-c064-44c0-b26c-ff31cc9b6efd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816875254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1816875254
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.480537091
Short name T49
Test name
Test status
Simulation time 338885146 ps
CPU time 19.43 seconds
Started Aug 12 06:19:58 PM PDT 24
Finished Aug 12 06:20:17 PM PDT 24
Peak memory 219460 kb
Host smart-57f0deaf-66ec-47f3-b510-ea38d3372166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480537091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.480537091
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3052034145
Short name T213
Test name
Test status
Simulation time 320248166 ps
CPU time 12.02 seconds
Started Aug 12 06:19:58 PM PDT 24
Finished Aug 12 06:20:10 PM PDT 24
Peak memory 219328 kb
Host smart-b2384f88-d349-4c95-80a2-a56943ec2530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052034145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3052034145
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.230551982
Short name T70
Test name
Test status
Simulation time 537794794 ps
CPU time 29.78 seconds
Started Aug 12 06:19:51 PM PDT 24
Finished Aug 12 06:20:21 PM PDT 24
Peak memory 219452 kb
Host smart-e247b1c5-a71c-41bd-9903-23f29dfee6af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230551982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.230551982
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1984429688
Short name T181
Test name
Test status
Simulation time 437600372 ps
CPU time 10.19 seconds
Started Aug 12 06:19:59 PM PDT 24
Finished Aug 12 06:20:10 PM PDT 24
Peak memory 218744 kb
Host smart-01dfca22-022c-460a-8ff5-b89aa9a28a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984429688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1984429688
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.490081305
Short name T50
Test name
Test status
Simulation time 18559890551 ps
CPU time 380.45 seconds
Started Aug 12 06:19:51 PM PDT 24
Finished Aug 12 06:26:12 PM PDT 24
Peak memory 239100 kb
Host smart-42415746-86b4-4096-9fe7-96c25348db55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490081305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.490081305
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.349537577
Short name T204
Test name
Test status
Simulation time 178574929 ps
CPU time 10.15 seconds
Started Aug 12 06:19:57 PM PDT 24
Finished Aug 12 06:20:07 PM PDT 24
Peak memory 219372 kb
Host smart-0f885dfe-4eea-4e22-a0a2-0c49d37fe494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349537577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.349537577
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2875796117
Short name T281
Test name
Test status
Simulation time 994411568 ps
CPU time 10.08 seconds
Started Aug 12 06:19:53 PM PDT 24
Finished Aug 12 06:20:03 PM PDT 24
Peak memory 217688 kb
Host smart-9892de9c-baac-4adb-a06f-97f43fac6ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875796117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2875796117
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1465072003
Short name T179
Test name
Test status
Simulation time 6320224784 ps
CPU time 161.52 seconds
Started Aug 12 06:19:52 PM PDT 24
Finished Aug 12 06:22:33 PM PDT 24
Peak memory 229084 kb
Host smart-47abf7ec-cf7d-4354-baf5-33b769643e95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465072003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1465072003
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3154213038
Short name T220
Test name
Test status
Simulation time 1831790184 ps
CPU time 22.7 seconds
Started Aug 12 06:19:59 PM PDT 24
Finished Aug 12 06:20:22 PM PDT 24
Peak memory 219420 kb
Host smart-f6dc56f1-e9b5-4f92-974a-0a9534e01fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154213038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3154213038
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2832776663
Short name T67
Test name
Test status
Simulation time 3990791731 ps
CPU time 17.32 seconds
Started Aug 12 06:19:45 PM PDT 24
Finished Aug 12 06:20:02 PM PDT 24
Peak memory 218780 kb
Host smart-8d704cfd-f7a0-4b02-9c87-5f0616c57571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832776663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2832776663
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.185122217
Short name T188
Test name
Test status
Simulation time 2195861866 ps
CPU time 23.19 seconds
Started Aug 12 06:19:49 PM PDT 24
Finished Aug 12 06:20:13 PM PDT 24
Peak memory 219432 kb
Host smart-36cae00e-1a42-412f-9acb-d6304777dc6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185122217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.185122217
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1849509995
Short name T288
Test name
Test status
Simulation time 507102877 ps
CPU time 10.18 seconds
Started Aug 12 06:19:58 PM PDT 24
Finished Aug 12 06:20:08 PM PDT 24
Peak memory 218556 kb
Host smart-88c36616-429a-4a55-9082-93f9047e2205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849509995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1849509995
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2456657986
Short name T175
Test name
Test status
Simulation time 4488828520 ps
CPU time 290.2 seconds
Started Aug 12 06:19:53 PM PDT 24
Finished Aug 12 06:24:43 PM PDT 24
Peak memory 230420 kb
Host smart-479d8be3-b80d-4929-b7d2-fa7c7d4f4a8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456657986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2456657986
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1507043445
Short name T297
Test name
Test status
Simulation time 2061968280 ps
CPU time 23.08 seconds
Started Aug 12 06:19:52 PM PDT 24
Finished Aug 12 06:20:15 PM PDT 24
Peak memory 219632 kb
Host smart-e10f5734-5a1d-4c6e-a586-32b51640948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507043445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1507043445
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4051549599
Short name T5
Test name
Test status
Simulation time 2554172662 ps
CPU time 12.56 seconds
Started Aug 12 06:19:56 PM PDT 24
Finished Aug 12 06:20:08 PM PDT 24
Peak memory 219384 kb
Host smart-11a6100a-218b-4114-8992-f5c9acaac787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051549599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4051549599
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1510109603
Short name T144
Test name
Test status
Simulation time 549869890 ps
CPU time 30.57 seconds
Started Aug 12 06:19:47 PM PDT 24
Finished Aug 12 06:20:18 PM PDT 24
Peak memory 219364 kb
Host smart-c97fbb46-6a24-472f-9a62-fa78243c16af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510109603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1510109603
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2403120637
Short name T309
Test name
Test status
Simulation time 272590919 ps
CPU time 10.35 seconds
Started Aug 12 06:19:17 PM PDT 24
Finished Aug 12 06:19:27 PM PDT 24
Peak memory 218596 kb
Host smart-22fc92f4-7f51-4c17-bdfd-f478bee31a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403120637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2403120637
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.127776546
Short name T51
Test name
Test status
Simulation time 31082717021 ps
CPU time 198 seconds
Started Aug 12 06:19:15 PM PDT 24
Finished Aug 12 06:22:33 PM PDT 24
Peak memory 239536 kb
Host smart-4888e447-7ead-4992-9648-3dc694b88611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127776546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.127776546
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.648312624
Short name T113
Test name
Test status
Simulation time 774437615 ps
CPU time 22.8 seconds
Started Aug 12 06:19:19 PM PDT 24
Finished Aug 12 06:19:42 PM PDT 24
Peak memory 219332 kb
Host smart-fe51bdfc-7ae6-45ea-8a7a-36d79da59ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648312624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.648312624
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2927688132
Short name T33
Test name
Test status
Simulation time 948121102 ps
CPU time 12.46 seconds
Started Aug 12 06:19:18 PM PDT 24
Finished Aug 12 06:19:30 PM PDT 24
Peak memory 219336 kb
Host smart-4dfb1d12-5628-44ab-98d7-9e91de1e103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927688132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2927688132
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4125695668
Short name T212
Test name
Test status
Simulation time 404428220 ps
CPU time 27.91 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:48 PM PDT 24
Peak memory 219344 kb
Host smart-2bc48c5d-3949-454a-bdaa-621c41f462c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125695668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4125695668
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3709128141
Short name T205
Test name
Test status
Simulation time 257520703 ps
CPU time 10.2 seconds
Started Aug 12 06:19:17 PM PDT 24
Finished Aug 12 06:19:28 PM PDT 24
Peak memory 218476 kb
Host smart-429413e6-69d2-4e72-87cd-4d36650aa62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709128141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3709128141
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2245281539
Short name T277
Test name
Test status
Simulation time 18276584378 ps
CPU time 267.41 seconds
Started Aug 12 06:19:17 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 225672 kb
Host smart-0b814b93-ae9d-4f6d-820b-d7a97f1ce9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245281539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2245281539
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2616077477
Short name T256
Test name
Test status
Simulation time 4497217268 ps
CPU time 22.71 seconds
Started Aug 12 06:19:21 PM PDT 24
Finished Aug 12 06:19:44 PM PDT 24
Peak memory 219480 kb
Host smart-53872e31-6b5f-4bd8-ac24-41f095fe5af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616077477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2616077477
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.793882750
Short name T142
Test name
Test status
Simulation time 1064919417 ps
CPU time 12.18 seconds
Started Aug 12 06:19:17 PM PDT 24
Finished Aug 12 06:19:30 PM PDT 24
Peak memory 219336 kb
Host smart-7d3163db-6b52-4465-8da4-f331cef94298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793882750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.793882750
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2815461531
Short name T95
Test name
Test status
Simulation time 537187828 ps
CPU time 12.29 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:19:37 PM PDT 24
Peak memory 219328 kb
Host smart-eb055c8f-b004-43e6-b223-1c1648c636e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815461531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2815461531
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1410068457
Short name T231
Test name
Test status
Simulation time 5272848358 ps
CPU time 42.45 seconds
Started Aug 12 06:19:18 PM PDT 24
Finished Aug 12 06:20:01 PM PDT 24
Peak memory 219412 kb
Host smart-16495a31-45e4-411f-b99e-986e284adce8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410068457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1410068457
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.185141796
Short name T196
Test name
Test status
Simulation time 916518227 ps
CPU time 8.36 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:19:33 PM PDT 24
Peak memory 218736 kb
Host smart-3b56af51-b54a-44c3-af2c-2e2f242211be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185141796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.185141796
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1393394449
Short name T110
Test name
Test status
Simulation time 2126065330 ps
CPU time 128.08 seconds
Started Aug 12 06:19:15 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 240648 kb
Host smart-8ac81b9a-82be-4616-80c5-3acfee4a28e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393394449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1393394449
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2137469490
Short name T111
Test name
Test status
Simulation time 2364766532 ps
CPU time 22.65 seconds
Started Aug 12 06:19:17 PM PDT 24
Finished Aug 12 06:19:40 PM PDT 24
Peak memory 219524 kb
Host smart-ee1888a3-550d-4220-a320-3f9c4627b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137469490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2137469490
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4027598665
Short name T8
Test name
Test status
Simulation time 186280499 ps
CPU time 10.46 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:31 PM PDT 24
Peak memory 219368 kb
Host smart-7ab816d4-c6c4-4bd6-b838-e93334ac3d39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027598665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4027598665
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1586302605
Short name T19
Test name
Test status
Simulation time 1052054021 ps
CPU time 17.64 seconds
Started Aug 12 06:19:21 PM PDT 24
Finished Aug 12 06:19:39 PM PDT 24
Peak memory 219284 kb
Host smart-125bba22-4494-4c90-b331-1ca49b084fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586302605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1586302605
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3681820658
Short name T177
Test name
Test status
Simulation time 876529334 ps
CPU time 21.95 seconds
Started Aug 12 06:19:16 PM PDT 24
Finished Aug 12 06:19:38 PM PDT 24
Peak memory 219340 kb
Host smart-aaf0fdfb-7524-4768-828b-38651e5347fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681820658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3681820658
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4016515966
Short name T159
Test name
Test status
Simulation time 718738627 ps
CPU time 8.42 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:29 PM PDT 24
Peak memory 218600 kb
Host smart-5314a933-0836-43f7-b554-7f0727f93d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016515966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4016515966
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3697045703
Short name T222
Test name
Test status
Simulation time 16769828182 ps
CPU time 264.31 seconds
Started Aug 12 06:19:18 PM PDT 24
Finished Aug 12 06:23:43 PM PDT 24
Peak memory 240028 kb
Host smart-827cf421-d2f7-4f9e-87d1-462011075b57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697045703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3697045703
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2177385559
Short name T30
Test name
Test status
Simulation time 2058833534 ps
CPU time 33.64 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:54 PM PDT 24
Peak memory 219436 kb
Host smart-046c3b98-0670-44b8-aeac-ece3c8240345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177385559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2177385559
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.304583591
Short name T37
Test name
Test status
Simulation time 1822732449 ps
CPU time 12.15 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:32 PM PDT 24
Peak memory 219348 kb
Host smart-ae50e2e2-86cd-4b76-8b86-f9209670698c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304583591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.304583591
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3833540322
Short name T190
Test name
Test status
Simulation time 187910206 ps
CPU time 10.56 seconds
Started Aug 12 06:19:20 PM PDT 24
Finished Aug 12 06:19:31 PM PDT 24
Peak memory 219300 kb
Host smart-65f9e0ba-0d40-46df-b084-7fa4ad6aec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833540322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3833540322
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2809874027
Short name T154
Test name
Test status
Simulation time 4955171837 ps
CPU time 9.73 seconds
Started Aug 12 06:19:22 PM PDT 24
Finished Aug 12 06:19:32 PM PDT 24
Peak memory 219116 kb
Host smart-421b3ee2-fba1-4a3e-89b4-0ab63c385021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809874027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2809874027
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2952730466
Short name T43
Test name
Test status
Simulation time 5551548104 ps
CPU time 281.86 seconds
Started Aug 12 06:19:19 PM PDT 24
Finished Aug 12 06:24:01 PM PDT 24
Peak memory 238968 kb
Host smart-e545262b-83df-4324-8775-52d493796dc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952730466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2952730466
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2049010953
Short name T202
Test name
Test status
Simulation time 332384839 ps
CPU time 19.79 seconds
Started Aug 12 06:19:19 PM PDT 24
Finished Aug 12 06:19:39 PM PDT 24
Peak memory 219488 kb
Host smart-1f7d3fcd-85f6-4a68-9088-f1b0b87722b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049010953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2049010953
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3273744143
Short name T265
Test name
Test status
Simulation time 860152031 ps
CPU time 12.37 seconds
Started Aug 12 06:19:19 PM PDT 24
Finished Aug 12 06:19:32 PM PDT 24
Peak memory 219296 kb
Host smart-e44c12da-e123-45df-9638-0f3c70d66f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273744143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3273744143
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1386431177
Short name T68
Test name
Test status
Simulation time 412232180 ps
CPU time 10.15 seconds
Started Aug 12 06:19:18 PM PDT 24
Finished Aug 12 06:19:29 PM PDT 24
Peak memory 219296 kb
Host smart-abcfc20c-e8cb-49c5-aa8f-29ed4a3fe9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386431177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1386431177
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2258634912
Short name T298
Test name
Test status
Simulation time 207994527 ps
CPU time 18.11 seconds
Started Aug 12 06:19:25 PM PDT 24
Finished Aug 12 06:19:44 PM PDT 24
Peak memory 219368 kb
Host smart-c28f0cb1-e8da-401a-9629-aaac56d01d14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258634912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2258634912
Directory /workspace/9.rom_ctrl_stress_all/latest
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