Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 15632 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 12407 1 T3 14 T4 17 T8 10



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 19716 1 T3 249 T4 173 T8 162
values[0x0] 4069 1 T23 2 T24 97 T26 2
values[0x1] 4254 1 T23 1 T24 99 T25 7



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6895 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 21144 1 T3 150 T4 105 T8 92



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 60 1 T3 1 T91 3 T11 1
valid_sources[0x01] 75 1 T64 1 T101 1 T91 2
valid_sources[0x02] 99 1 T3 1 T16 2 T10 3
valid_sources[0x03] 80 1 T3 1 T16 8 T47 14
valid_sources[0x04] 132 1 T3 1 T16 3 T64 1
valid_sources[0x05] 75 1 T16 1 T101 1 T91 1
valid_sources[0x06] 124 1 T16 2 T64 1 T101 1
valid_sources[0x07] 125 1 T10 1 T91 2 T11 1
valid_sources[0x08] 109 1 T16 1 T64 1 T91 1
valid_sources[0x09] 79 1 T3 1 T10 1 T64 3
valid_sources[0x0a] 140 1 T3 3 T16 1 T64 1
valid_sources[0x0b] 132 1 T101 4 T91 2 T114 3
valid_sources[0x0c] 113 1 T16 3 T115 1 T116 3
valid_sources[0x0d] 79 1 T3 4 T16 2 T64 3
valid_sources[0x0e] 92 1 T4 4 T101 1 T91 2
valid_sources[0x0f] 99 1 T16 2 T64 2 T101 1
valid_sources[0x10] 72 1 T16 3 T10 1 T64 4
valid_sources[0x11] 110 1 T101 1 T91 1 T114 2
valid_sources[0x12] 180 1 T3 2 T16 2 T64 1
valid_sources[0x13] 119 1 T19 13 T64 3 T91 4
valid_sources[0x14] 86 1 T4 2 T16 2 T10 1
valid_sources[0x15] 81 1 T16 3 T91 4 T79 1
valid_sources[0x16] 112 1 T4 12 T16 2 T64 2
valid_sources[0x17] 142 1 T16 1 T64 2 T101 2
valid_sources[0x18] 93 1 T3 1 T16 5 T11 1
valid_sources[0x19] 168 1 T101 2 T91 2 T11 1
valid_sources[0x1a] 121 1 T3 1 T16 1 T10 1
valid_sources[0x1b] 183 1 T3 2 T64 3 T101 1
valid_sources[0x1c] 76 1 T101 2 T91 2 T11 3
valid_sources[0x1d] 110 1 T3 1 T4 7 T16 1
valid_sources[0x1e] 95 1 T101 2 T91 2 T116 3
valid_sources[0x1f] 111 1 T16 2 T64 1 T101 2
valid_sources[0x20] 103 1 T3 2 T4 12 T64 1
valid_sources[0x21] 74 1 T3 1 T64 3 T101 1
valid_sources[0x22] 102 1 T3 2 T16 1 T101 4
valid_sources[0x23] 263 1 T3 2 T16 6 T19 107
valid_sources[0x24] 100 1 T101 4 T91 4 T11 3
valid_sources[0x25] 143 1 T16 2 T101 2 T91 6
valid_sources[0x26] 93 1 T3 1 T101 2 T11 1
valid_sources[0x27] 102 1 T3 1 T16 2 T64 2
valid_sources[0x28] 64 1 T101 1 T91 1 T115 2
valid_sources[0x29] 111 1 T3 1 T64 1 T101 1
valid_sources[0x2a] 66 1 T3 1 T91 1 T116 2
valid_sources[0x2b] 180 1 T4 4 T16 1 T64 1
valid_sources[0x2c] 84 1 T3 2 T101 1 T91 2
valid_sources[0x2d] 95 1 T3 3 T16 1 T91 3
valid_sources[0x2e] 93 1 T3 4 T4 2 T16 4
valid_sources[0x2f] 145 1 T16 2 T19 24 T64 1
valid_sources[0x30] 117 1 T3 3 T16 1 T64 1
valid_sources[0x31] 102 1 T3 1 T101 1 T91 1
valid_sources[0x32] 96 1 T3 1 T16 1 T10 1
valid_sources[0x33] 89 1 T3 1 T91 1 T117 1
valid_sources[0x34] 67 1 T3 1 T101 1 T91 2
valid_sources[0x35] 157 1 T3 1 T16 2 T64 1
valid_sources[0x36] 110 1 T3 3 T91 1 T94 16
valid_sources[0x37] 149 1 T101 1 T117 2 T118 1
valid_sources[0x38] 77 1 T3 2 T115 1 T114 2
valid_sources[0x39] 163 1 T3 1 T16 1 T17 1
valid_sources[0x3a] 161 1 T3 1 T16 1 T64 1
valid_sources[0x3b] 154 1 T3 1 T101 5 T102 51
valid_sources[0x3c] 89 1 T3 1 T16 1 T101 2
valid_sources[0x3d] 94 1 T3 1 T19 13 T64 3
valid_sources[0x3e] 176 1 T16 4 T64 1 T115 1
valid_sources[0x3f] 79 1 T3 3 T16 1 T64 3
valid_sources[0x40] 65 1 T3 3 T4 2 T10 1
valid_sources[0x41] 61 1 T3 3 T64 2 T101 1
valid_sources[0x42] 134 1 T16 2 T64 1 T101 1
valid_sources[0x43] 87 1 T101 1 T91 2 T93 5
valid_sources[0x44] 98 1 T3 1 T64 2 T91 5
valid_sources[0x45] 78 1 T16 5 T64 2 T101 4
valid_sources[0x46] 113 1 T16 1 T46 20 T116 1
valid_sources[0x47] 143 1 T3 1 T16 2 T101 3
valid_sources[0x48] 93 1 T16 1 T64 4 T91 4
valid_sources[0x49] 95 1 T64 1 T101 3 T91 2
valid_sources[0x4a] 72 1 T3 2 T4 5 T16 5
valid_sources[0x4b] 120 1 T3 4 T16 1 T101 3
valid_sources[0x4c] 148 1 T16 4 T19 17 T64 1
valid_sources[0x4d] 115 1 T3 1 T8 2 T10 1
valid_sources[0x4e] 142 1 T4 7 T16 4 T64 1
valid_sources[0x4f] 172 1 T3 1 T8 43 T16 2
valid_sources[0x50] 121 1 T3 1 T64 1 T101 3
valid_sources[0x51] 111 1 T3 1 T64 2 T115 1
valid_sources[0x52] 112 1 T16 2 T10 1 T64 1
valid_sources[0x53] 81 1 T3 1 T16 1 T64 1
valid_sources[0x54] 103 1 T4 2 T16 1 T30 2
valid_sources[0x55] 133 1 T101 2 T115 2 T75 8
valid_sources[0x56] 105 1 T3 2 T16 5 T64 1
valid_sources[0x57] 95 1 T16 4 T101 1 T91 3
valid_sources[0x58] 86 1 T16 1 T64 2 T116 9
valid_sources[0x59] 304 1 T4 12 T101 2 T91 4
valid_sources[0x5a] 105 1 T3 3 T16 3 T47 23
valid_sources[0x5b] 155 1 T3 2 T4 2 T16 1
valid_sources[0x5c] 83 1 T3 2 T8 11 T16 2
valid_sources[0x5d] 122 1 T16 3 T10 3 T101 2
valid_sources[0x5e] 145 1 T3 3 T16 1 T19 24
valid_sources[0x5f] 98 1 T4 5 T16 1 T18 1
valid_sources[0x60] 145 1 T3 4 T4 2 T16 1
valid_sources[0x61] 93 1 T3 1 T16 3 T64 1
valid_sources[0x62] 88 1 T16 1 T101 2 T116 3
valid_sources[0x63] 93 1 T8 9 T16 3 T10 2
valid_sources[0x64] 92 1 T16 1 T10 1 T64 1
valid_sources[0x65] 70 1 T3 2 T16 2 T91 1
valid_sources[0x66] 59 1 T4 1 T16 1 T101 1
valid_sources[0x67] 80 1 T3 2 T16 6 T64 1
valid_sources[0x68] 120 1 T16 2 T64 1 T91 4
valid_sources[0x69] 79 1 T3 1 T10 1 T64 2
valid_sources[0x6a] 176 1 T16 3 T7 12 T101 1
valid_sources[0x6b] 96 1 T16 4 T64 2 T91 1
valid_sources[0x6c] 103 1 T16 3 T91 1 T11 1
valid_sources[0x6d] 68 1 T10 1 T64 3 T101 1
valid_sources[0x6e] 106 1 T64 2 T101 5 T76 6
valid_sources[0x6f] 133 1 T3 3 T16 6 T64 3
valid_sources[0x70] 109 1 T3 5 T16 3 T64 1
valid_sources[0x71] 83 1 T3 2 T16 2 T101 3
valid_sources[0x72] 91 1 T3 1 T115 1 T119 1
valid_sources[0x73] 95 1 T18 1 T64 3 T101 1
valid_sources[0x74] 98 1 T3 3 T16 1 T64 1
valid_sources[0x75] 208 1 T3 1 T16 3 T101 3
valid_sources[0x76] 127 1 T3 1 T64 1 T101 6
valid_sources[0x77] 127 1 T3 1 T16 3 T64 3
valid_sources[0x78] 41 1 T101 1 T91 1 T76 3
valid_sources[0x79] 166 1 T3 2 T101 1 T91 1
valid_sources[0x7a] 89 1 T16 3 T10 1 T64 2
valid_sources[0x7b] 102 1 T9 11 T16 2 T64 1
valid_sources[0x7c] 104 1 T3 1 T16 3 T10 2
valid_sources[0x7d] 93 1 T3 1 T16 1 T10 1
valid_sources[0x7e] 97 1 T3 1 T101 1 T91 1
valid_sources[0x7f] 84 1 T3 2 T64 2 T101 1
valid_sources[0x80] 56 1 T4 4 T16 4 T101 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 4465 1 T3 14 T4 17 T8 10
values[0x0] all_enables biggest_size 3991 1 T24 94 T39 51 T40 305
values[0x1] all_enables biggest_size 3951 1 T24 87 T25 1 T39 47


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6963 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 24365 1 T1 5 T13 1 T5 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9936 1 T2 10 T13 1 T5 1
values[0x0] 10373 1 T1 10 T21 1 T22 8
values[0x1] 11019 1 T1 6 T21 2 T22 10



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4956 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 26372 1 T1 5 T13 1 T5 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 131 1 T93 3 T31 2 T76 1
valid_sources[0x01] 159 1 T29 1 T120 2 T121 1
valid_sources[0x02] 101 1 T5 1 T8 1 T11 3
valid_sources[0x03] 139 1 T8 2 T122 1 T123 1
valid_sources[0x04] 115 1 T15 1 T30 2 T54 1
valid_sources[0x05] 170 1 T8 2 T113 1 T124 1
valid_sources[0x06] 103 1 T30 2 T125 10 T126 1
valid_sources[0x07] 131 1 T56 2 T127 1 T128 1
valid_sources[0x08] 98 1 T30 1 T76 3 T121 2
valid_sources[0x09] 111 1 T6 1 T129 9 T20 1
valid_sources[0x0a] 91 1 T93 1 T130 1 T131 1
valid_sources[0x0b] 72 1 T126 1 T132 1 T133 1
valid_sources[0x0c] 107 1 T134 1 T121 2 T135 3
valid_sources[0x0d] 115 1 T8 1 T6 1 T7 3
valid_sources[0x0e] 125 1 T136 1 T137 1 T138 1
valid_sources[0x0f] 91 1 T8 1 T76 1 T134 1
valid_sources[0x10] 78 1 T11 1 T136 2 T76 1
valid_sources[0x11] 109 1 T50 5 T139 1 T140 1
valid_sources[0x12] 95 1 T20 1 T141 2 T142 2
valid_sources[0x13] 108 1 T8 1 T18 3 T46 3
valid_sources[0x14] 78 1 T30 1 T93 1 T31 1
valid_sources[0x15] 109 1 T29 1 T12 1 T124 2
valid_sources[0x16] 94 1 T141 1 T143 1 T138 1
valid_sources[0x17] 89 1 T8 1 T18 1 T31 4
valid_sources[0x18] 74 1 T21 1 T142 1 T23 1
valid_sources[0x19] 168 1 T20 1 T144 1 T37 26
valid_sources[0x1a] 136 1 T29 1 T76 1 T126 1
valid_sources[0x1b] 106 1 T18 3 T75 1 T144 1
valid_sources[0x1c] 126 1 T8 1 T145 1 T76 1
valid_sources[0x1d] 166 1 T141 1 T121 1 T146 1
valid_sources[0x1e] 112 1 T141 1 T147 1 T134 1
valid_sources[0x1f] 99 1 T141 1 T113 1 T130 2
valid_sources[0x20] 131 1 T8 1 T52 6 T31 2
valid_sources[0x21] 123 1 T7 4 T75 1 T148 8
valid_sources[0x22] 104 1 T14 1 T145 1 T75 1
valid_sources[0x23] 65 1 T145 1 T127 1 T76 2
valid_sources[0x24] 87 1 T8 1 T93 1 T75 1
valid_sources[0x25] 99 1 T93 2 T11 1 T12 2
valid_sources[0x26] 113 1 T14 2 T8 1 T29 1
valid_sources[0x27] 109 1 T145 1 T127 1 T76 1
valid_sources[0x28] 128 1 T32 2 T76 1 T113 1
valid_sources[0x29] 119 1 T47 2 T120 1 T121 1
valid_sources[0x2a] 131 1 T6 2 T11 2 T76 1
valid_sources[0x2b] 85 1 T8 1 T145 1 T76 1
valid_sources[0x2c] 142 1 T93 1 T149 1 T124 1
valid_sources[0x2d] 123 1 T75 1 T136 2 T135 1
valid_sources[0x2e] 188 1 T18 1 T12 7 T127 2
valid_sources[0x2f] 206 1 T150 1 T151 1 T132 1
valid_sources[0x30] 183 1 T8 2 T152 2 T153 1
valid_sources[0x31] 135 1 T17 1 T7 1 T127 2
valid_sources[0x32] 119 1 T75 1 T154 1 T155 1
valid_sources[0x33] 76 1 T75 1 T156 2 T133 1
valid_sources[0x34] 136 1 T20 3 T76 1 T121 1
valid_sources[0x35] 92 1 T8 1 T9 1 T31 1
valid_sources[0x36] 120 1 T32 5 T75 1 T144 1
valid_sources[0x37] 86 1 T31 1 T11 2 T75 1
valid_sources[0x38] 154 1 T9 1 T130 4 T157 1
valid_sources[0x39] 118 1 T8 1 T11 1 T127 1
valid_sources[0x3a] 89 1 T8 1 T158 1 T142 1
valid_sources[0x3b] 95 1 T31 2 T149 1 T121 1
valid_sources[0x3c] 97 1 T8 1 T75 1 T138 1
valid_sources[0x3d] 93 1 T30 1 T11 2 T142 1
valid_sources[0x3e] 82 1 T14 1 T55 1 T20 1
valid_sources[0x3f] 95 1 T1 16 T53 1 T128 1
valid_sources[0x40] 144 1 T14 1 T75 1 T126 1
valid_sources[0x41] 181 1 T159 1 T160 1 T161 2
valid_sources[0x42] 112 1 T6 1 T11 2 T118 4
valid_sources[0x43] 74 1 T29 1 T56 2 T145 1
valid_sources[0x44] 106 1 T14 1 T6 1 T30 1
valid_sources[0x45] 94 1 T6 1 T145 1 T144 1
valid_sources[0x46] 116 1 T8 1 T93 1 T121 1
valid_sources[0x47] 217 1 T6 1 T76 1 T77 1
valid_sources[0x48] 81 1 T8 1 T76 1 T134 1
valid_sources[0x49] 91 1 T150 1 T162 3 T163 32
valid_sources[0x4a] 185 1 T9 2 T30 1 T145 2
valid_sources[0x4b] 194 1 T47 2 T150 1 T134 1
valid_sources[0x4c] 107 1 T6 1 T55 2 T76 1
valid_sources[0x4d] 128 1 T18 3 T30 1 T152 2
valid_sources[0x4e] 122 1 T76 1 T134 1 T128 1
valid_sources[0x4f] 113 1 T7 3 T47 2 T75 1
valid_sources[0x50] 89 1 T124 2 T121 1 T151 1
valid_sources[0x51] 105 1 T14 1 T76 1 T120 1
valid_sources[0x52] 249 1 T8 2 T164 1 T38 23
valid_sources[0x53] 116 1 T31 1 T149 1 T135 2
valid_sources[0x54] 203 1 T20 1 T144 3 T78 1
valid_sources[0x55] 106 1 T14 1 T75 1 T77 1
valid_sources[0x56] 286 1 T93 1 T75 2 T20 1
valid_sources[0x57] 112 1 T20 1 T141 2 T113 1
valid_sources[0x58] 75 1 T92 1 T138 1 T161 2
valid_sources[0x59] 66 1 T8 1 T6 1 T18 2
valid_sources[0x5a] 81 1 T8 1 T93 1 T77 3
valid_sources[0x5b] 109 1 T41 12 T11 1 T120 1
valid_sources[0x5c] 85 1 T8 1 T9 1 T77 1
valid_sources[0x5d] 91 1 T14 1 T76 2 T165 1
valid_sources[0x5e] 153 1 T166 1 T167 16 T168 1
valid_sources[0x5f] 90 1 T153 4 T169 3 T170 1
valid_sources[0x60] 156 1 T8 2 T10 8 T144 1
valid_sources[0x61] 143 1 T51 20 T54 1 T12 2
valid_sources[0x62] 93 1 T18 2 T93 3 T31 1
valid_sources[0x63] 86 1 T113 4 T130 1 T151 2
valid_sources[0x64] 116 1 T93 1 T12 8 T149 1
valid_sources[0x65] 152 1 T29 1 T93 1 T76 1
valid_sources[0x66] 97 1 T2 3 T8 1 T6 1
valid_sources[0x67] 139 1 T93 2 T20 1 T124 2
valid_sources[0x68] 87 1 T6 1 T31 1 T77 1
valid_sources[0x69] 116 1 T124 1 T171 3 T138 1
valid_sources[0x6a] 82 1 T8 2 T10 1 T29 3
valid_sources[0x6b] 84 1 T30 2 T131 1 T172 1
valid_sources[0x6c] 94 1 T47 3 T118 4 T121 1
valid_sources[0x6d] 94 1 T6 1 T17 4 T93 1
valid_sources[0x6e] 91 1 T173 1 T144 3 T78 1
valid_sources[0x6f] 188 1 T31 1 T11 1 T75 1
valid_sources[0x70] 144 1 T8 3 T9 2 T31 1
valid_sources[0x71] 123 1 T18 2 T142 2 T131 1
valid_sources[0x72] 173 1 T6 1 T17 13 T54 1
valid_sources[0x73] 97 1 T31 1 T126 1 T128 1
valid_sources[0x74] 112 1 T75 2 T138 2 T169 2
valid_sources[0x75] 140 1 T14 1 T76 1 T174 1
valid_sources[0x76] 109 1 T93 1 T151 1 T169 1
valid_sources[0x77] 113 1 T8 1 T9 1 T171 1
valid_sources[0x78] 111 1 T8 1 T29 1 T175 7
valid_sources[0x79] 171 1 T31 1 T54 1 T117 32
valid_sources[0x7a] 129 1 T154 2 T146 2 T169 1
valid_sources[0x7b] 116 1 T55 2 T136 1 T127 1
valid_sources[0x7c] 108 1 T7 4 T11 3 T32 8
valid_sources[0x7d] 67 1 T6 1 T55 1 T78 1
valid_sources[0x7e] 289 1 T56 1 T145 1 T75 1
valid_sources[0x7f] 133 1 T93 1 T31 2 T113 1
valid_sources[0x80] 127 1 T2 2 T22 18 T127 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 5310 1 T13 1 T5 1 T8 35
values[0x0] all_enables biggest_size 9585 1 T1 4 T21 1 T22 5
values[0x1] all_enables biggest_size 9470 1 T1 1 T22 2 T50 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%