Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

36492

1

T3

235

T4

156

T8

152

full_word

14237

1

T3

14

T4

17

T8

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	50419	1			T3	249		T4	173		T8	162
auto[TlIntgErrCmd]	96	1			T23	5		T25	2		T26	6
auto[TlIntgErrData]	108	1			T23	1		T25	5		T26	6
auto[TlIntgErrBoth]	106	1			T23	4		T25	3		T26	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21743

1

T3

249

T4

173

T8

162

auto[1]

28986

1

T23

5

T24

1321

T25

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16988	1			T3	235		T4	156		T8	152
auto[TlIntgErrNone]	partial	auto[1]	19217	1			T24	1048		T39	241		T40	747
auto[TlIntgErrNone]	full_word	auto[0]	4625	1			T3	14		T4	17		T8	10
auto[TlIntgErrNone]	full_word	auto[1]	9589	1			T24	273		T39	119		T40	667
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T23	3		T25	1		T26	3
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T23	2		T26	3		T42	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T43	1		T107	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T25	1		T43	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T23	1		T25	2		T26	3
auto[TlIntgErrData]	partial	auto[1]	47	1			T25	3		T26	2		T42	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T26	1		T43	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T59	1		T111	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T23	1		T26	3		T43	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T23	3		T25	3		T26	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T26	1		T59	1		T106	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T109	1		T111	2		T105	1