Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11444

1

T2

3

T3

25

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20092	1			T2	3		T3	186		T4	26
values[0x0]	3579	1			T15	652		T26	90		T29	99
values[0x1]	3806	1			T15	651		T26	77		T27	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7148	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20329

1

T2

3

T3

115

T4

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	120	1			T20	3		T127	1		T128	3
valid_sources[0x01]	94	1			T20	4		T128	1		T129	2
valid_sources[0x02]	104	1			T19	2		T20	2		T127	2
valid_sources[0x03]	80	1			T20	2		T66	1		T128	1
valid_sources[0x04]	115	1			T19	2		T88	1		T127	1
valid_sources[0x05]	87	1			T20	1		T88	1		T127	1
valid_sources[0x06]	58	1			T9	1		T20	2		T128	2
valid_sources[0x07]	84	1			T19	1		T20	3		T127	2
valid_sources[0x08]	68	1			T20	2		T128	2		T112	6
valid_sources[0x09]	88	1			T19	3		T20	1		T65	2
valid_sources[0x0a]	90	1			T20	1		T128	2		T112	3
valid_sources[0x0b]	128	1			T9	1		T19	2		T20	1
valid_sources[0x0c]	99	1			T20	1		T112	1		T129	2
valid_sources[0x0d]	108	1			T19	2		T20	1		T66	1
valid_sources[0x0e]	73	1			T20	3		T128	2		T129	3
valid_sources[0x0f]	88	1			T20	2		T127	2		T128	1
valid_sources[0x10]	96	1			T20	1		T88	1		T128	2
valid_sources[0x11]	139	1			T3	68		T19	2		T128	2
valid_sources[0x12]	132	1			T9	2		T128	2		T17	8
valid_sources[0x13]	98	1			T88	1		T128	1		T129	2
valid_sources[0x14]	151	1			T19	2		T20	2		T129	2
valid_sources[0x15]	108	1			T9	2		T19	1		T20	2
valid_sources[0x16]	118	1			T4	7		T20	1		T127	1
valid_sources[0x17]	81	1			T20	1		T111	15		T128	2
valid_sources[0x18]	100	1			T88	1		T128	4		T130	1
valid_sources[0x19]	65	1			T9	2		T19	2		T20	1
valid_sources[0x1a]	152	1			T20	1		T128	3		T129	1
valid_sources[0x1b]	129	1			T9	1		T20	2		T128	1
valid_sources[0x1c]	72	1			T20	1		T127	1		T128	1
valid_sources[0x1d]	131	1			T9	3		T19	3		T65	2
valid_sources[0x1e]	143	1			T19	1		T20	3		T66	2
valid_sources[0x1f]	74	1			T66	1		T128	1		T131	1
valid_sources[0x20]	64	1			T128	2		T129	3		T130	1
valid_sources[0x21]	83	1			T19	2		T20	4		T128	4
valid_sources[0x22]	71	1			T19	2		T20	1		T127	1
valid_sources[0x23]	69	1			T20	1		T66	1		T88	1
valid_sources[0x24]	150	1			T19	3		T20	2		T68	1
valid_sources[0x25]	97	1			T128	2		T129	3		T130	1
valid_sources[0x26]	76	1			T19	1		T127	1		T128	3
valid_sources[0x27]	161	1			T20	1		T127	1		T129	2
valid_sources[0x28]	108	1			T6	1		T112	1		T130	2
valid_sources[0x29]	137	1			T66	2		T112	1		T129	3
valid_sources[0x2a]	114	1			T20	1		T110	37		T130	1
valid_sources[0x2b]	87	1			T13	1		T127	1		T129	2
valid_sources[0x2c]	80	1			T66	2		T127	1		T128	3
valid_sources[0x2d]	109	1			T20	1		T66	1		T127	2
valid_sources[0x2e]	83	1			T20	2		T12	2		T67	11
valid_sources[0x2f]	106	1			T20	2		T66	1		T127	2
valid_sources[0x30]	187	1			T20	2		T110	18		T127	1
valid_sources[0x31]	95	1			T20	2		T128	3		T129	3
valid_sources[0x32]	79	1			T20	1		T72	14		T129	3
valid_sources[0x33]	100	1			T20	3		T129	2		T130	2
valid_sources[0x34]	113	1			T66	4		T128	2		T112	1
valid_sources[0x35]	78	1			T19	1		T20	1		T128	2
valid_sources[0x36]	92	1			T20	2		T66	1		T128	1
valid_sources[0x37]	95	1			T20	2		T112	1		T129	2
valid_sources[0x38]	85	1			T20	2		T132	6		T89	2
valid_sources[0x39]	105	1			T3	22		T19	3		T20	2
valid_sources[0x3a]	80	1			T19	1		T88	1		T128	2
valid_sources[0x3b]	121	1			T20	1		T129	1		T130	2
valid_sources[0x3c]	136	1			T20	1		T65	8		T127	1
valid_sources[0x3d]	112	1			T110	18		T66	1		T128	1
valid_sources[0x3e]	174	1			T66	1		T128	1		T129	3
valid_sources[0x3f]	139	1			T2	3		T65	19		T66	3
valid_sources[0x40]	99	1			T6	1		T20	1		T66	3
valid_sources[0x41]	129	1			T20	2		T66	2		T128	1
valid_sources[0x42]	74	1			T19	2		T20	1		T128	1
valid_sources[0x43]	76	1			T19	1		T129	1		T133	2
valid_sources[0x44]	100	1			T20	1		T128	3		T134	16
valid_sources[0x45]	91	1			T3	11		T19	3		T20	1
valid_sources[0x46]	103	1			T20	2		T66	2		T128	3
valid_sources[0x47]	120	1			T88	2		T129	1		T130	2
valid_sources[0x48]	114	1			T20	1		T66	3		T88	1
valid_sources[0x49]	91	1			T20	3		T128	2		T129	3
valid_sources[0x4a]	143	1			T20	1		T112	2		T135	1
valid_sources[0x4b]	125	1			T20	2		T110	22		T128	2
valid_sources[0x4c]	120	1			T20	2		T65	5		T129	2
valid_sources[0x4d]	128	1			T128	2		T129	1		T133	2
valid_sources[0x4e]	90	1			T9	1		T19	1		T20	1
valid_sources[0x4f]	86	1			T3	10		T19	1		T20	3
valid_sources[0x50]	96	1			T20	1		T66	2		T128	2
valid_sources[0x51]	76	1			T19	4		T20	1		T127	3
valid_sources[0x52]	113	1			T20	2		T66	1		T128	1
valid_sources[0x53]	79	1			T19	3		T20	1		T127	1
valid_sources[0x54]	73	1			T9	1		T66	2		T127	1
valid_sources[0x55]	69	1			T19	1		T20	1		T66	2
valid_sources[0x56]	122	1			T20	2		T127	1		T112	2
valid_sources[0x57]	184	1			T10	22		T19	1		T20	2
valid_sources[0x58]	98	1			T66	1		T127	1		T129	2
valid_sources[0x59]	73	1			T20	2		T66	2		T127	2
valid_sources[0x5a]	83	1			T9	4		T67	11		T128	3
valid_sources[0x5b]	83	1			T128	2		T112	2		T129	2
valid_sources[0x5c]	97	1			T20	2		T111	30		T128	1
valid_sources[0x5d]	99	1			T20	1		T66	1		T128	2
valid_sources[0x5e]	150	1			T9	3		T19	2		T128	3
valid_sources[0x5f]	128	1			T20	1		T129	2		T130	2
valid_sources[0x60]	104	1			T128	2		T129	3		T130	1
valid_sources[0x61]	111	1			T9	3		T20	3		T129	1
valid_sources[0x62]	118	1			T19	1		T20	3		T88	1
valid_sources[0x63]	181	1			T3	15		T19	2		T20	3
valid_sources[0x64]	190	1			T19	2		T127	1		T130	1
valid_sources[0x65]	199	1			T19	1		T20	1		T65	16
valid_sources[0x66]	148	1			T20	2		T88	1		T128	2
valid_sources[0x67]	93	1			T19	1		T66	1		T128	1
valid_sources[0x68]	88	1			T19	4		T20	1		T66	2
valid_sources[0x69]	104	1			T6	1		T20	4		T128	5
valid_sources[0x6a]	103	1			T19	4		T20	2		T13	2
valid_sources[0x6b]	159	1			T19	1		T20	1		T128	2
valid_sources[0x6c]	105	1			T19	5		T66	2		T128	2
valid_sources[0x6d]	84	1			T19	1		T20	1		T128	3
valid_sources[0x6e]	91	1			T20	2		T133	1		T70	1
valid_sources[0x6f]	148	1			T20	1		T136	10		T70	1
valid_sources[0x70]	106	1			T20	1		T110	37		T66	1
valid_sources[0x71]	105	1			T19	2		T20	1		T128	1
valid_sources[0x72]	104	1			T20	2		T127	1		T128	1
valid_sources[0x73]	128	1			T19	1		T20	2		T127	1
valid_sources[0x74]	100	1			T9	1		T20	1		T65	1
valid_sources[0x75]	105	1			T19	3		T20	1		T128	2
valid_sources[0x76]	160	1			T19	1		T20	2		T128	1
valid_sources[0x77]	140	1			T66	1		T128	2		T112	1
valid_sources[0x78]	62	1			T20	1		T128	1		T129	1
valid_sources[0x79]	70	1			T20	1		T127	1		T128	1
valid_sources[0x7a]	125	1			T19	1		T20	2		T111	23
valid_sources[0x7b]	98	1			T19	5		T20	4		T16	9
valid_sources[0x7c]	115	1			T3	44		T9	1		T20	4
valid_sources[0x7d]	162	1			T20	2		T66	2		T127	1
valid_sources[0x7e]	161	1			T9	1		T20	1		T66	4
valid_sources[0x7f]	127	1			T20	1		T128	2		T129	2
valid_sources[0x80]	99	1			T66	1		T128	2		T129	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4345

1

T2

3

T3

25

T4

3

values[0x0]

all_enables

biggest_size

3514

1

T15

647

T26

89

T29

99

values[0x1]

all_enables

biggest_size

3585

1

T15

635

T26

74

T27

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24151

1

T1

1

T2

12

T4

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10262	1			T1	1		T2	18		T4	16
values[0x0]	10327	1			T5	8		T24	3		T25	5
values[0x1]	10729	1			T5	6		T24	5		T25	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26173

1

T1

1

T2

13

T4

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	98	1			T72	1		T89	1		T15	11
valid_sources[0x01]	87	1			T4	4		T34	1		T17	1
valid_sources[0x02]	132	1			T17	1		T135	2		T137	1
valid_sources[0x03]	77	1			T89	1		T47	1		T15	1
valid_sources[0x04]	231	1			T66	1		T89	1		T138	14
valid_sources[0x05]	112	1			T2	1		T13	1		T68	1
valid_sources[0x06]	125	1			T66	1		T37	3		T17	1
valid_sources[0x07]	168	1			T4	3		T33	1		T139	3
valid_sources[0x08]	121	1			T55	1		T140	3		T141	4
valid_sources[0x09]	114	1			T2	2		T66	1		T89	1
valid_sources[0x0a]	133	1			T66	1		T72	1		T70	2
valid_sources[0x0b]	64	1			T79	1		T142	1		T143	1
valid_sources[0x0c]	90	1			T77	1		T89	1		T135	1
valid_sources[0x0d]	204	1			T44	29		T70	2		T144	11
valid_sources[0x0e]	88	1			T1	1		T145	1		T15	6
valid_sources[0x0f]	160	1			T66	1		T72	2		T146	1
valid_sources[0x10]	124	1			T70	2		T30	1		T31	1
valid_sources[0x11]	83	1			T34	3		T147	2		T47	1
valid_sources[0x12]	162	1			T6	1		T11	1		T17	2
valid_sources[0x13]	215	1			T17	1		T15	15		T148	1
valid_sources[0x14]	199	1			T66	1		T89	1		T149	1
valid_sources[0x15]	100	1			T7	1		T66	1		T112	1
valid_sources[0x16]	128	1			T78	1		T35	10		T17	3
valid_sources[0x17]	87	1			T150	1		T66	1		T72	3
valid_sources[0x18]	131	1			T89	1		T138	19		T47	1
valid_sources[0x19]	69	1			T37	2		T90	1		T15	1
valid_sources[0x1a]	85	1			T11	1		T88	6		T89	1
valid_sources[0x1b]	109	1			T66	1		T13	1		T47	1
valid_sources[0x1c]	48	1			T151	1		T90	1		T15	5
valid_sources[0x1d]	160	1			T66	1		T125	1		T18	1
valid_sources[0x1e]	105	1			T70	1		T23	2		T126	1
valid_sources[0x1f]	117	1			T72	4		T79	1		T40	1
valid_sources[0x20]	306	1			T68	1		T137	1		T47	1
valid_sources[0x21]	109	1			T89	2		T79	6		T147	2
valid_sources[0x22]	122	1			T2	1		T40	1		T15	1
valid_sources[0x23]	170	1			T77	1		T69	1		T78	1
valid_sources[0x24]	107	1			T11	4		T89	1		T135	2
valid_sources[0x25]	121	1			T152	1		T15	28		T153	1
valid_sources[0x26]	71	1			T78	1		T137	1		T30	2
valid_sources[0x27]	154	1			T66	1		T17	2		T135	1
valid_sources[0x28]	180	1			T6	1		T112	1		T135	2
valid_sources[0x29]	162	1			T5	3		T76	2		T142	1
valid_sources[0x2a]	168	1			T89	1		T21	10		T143	2
valid_sources[0x2b]	98	1			T68	2		T70	1		T147	1
valid_sources[0x2c]	91	1			T14	3		T70	2		T18	1
valid_sources[0x2d]	134	1			T112	4		T142	2		T15	49
valid_sources[0x2e]	69	1			T12	20		T34	3		T70	3
valid_sources[0x2f]	172	1			T11	1		T66	1		T89	2
valid_sources[0x30]	80	1			T24	1		T112	2		T77	1
valid_sources[0x31]	57	1			T66	2		T89	1		T139	1
valid_sources[0x32]	142	1			T4	1		T10	1		T66	1
valid_sources[0x33]	176	1			T112	3		T15	15		T154	1
valid_sources[0x34]	125	1			T155	1		T144	1		T143	1
valid_sources[0x35]	198	1			T71	64		T112	1		T89	1
valid_sources[0x36]	89	1			T72	1		T90	1		T143	1
valid_sources[0x37]	82	1			T156	1		T47	1		T90	1
valid_sources[0x38]	95	1			T13	1		T112	1		T17	1
valid_sources[0x39]	143	1			T88	1		T70	1		T138	1
valid_sources[0x3a]	141	1			T24	1		T66	1		T89	1
valid_sources[0x3b]	154	1			T89	1		T137	1		T90	2
valid_sources[0x3c]	101	1			T15	2		T157	1		T158	3
valid_sources[0x3d]	128	1			T66	1		T17	1		T15	32
valid_sources[0x3e]	73	1			T88	1		T138	1		T146	1
valid_sources[0x3f]	100	1			T138	3		T15	1		T159	1
valid_sources[0x40]	130	1			T69	1		T30	1		T31	2
valid_sources[0x41]	113	1			T11	2		T112	3		T89	1
valid_sources[0x42]	179	1			T72	2		T89	1		T160	1
valid_sources[0x43]	102	1			T11	3		T147	1		T139	2
valid_sources[0x44]	141	1			T17	2		T15	31		T161	1
valid_sources[0x45]	129	1			T69	1		T15	10		T162	1
valid_sources[0x46]	120	1			T5	1		T72	2		T15	7
valid_sources[0x47]	143	1			T10	1		T135	1		T54	1
valid_sources[0x48]	73	1			T70	2		T18	2		T47	1
valid_sources[0x49]	160	1			T66	1		T22	4		T147	1
valid_sources[0x4a]	84	1			T28	1		T89	1		T142	1
valid_sources[0x4b]	94	1			T5	1		T70	2		T15	1
valid_sources[0x4c]	146	1			T2	1		T137	1		T152	2
valid_sources[0x4d]	101	1			T66	1		T17	4		T23	1
valid_sources[0x4e]	100	1			T2	1		T77	1		T40	1
valid_sources[0x4f]	123	1			T15	2		T162	1		T26	2
valid_sources[0x50]	171	1			T5	3		T145	1		T70	1
valid_sources[0x51]	237	1			T35	1		T126	2		T15	28
valid_sources[0x52]	180	1			T66	1		T40	3		T151	1
valid_sources[0x53]	158	1			T11	1		T15	11		T163	1
valid_sources[0x54]	77	1			T17	1		T47	1		T15	3
valid_sources[0x55]	92	1			T11	1		T17	1		T151	1
valid_sources[0x56]	75	1			T66	1		T77	1		T17	1
valid_sources[0x57]	150	1			T6	3		T72	2		T70	1
valid_sources[0x58]	115	1			T137	1		T15	26		T164	2
valid_sources[0x59]	219	1			T35	1		T18	1		T47	1
valid_sources[0x5a]	157	1			T12	1		T112	6		T89	1
valid_sources[0x5b]	83	1			T78	1		T137	1		T146	2
valid_sources[0x5c]	156	1			T2	1		T79	2		T90	1
valid_sources[0x5d]	96	1			T35	8		T17	1		T165	1
valid_sources[0x5e]	67	1			T69	1		T166	3		T15	1
valid_sources[0x5f]	129	1			T22	1		T167	1		T137	1
valid_sources[0x60]	70	1			T66	1		T112	1		T147	1
valid_sources[0x61]	77	1			T66	1		T18	4		T23	3
valid_sources[0x62]	81	1			T11	2		T70	1		T146	1
valid_sources[0x63]	159	1			T16	16		T112	1		T139	4
valid_sources[0x64]	138	1			T11	1		T137	1		T168	6
valid_sources[0x65]	86	1			T88	2		T89	1		T17	2
valid_sources[0x66]	122	1			T69	1		T17	2		T151	2
valid_sources[0x67]	154	1			T66	1		T137	1		T166	13
valid_sources[0x68]	145	1			T11	5		T72	2		T135	1
valid_sources[0x69]	205	1			T10	2		T66	1		T142	1
valid_sources[0x6a]	120	1			T72	1		T89	1		T34	4
valid_sources[0x6b]	73	1			T70	1		T23	1		T15	1
valid_sources[0x6c]	162	1			T33	4		T146	2		T90	1
valid_sources[0x6d]	100	1			T90	1		T15	1		T169	1
valid_sources[0x6e]	95	1			T89	1		T15	10		T170	1
valid_sources[0x6f]	132	1			T2	1		T6	1		T77	1
valid_sources[0x70]	88	1			T2	2		T112	1		T89	1
valid_sources[0x71]	116	1			T10	1		T70	1		T47	1
valid_sources[0x72]	105	1			T89	1		T22	1		T70	1
valid_sources[0x73]	135	1			T66	1		T34	3		T145	1
valid_sources[0x74]	138	1			T17	2		T135	1		T156	1
valid_sources[0x75]	194	1			T72	1		T15	43		T140	1
valid_sources[0x76]	109	1			T66	2		T89	1		T142	1
valid_sources[0x77]	140	1			T4	1		T147	2		T90	1
valid_sources[0x78]	104	1			T24	1		T13	2		T112	1
valid_sources[0x79]	215	1			T89	1		T47	1		T152	1
valid_sources[0x7a]	172	1			T22	2		T15	7		T148	1
valid_sources[0x7b]	91	1			T24	2		T34	1		T137	1
valid_sources[0x7c]	83	1			T2	1		T6	4		T88	4
valid_sources[0x7d]	134	1			T25	11		T112	1		T147	1
valid_sources[0x7e]	104	1			T68	1		T137	1		T15	23
valid_sources[0x7f]	171	1			T88	1		T135	2		T90	1
valid_sources[0x80]	178	1			T11	5		T17	1		T15	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5383

1

T1

1

T2

12

T4

8

values[0x0]

all_enables

biggest_size

9514

1

T5

1

T24

2

T25

2

values[0x1]

all_enables

biggest_size

9254

1

T5

1

T24

1

T25

2