Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

33392

1

T3

161

T4

23

T9

48

full_word

12967

1

T2

2

T3

25

T4

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	46029	1			T2	2		T3	186		T4	26
auto[TlIntgErrCmd]	107	1			T27	5		T63	7		T64	2
auto[TlIntgErrData]	108	1			T27	8		T63	5		T64	5
auto[TlIntgErrBoth]	115	1			T27	7		T63	8		T64	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T2

2

T3

186

T4

26

auto[1]

24290

1

T15

3974

T26

543

T27

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17424	1			T3	161		T4	23		T9	48
auto[TlIntgErrNone]	partial	auto[1]	15664	1			T15	2456		T26	351		T29	175
auto[TlIntgErrNone]	full_word	auto[0]	4481	1			T2	2		T3	25		T4	3
auto[TlIntgErrNone]	full_word	auto[1]	8460	1			T15	1518		T26	192		T29	214
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T27	3		T63	3		T114	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T27	1		T63	2		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T27	1		T63	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T63	1		T116	1		T120	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T27	3		T63	3		T64	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T27	5		T63	2		T64	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T64	2		T115	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T121	1		T122	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T27	4		T63	5		T64	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T27	2		T63	3		T64	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T117	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T27	1		T118	2		T124	1