Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

508289

1

T3

80

T7

19667

T8

32

full_word

317120

1

T1

10

T3

8

T7

12300

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	825119	1			T1	10		T3	88		T7	31967
auto[TlIntgErrCmd]	92	1			T52	6		T53	2		T54	5
auto[TlIntgErrData]	101	1			T52	7		T53	5		T54	9
auto[TlIntgErrBoth]	97	1			T52	7		T53	3		T54	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152047

1

T1

10

T3

88

T7

5213

auto[1]

673362

1

T7

26754

T9

15624

T11

16207

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	75141	1			T3	80		T7	2236		T8	32
auto[TlIntgErrNone]	partial	auto[1]	432883	1			T7	17431		T9	10303		T11	10077
auto[TlIntgErrNone]	full_word	auto[0]	76783	1			T1	10		T3	8		T7	2977
auto[TlIntgErrNone]	full_word	auto[1]	240312	1			T7	9323		T9	5321		T11	6130
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T52	4		T53	1		T54	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T52	2		T53	1		T54	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T103	1		T109	1		T107	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T54	1		T106	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T52	2		T53	3		T54	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T52	5		T53	2		T54	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T54	1		T109	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T54	1		T109	1		T107	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T52	4		T53	1		T54	5
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T52	2		T53	2		T54	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T102	1		T111	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T52	1		T111	2		T113	2