Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_tlul_cg	100.00	1	100	1	64	64

---

Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_tlul_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rom_ctrl_tlul_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regs_req_check	3	0	3	100.00	100	1	1	0
cp_rom_req_check	3	0	3	100.00	100	1	1	0

Summary for Variable cp_regs_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_regs_req_check

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
req_after_done	264352	1			T2	80		T4	32		T10	660
req_and_done	16	1			T13	1		T24	1		T114	1
req_before_done	22	1			T20	1		T115	2		T79	1

---

Summary for Variable cp_rom_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rom_req_check

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
req_after_done	374468	1			T1	3		T2	151		T8	9
req_and_done	66	1			T1	1		T8	1		T16	1
req_before_done	274	1			T2	2		T4	2		T10	2