Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263066

1

T1

8

T2

19

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	95460	1			T1	149		T2	167		T4	59
values[0x0]	98327	1			T10	1346		T20	3292		T12	704
values[0x1]	101868	1			T10	1303		T20	3343		T12	725

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

280447

1

T1

87

T2

113

T4

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1116	1			T8	3		T10	11		T20	37
valid_sources[0x01]	1035	1			T10	11		T17	1		T45	4
valid_sources[0x02]	946	1			T10	10		T15	2		T45	1
valid_sources[0x03]	1150	1			T1	1		T10	11		T97	1
valid_sources[0x04]	965	1			T8	1		T10	13		T20	44
valid_sources[0x05]	1185	1			T10	16		T20	37		T12	6
valid_sources[0x06]	1158	1			T8	1		T10	14		T20	34
valid_sources[0x07]	967	1			T8	3		T10	15		T73	2
valid_sources[0x08]	923	1			T10	10		T11	1		T73	2
valid_sources[0x09]	991	1			T1	3		T10	17		T45	1
valid_sources[0x0a]	890	1			T8	1		T10	14		T18	1
valid_sources[0x0b]	1451	1			T10	11		T45	3		T20	33
valid_sources[0x0c]	1437	1			T8	3		T10	18		T45	5
valid_sources[0x0d]	1179	1			T10	23		T73	1		T20	45
valid_sources[0x0e]	2011	1			T10	8		T11	5		T73	2
valid_sources[0x0f]	905	1			T8	3		T10	16		T11	1
valid_sources[0x10]	1004	1			T8	1		T10	12		T97	1
valid_sources[0x11]	1082	1			T10	12		T20	31		T12	9
valid_sources[0x12]	1028	1			T10	24		T45	5		T20	49
valid_sources[0x13]	1177	1			T8	3		T10	26		T73	1
valid_sources[0x14]	1689	1			T4	1		T8	3		T10	22
valid_sources[0x15]	1558	1			T10	15		T97	1		T20	33
valid_sources[0x16]	960	1			T1	2		T10	11		T45	1
valid_sources[0x17]	1084	1			T10	14		T20	47		T12	6
valid_sources[0x18]	1113	1			T10	18		T20	41		T12	12
valid_sources[0x19]	1048	1			T1	2		T8	1		T10	16
valid_sources[0x1a]	993	1			T8	1		T10	13		T45	1
valid_sources[0x1b]	994	1			T1	4		T8	4		T10	13
valid_sources[0x1c]	1037	1			T10	13		T97	1		T11	3
valid_sources[0x1d]	1403	1			T10	16		T97	1		T11	1
valid_sources[0x1e]	933	1			T10	16		T97	1		T20	34
valid_sources[0x1f]	921	1			T1	3		T10	10		T73	2
valid_sources[0x20]	1260	1			T8	4		T10	20		T20	32
valid_sources[0x21]	928	1			T10	12		T20	42		T12	12
valid_sources[0x22]	931	1			T8	1		T10	14		T11	1
valid_sources[0x23]	910	1			T10	15		T11	1		T20	33
valid_sources[0x24]	1516	1			T1	1		T2	35		T10	19
valid_sources[0x25]	1073	1			T1	1		T8	1		T10	15
valid_sources[0x26]	1114	1			T10	19		T45	2		T20	54
valid_sources[0x27]	1129	1			T8	1		T10	18		T97	2
valid_sources[0x28]	900	1			T10	14		T11	4		T20	25
valid_sources[0x29]	1027	1			T10	22		T45	4		T97	1
valid_sources[0x2a]	914	1			T8	1		T10	15		T73	3
valid_sources[0x2b]	1548	1			T1	2		T10	10		T45	4
valid_sources[0x2c]	860	1			T10	8		T17	1		T45	2
valid_sources[0x2d]	960	1			T10	16		T20	45		T99	1
valid_sources[0x2e]	968	1			T2	29		T10	24		T20	40
valid_sources[0x2f]	1153	1			T8	5		T10	13		T73	1
valid_sources[0x30]	2027	1			T8	3		T10	17		T97	1
valid_sources[0x31]	1193	1			T10	18		T97	1		T73	1
valid_sources[0x32]	1952	1			T10	11		T11	3		T20	42
valid_sources[0x33]	1115	1			T8	8		T10	3		T18	5
valid_sources[0x34]	1508	1			T8	7		T10	14		T73	2
valid_sources[0x35]	972	1			T8	1		T10	18		T11	4
valid_sources[0x36]	1001	1			T8	3		T10	14		T45	1
valid_sources[0x37]	1167	1			T10	20		T97	3		T20	37
valid_sources[0x38]	2075	1			T1	4		T10	16		T45	1
valid_sources[0x39]	1181	1			T8	1		T10	20		T45	1
valid_sources[0x3a]	1024	1			T8	1		T10	28		T18	5
valid_sources[0x3b]	1575	1			T1	4		T10	12		T45	7
valid_sources[0x3c]	915	1			T10	12		T20	39		T12	11
valid_sources[0x3d]	1101	1			T1	8		T4	6		T8	3
valid_sources[0x3e]	847	1			T8	2		T10	6		T73	1
valid_sources[0x3f]	950	1			T10	9		T20	27		T12	4
valid_sources[0x40]	923	1			T10	18		T97	1		T11	1
valid_sources[0x41]	1845	1			T8	1		T10	11		T45	2
valid_sources[0x42]	1097	1			T10	7		T11	1		T20	35
valid_sources[0x43]	1188	1			T8	1		T10	13		T14	18
valid_sources[0x44]	1008	1			T1	3		T10	14		T20	53
valid_sources[0x45]	981	1			T10	14		T20	14		T12	17
valid_sources[0x46]	1174	1			T10	19		T73	1		T20	30
valid_sources[0x47]	1178	1			T10	13		T45	2		T97	2
valid_sources[0x48]	1237	1			T1	1		T10	10		T45	2
valid_sources[0x49]	904	1			T8	4		T10	14		T20	36
valid_sources[0x4a]	975	1			T10	8		T45	1		T97	1
valid_sources[0x4b]	1111	1			T10	5		T11	3		T20	32
valid_sources[0x4c]	994	1			T1	2		T8	5		T10	15
valid_sources[0x4d]	984	1			T10	13		T73	2		T20	20
valid_sources[0x4e]	945	1			T10	10		T20	37		T12	10
valid_sources[0x4f]	942	1			T8	1		T10	18		T97	1
valid_sources[0x50]	1305	1			T10	15		T45	4		T97	1
valid_sources[0x51]	1435	1			T8	6		T10	6		T45	2
valid_sources[0x52]	1375	1			T10	9		T20	42		T12	2
valid_sources[0x53]	1005	1			T8	4		T10	13		T45	1
valid_sources[0x54]	1177	1			T10	15		T45	3		T97	1
valid_sources[0x55]	943	1			T10	12		T17	1		T73	2
valid_sources[0x56]	1450	1			T10	9		T20	43		T12	5
valid_sources[0x57]	896	1			T1	3		T10	12		T97	1
valid_sources[0x58]	975	1			T1	8		T8	2		T10	13
valid_sources[0x59]	1412	1			T1	3		T8	5		T10	18
valid_sources[0x5a]	1210	1			T8	11		T10	11		T45	4
valid_sources[0x5b]	1281	1			T1	2		T10	12		T20	33
valid_sources[0x5c]	1146	1			T8	6		T10	11		T97	2
valid_sources[0x5d]	1007	1			T2	28		T10	24		T97	2
valid_sources[0x5e]	1003	1			T1	6		T8	5		T10	10
valid_sources[0x5f]	1173	1			T10	20		T45	1		T97	1
valid_sources[0x60]	928	1			T8	3		T10	14		T45	3
valid_sources[0x61]	1546	1			T1	2		T10	10		T45	2
valid_sources[0x62]	1329	1			T1	1		T8	2		T10	12
valid_sources[0x63]	1137	1			T10	11		T73	1		T20	32
valid_sources[0x64]	1228	1			T1	1		T4	6		T8	4
valid_sources[0x65]	938	1			T10	8		T45	1		T11	1
valid_sources[0x66]	897	1			T4	4		T8	4		T10	17
valid_sources[0x67]	1190	1			T8	10		T10	13		T11	2
valid_sources[0x68]	974	1			T8	4		T10	15		T97	1
valid_sources[0x69]	1165	1			T10	16		T45	2		T97	1
valid_sources[0x6a]	1330	1			T8	1		T10	13		T97	1
valid_sources[0x6b]	1058	1			T10	9		T11	2		T20	51
valid_sources[0x6c]	1003	1			T4	1		T8	5		T10	10
valid_sources[0x6d]	1149	1			T1	3		T4	4		T10	13
valid_sources[0x6e]	884	1			T10	14		T97	1		T11	3
valid_sources[0x6f]	1126	1			T10	14		T73	1		T20	48
valid_sources[0x70]	1056	1			T4	6		T8	7		T10	10
valid_sources[0x71]	1283	1			T10	11		T97	1		T20	33
valid_sources[0x72]	1185	1			T4	4		T10	15		T11	1
valid_sources[0x73]	974	1			T10	14		T16	11		T45	1
valid_sources[0x74]	1030	1			T1	2		T8	10		T10	17
valid_sources[0x75]	1029	1			T8	3		T10	14		T20	40
valid_sources[0x76]	1068	1			T8	3		T10	18		T45	4
valid_sources[0x77]	1117	1			T10	11		T45	7		T97	2
valid_sources[0x78]	1018	1			T10	14		T73	1		T20	34
valid_sources[0x79]	890	1			T10	24		T73	2		T20	36
valid_sources[0x7a]	946	1			T1	2		T8	7		T10	20
valid_sources[0x7b]	989	1			T10	4		T45	1		T97	1
valid_sources[0x7c]	1453	1			T10	9		T11	1		T73	3
valid_sources[0x7d]	929	1			T8	1		T10	21		T20	25
valid_sources[0x7e]	1460	1			T8	3		T10	10		T20	40
valid_sources[0x7f]	1558	1			T8	1		T10	21		T45	2
valid_sources[0x80]	1007	1			T8	9		T10	14		T73	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68270

1

T1

8

T2

19

T4

3

values[0x0]

all_enables

biggest_size

97462

1

T10

1334

T20

3264

T12

699

values[0x1]

all_enables

biggest_size

97334

1

T10

1253

T20

3201

T12

700

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231041

1

T2

38

T3

3

T4

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	70738	1			T2	80		T4	32		T5	1
values[0x0]	88073	1			T3	4		T7	9		T10	1503
values[0x1]	100078	1			T3	1		T7	4		T10	1621

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

243942

1

T2

45

T3

3

T4

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1077	1			T2	1		T10	26		T73	1
valid_sources[0x01]	903	1			T7	3		T10	17		T20	36
valid_sources[0x02]	896	1			T10	21		T20	25		T53	16
valid_sources[0x03]	827	1			T10	8		T20	27		T53	22
valid_sources[0x04]	935	1			T10	30		T43	1		T20	23
valid_sources[0x05]	897	1			T10	16		T18	1		T20	38
valid_sources[0x06]	1070	1			T10	7		T20	36		T53	29
valid_sources[0x07]	1202	1			T10	23		T64	1		T20	29
valid_sources[0x08]	1298	1			T10	16		T20	41		T53	18
valid_sources[0x09]	1005	1			T10	12		T20	31		T53	13
valid_sources[0x0a]	1278	1			T10	22		T20	32		T12	1
valid_sources[0x0b]	1022	1			T10	15		T20	29		T53	8
valid_sources[0x0c]	890	1			T10	13		T20	33		T53	16
valid_sources[0x0d]	1068	1			T10	10		T20	25		T53	28
valid_sources[0x0e]	1294	1			T2	1		T10	17		T20	34
valid_sources[0x0f]	1171	1			T2	1		T10	14		T20	35
valid_sources[0x10]	1319	1			T10	13		T20	28		T12	20
valid_sources[0x11]	943	1			T10	18		T20	37		T53	28
valid_sources[0x12]	868	1			T10	14		T20	35		T53	10
valid_sources[0x13]	881	1			T10	23		T20	27		T53	12
valid_sources[0x14]	1170	1			T10	16		T73	3		T20	38
valid_sources[0x15]	910	1			T2	2		T10	20		T20	41
valid_sources[0x16]	1319	1			T2	1		T10	16		T19	1
valid_sources[0x17]	1305	1			T10	14		T20	25		T12	7
valid_sources[0x18]	1106	1			T10	14		T20	31		T53	24
valid_sources[0x19]	791	1			T10	11		T73	2		T20	31
valid_sources[0x1a]	1296	1			T2	1		T10	23		T73	3
valid_sources[0x1b]	1173	1			T10	15		T19	1		T20	35
valid_sources[0x1c]	1224	1			T10	22		T19	2		T20	29
valid_sources[0x1d]	1006	1			T2	1		T4	1		T10	14
valid_sources[0x1e]	993	1			T2	2		T4	1		T10	20
valid_sources[0x1f]	839	1			T10	15		T20	34		T53	12
valid_sources[0x20]	1347	1			T10	22		T20	38		T53	26
valid_sources[0x21]	1133	1			T2	1		T10	14		T20	36
valid_sources[0x22]	700	1			T7	1		T10	17		T73	2
valid_sources[0x23]	918	1			T10	12		T44	3		T20	41
valid_sources[0x24]	874	1			T10	19		T20	36		T48	1
valid_sources[0x25]	962	1			T10	15		T43	1		T20	24
valid_sources[0x26]	1274	1			T10	9		T20	35		T12	103
valid_sources[0x27]	734	1			T2	2		T10	18		T17	27
valid_sources[0x28]	1163	1			T10	23		T20	29		T53	9
valid_sources[0x29]	1147	1			T2	1		T10	20		T20	38
valid_sources[0x2a]	1237	1			T10	13		T20	26		T53	21
valid_sources[0x2b]	771	1			T10	16		T20	32		T53	12
valid_sources[0x2c]	850	1			T10	13		T73	2		T20	37
valid_sources[0x2d]	1120	1			T2	1		T10	14		T15	3
valid_sources[0x2e]	834	1			T2	1		T10	13		T20	24
valid_sources[0x2f]	923	1			T10	15		T20	37		T53	17
valid_sources[0x30]	853	1			T10	16		T20	25		T99	1
valid_sources[0x31]	889	1			T10	16		T20	28		T53	27
valid_sources[0x32]	815	1			T10	19		T28	1		T20	29
valid_sources[0x33]	954	1			T10	15		T20	28		T99	1
valid_sources[0x34]	1285	1			T10	18		T20	37		T53	9
valid_sources[0x35]	850	1			T10	13		T19	1		T73	1
valid_sources[0x36]	1323	1			T10	20		T20	35		T53	23
valid_sources[0x37]	1030	1			T10	13		T20	22		T53	12
valid_sources[0x38]	928	1			T10	10		T20	31		T53	11
valid_sources[0x39]	1662	1			T10	13		T20	34		T12	40
valid_sources[0x3a]	1130	1			T10	11		T18	1		T19	2
valid_sources[0x3b]	1453	1			T2	1		T7	1		T10	24
valid_sources[0x3c]	872	1			T10	24		T20	28		T53	23
valid_sources[0x3d]	678	1			T10	13		T20	34		T53	22
valid_sources[0x3e]	907	1			T2	2		T4	1		T10	15
valid_sources[0x3f]	799	1			T10	18		T20	21		T53	24
valid_sources[0x40]	682	1			T10	16		T28	2		T18	1
valid_sources[0x41]	1078	1			T10	15		T20	37		T12	113
valid_sources[0x42]	1377	1			T10	13		T20	31		T12	2
valid_sources[0x43]	1316	1			T10	10		T65	2		T20	40
valid_sources[0x44]	1181	1			T2	1		T7	1		T10	19
valid_sources[0x45]	740	1			T10	21		T20	36		T53	19
valid_sources[0x46]	667	1			T10	12		T28	1		T20	31
valid_sources[0x47]	1296	1			T10	22		T73	2		T20	33
valid_sources[0x48]	1117	1			T4	1		T7	1		T10	14
valid_sources[0x49]	1035	1			T10	23		T43	1		T20	29
valid_sources[0x4a]	1087	1			T10	23		T20	33		T53	4
valid_sources[0x4b]	754	1			T2	1		T10	17		T20	35
valid_sources[0x4c]	717	1			T10	28		T73	1		T20	34
valid_sources[0x4d]	864	1			T10	16		T20	26		T53	25
valid_sources[0x4e]	899	1			T10	14		T20	30		T53	25
valid_sources[0x4f]	824	1			T10	26		T20	26		T99	1
valid_sources[0x50]	1082	1			T10	12		T20	28		T53	12
valid_sources[0x51]	1170	1			T2	1		T10	22		T20	32
valid_sources[0x52]	969	1			T10	11		T20	28		T53	25
valid_sources[0x53]	901	1			T10	15		T47	1		T20	32
valid_sources[0x54]	833	1			T4	3		T10	18		T20	31
valid_sources[0x55]	929	1			T10	13		T20	27		T53	29
valid_sources[0x56]	867	1			T2	1		T10	18		T19	1
valid_sources[0x57]	796	1			T10	12		T20	36		T53	18
valid_sources[0x58]	841	1			T10	24		T63	12		T20	36
valid_sources[0x59]	1090	1			T10	23		T20	28		T53	15
valid_sources[0x5a]	825	1			T2	1		T5	1		T10	13
valid_sources[0x5b]	802	1			T10	12		T20	30		T53	14
valid_sources[0x5c]	989	1			T2	3		T10	20		T20	30
valid_sources[0x5d]	1227	1			T2	2		T10	25		T20	33
valid_sources[0x5e]	906	1			T10	16		T20	29		T53	18
valid_sources[0x5f]	1047	1			T2	4		T10	15		T20	35
valid_sources[0x60]	820	1			T10	12		T20	30		T53	12
valid_sources[0x61]	1053	1			T10	15		T20	34		T53	6
valid_sources[0x62]	857	1			T10	23		T18	1		T19	1
valid_sources[0x63]	818	1			T4	5		T10	23		T15	1
valid_sources[0x64]	942	1			T10	17		T15	1		T20	34
valid_sources[0x65]	1398	1			T2	2		T10	16		T18	1
valid_sources[0x66]	1246	1			T10	17		T20	22		T53	26
valid_sources[0x67]	1219	1			T10	8		T20	35		T12	2
valid_sources[0x68]	702	1			T10	22		T20	39		T53	16
valid_sources[0x69]	1037	1			T10	10		T73	2		T20	30
valid_sources[0x6a]	761	1			T10	29		T20	36		T53	14
valid_sources[0x6b]	1228	1			T4	7		T10	11		T20	37
valid_sources[0x6c]	884	1			T2	1		T10	11		T20	45
valid_sources[0x6d]	904	1			T10	16		T20	41		T53	19
valid_sources[0x6e]	916	1			T10	15		T20	26		T53	13
valid_sources[0x6f]	1092	1			T10	20		T20	32		T53	33
valid_sources[0x70]	1111	1			T10	22		T19	1		T20	38
valid_sources[0x71]	897	1			T10	15		T20	26		T53	13
valid_sources[0x72]	1210	1			T10	14		T20	37		T53	27
valid_sources[0x73]	823	1			T10	13		T20	27		T53	28
valid_sources[0x74]	1037	1			T2	1		T10	22		T15	2
valid_sources[0x75]	958	1			T2	3		T10	18		T20	23
valid_sources[0x76]	857	1			T10	27		T20	41		T53	31
valid_sources[0x77]	748	1			T2	1		T10	19		T20	37
valid_sources[0x78]	1148	1			T10	18		T18	1		T19	1
valid_sources[0x79]	977	1			T10	25		T73	4		T20	38
valid_sources[0x7a]	817	1			T2	1		T10	18		T20	29
valid_sources[0x7b]	964	1			T10	19		T20	29		T12	29
valid_sources[0x7c]	740	1			T10	14		T20	36		T53	28
valid_sources[0x7d]	1080	1			T2	1		T10	14		T15	4
valid_sources[0x7e]	1204	1			T10	20		T20	28		T53	23
valid_sources[0x7f]	972	1			T10	18		T64	1		T20	33
valid_sources[0x80]	970	1			T4	1		T10	15		T18	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59764

1

T2

38

T4

10

T10

1035

values[0x0]

all_enables

biggest_size

85927

1

T3

2

T7

3

T10

1479

values[0x1]

all_enables

biggest_size

85350

1

T3

1

T10

1461

T28

1