Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

491714

1

T1

141

T2

148

T4

56

full_word

305944

1

T1

8

T2

19

T4

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	797348	1			T1	149		T2	167		T4	59
auto[TlIntgErrCmd]	107	1			T57	6		T58	5		T59	2
auto[TlIntgErrData]	111	1			T57	9		T58	3		T59	12
auto[TlIntgErrBoth]	92	1			T57	5		T58	2		T59	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147892

1

T1

149

T2

167

T4

59

auto[1]

649766

1

T10

9055

T20

21215

T12

5299

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	73173	1			T1	141		T2	148		T4	56
auto[TlIntgErrNone]	partial	auto[1]	418258	1			T10	5908		T20	13593		T12	3598
auto[TlIntgErrNone]	full_word	auto[0]	74581	1			T1	8		T2	19		T4	3
auto[TlIntgErrNone]	full_word	auto[1]	231336	1			T10	3147		T20	7622		T12	1701
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T57	2		T58	3		T101	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T57	3		T58	1		T59	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T57	1		T58	1		T101	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T57	5		T58	1		T59	4
auto[TlIntgErrData]	partial	auto[1]	48	1			T57	3		T58	1		T59	7
auto[TlIntgErrData]	full_word	auto[0]	6	1			T58	1		T59	1		T102	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T57	1		T103	1		T104	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T59	3		T101	1		T105	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T57	5		T58	2		T59	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T101	1		T106	1		T107	2
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T59	1		T105	1		T108	1