Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	98.28	97.26		100.00	79.41

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.99	100.00	98.28	97.26		100.00	79.41

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	98.28	97.26		100.00	79.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	96.89	92.70	97.68	100.00	98.97	97.90

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	98.02	100.00	98.15	90.00	100.00	100.00	100.00
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	93.60	90.70	83.97	97.66		95.65	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
212	1	1
258	1	1
313	1	1
414	8	8
415	8	8
417	8	8
418	8	8
420	8	8
421	8	8
425	1	1
427	1	1
430	1	1
431	1	1
432	1	1
433	1	1
438	1	1
442	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       212
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       258
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T19,T15
1	1	Covered	T1,T2,T4

 LINE       418
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T26,T27
1	0	Not Covered

 LINE       427
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T19,T15
1	0	Covered	T5,T6,T9

 LINE       438
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T28
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T7,T28

 LINE       442
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T17,T19,T15
0	1	0	Covered	T5,T6,T9
1	0	0	Covered	T25,T26,T27

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	62	56	90.32
Total Bits	2884	2805	97.26
Total Bits 0->1	1442	1402	97.23
Total Bits 1->0	1442	1403	97.30

Ports	62	56	90.32
Port Bits	2884	2805	97.26
Port Bits 0->1	1442	1402	97.23
Port Bits 1->0	1442	1403	97.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_cfg_i.test	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T9,T10	Yes	T2,T6,T9	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T2,T9,T10	Yes	T2,T10,T14	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_o.a_ready	Yes	Yes	T2,T4,T10	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T10,T20,T12	Yes	T10,T20,T12	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T10,*T20,*T12	Yes	T10,T20,T12	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T5	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
regs_tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_error	Yes	Yes	T10,T20,T12	Yes	T10,T20,T12	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T4,*T7	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T4,T10	OUTPUT
keymgr_data_o.valid	Yes	Yes	T2,T4,T10	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T2,T4,T5	Yes	T2,T3,T4	OUTPUT
kmac_data_i.error	No	Yes	T5,T6,T9	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T10,T17,T18	Yes	T9,T10,T16	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T5,T9	Yes	T2,T4,T10	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	212	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	34	100.00	27	79.41
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	34	100.00	27	79.41

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	43220971	43043830	0	0
BusRomIndicesMatch_A	43198489	43028811	0	0
FpvSecCmRegWeOnehotCheck_A	43220971	70	0	0
FpvSecCmReqFifoRptrCheck_A	43220971	0	0	0
FpvSecCmReqFifoWptrCheck_A	43220971	0	0	0
FpvSecCmRspFifoRptrCheck_A	43220971	0	0	0
FpvSecCmRspFifoWptrCheck_A	43220971	0	0	0
FpvSecCmSramReqFifoRptrCheck_A	43220971	0	0	0
FpvSecCmSramReqFifoWptrCheck_A	43220971	0	0	0
KeymgrDataODataKnown_A	43220971	7907719	0	0
KeymgrDataODataKnown_AKnownEnable	43220971	43043830	0	0
KeymgrDataOValidKnown_A	43220971	43043830	0	0
KeymgrValidChk_A	43220971	7900053	0	0
KmacDataODataKnown_A	43220971	35014058	0	0
KmacDataODataKnown_AKnownEnable	43220971	43043830	0	0
KmacDataOValidKnown_A	43220971	43043830	0	0
PwrmgrDataChk_A	43220971	7900053	0	0
PwrmgrDataOKnown_A	43220971	43043830	0	0
RegsTlOAReadyKnown_A	43220971	43043830	0	0
RegsTlODDataKnown_A	43220971	1150446	0	0
RegsTlODDataKnown_AKnownEnable	43220971	43043830	0	0
RegsTlODValidKnown_A	43220971	43043830	0	0
RomTlOAReadyKnown_A	43220971	43043830	0	0
RomTlODDataKnown_A	43220971	1673162	0	0
RomTlODDataKnown_AKnownEnable	43220971	43043830	0	0
RomTlODValidKnown_A	43220971	43043830	0	0
StabilityChkKmac_A	43220971	35011433	0	0
StabilityChkkeymgr_A	43220971	7906574	0	0
TlAccessChk_A	43220971	35136111	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	43220971	70	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	43220971	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	43220971	516	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	43220971	53047	0	0
gen_fsm_scramble_enabled_asserts.InvalidStateTerminal_A	43220971	51777	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43198489	43028811	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	70	0	0
T25	33737	10	0	0
T26	35081	20	0	0
T27	0	10	0	0
T29	0	20	0	0
T30	0	10	0	0
T31	228351	0	0	0
T32	26961	0	0	0
T33	180851	0	0	0
T34	458277	0	0	0
T35	26031	0	0	0
T36	89255	0	0	0
T37	24748	0	0	0
T38	70267	0	0	0

FpvSecCmReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	0	0	0

FpvSecCmReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	0	0	0

FpvSecCmRspFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	0	0	0

FpvSecCmRspFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	0	0	0

FpvSecCmSramReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	0	0	0

FpvSecCmSramReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	7907719	0	0
T1	26095	1354	0	0
T2	78955	4919	0	0
T3	16547	66	0	0
T4	77661	2033	0	0
T5	49615	241	0	0
T6	49540	59	0	0
T7	98290	61	0	0
T8	18142	1651	0	0
T9	33219	260	0	0
T10	155530	67466	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	7900053	0	0
T1	26095	1353	0	0
T2	78955	4916	0	0
T3	16547	65	0	0
T4	77661	2030	0	0
T5	49615	240	0	0
T6	49540	58	0	0
T7	98290	60	0	0
T8	18142	1650	0	0
T9	33219	259	0	0
T10	155530	67463	0	0

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	35014058	0	0
T1	26095	24623	0	0
T2	78955	73651	0	0
T3	16547	16376	0	0
T4	77661	75135	0	0
T5	49615	49080	0	0
T6	49540	49108	0	0
T7	98290	98048	0	0
T8	18142	16376	0	0
T9	33219	32752	0	0
T10	155530	87774	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	7900053	0	0
T1	26095	1353	0	0
T2	78955	4916	0	0
T3	16547	65	0	0
T4	77661	2030	0	0
T5	49615	240	0	0
T6	49540	58	0	0
T7	98290	60	0	0
T8	18142	1650	0	0
T9	33219	259	0	0
T10	155530	67463	0	0

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	1150446	0	0
T2	78955	80	0	0
T3	16547	5	0	0
T4	77661	32	0	0
T5	49615	1	0	0
T6	49540	1	0	0
T7	98290	13	0	0
T8	18142	0	0	0
T9	33219	1	0	0
T10	155530	10687	0	0
T16	52521	32	0	0
T17	0	27	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	1673162	0	0
T1	26095	149	0	0
T2	78955	167	0	0
T3	16547	0	0	0
T4	77661	59	0	0
T5	49615	0	0	0
T6	49540	0	0	0
T7	98290	0	0	0
T8	18142	346	0	0
T9	33219	0	0	0
T10	155530	10961	0	0
T14	0	151	0	0
T16	0	61	0	0
T17	0	6	0	0
T18	0	48	0	0
T19	0	3	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	43043830	0	0
T1	26095	26040	0	0
T2	78955	78673	0	0
T3	16547	16463	0	0
T4	77661	77295	0	0
T5	49615	49488	0	0
T6	49540	49388	0	0
T7	98290	98193	0	0
T8	18142	18048	0	0
T9	33219	33069	0	0
T10	155530	155387	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	35011433	0	0
T1	26095	24622	0	0
T2	78955	73647	0	0
T3	16547	16375	0	0
T4	77661	75130	0	0
T5	49615	49078	0	0
T6	49540	49106	0	0
T7	98290	98047	0	0
T8	18142	16375	0	0
T9	33219	32750	0	0
T10	155530	87763	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	7906574	0	0
T1	26095	1353	0	0
T2	78955	4916	0	0
T3	16547	65	0	0
T4	77661	2030	0	0
T5	49615	240	0	0
T6	49540	58	0	0
T7	98290	60	0	0
T8	18142	1650	0	0
T9	33219	259	0	0
T10	155530	67463	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	35136111	0	0
T1	26095	24686	0	0
T2	78955	73754	0	0
T3	16547	16397	0	0
T4	77661	75262	0	0
T5	49615	49247	0	0
T6	49540	49329	0	0
T7	98290	98132	0	0
T8	18142	16397	0	0
T9	33219	32809	0	0
T10	155530	87921	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	70	0	0
T25	33737	10	0	0
T26	35081	20	0	0
T27	0	10	0	0
T29	0	20	0	0
T30	0	10	0	0
T31	228351	0	0	0
T32	26961	0	0	0
T33	180851	0	0	0
T34	458277	0	0	0
T35	26031	0	0	0
T36	89255	0	0	0
T37	24748	0	0	0
T38	70267	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	516	0	0
T14	25728	0	0	0
T15	268228	5	0	0
T17	282869	10	0	0
T18	34868	0	0	0
T19	628255	20	0	0
T25	0	10	0	0
T26	0	20	0	0
T28	24977	0	0	0
T33	0	10	0	0
T34	0	5	0	0
T39	0	5	0	0
T40	0	5	0	0
T41	0	5	0	0
T42	33244	0	0	0
T43	16570	0	0	0
T44	16799	0	0	0
T45	25839	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	53047	0	0
T5	49615	30	0	0
T6	49540	35	0	0
T7	98290	0	0	0
T8	18142	0	0	0
T9	33219	34	0	0
T10	155530	0	0	0
T14	25728	0	0	0
T15	0	718	0	0
T16	52521	0	0	0
T17	282869	782	0	0
T19	0	1556	0	0
T28	24977	0	0	0
T42	0	66	0	0
T46	0	34	0	0
T47	0	35	0	0
T48	0	32	0	0

gen_fsm_scramble_enabled_asserts.InvalidStateTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43220971	51777	0	0
T5	49615	29	0	0
T6	49540	34	0	0
T7	98290	0	0	0
T8	18142	0	0	0
T9	33219	33	0	0
T10	155530	0	0	0
T14	25728	0	0	0
T15	0	698	0	0
T16	52521	0	0	0
T17	282869	759	0	0
T19	0	1525	0	0
T28	24977	0	0	0
T42	0	65	0	0
T46	0	33	0	0
T47	0	34	0	0
T48	0	31	0	0