Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

608694

1

T1

7378

T7

27511

T8

20

full_word

380342

1

T1

4492

T2

4

T5

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	988766	1			T1	11870		T2	4		T5	4
auto[TlIntgErrCmd]	94	1			T48	4		T49	3		T50	5
auto[TlIntgErrData]	83	1			T48	2		T49	2		T50	5
auto[TlIntgErrBoth]	93	1			T48	4		T49	5		T50	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177157

1

T1

2177

T2

4

T5

4

auto[1]

811879

1

T1

9693

T7

38495

T11

11729

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	85374	1			T1	1077		T7	3141		T8	20
auto[TlIntgErrNone]	partial	auto[1]	523073	1			T1	6301		T7	24370		T11	7655
auto[TlIntgErrNone]	full_word	auto[0]	91655	1			T1	1100		T2	4		T5	4
auto[TlIntgErrNone]	full_word	auto[1]	288664	1			T1	3392		T7	14125		T11	4074
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T48	2		T49	2		T50	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T48	1		T49	1		T50	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T105	1		T108	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T48	1		T111	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T48	1		T50	3		T107	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T48	1		T49	2		T50	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T112	1		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T105	1		T115	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T48	2		T49	2		T50	5
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T48	2		T49	3		T50	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T109	1		T116	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T109	1		T112	1		-	-