Unified Coverage Report :: Module :: rom_ctrl_fsm

Module : rom_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.64	100.00	98.18		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm	99.64	100.00	98.18		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.64	100.00	98.18		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.02	100.00	98.15	90.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.99	100.00	98.28	97.26		100.00	79.41	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_compare	97.95	100.00	97.67	90.00	100.00	100.00	100.00
u_counter	100.00	100.00	100.00			100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		58	58	100.00
ALWAYS	138	3	3	100.00
ALWAYS	141	19	19	100.00
ALWAYS	209	3	3	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
ALWAYS	261	5	5	100.00
ALWAYS	270	3	3	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	312	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	3	3
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
			MISSING_ELSE
154	1	1
155	1	1
156	1	1
157	1	1
163	2	2
			MISSING_ELSE
167	2	2
			MISSING_ELSE
171	2	2
			MISSING_ELSE
194	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
			MISSING_ELSE
209	3	3
216	1	1
217	1	1
220	1	1
223	1	1
224	1	1
231	1	1
232	1	1
233	1	1
239	1	1
241	1	1
242	1	1
243	1	1
247	1	1
251	1	1
261	1	1
262	1	1
263	1	1
			MISSING_ELSE
265	1	1
266	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
277	1	1
278	1	1
279	1	1
288	1	1
289	1	1
291	1	1
304	1	1
307	1	1
309	1	1
310	1	1
312	1	1

---

Cond Coverage for Module : rom_ctrl_fsm

	Total	Covered	Percent
Conditions	55	54	98.18
Logical	55	54	98.18
Non-Logical	0	0
Event	0	0

 LINE       148
 EXPRESSION (counter_lnt && kmac_rom_rdy_i && kmac_rom_vld_o)
             -----1-----    -------2------    -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (kmac_err_i ? Invalid : KmacAhead)
             -----1----

-1-	Status	Tests
0	Covered	T7,T9,T10
1	Covered	T37,T38,T39

 LINE       157
 EXPRESSION (kmac_err_i ? Invalid : Checking)
             -----1----

-1-	Status	Tests
0	Covered	T30,T40,T41
1	Covered	T42,T43

 LINE       163
 EXPRESSION (kmac_err_i ? Invalid : Checking)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T21

 LINE       194
 EXPRESSION 
 Number  Term
      1  (checker_done && ((!(state_q inside {Checking, Done})))) || 
      2  (counter_done && (state_q == ReadingLow)) || 
      3  (kmac_done_i && ((!(state_q inside {ReadingHigh, RomAhead})))))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T2,T9,T14
1	0	0	Covered	T2,T5,T9

 LINE       194
 SUB-EXPRESSION (checker_done && ((!(state_q inside {Checking, Done}))))
                 ------1-----    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T9

 LINE       194
 SUB-EXPRESSION (counter_done && (state_q == ReadingLow))
                 ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T9,T14

 LINE       194
 SUB-EXPRESSION (state_q == ReadingLow)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 SUB-EXPRESSION (kmac_done_i && ((!(state_q inside {ReadingHigh, RomAhead}))))
                 -----1-----    ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION (((state_q == ReadingHigh) || (state_q == KmacAhead)) & ((~counter_done)))
             --------------------------1-------------------------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION ((state_q == ReadingHigh) || (state_q == KmacAhead))
                 ------------1-----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (state_q == ReadingHigh)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (state_q == KmacAhead)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       265
 EXPRESSION (counter_read_req && (state_q == ReadingLow) && ((!counter_lnt)))
             --------1-------    -----------2-----------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       265
 SUB-EXPRESSION (state_q == ReadingLow)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (kmac_rom_rdy_i | (state_q inside {ReadingHigh, KmacAhead}))
             -------1------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       291
 EXPRESSION ((state_q != Checking) && (state_d == Checking))
             ----------1----------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 SUB-EXPRESSION (state_q != Checking)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       291
 SUB-EXPRESSION (state_d == Checking)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       312
 EXPRESSION (fsm_alert | checker_alert | unexpected_counter_change)
             ----1----   ------2------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T9,T15
0	1	0	Covered	T2,T5,T9
1	0	0	Covered	T2,T4,T5

---

FSM Coverage for Module : rom_ctrl_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Checking	157	Covered	T1,T2,T3
Done	171	Covered	T1,T2,T3
Invalid	156	Covered	T2,T4,T5
KmacAhead	156	Covered	T7,T9,T10
ReadingHigh	149	Covered	T1,T2,T3
ReadingLow	145	Covered	T1,T2,T3
RomAhead	155	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Checking->Done	171	Covered	T1,T2,T3
Checking->Invalid	197	Covered	T5,T9,T14
Done->Invalid	197	Covered	T2,T5,T9
KmacAhead->Checking	167	Covered	T7,T9,T10
KmacAhead->Invalid	197	Covered	T9,T28,T32
ReadingHigh->Checking	157	Covered	T30,T40,T41
ReadingHigh->Invalid	156	Covered	T5,T9,T14
ReadingHigh->KmacAhead	156	Covered	T7,T9,T10
ReadingHigh->RomAhead	155	Covered	T1,T2,T3
ReadingLow->Invalid	197	Covered	T2,T5,T9
ReadingLow->ReadingHigh	149	Covered	T1,T2,T3
RomAhead->Checking	163	Covered	T1,T2,T3
RomAhead->Invalid	163	Covered	T4,T5,T9

---

Branch Coverage for Module : rom_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		33	33	100.00
IF	138	2	2	100.00
CASE	144	17	17	100.00
IF	194	2	2	100.00
IF	203	2	2	100.00
IF	209	2	2	100.00
IF	262	2	2	100.00
IF	265	2	2	100.00
IF	270	2	2	100.00
IF	288	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	148	if (((counter_lnt && kmac_rom_rdy_i) && kmac_rom_vld_o))
-3-:	154	case ({kmac_done_i, counter_done})
-4-:	156	(kmac_err_i) ? 
-5-:	157	(kmac_err_i) ? 
-6-:	163	if (kmac_done_i)
-7-:	163	(kmac_err_i) ? 
-8-:	167	if (counter_done)
-9-:	171	if (checker_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ReadingLow	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadingLow	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadingHigh	-	2'b01	-	-	-	-	-	-	Covered	T1,T2,T3
ReadingHigh	-	2'b10	1	-	-	-	-	-	Covered	T37,T38,T39
ReadingHigh	-	2'b10	0	-	-	-	-	-	Covered	T7,T9,T10
ReadingHigh	-	2'b11	-	1	-	-	-	-	Covered	T42,T43
ReadingHigh	-	2'b11	-	0	-	-	-	-	Covered	T30,T40,T41
ReadingHigh	-	default	-	-	-	-	-	-	Covered	T1,T2,T3
RomAhead	-	-	-	-	1	1	-	-	Covered	T4,T20,T21
RomAhead	-	-	-	-	1	0	-	-	Covered	T1,T2,T3
RomAhead	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
KmacAhead	-	-	-	-	-	-	1	-	Covered	T7,T9,T10
KmacAhead	-	-	-	-	-	-	0	-	Covered	T7,T9,T10
Checking	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
Checking	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
Done	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	194	if ((((checker_done && (!(state_q inside {Checking, Done}))) || (counter_done && (state_q == ReadingLow))) || (kmac_done_i && (!(state_q inside {ReadingHigh, RomAhead})))))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if (alert_o)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	262	if (kmac_rom_rdy_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	if (((counter_read_req && (state_q == ReadingLow)) && (!counter_lnt)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	270	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
LastImpliesValid_A	43158557	2001	0	0
RelAddrWide_A	43158557	10692	0	0
SecCmCFILinear_A	43158557	5049	0	1254
u_state_regs_A	43158557	42990878	0	0

LastImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43158557	2001	0	0
T1	312772	8	0	0
T2	242948	14	0	0
T3	24843	1	0	0
T4	49860	3	0	0
T5	511899	27	0	0
T6	16566	1	0	0
T7	454329	9	0	0
T8	25833	1	0	0
T9	613847	36	0	0
T10	16554	1	0	0

RelAddrWide_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43158557	10692	0	0
T1	312772	56	0	0
T2	242948	72	0	0
T3	24843	8	0	0
T4	49860	16	0	0
T5	511899	142	0	0
T6	16566	8	0	0
T7	454329	72	0	0
T8	25833	8	0	0
T9	613847	171	0	0
T10	16554	8	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43158557	5049	0	1254
T1	312772	24	0	4
T2	242948	40	0	4
T3	24843	0	0	4
T4	49860	3	0	4
T5	511899	77	0	4
T6	16566	0	0	4
T7	454329	32	0	4
T8	25833	0	0	4
T9	613847	104	0	4
T10	16554	0	0	4
T11	0	8	0	0
T14	0	61	0	0
T15	0	39	0	0
T17	0	30	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43158557	42990878	0	0
T1	312772	312626	0	0
T2	242948	241762	0	0
T3	24843	24772	0	0
T4	49860	49735	0	0
T5	511899	509763	0	0
T6	16566	16480	0	0
T7	454329	454163	0	0
T8	25833	25773	0	0
T9	613847	610609	0	0
T10	16554	16460	0	0