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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.53 96.89 92.42 97.68 100.00 98.62 98.05 99.06


Total test records in report: 453
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T303 /workspace/coverage/default/45.rom_ctrl_alert_test.3844927693 Aug 18 05:24:28 PM PDT 24 Aug 18 05:24:37 PM PDT 24 340179899 ps
T304 /workspace/coverage/default/30.rom_ctrl_alert_test.4179270978 Aug 18 05:24:05 PM PDT 24 Aug 18 05:24:15 PM PDT 24 506204052 ps
T305 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1187333913 Aug 18 05:23:22 PM PDT 24 Aug 18 05:25:44 PM PDT 24 5502329167 ps
T306 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2387817991 Aug 18 05:24:33 PM PDT 24 Aug 18 05:24:55 PM PDT 24 2358507212 ps
T307 /workspace/coverage/default/29.rom_ctrl_alert_test.2768764888 Aug 18 05:23:56 PM PDT 24 Aug 18 05:24:05 PM PDT 24 249517670 ps
T308 /workspace/coverage/default/37.rom_ctrl_stress_all.10854535 Aug 18 05:24:15 PM PDT 24 Aug 18 05:24:37 PM PDT 24 2079909239 ps
T309 /workspace/coverage/default/46.rom_ctrl_alert_test.1667783782 Aug 18 05:24:33 PM PDT 24 Aug 18 05:24:41 PM PDT 24 340543662 ps
T310 /workspace/coverage/default/14.rom_ctrl_stress_all.723247633 Aug 18 05:23:21 PM PDT 24 Aug 18 05:23:43 PM PDT 24 785006095 ps
T311 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1486099750 Aug 18 05:24:02 PM PDT 24 Aug 18 05:28:43 PM PDT 24 9225764261 ps
T312 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2943823384 Aug 18 05:23:20 PM PDT 24 Aug 18 05:23:41 PM PDT 24 377815888 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.955709446 Aug 18 05:22:59 PM PDT 24 Aug 18 05:24:58 PM PDT 24 2480208919 ps
T313 /workspace/coverage/default/7.rom_ctrl_stress_all.3689263787 Aug 18 05:23:09 PM PDT 24 Aug 18 05:23:43 PM PDT 24 558617204 ps
T314 /workspace/coverage/default/17.rom_ctrl_alert_test.1208677032 Aug 18 05:23:28 PM PDT 24 Aug 18 05:23:36 PM PDT 24 752602562 ps
T315 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3499050109 Aug 18 05:23:56 PM PDT 24 Aug 18 05:24:07 PM PDT 24 340388557 ps
T316 /workspace/coverage/default/14.rom_ctrl_alert_test.3158220758 Aug 18 05:23:28 PM PDT 24 Aug 18 05:23:36 PM PDT 24 664651812 ps
T317 /workspace/coverage/default/45.rom_ctrl_stress_all.3840836751 Aug 18 05:24:27 PM PDT 24 Aug 18 05:24:56 PM PDT 24 2208188396 ps
T318 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1668814915 Aug 18 05:24:13 PM PDT 24 Aug 18 05:29:14 PM PDT 24 19427641996 ps
T319 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2817172320 Aug 18 05:23:13 PM PDT 24 Aug 18 05:27:19 PM PDT 24 6241622202 ps
T320 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1811712147 Aug 18 05:23:08 PM PDT 24 Aug 18 05:23:18 PM PDT 24 177437820 ps
T321 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3575188759 Aug 18 05:24:32 PM PDT 24 Aug 18 05:24:44 PM PDT 24 268656773 ps
T322 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2740186811 Aug 18 05:22:59 PM PDT 24 Aug 18 05:23:21 PM PDT 24 2059830317 ps
T323 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3538866212 Aug 18 05:23:22 PM PDT 24 Aug 18 05:23:51 PM PDT 24 4119939543 ps
T324 /workspace/coverage/default/46.rom_ctrl_stress_all.1915037294 Aug 18 05:24:26 PM PDT 24 Aug 18 05:24:55 PM PDT 24 738520453 ps
T16 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4185687041 Aug 18 05:23:27 PM PDT 24 Aug 18 05:26:21 PM PDT 24 15509594240 ps
T325 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.27055332 Aug 18 05:24:25 PM PDT 24 Aug 18 05:25:22 PM PDT 24 14322382973 ps
T137 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2898610396 Aug 18 05:23:10 PM PDT 24 Aug 18 05:24:11 PM PDT 24 5577360079 ps
T326 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2790278439 Aug 18 05:24:33 PM PDT 24 Aug 18 05:24:43 PM PDT 24 674213189 ps
T327 /workspace/coverage/default/1.rom_ctrl_stress_all.37504105 Aug 18 05:22:59 PM PDT 24 Aug 18 05:23:41 PM PDT 24 847174074 ps
T328 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2498871074 Aug 18 05:22:58 PM PDT 24 Aug 18 05:27:03 PM PDT 24 6957563756 ps
T329 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2110376897 Aug 18 05:23:08 PM PDT 24 Aug 18 05:26:28 PM PDT 24 3782671028 ps
T330 /workspace/coverage/default/8.rom_ctrl_alert_test.3432448758 Aug 18 05:23:32 PM PDT 24 Aug 18 05:23:40 PM PDT 24 664378567 ps
T331 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.771736497 Aug 18 05:24:24 PM PDT 24 Aug 18 05:24:42 PM PDT 24 1325198320 ps
T332 /workspace/coverage/default/16.rom_ctrl_stress_all.2984837719 Aug 18 05:23:30 PM PDT 24 Aug 18 05:24:03 PM PDT 24 539175061 ps
T333 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3720098310 Aug 18 05:24:24 PM PDT 24 Aug 18 05:26:50 PM PDT 24 2315486941 ps
T334 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4144563095 Aug 18 05:23:00 PM PDT 24 Aug 18 05:23:11 PM PDT 24 178828216 ps
T335 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3485575299 Aug 18 05:23:29 PM PDT 24 Aug 18 05:28:39 PM PDT 24 4533076261 ps
T336 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2461391734 Aug 18 05:23:20 PM PDT 24 Aug 18 05:27:34 PM PDT 24 8623805851 ps
T337 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4258529951 Aug 18 05:24:23 PM PDT 24 Aug 18 05:28:08 PM PDT 24 40135288518 ps
T338 /workspace/coverage/default/18.rom_ctrl_alert_test.1892689436 Aug 18 05:23:26 PM PDT 24 Aug 18 05:23:34 PM PDT 24 661859538 ps
T339 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3319614899 Aug 18 05:24:33 PM PDT 24 Aug 18 05:29:29 PM PDT 24 23021807942 ps
T340 /workspace/coverage/default/9.rom_ctrl_alert_test.4001339180 Aug 18 05:23:22 PM PDT 24 Aug 18 05:23:31 PM PDT 24 1027868551 ps
T341 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3491100257 Aug 18 05:23:18 PM PDT 24 Aug 18 05:23:29 PM PDT 24 271024621 ps
T342 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2249648913 Aug 18 05:23:32 PM PDT 24 Aug 18 05:23:50 PM PDT 24 1375502775 ps
T343 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.4008686170 Aug 18 05:23:45 PM PDT 24 Aug 18 05:25:03 PM PDT 24 1937119455 ps
T344 /workspace/coverage/default/49.rom_ctrl_alert_test.233653149 Aug 18 05:24:33 PM PDT 24 Aug 18 05:24:41 PM PDT 24 688893608 ps
T136 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.388146876 Aug 18 05:24:03 PM PDT 24 Aug 18 05:25:36 PM PDT 24 6320949242 ps
T345 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1935949333 Aug 18 05:24:16 PM PDT 24 Aug 18 05:24:34 PM PDT 24 431540316 ps
T346 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.247340610 Aug 18 05:24:27 PM PDT 24 Aug 18 05:29:01 PM PDT 24 5511008963 ps
T347 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1238360076 Aug 18 05:24:32 PM PDT 24 Aug 18 05:30:47 PM PDT 24 32970531103 ps
T348 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3281289950 Aug 18 05:23:30 PM PDT 24 Aug 18 05:23:48 PM PDT 24 1322241725 ps
T349 /workspace/coverage/default/2.rom_ctrl_smoke.3538922117 Aug 18 05:23:00 PM PDT 24 Aug 18 05:23:12 PM PDT 24 294477132 ps
T350 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2721342558 Aug 18 05:23:28 PM PDT 24 Aug 18 05:24:30 PM PDT 24 1811448887 ps
T351 /workspace/coverage/default/2.rom_ctrl_stress_all.2494349062 Aug 18 05:22:58 PM PDT 24 Aug 18 05:23:14 PM PDT 24 498754638 ps
T352 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1703024620 Aug 18 05:23:55 PM PDT 24 Aug 18 05:24:23 PM PDT 24 1992900629 ps
T353 /workspace/coverage/default/24.rom_ctrl_stress_all.2420633206 Aug 18 05:23:47 PM PDT 24 Aug 18 05:24:45 PM PDT 24 1330458566 ps
T354 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4207334069 Aug 18 05:23:13 PM PDT 24 Aug 18 05:23:34 PM PDT 24 1983819615 ps
T355 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2160033161 Aug 18 05:23:30 PM PDT 24 Aug 18 05:23:52 PM PDT 24 516188213 ps
T356 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3139295593 Aug 18 05:24:29 PM PDT 24 Aug 18 05:24:48 PM PDT 24 1440147578 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4170237091 Aug 18 06:05:38 PM PDT 24 Aug 18 06:05:48 PM PDT 24 726268473 ps
T62 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2494901489 Aug 18 06:06:46 PM PDT 24 Aug 18 06:09:23 PM PDT 24 1009222958 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3737036279 Aug 18 06:05:40 PM PDT 24 Aug 18 06:06:16 PM PDT 24 1333144415 ps
T102 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1139933263 Aug 18 06:05:31 PM PDT 24 Aug 18 06:05:41 PM PDT 24 250908377 ps
T357 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2519858934 Aug 18 06:06:28 PM PDT 24 Aug 18 06:06:38 PM PDT 24 515248155 ps
T358 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2772080077 Aug 18 06:05:21 PM PDT 24 Aug 18 06:05:35 PM PDT 24 3923155563 ps
T68 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3662238974 Aug 18 06:05:21 PM PDT 24 Aug 18 06:05:29 PM PDT 24 170777214 ps
T359 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2516014175 Aug 18 06:06:58 PM PDT 24 Aug 18 06:07:10 PM PDT 24 255909017 ps
T360 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1498805595 Aug 18 06:06:33 PM PDT 24 Aug 18 06:06:42 PM PDT 24 1291897437 ps
T361 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1370987789 Aug 18 06:05:39 PM PDT 24 Aug 18 06:05:47 PM PDT 24 920747619 ps
T362 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3790811033 Aug 18 06:06:13 PM PDT 24 Aug 18 06:06:23 PM PDT 24 1082405208 ps
T103 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1156698943 Aug 18 06:06:49 PM PDT 24 Aug 18 06:06:59 PM PDT 24 516462098 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4085775697 Aug 18 06:06:22 PM PDT 24 Aug 18 06:07:43 PM PDT 24 601516458 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2349229196 Aug 18 06:05:30 PM PDT 24 Aug 18 06:05:38 PM PDT 24 688278650 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1857541245 Aug 18 06:06:56 PM PDT 24 Aug 18 06:07:04 PM PDT 24 340247001 ps
T364 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1020320559 Aug 18 06:07:07 PM PDT 24 Aug 18 06:07:20 PM PDT 24 1030315717 ps
T64 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1554938155 Aug 18 06:06:15 PM PDT 24 Aug 18 06:07:35 PM PDT 24 493452073 ps
T365 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2169517685 Aug 18 06:06:38 PM PDT 24 Aug 18 06:06:49 PM PDT 24 540487857 ps
T366 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2724002805 Aug 18 06:06:32 PM PDT 24 Aug 18 06:06:45 PM PDT 24 254946027 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2796425886 Aug 18 06:05:34 PM PDT 24 Aug 18 06:05:43 PM PDT 24 1771320977 ps
T367 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.626785836 Aug 18 06:06:58 PM PDT 24 Aug 18 06:07:09 PM PDT 24 258163948 ps
T121 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1463989650 Aug 18 06:05:40 PM PDT 24 Aug 18 06:07:01 PM PDT 24 1245966229 ps
T368 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1611298906 Aug 18 06:07:05 PM PDT 24 Aug 18 06:07:16 PM PDT 24 1362311259 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1265367547 Aug 18 06:05:49 PM PDT 24 Aug 18 06:05:57 PM PDT 24 1499313549 ps
T116 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1232518607 Aug 18 06:06:58 PM PDT 24 Aug 18 06:08:18 PM PDT 24 2822913300 ps
T71 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1296316620 Aug 18 06:06:21 PM PDT 24 Aug 18 06:06:30 PM PDT 24 515102424 ps
T72 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1486410241 Aug 18 06:06:29 PM PDT 24 Aug 18 06:07:04 PM PDT 24 713809731 ps
T111 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1632363224 Aug 18 06:06:08 PM PDT 24 Aug 18 06:06:16 PM PDT 24 167723146 ps
T125 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1218338939 Aug 18 06:07:06 PM PDT 24 Aug 18 06:09:37 PM PDT 24 594813129 ps
T105 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1094740185 Aug 18 06:06:05 PM PDT 24 Aug 18 06:06:18 PM PDT 24 2047632913 ps
T106 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2933144109 Aug 18 06:06:30 PM PDT 24 Aug 18 06:06:38 PM PDT 24 688842643 ps
T73 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.891990952 Aug 18 06:05:37 PM PDT 24 Aug 18 06:05:52 PM PDT 24 180184555 ps
T369 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2198519262 Aug 18 06:06:57 PM PDT 24 Aug 18 06:07:06 PM PDT 24 2055443281 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3422506078 Aug 18 06:05:51 PM PDT 24 Aug 18 06:06:00 PM PDT 24 1651423687 ps
T74 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3328790257 Aug 18 06:06:42 PM PDT 24 Aug 18 06:07:18 PM PDT 24 696266716 ps
T120 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.183825885 Aug 18 06:07:05 PM PDT 24 Aug 18 06:08:27 PM PDT 24 705034404 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3916199758 Aug 18 06:06:13 PM PDT 24 Aug 18 06:06:22 PM PDT 24 269994548 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2675976675 Aug 18 06:05:50 PM PDT 24 Aug 18 06:05:59 PM PDT 24 262157143 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.876585427 Aug 18 06:05:57 PM PDT 24 Aug 18 06:06:12 PM PDT 24 4206680010 ps
T76 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.323302790 Aug 18 06:05:49 PM PDT 24 Aug 18 06:05:57 PM PDT 24 573497774 ps
T122 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.43018575 Aug 18 06:06:30 PM PDT 24 Aug 18 06:09:05 PM PDT 24 427068875 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1149039801 Aug 18 06:06:14 PM PDT 24 Aug 18 06:06:23 PM PDT 24 3528594908 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1825359171 Aug 18 06:05:57 PM PDT 24 Aug 18 06:06:06 PM PDT 24 250855174 ps
T375 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3037928334 Aug 18 06:06:49 PM PDT 24 Aug 18 06:06:57 PM PDT 24 193345389 ps
T376 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1589427959 Aug 18 06:06:30 PM PDT 24 Aug 18 06:06:42 PM PDT 24 473665069 ps
T377 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2872517183 Aug 18 06:06:21 PM PDT 24 Aug 18 06:06:30 PM PDT 24 250877480 ps
T378 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.783526497 Aug 18 06:07:06 PM PDT 24 Aug 18 06:07:14 PM PDT 24 722569739 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2031185981 Aug 18 06:05:47 PM PDT 24 Aug 18 06:05:57 PM PDT 24 529137495 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1176662300 Aug 18 06:06:06 PM PDT 24 Aug 18 06:06:19 PM PDT 24 325844018 ps
T107 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3506381075 Aug 18 06:06:22 PM PDT 24 Aug 18 06:06:32 PM PDT 24 1121450486 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.830559456 Aug 18 06:06:22 PM PDT 24 Aug 18 06:06:33 PM PDT 24 660756121 ps
T108 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3158434057 Aug 18 06:06:07 PM PDT 24 Aug 18 06:06:15 PM PDT 24 346151172 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3954562650 Aug 18 06:05:31 PM PDT 24 Aug 18 06:05:47 PM PDT 24 476364559 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4158139006 Aug 18 06:06:07 PM PDT 24 Aug 18 06:06:16 PM PDT 24 721397156 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3629724598 Aug 18 06:06:48 PM PDT 24 Aug 18 06:06:56 PM PDT 24 551717537 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.688035895 Aug 18 06:07:05 PM PDT 24 Aug 18 06:07:15 PM PDT 24 4101210996 ps
T109 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1639940094 Aug 18 06:05:31 PM PDT 24 Aug 18 06:05:39 PM PDT 24 174756385 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3081189074 Aug 18 06:05:31 PM PDT 24 Aug 18 06:05:45 PM PDT 24 251934309 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4171732354 Aug 18 06:05:22 PM PDT 24 Aug 18 06:05:32 PM PDT 24 1029522737 ps
T386 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1808996557 Aug 18 06:06:57 PM PDT 24 Aug 18 06:07:40 PM PDT 24 5345890420 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.82063645 Aug 18 06:06:40 PM PDT 24 Aug 18 06:06:49 PM PDT 24 993121590 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.105293850 Aug 18 06:05:31 PM PDT 24 Aug 18 06:05:40 PM PDT 24 985346448 ps
T117 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3507121882 Aug 18 06:06:05 PM PDT 24 Aug 18 06:07:25 PM PDT 24 457255300 ps
T119 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.492338804 Aug 18 06:05:49 PM PDT 24 Aug 18 06:07:08 PM PDT 24 250190408 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.706802844 Aug 18 06:05:51 PM PDT 24 Aug 18 06:05:59 PM PDT 24 182520685 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2942634931 Aug 18 06:05:39 PM PDT 24 Aug 18 06:05:47 PM PDT 24 687894331 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2376155616 Aug 18 06:06:23 PM PDT 24 Aug 18 06:06:33 PM PDT 24 945448124 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3942900653 Aug 18 06:05:59 PM PDT 24 Aug 18 06:06:08 PM PDT 24 517771237 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3903762381 Aug 18 06:05:39 PM PDT 24 Aug 18 06:05:49 PM PDT 24 257828945 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1788021108 Aug 18 06:05:30 PM PDT 24 Aug 18 06:05:39 PM PDT 24 972432476 ps
T394 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.945171131 Aug 18 06:06:30 PM PDT 24 Aug 18 06:06:43 PM PDT 24 1318171741 ps
T395 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.214387042 Aug 18 06:06:39 PM PDT 24 Aug 18 06:06:49 PM PDT 24 250455291 ps
T396 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2687421697 Aug 18 06:06:06 PM PDT 24 Aug 18 06:06:43 PM PDT 24 724031033 ps
T118 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3646323115 Aug 18 06:06:29 PM PDT 24 Aug 18 06:09:00 PM PDT 24 7369716402 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2327336075 Aug 18 06:06:39 PM PDT 24 Aug 18 06:06:49 PM PDT 24 266377595 ps
T398 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3703523561 Aug 18 06:06:56 PM PDT 24 Aug 18 06:07:07 PM PDT 24 1646943615 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1090390340 Aug 18 06:06:47 PM PDT 24 Aug 18 06:07:50 PM PDT 24 5606990791 ps
T86 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2913060705 Aug 18 06:06:22 PM PDT 24 Aug 18 06:07:26 PM PDT 24 6115119014 ps
T399 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.336309077 Aug 18 06:06:14 PM PDT 24 Aug 18 06:06:23 PM PDT 24 254127059 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3337257792 Aug 18 06:05:31 PM PDT 24 Aug 18 06:06:14 PM PDT 24 3892567296 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2902598619 Aug 18 06:05:48 PM PDT 24 Aug 18 06:06:50 PM PDT 24 1625355694 ps
T402 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2337481774 Aug 18 06:06:50 PM PDT 24 Aug 18 06:07:08 PM PDT 24 984703028 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1246609361 Aug 18 06:07:06 PM PDT 24 Aug 18 06:08:00 PM PDT 24 5735142882 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3325118843 Aug 18 06:06:23 PM PDT 24 Aug 18 06:06:33 PM PDT 24 183616126 ps
T126 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1177285259 Aug 18 06:06:58 PM PDT 24 Aug 18 06:09:30 PM PDT 24 356622358 ps
T404 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.811696892 Aug 18 06:07:17 PM PDT 24 Aug 18 06:07:31 PM PDT 24 503000614 ps
T405 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3770590323 Aug 18 06:06:17 PM PDT 24 Aug 18 06:06:26 PM PDT 24 2063982128 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.868489121 Aug 18 06:05:22 PM PDT 24 Aug 18 06:06:43 PM PDT 24 236278931 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.73275648 Aug 18 06:05:59 PM PDT 24 Aug 18 06:06:08 PM PDT 24 884339660 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2767568812 Aug 18 06:05:21 PM PDT 24 Aug 18 06:06:25 PM PDT 24 1595478119 ps
T409 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3626987021 Aug 18 06:05:39 PM PDT 24 Aug 18 06:05:49 PM PDT 24 1051028760 ps
T88 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1372692894 Aug 18 06:06:55 PM PDT 24 Aug 18 06:07:03 PM PDT 24 174651890 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2536732900 Aug 18 06:06:28 PM PDT 24 Aug 18 06:09:02 PM PDT 24 310474706 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1864304143 Aug 18 06:06:21 PM PDT 24 Aug 18 06:06:31 PM PDT 24 517516930 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3919798387 Aug 18 06:06:39 PM PDT 24 Aug 18 06:06:47 PM PDT 24 660422236 ps
T89 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1929546772 Aug 18 06:06:13 PM PDT 24 Aug 18 06:06:49 PM PDT 24 2860725998 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4009430335 Aug 18 06:05:21 PM PDT 24 Aug 18 06:05:35 PM PDT 24 3096775439 ps
T127 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1213200495 Aug 18 06:06:21 PM PDT 24 Aug 18 06:08:55 PM PDT 24 336742382 ps
T90 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3107844119 Aug 18 06:06:23 PM PDT 24 Aug 18 06:07:00 PM PDT 24 5285317944 ps
T414 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.137520843 Aug 18 06:06:43 PM PDT 24 Aug 18 06:09:14 PM PDT 24 1504111409 ps
T415 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4260890574 Aug 18 06:06:23 PM PDT 24 Aug 18 06:06:36 PM PDT 24 945297516 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.720598294 Aug 18 06:05:48 PM PDT 24 Aug 18 06:06:05 PM PDT 24 3597404820 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1551749792 Aug 18 06:05:33 PM PDT 24 Aug 18 06:05:43 PM PDT 24 249293569 ps
T418 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1952789839 Aug 18 06:06:33 PM PDT 24 Aug 18 06:07:15 PM PDT 24 1960307220 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2220415734 Aug 18 06:06:07 PM PDT 24 Aug 18 06:06:15 PM PDT 24 347216687 ps
T420 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3669163981 Aug 18 06:07:07 PM PDT 24 Aug 18 06:07:17 PM PDT 24 3212162646 ps
T421 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1677264201 Aug 18 06:06:40 PM PDT 24 Aug 18 06:06:48 PM PDT 24 173126762 ps
T128 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2713646100 Aug 18 06:06:50 PM PDT 24 Aug 18 06:08:09 PM PDT 24 2462141312 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.501068187 Aug 18 06:05:55 PM PDT 24 Aug 18 06:06:06 PM PDT 24 826900750 ps
T129 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3174256468 Aug 18 06:05:59 PM PDT 24 Aug 18 06:07:19 PM PDT 24 1107630105 ps
T423 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2666517525 Aug 18 06:06:21 PM PDT 24 Aug 18 06:06:36 PM PDT 24 3518767404 ps
T424 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1397017911 Aug 18 06:07:07 PM PDT 24 Aug 18 06:07:19 PM PDT 24 338330154 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3008124726 Aug 18 06:05:22 PM PDT 24 Aug 18 06:05:37 PM PDT 24 1667807055 ps
T123 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.379721415 Aug 18 06:06:14 PM PDT 24 Aug 18 06:07:36 PM PDT 24 937460531 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4278881183 Aug 18 06:06:13 PM PDT 24 Aug 18 06:06:26 PM PDT 24 279823881 ps
T427 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4268856080 Aug 18 06:06:12 PM PDT 24 Aug 18 06:06:24 PM PDT 24 603739185 ps
T428 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.264561300 Aug 18 06:06:20 PM PDT 24 Aug 18 06:07:03 PM PDT 24 2076289033 ps
T429 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3430956782 Aug 18 06:06:37 PM PDT 24 Aug 18 06:06:50 PM PDT 24 174612741 ps
T430 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.446606677 Aug 18 06:07:05 PM PDT 24 Aug 18 06:08:07 PM PDT 24 1545216298 ps
T431 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2447543729 Aug 18 06:06:23 PM PDT 24 Aug 18 06:06:34 PM PDT 24 169920252 ps
T432 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4279320195 Aug 18 06:06:29 PM PDT 24 Aug 18 06:06:36 PM PDT 24 325364093 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1674185849 Aug 18 06:05:55 PM PDT 24 Aug 18 06:06:36 PM PDT 24 3623920438 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3557692937 Aug 18 06:05:22 PM PDT 24 Aug 18 06:05:30 PM PDT 24 1031638260 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2989030162 Aug 18 06:05:53 PM PDT 24 Aug 18 06:06:03 PM PDT 24 1763830359 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.905003795 Aug 18 06:05:49 PM PDT 24 Aug 18 06:05:58 PM PDT 24 254537771 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4113285136 Aug 18 06:06:47 PM PDT 24 Aug 18 06:06:59 PM PDT 24 177328011 ps
T91 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2123611766 Aug 18 06:06:48 PM PDT 24 Aug 18 06:07:42 PM PDT 24 2144454541 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.807044235 Aug 18 06:05:40 PM PDT 24 Aug 18 06:05:54 PM PDT 24 495441432 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.486486619 Aug 18 06:07:15 PM PDT 24 Aug 18 06:07:25 PM PDT 24 1081372012 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1600514791 Aug 18 06:06:50 PM PDT 24 Aug 18 06:06:58 PM PDT 24 174645368 ps
T441 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1873813902 Aug 18 06:06:04 PM PDT 24 Aug 18 06:06:18 PM PDT 24 279858078 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1265526024 Aug 18 06:05:20 PM PDT 24 Aug 18 06:05:28 PM PDT 24 167509255 ps
T124 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1202717822 Aug 18 06:05:31 PM PDT 24 Aug 18 06:07:59 PM PDT 24 568892747 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.660947409 Aug 18 06:05:34 PM PDT 24 Aug 18 06:05:42 PM PDT 24 180507737 ps
T444 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1566068170 Aug 18 06:07:06 PM PDT 24 Aug 18 06:07:15 PM PDT 24 576487062 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.158170232 Aug 18 06:05:49 PM PDT 24 Aug 18 06:06:04 PM PDT 24 506937031 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1952341248 Aug 18 06:06:05 PM PDT 24 Aug 18 06:06:13 PM PDT 24 920274586 ps
T92 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2751267946 Aug 18 06:06:13 PM PDT 24 Aug 18 06:06:56 PM PDT 24 16947101991 ps
T447 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2072888067 Aug 18 06:06:47 PM PDT 24 Aug 18 06:06:56 PM PDT 24 250520843 ps
T448 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1753155972 Aug 18 06:07:00 PM PDT 24 Aug 18 06:07:10 PM PDT 24 497504693 ps
T449 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.932923809 Aug 18 06:06:23 PM PDT 24 Aug 18 06:06:31 PM PDT 24 175130103 ps
T450 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2265709309 Aug 18 06:06:14 PM PDT 24 Aug 18 06:06:25 PM PDT 24 332088331 ps
T451 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1100071090 Aug 18 06:06:51 PM PDT 24 Aug 18 06:07:46 PM PDT 24 12857725588 ps
T452 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3808449637 Aug 18 06:06:30 PM PDT 24 Aug 18 06:06:38 PM PDT 24 697740284 ps
T453 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3448651678 Aug 18 06:06:46 PM PDT 24 Aug 18 06:06:56 PM PDT 24 270821410 ps

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1454873265
Short name T6
Test name
Test status
Simulation time 18895428672 ps
CPU time 182.88 seconds
Started Aug 18 05:23:56 PM PDT 24
Finished Aug 18 05:26:59 PM PDT 24
Peak memory 235664 kb
Host smart-d20275a1-90ce-4136-8c93-f2e82d36b7ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454873265 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1454873265
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1020539210
Short name T18
Test name
Test status
Simulation time 34579305338 ps
CPU time 282.52 seconds
Started Aug 18 05:23:58 PM PDT 24
Finished Aug 18 05:28:40 PM PDT 24
Peak memory 239668 kb
Host smart-370f5edc-37f8-45f1-b20a-f8e5643fc198
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020539210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1020539210
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.650659691
Short name T41
Test name
Test status
Simulation time 8356581972 ps
CPU time 295.18 seconds
Started Aug 18 05:23:10 PM PDT 24
Finished Aug 18 05:28:05 PM PDT 24
Peak memory 240280 kb
Host smart-a510a5c9-f0f2-42ae-ae90-9f147a519c10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650659691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.650659691
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2494901489
Short name T62
Test name
Test status
Simulation time 1009222958 ps
CPU time 156.37 seconds
Started Aug 18 06:06:46 PM PDT 24
Finished Aug 18 06:09:23 PM PDT 24
Peak memory 219620 kb
Host smart-319eb0b5-acfc-4287-b776-346d45526439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494901489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2494901489
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3251085122
Short name T57
Test name
Test status
Simulation time 689106565 ps
CPU time 18.38 seconds
Started Aug 18 05:24:05 PM PDT 24
Finished Aug 18 05:24:23 PM PDT 24
Peak memory 218488 kb
Host smart-d22a066d-e46c-498b-a3bb-5f39bfc4635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251085122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3251085122
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.503669397
Short name T7
Test name
Test status
Simulation time 249450576 ps
CPU time 9.47 seconds
Started Aug 18 05:23:56 PM PDT 24
Finished Aug 18 05:24:06 PM PDT 24
Peak memory 218300 kb
Host smart-b0d21105-8042-4843-bbef-a89a018eaccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503669397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.503669397
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.371466565
Short name T21
Test name
Test status
Simulation time 1252395697 ps
CPU time 116.88 seconds
Started Aug 18 05:23:08 PM PDT 24
Finished Aug 18 05:25:05 PM PDT 24
Peak memory 238832 kb
Host smart-86000e34-06fa-4cf7-acc8-f15c38cddbc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371466565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.371466565
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1202717822
Short name T124
Test name
Test status
Simulation time 568892747 ps
CPU time 147.75 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:07:59 PM PDT 24
Peak memory 214820 kb
Host smart-98452216-f07e-4ec3-87c5-e0bd0c903de7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202717822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1202717822
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2796425886
Short name T69
Test name
Test status
Simulation time 1771320977 ps
CPU time 9.25 seconds
Started Aug 18 06:05:34 PM PDT 24
Finished Aug 18 06:05:43 PM PDT 24
Peak memory 211404 kb
Host smart-078d2908-6554-423b-9860-132b6527ade9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796425886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2796425886
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4185687041
Short name T16
Test name
Test status
Simulation time 15509594240 ps
CPU time 173.44 seconds
Started Aug 18 05:23:27 PM PDT 24
Finished Aug 18 05:26:21 PM PDT 24
Peak memory 227412 kb
Host smart-04ddbd1e-baf7-45eb-91a8-fd916428aaf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185687041 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4185687041
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3232149266
Short name T49
Test name
Test status
Simulation time 2006351744 ps
CPU time 29.43 seconds
Started Aug 18 05:23:08 PM PDT 24
Finished Aug 18 05:23:38 PM PDT 24
Peak memory 219132 kb
Host smart-d6bc3642-4796-4726-bd75-5844db4295ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232149266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3232149266
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3928493477
Short name T14
Test name
Test status
Simulation time 2126500819 ps
CPU time 41.52 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 219020 kb
Host smart-9a197a55-b670-4e27-a42c-72160b399975
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928493477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3928493477
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2249648913
Short name T342
Test name
Test status
Simulation time 1375502775 ps
CPU time 18.07 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:23:50 PM PDT 24
Peak memory 218724 kb
Host smart-5683e1c4-e374-490a-818f-d8eab94b7c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249648913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2249648913
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2817924919
Short name T38
Test name
Test status
Simulation time 78379834260 ps
CPU time 266.8 seconds
Started Aug 18 05:24:26 PM PDT 24
Finished Aug 18 05:28:53 PM PDT 24
Peak memory 237704 kb
Host smart-3a73c0c9-172b-48a0-9fe3-8264f34346e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817924919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2817924919
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1554938155
Short name T64
Test name
Test status
Simulation time 493452073 ps
CPU time 79.26 seconds
Started Aug 18 06:06:15 PM PDT 24
Finished Aug 18 06:07:35 PM PDT 24
Peak memory 213500 kb
Host smart-d4221c7e-97d2-4acc-bc51-2f1b80b361b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554938155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1554938155
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2123611766
Short name T91
Test name
Test status
Simulation time 2144454541 ps
CPU time 53.75 seconds
Started Aug 18 06:06:48 PM PDT 24
Finished Aug 18 06:07:42 PM PDT 24
Peak memory 214460 kb
Host smart-51ec4ce9-ed56-4e1e-a345-8cb0815a9f7d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123611766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2123611766
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3605117796
Short name T13
Test name
Test status
Simulation time 2947496999 ps
CPU time 147.35 seconds
Started Aug 18 05:24:02 PM PDT 24
Finished Aug 18 05:26:30 PM PDT 24
Peak memory 224280 kb
Host smart-ed883431-0301-4f80-8869-a5c05d056a05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605117796 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3605117796
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3646323115
Short name T118
Test name
Test status
Simulation time 7369716402 ps
CPU time 150.61 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:09:00 PM PDT 24
Peak memory 219684 kb
Host smart-6bf1a627-66ed-427f-8797-0dcdd8771df0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646323115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3646323115
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1139933263
Short name T102
Test name
Test status
Simulation time 250908377 ps
CPU time 9.5 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:05:41 PM PDT 24
Peak memory 211980 kb
Host smart-065944ee-e968-463b-b9cb-fe5b0ac8d889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139933263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1139933263
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3954562650
Short name T83
Test name
Test status
Simulation time 476364559 ps
CPU time 15.8 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 212356 kb
Host smart-494df74f-7aef-48c1-9dad-33f90441a011
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954562650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3954562650
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1881376835
Short name T93
Test name
Test status
Simulation time 264756556 ps
CPU time 11.57 seconds
Started Aug 18 05:23:17 PM PDT 24
Finished Aug 18 05:23:29 PM PDT 24
Peak memory 218496 kb
Host smart-35434f9b-8c05-46db-a09c-e186fc954284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881376835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1881376835
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3662238974
Short name T68
Test name
Test status
Simulation time 170777214 ps
CPU time 7.92 seconds
Started Aug 18 06:05:21 PM PDT 24
Finished Aug 18 06:05:29 PM PDT 24
Peak memory 211552 kb
Host smart-bc5b4b11-492c-4aa3-9739-47765b65813f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662238974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3662238974
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3557692937
Short name T434
Test name
Test status
Simulation time 1031638260 ps
CPU time 7.66 seconds
Started Aug 18 06:05:22 PM PDT 24
Finished Aug 18 06:05:30 PM PDT 24
Peak memory 211508 kb
Host smart-afdf22d7-8ac6-412e-bf73-60316fc9de2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557692937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3557692937
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3008124726
Short name T425
Test name
Test status
Simulation time 1667807055 ps
CPU time 14.74 seconds
Started Aug 18 06:05:22 PM PDT 24
Finished Aug 18 06:05:37 PM PDT 24
Peak memory 212788 kb
Host smart-c7e652c7-8491-46d5-8606-4e1f03431814
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008124726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3008124726
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.660947409
Short name T443
Test name
Test status
Simulation time 180507737 ps
CPU time 8.27 seconds
Started Aug 18 06:05:34 PM PDT 24
Finished Aug 18 06:05:42 PM PDT 24
Peak memory 216428 kb
Host smart-0e61b35b-a1b2-4e09-a9f2-0a07453969c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660947409 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.660947409
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1265526024
Short name T442
Test name
Test status
Simulation time 167509255 ps
CPU time 7.92 seconds
Started Aug 18 06:05:20 PM PDT 24
Finished Aug 18 06:05:28 PM PDT 24
Peak memory 211628 kb
Host smart-93f3b026-afca-44df-a592-1fc6819c7fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265526024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1265526024
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4171732354
Short name T385
Test name
Test status
Simulation time 1029522737 ps
CPU time 9.02 seconds
Started Aug 18 06:05:22 PM PDT 24
Finished Aug 18 06:05:32 PM PDT 24
Peak memory 211360 kb
Host smart-20a2e524-1495-4969-899f-0ab10ea2c846
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171732354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4171732354
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2772080077
Short name T358
Test name
Test status
Simulation time 3923155563 ps
CPU time 13.03 seconds
Started Aug 18 06:05:21 PM PDT 24
Finished Aug 18 06:05:35 PM PDT 24
Peak memory 211460 kb
Host smart-5e016542-c8f9-401d-90e8-0a24bf33664f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772080077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2772080077
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2767568812
Short name T408
Test name
Test status
Simulation time 1595478119 ps
CPU time 63.22 seconds
Started Aug 18 06:05:21 PM PDT 24
Finished Aug 18 06:06:25 PM PDT 24
Peak memory 215480 kb
Host smart-56e9a0e2-6309-445b-8344-e57fb641aecf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767568812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2767568812
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4009430335
Short name T413
Test name
Test status
Simulation time 3096775439 ps
CPU time 13.97 seconds
Started Aug 18 06:05:21 PM PDT 24
Finished Aug 18 06:05:35 PM PDT 24
Peak memory 218872 kb
Host smart-b30e691a-c471-43ed-82c1-469de45dd90c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009430335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4009430335
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.868489121
Short name T406
Test name
Test status
Simulation time 236278931 ps
CPU time 80.07 seconds
Started Aug 18 06:05:22 PM PDT 24
Finished Aug 18 06:06:43 PM PDT 24
Peak memory 214472 kb
Host smart-e80e1eb8-f034-42a8-9be7-26bcf59df80e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868489121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.868489121
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1788021108
Short name T393
Test name
Test status
Simulation time 972432476 ps
CPU time 8.09 seconds
Started Aug 18 06:05:30 PM PDT 24
Finished Aug 18 06:05:39 PM PDT 24
Peak memory 211464 kb
Host smart-43ccafe9-4018-4540-a4b5-05dde1b85a2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788021108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1788021108
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3626987021
Short name T409
Test name
Test status
Simulation time 1051028760 ps
CPU time 10.18 seconds
Started Aug 18 06:05:39 PM PDT 24
Finished Aug 18 06:05:49 PM PDT 24
Peak memory 218148 kb
Host smart-f7e8a26a-1ba9-41f7-ba3b-312df0efed6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626987021 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3626987021
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1551749792
Short name T417
Test name
Test status
Simulation time 249293569 ps
CPU time 9.45 seconds
Started Aug 18 06:05:33 PM PDT 24
Finished Aug 18 06:05:43 PM PDT 24
Peak memory 211476 kb
Host smart-8a9b006f-31bc-4876-81b0-95b52c311d23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551749792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1551749792
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2349229196
Short name T363
Test name
Test status
Simulation time 688278650 ps
CPU time 7.7 seconds
Started Aug 18 06:05:30 PM PDT 24
Finished Aug 18 06:05:38 PM PDT 24
Peak memory 211304 kb
Host smart-a1023965-1dfb-4e6a-accb-adc4e150073d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349229196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2349229196
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.105293850
Short name T387
Test name
Test status
Simulation time 985346448 ps
CPU time 8.99 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:05:40 PM PDT 24
Peak memory 211336 kb
Host smart-7f70dab2-7bf2-4b22-9101-6058e8c05f3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105293850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
105293850
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3337257792
Short name T400
Test name
Test status
Simulation time 3892567296 ps
CPU time 42.56 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:06:14 PM PDT 24
Peak memory 215664 kb
Host smart-cb3adaa7-3adc-4ba7-a796-d45eb578b07c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337257792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3337257792
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1639940094
Short name T109
Test name
Test status
Simulation time 174756385 ps
CPU time 8.1 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:05:39 PM PDT 24
Peak memory 212196 kb
Host smart-94b0b2f5-71f3-4a65-8e1e-d4f07fc15de7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639940094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1639940094
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3081189074
Short name T384
Test name
Test status
Simulation time 251934309 ps
CPU time 14.04 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:05:45 PM PDT 24
Peak memory 219300 kb
Host smart-2ee4af04-e0c7-4ffd-993c-354a95cecb96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081189074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3081189074
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3808449637
Short name T452
Test name
Test status
Simulation time 697740284 ps
CPU time 7.86 seconds
Started Aug 18 06:06:30 PM PDT 24
Finished Aug 18 06:06:38 PM PDT 24
Peak memory 219684 kb
Host smart-f6b9c90a-d4a9-40f4-b9c3-006ee24c82bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808449637 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3808449637
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4279320195
Short name T432
Test name
Test status
Simulation time 325364093 ps
CPU time 7.83 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:06:36 PM PDT 24
Peak memory 211412 kb
Host smart-c4a6ea23-81ce-41dd-93cd-9387109ebfdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279320195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4279320195
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3107844119
Short name T90
Test name
Test status
Simulation time 5285317944 ps
CPU time 36.42 seconds
Started Aug 18 06:06:23 PM PDT 24
Finished Aug 18 06:07:00 PM PDT 24
Peak memory 214596 kb
Host smart-5ca3f087-0799-4e05-94dd-dabc474755fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107844119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3107844119
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.945171131
Short name T394
Test name
Test status
Simulation time 1318171741 ps
CPU time 13.23 seconds
Started Aug 18 06:06:30 PM PDT 24
Finished Aug 18 06:06:43 PM PDT 24
Peak memory 213248 kb
Host smart-fdefce64-9cf4-495e-9991-68274a5657d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945171131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.945171131
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2666517525
Short name T423
Test name
Test status
Simulation time 3518767404 ps
CPU time 14.2 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:06:36 PM PDT 24
Peak memory 218412 kb
Host smart-3eb6ba9b-0694-4e57-913a-517a9b8f49a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666517525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2666517525
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.43018575
Short name T122
Test name
Test status
Simulation time 427068875 ps
CPU time 154.87 seconds
Started Aug 18 06:06:30 PM PDT 24
Finished Aug 18 06:09:05 PM PDT 24
Peak memory 219592 kb
Host smart-66c8b8d8-cfa1-473b-834e-a3f2312e812e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43018575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_int
g_err.43018575
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2519858934
Short name T357
Test name
Test status
Simulation time 515248155 ps
CPU time 9.86 seconds
Started Aug 18 06:06:28 PM PDT 24
Finished Aug 18 06:06:38 PM PDT 24
Peak memory 215696 kb
Host smart-97391821-5c5e-48cf-b874-cd9ab7831066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519858934 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2519858934
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1498805595
Short name T360
Test name
Test status
Simulation time 1291897437 ps
CPU time 9.1 seconds
Started Aug 18 06:06:33 PM PDT 24
Finished Aug 18 06:06:42 PM PDT 24
Peak memory 211800 kb
Host smart-acb6caec-8c8c-4356-b226-0ed5bee41b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498805595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1498805595
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1486410241
Short name T72
Test name
Test status
Simulation time 713809731 ps
CPU time 34.79 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:07:04 PM PDT 24
Peak memory 213504 kb
Host smart-e25d2d2c-edbd-4fdf-bfe2-864eb370436f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486410241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1486410241
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2933144109
Short name T106
Test name
Test status
Simulation time 688842643 ps
CPU time 7.96 seconds
Started Aug 18 06:06:30 PM PDT 24
Finished Aug 18 06:06:38 PM PDT 24
Peak memory 211804 kb
Host smart-c9f9c390-b481-4af5-b7c1-d42122b4c250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933144109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2933144109
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2724002805
Short name T366
Test name
Test status
Simulation time 254946027 ps
CPU time 13.03 seconds
Started Aug 18 06:06:32 PM PDT 24
Finished Aug 18 06:06:45 PM PDT 24
Peak memory 218080 kb
Host smart-6eafee2c-3cd1-4071-8556-24b3dd58b770
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724002805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2724002805
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2169517685
Short name T365
Test name
Test status
Simulation time 540487857 ps
CPU time 10.23 seconds
Started Aug 18 06:06:38 PM PDT 24
Finished Aug 18 06:06:49 PM PDT 24
Peak memory 217488 kb
Host smart-eb05278e-7d99-4c53-957c-1ceb3029918f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169517685 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2169517685
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.82063645
Short name T110
Test name
Test status
Simulation time 993121590 ps
CPU time 9.12 seconds
Started Aug 18 06:06:40 PM PDT 24
Finished Aug 18 06:06:49 PM PDT 24
Peak memory 211928 kb
Host smart-ad58a5b8-d752-4edf-8b01-5c95bab7405d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82063645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.82063645
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1952789839
Short name T418
Test name
Test status
Simulation time 1960307220 ps
CPU time 42 seconds
Started Aug 18 06:06:33 PM PDT 24
Finished Aug 18 06:07:15 PM PDT 24
Peak memory 214488 kb
Host smart-b521cbaa-4b36-427d-a3ab-340a69165a7b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952789839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1952789839
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3919798387
Short name T412
Test name
Test status
Simulation time 660422236 ps
CPU time 7.93 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:06:47 PM PDT 24
Peak memory 212128 kb
Host smart-3b2b470b-3f9a-4057-90c9-305da89266cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919798387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3919798387
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1589427959
Short name T376
Test name
Test status
Simulation time 473665069 ps
CPU time 11.52 seconds
Started Aug 18 06:06:30 PM PDT 24
Finished Aug 18 06:06:42 PM PDT 24
Peak memory 219568 kb
Host smart-374aaf24-d314-49f2-8db3-d1c8488a6a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589427959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1589427959
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2536732900
Short name T410
Test name
Test status
Simulation time 310474706 ps
CPU time 153.5 seconds
Started Aug 18 06:06:28 PM PDT 24
Finished Aug 18 06:09:02 PM PDT 24
Peak memory 215004 kb
Host smart-9f093663-e087-427d-a2ee-994c6421808c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536732900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2536732900
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2327336075
Short name T397
Test name
Test status
Simulation time 266377595 ps
CPU time 10.04 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:06:49 PM PDT 24
Peak memory 218068 kb
Host smart-ebd8883f-1427-48e1-90d8-a6e5190d5437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327336075 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2327336075
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1677264201
Short name T421
Test name
Test status
Simulation time 173126762 ps
CPU time 7.84 seconds
Started Aug 18 06:06:40 PM PDT 24
Finished Aug 18 06:06:48 PM PDT 24
Peak memory 211672 kb
Host smart-ed15e707-8005-4fab-942f-e524c1f85090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677264201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1677264201
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3328790257
Short name T74
Test name
Test status
Simulation time 696266716 ps
CPU time 36.25 seconds
Started Aug 18 06:06:42 PM PDT 24
Finished Aug 18 06:07:18 PM PDT 24
Peak memory 214460 kb
Host smart-5e54dfe2-bbb8-4d73-9f29-572b1058cb31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328790257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3328790257
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.214387042
Short name T395
Test name
Test status
Simulation time 250455291 ps
CPU time 9.19 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:06:49 PM PDT 24
Peak memory 211892 kb
Host smart-4b394cb6-1115-43ea-965c-6c4a74280f8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214387042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.214387042
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3430956782
Short name T429
Test name
Test status
Simulation time 174612741 ps
CPU time 13.03 seconds
Started Aug 18 06:06:37 PM PDT 24
Finished Aug 18 06:06:50 PM PDT 24
Peak memory 218248 kb
Host smart-a1983de1-0019-4db6-bf24-d154755ab87a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430956782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3430956782
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.137520843
Short name T414
Test name
Test status
Simulation time 1504111409 ps
CPU time 151.14 seconds
Started Aug 18 06:06:43 PM PDT 24
Finished Aug 18 06:09:14 PM PDT 24
Peak memory 214872 kb
Host smart-060e996e-2b07-407f-97a3-cca0ddae051b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137520843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.137520843
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3037928334
Short name T375
Test name
Test status
Simulation time 193345389 ps
CPU time 8.62 seconds
Started Aug 18 06:06:49 PM PDT 24
Finished Aug 18 06:06:57 PM PDT 24
Peak memory 217160 kb
Host smart-0f33418e-10c7-499b-bbb9-93c392d7b26f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037928334 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3037928334
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2072888067
Short name T447
Test name
Test status
Simulation time 250520843 ps
CPU time 9.4 seconds
Started Aug 18 06:06:47 PM PDT 24
Finished Aug 18 06:06:56 PM PDT 24
Peak memory 212004 kb
Host smart-a2ccdbf6-4c97-4f79-88ac-a7636751117d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072888067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2072888067
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1090390340
Short name T85
Test name
Test status
Simulation time 5606990791 ps
CPU time 62.24 seconds
Started Aug 18 06:06:47 PM PDT 24
Finished Aug 18 06:07:50 PM PDT 24
Peak memory 216224 kb
Host smart-aba88665-dd4c-4f78-8339-142bdbf96e05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090390340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1090390340
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1156698943
Short name T103
Test name
Test status
Simulation time 516462098 ps
CPU time 9.41 seconds
Started Aug 18 06:06:49 PM PDT 24
Finished Aug 18 06:06:59 PM PDT 24
Peak memory 211940 kb
Host smart-5fefbbfa-5dd6-4280-b640-e06e581f0c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156698943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1156698943
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4113285136
Short name T437
Test name
Test status
Simulation time 177328011 ps
CPU time 12.23 seconds
Started Aug 18 06:06:47 PM PDT 24
Finished Aug 18 06:06:59 PM PDT 24
Peak memory 218196 kb
Host smart-c7f95da0-74d6-4d6a-be40-cf7a20c8a299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113285136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4113285136
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3448651678
Short name T453
Test name
Test status
Simulation time 270821410 ps
CPU time 9.66 seconds
Started Aug 18 06:06:46 PM PDT 24
Finished Aug 18 06:06:56 PM PDT 24
Peak memory 216428 kb
Host smart-94d833fe-58f5-4b7b-907f-4f982f33f572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448651678 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3448651678
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3629724598
Short name T383
Test name
Test status
Simulation time 551717537 ps
CPU time 7.82 seconds
Started Aug 18 06:06:48 PM PDT 24
Finished Aug 18 06:06:56 PM PDT 24
Peak memory 211704 kb
Host smart-ff9fc155-9ff7-4a39-a8d5-2b779716bf99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629724598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3629724598
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1600514791
Short name T440
Test name
Test status
Simulation time 174645368 ps
CPU time 7.86 seconds
Started Aug 18 06:06:50 PM PDT 24
Finished Aug 18 06:06:58 PM PDT 24
Peak memory 212004 kb
Host smart-26c69213-0c8a-4c96-bff3-28f66f4ece05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600514791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1600514791
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2337481774
Short name T402
Test name
Test status
Simulation time 984703028 ps
CPU time 18.1 seconds
Started Aug 18 06:06:50 PM PDT 24
Finished Aug 18 06:07:08 PM PDT 24
Peak memory 219668 kb
Host smart-989248e2-92b4-446a-9bd0-5ea94c250175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337481774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2337481774
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2713646100
Short name T128
Test name
Test status
Simulation time 2462141312 ps
CPU time 78.9 seconds
Started Aug 18 06:06:50 PM PDT 24
Finished Aug 18 06:08:09 PM PDT 24
Peak memory 214544 kb
Host smart-a78e7721-bed5-43bf-a04c-d03cf7e2a64b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713646100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2713646100
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.626785836
Short name T367
Test name
Test status
Simulation time 258163948 ps
CPU time 10.48 seconds
Started Aug 18 06:06:58 PM PDT 24
Finished Aug 18 06:07:09 PM PDT 24
Peak memory 218000 kb
Host smart-10132560-4338-45b2-8d21-e2d616662672
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626785836 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.626785836
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2198519262
Short name T369
Test name
Test status
Simulation time 2055443281 ps
CPU time 9.33 seconds
Started Aug 18 06:06:57 PM PDT 24
Finished Aug 18 06:07:06 PM PDT 24
Peak memory 211604 kb
Host smart-3f61dc6f-7451-4e35-901b-9ded32457435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198519262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2198519262
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1100071090
Short name T451
Test name
Test status
Simulation time 12857725588 ps
CPU time 54.24 seconds
Started Aug 18 06:06:51 PM PDT 24
Finished Aug 18 06:07:46 PM PDT 24
Peak memory 215788 kb
Host smart-cb7ef29e-6181-4d8a-8468-9d4fcb83ea3a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100071090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1100071090
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1857541245
Short name T104
Test name
Test status
Simulation time 340247001 ps
CPU time 7.9 seconds
Started Aug 18 06:06:56 PM PDT 24
Finished Aug 18 06:07:04 PM PDT 24
Peak memory 212100 kb
Host smart-ff79f340-f2ab-4a30-aec9-1bc004f288d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857541245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1857541245
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2516014175
Short name T359
Test name
Test status
Simulation time 255909017 ps
CPU time 11.33 seconds
Started Aug 18 06:06:58 PM PDT 24
Finished Aug 18 06:07:10 PM PDT 24
Peak memory 218264 kb
Host smart-9a0835f6-2590-48a6-a8b5-dbff531a50a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516014175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2516014175
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1232518607
Short name T116
Test name
Test status
Simulation time 2822913300 ps
CPU time 79.93 seconds
Started Aug 18 06:06:58 PM PDT 24
Finished Aug 18 06:08:18 PM PDT 24
Peak memory 213400 kb
Host smart-6857f350-8f52-4c41-b2d9-018146d8b1a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232518607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1232518607
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3669163981
Short name T420
Test name
Test status
Simulation time 3212162646 ps
CPU time 10.17 seconds
Started Aug 18 06:07:07 PM PDT 24
Finished Aug 18 06:07:17 PM PDT 24
Peak memory 219752 kb
Host smart-1fb27c82-65a8-4c50-ad1a-369c075d719f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669163981 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3669163981
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1372692894
Short name T88
Test name
Test status
Simulation time 174651890 ps
CPU time 7.93 seconds
Started Aug 18 06:06:55 PM PDT 24
Finished Aug 18 06:07:03 PM PDT 24
Peak memory 211412 kb
Host smart-f4a45628-48da-44c5-a33c-dee8ad5a23dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372692894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1372692894
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1808996557
Short name T386
Test name
Test status
Simulation time 5345890420 ps
CPU time 42.2 seconds
Started Aug 18 06:06:57 PM PDT 24
Finished Aug 18 06:07:40 PM PDT 24
Peak memory 214936 kb
Host smart-09201a2b-e9c5-4ee4-9f8c-0f6c860d65e7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808996557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1808996557
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1753155972
Short name T448
Test name
Test status
Simulation time 497504693 ps
CPU time 9.45 seconds
Started Aug 18 06:07:00 PM PDT 24
Finished Aug 18 06:07:10 PM PDT 24
Peak memory 212212 kb
Host smart-a86b574b-1fc7-4b53-afaf-1d5038086870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753155972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1753155972
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3703523561
Short name T398
Test name
Test status
Simulation time 1646943615 ps
CPU time 10.64 seconds
Started Aug 18 06:06:56 PM PDT 24
Finished Aug 18 06:07:07 PM PDT 24
Peak memory 217928 kb
Host smart-9288ad70-bee8-404d-b93d-fe83e6125357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703523561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3703523561
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1177285259
Short name T126
Test name
Test status
Simulation time 356622358 ps
CPU time 152 seconds
Started Aug 18 06:06:58 PM PDT 24
Finished Aug 18 06:09:30 PM PDT 24
Peak memory 219620 kb
Host smart-b678e8b4-b0c0-40b7-9878-61b028ebe672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177285259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1177285259
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1611298906
Short name T368
Test name
Test status
Simulation time 1362311259 ps
CPU time 10.56 seconds
Started Aug 18 06:07:05 PM PDT 24
Finished Aug 18 06:07:16 PM PDT 24
Peak memory 218164 kb
Host smart-0f5f7613-18df-4c06-ac53-019e638ffbbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611298906 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1611298906
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.688035895
Short name T84
Test name
Test status
Simulation time 4101210996 ps
CPU time 9.54 seconds
Started Aug 18 06:07:05 PM PDT 24
Finished Aug 18 06:07:15 PM PDT 24
Peak memory 211572 kb
Host smart-8eb84f67-1f5d-4219-844e-f24f8c1f4194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688035895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.688035895
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1246609361
Short name T87
Test name
Test status
Simulation time 5735142882 ps
CPU time 53.89 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:08:00 PM PDT 24
Peak memory 215640 kb
Host smart-ce193330-1695-49b9-b22f-e33efa425437
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246609361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1246609361
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1566068170
Short name T444
Test name
Test status
Simulation time 576487062 ps
CPU time 9.2 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:07:15 PM PDT 24
Peak memory 211864 kb
Host smart-a6c63ed8-f667-47b0-9a95-4d5202bb8e8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566068170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1566068170
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1397017911
Short name T424
Test name
Test status
Simulation time 338330154 ps
CPU time 11.27 seconds
Started Aug 18 06:07:07 PM PDT 24
Finished Aug 18 06:07:19 PM PDT 24
Peak memory 218096 kb
Host smart-d828b68b-10d3-4bcc-ae69-349259bceae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397017911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1397017911
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.183825885
Short name T120
Test name
Test status
Simulation time 705034404 ps
CPU time 82.42 seconds
Started Aug 18 06:07:05 PM PDT 24
Finished Aug 18 06:08:27 PM PDT 24
Peak memory 214348 kb
Host smart-c1f41e2c-95ca-43ff-bd18-b0dc791a0bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183825885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.183825885
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.486486619
Short name T439
Test name
Test status
Simulation time 1081372012 ps
CPU time 9.95 seconds
Started Aug 18 06:07:15 PM PDT 24
Finished Aug 18 06:07:25 PM PDT 24
Peak memory 217464 kb
Host smart-f6fe21ea-b04f-4641-b5fc-aab24c0b6e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486486619 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.486486619
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.783526497
Short name T378
Test name
Test status
Simulation time 722569739 ps
CPU time 7.92 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:07:14 PM PDT 24
Peak memory 211904 kb
Host smart-394d8ee1-d041-467a-aece-87933bef2362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783526497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.783526497
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.446606677
Short name T430
Test name
Test status
Simulation time 1545216298 ps
CPU time 62.42 seconds
Started Aug 18 06:07:05 PM PDT 24
Finished Aug 18 06:08:07 PM PDT 24
Peak memory 215444 kb
Host smart-9dab0ae8-aa74-438d-a290-9341060af6d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446606677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.446606677
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.811696892
Short name T404
Test name
Test status
Simulation time 503000614 ps
CPU time 13.69 seconds
Started Aug 18 06:07:17 PM PDT 24
Finished Aug 18 06:07:31 PM PDT 24
Peak memory 213332 kb
Host smart-24562623-e746-4368-ad34-5a6d9431def1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811696892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.811696892
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1020320559
Short name T364
Test name
Test status
Simulation time 1030315717 ps
CPU time 13.52 seconds
Started Aug 18 06:07:07 PM PDT 24
Finished Aug 18 06:07:20 PM PDT 24
Peak memory 218200 kb
Host smart-8426dd81-9b42-4bcd-ac6a-e821d9d36b90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020320559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1020320559
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1218338939
Short name T125
Test name
Test status
Simulation time 594813129 ps
CPU time 151.4 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:09:37 PM PDT 24
Peak memory 219572 kb
Host smart-d0b7dbe0-60cc-4e77-9bcf-bd4242b6b70c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218338939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1218338939
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1265367547
Short name T70
Test name
Test status
Simulation time 1499313549 ps
CPU time 7.81 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:05:57 PM PDT 24
Peak memory 211368 kb
Host smart-43b3dd22-0c0a-4d4c-8cc1-c807a3ba3f8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265367547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1265367547
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4170237091
Short name T65
Test name
Test status
Simulation time 726268473 ps
CPU time 9.32 seconds
Started Aug 18 06:05:38 PM PDT 24
Finished Aug 18 06:05:48 PM PDT 24
Peak memory 211608 kb
Host smart-80c11f10-5727-418b-8633-156300d983ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170237091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4170237091
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.891990952
Short name T73
Test name
Test status
Simulation time 180184555 ps
CPU time 14.54 seconds
Started Aug 18 06:05:37 PM PDT 24
Finished Aug 18 06:05:52 PM PDT 24
Peak memory 212396 kb
Host smart-832fd1aa-9dca-4798-b8b5-6d9cefec3cdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891990952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.891990952
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2031185981
Short name T379
Test name
Test status
Simulation time 529137495 ps
CPU time 10.05 seconds
Started Aug 18 06:05:47 PM PDT 24
Finished Aug 18 06:05:57 PM PDT 24
Peak memory 219676 kb
Host smart-c354e88f-31db-4035-9823-8e55679a37f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031185981 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2031185981
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3903762381
Short name T392
Test name
Test status
Simulation time 257828945 ps
CPU time 9.59 seconds
Started Aug 18 06:05:39 PM PDT 24
Finished Aug 18 06:05:49 PM PDT 24
Peak memory 211652 kb
Host smart-4e8bc773-3d0e-4bbd-b4fd-cef8c82a7109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903762381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3903762381
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2942634931
Short name T389
Test name
Test status
Simulation time 687894331 ps
CPU time 7.71 seconds
Started Aug 18 06:05:39 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 211304 kb
Host smart-fb2e2271-5e1e-4418-84d5-2c9ac55abc78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942634931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2942634931
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1370987789
Short name T361
Test name
Test status
Simulation time 920747619 ps
CPU time 7.58 seconds
Started Aug 18 06:05:39 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 211360 kb
Host smart-e4b0683a-c222-43d3-abe0-5fd2503e1056
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370987789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1370987789
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3737036279
Short name T66
Test name
Test status
Simulation time 1333144415 ps
CPU time 35.82 seconds
Started Aug 18 06:05:40 PM PDT 24
Finished Aug 18 06:06:16 PM PDT 24
Peak memory 213432 kb
Host smart-2a6ea3bd-8290-4d6a-827a-8f89972eeb28
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737036279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3737036279
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.905003795
Short name T436
Test name
Test status
Simulation time 254537771 ps
CPU time 9.44 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:05:58 PM PDT 24
Peak memory 212148 kb
Host smart-386d34bc-723b-4c74-9189-1bf4818d31a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905003795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.905003795
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.807044235
Short name T438
Test name
Test status
Simulation time 495441432 ps
CPU time 13.35 seconds
Started Aug 18 06:05:40 PM PDT 24
Finished Aug 18 06:05:54 PM PDT 24
Peak memory 218156 kb
Host smart-8d2d21b6-cc84-4674-b548-8deae7e80562
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807044235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.807044235
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1463989650
Short name T121
Test name
Test status
Simulation time 1245966229 ps
CPU time 81.06 seconds
Started Aug 18 06:05:40 PM PDT 24
Finished Aug 18 06:07:01 PM PDT 24
Peak memory 213036 kb
Host smart-fed76f70-73db-46a2-9963-f7d5d666c1be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463989650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1463989650
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.323302790
Short name T76
Test name
Test status
Simulation time 573497774 ps
CPU time 7.91 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:05:57 PM PDT 24
Peak memory 211388 kb
Host smart-00b258ea-4842-47a0-8599-9f071dee1dc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323302790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.323302790
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2989030162
Short name T435
Test name
Test status
Simulation time 1763830359 ps
CPU time 9.74 seconds
Started Aug 18 06:05:53 PM PDT 24
Finished Aug 18 06:06:03 PM PDT 24
Peak memory 211824 kb
Host smart-0547b84f-2c6c-4014-960c-fdd07b4e616c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989030162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2989030162
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.720598294
Short name T416
Test name
Test status
Simulation time 3597404820 ps
CPU time 16.45 seconds
Started Aug 18 06:05:48 PM PDT 24
Finished Aug 18 06:06:05 PM PDT 24
Peak memory 212920 kb
Host smart-7b3287c4-3bbd-42a7-af68-4bd812f708a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720598294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.720598294
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.876585427
Short name T372
Test name
Test status
Simulation time 4206680010 ps
CPU time 14.79 seconds
Started Aug 18 06:05:57 PM PDT 24
Finished Aug 18 06:06:12 PM PDT 24
Peak memory 219760 kb
Host smart-6d65e872-cda7-41b2-b836-2d8107060f60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876585427 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.876585427
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2675976675
Short name T75
Test name
Test status
Simulation time 262157143 ps
CPU time 9.19 seconds
Started Aug 18 06:05:50 PM PDT 24
Finished Aug 18 06:05:59 PM PDT 24
Peak memory 211472 kb
Host smart-b5b57ca2-50b9-44b0-9fcf-e7bd603c4a4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675976675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2675976675
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.706802844
Short name T388
Test name
Test status
Simulation time 182520685 ps
CPU time 7.77 seconds
Started Aug 18 06:05:51 PM PDT 24
Finished Aug 18 06:05:59 PM PDT 24
Peak memory 211316 kb
Host smart-71bae73a-c5a6-40e3-9683-bb7e8928f07d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706802844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.706802844
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3422506078
Short name T370
Test name
Test status
Simulation time 1651423687 ps
CPU time 9.27 seconds
Started Aug 18 06:05:51 PM PDT 24
Finished Aug 18 06:06:00 PM PDT 24
Peak memory 211392 kb
Host smart-8b6cff8e-60c9-4899-b658-59b4cdf925af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422506078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3422506078
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2902598619
Short name T401
Test name
Test status
Simulation time 1625355694 ps
CPU time 62.57 seconds
Started Aug 18 06:05:48 PM PDT 24
Finished Aug 18 06:06:50 PM PDT 24
Peak memory 214524 kb
Host smart-41d686c1-eeca-4237-822b-cea67d691ab2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902598619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2902598619
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3942900653
Short name T391
Test name
Test status
Simulation time 517771237 ps
CPU time 9.42 seconds
Started Aug 18 06:05:59 PM PDT 24
Finished Aug 18 06:06:08 PM PDT 24
Peak memory 211888 kb
Host smart-5cb00916-1856-4fe0-ab0f-42753c0a1284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942900653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3942900653
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.158170232
Short name T445
Test name
Test status
Simulation time 506937031 ps
CPU time 14.62 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:06:04 PM PDT 24
Peak memory 218512 kb
Host smart-71429775-2986-425e-8c13-85c693f7f742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158170232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.158170232
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.492338804
Short name T119
Test name
Test status
Simulation time 250190408 ps
CPU time 79.32 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:07:08 PM PDT 24
Peak memory 213604 kb
Host smart-ded2fa94-4248-4747-b818-3a89c4423eff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492338804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.492338804
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1632363224
Short name T111
Test name
Test status
Simulation time 167723146 ps
CPU time 7.85 seconds
Started Aug 18 06:06:08 PM PDT 24
Finished Aug 18 06:06:16 PM PDT 24
Peak memory 211536 kb
Host smart-7f639a2c-ebb9-4fdb-b6cc-59c4374af1de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632363224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1632363224
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2220415734
Short name T419
Test name
Test status
Simulation time 347216687 ps
CPU time 8.18 seconds
Started Aug 18 06:06:07 PM PDT 24
Finished Aug 18 06:06:15 PM PDT 24
Peak memory 211456 kb
Host smart-13a3c832-813c-4539-a329-41b5d37b79b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220415734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2220415734
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1176662300
Short name T380
Test name
Test status
Simulation time 325844018 ps
CPU time 12.69 seconds
Started Aug 18 06:06:06 PM PDT 24
Finished Aug 18 06:06:19 PM PDT 24
Peak memory 211344 kb
Host smart-78597a26-7d08-4b78-98d0-56657cfb4eec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176662300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1176662300
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4158139006
Short name T382
Test name
Test status
Simulation time 721397156 ps
CPU time 8.7 seconds
Started Aug 18 06:06:07 PM PDT 24
Finished Aug 18 06:06:16 PM PDT 24
Peak memory 218444 kb
Host smart-6f31b04d-ead4-477e-adde-e2fd179a8388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158139006 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4158139006
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1952341248
Short name T446
Test name
Test status
Simulation time 920274586 ps
CPU time 7.85 seconds
Started Aug 18 06:06:05 PM PDT 24
Finished Aug 18 06:06:13 PM PDT 24
Peak memory 211616 kb
Host smart-98d51a24-a402-4398-bd03-bcb243fcc5a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952341248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1952341248
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1825359171
Short name T374
Test name
Test status
Simulation time 250855174 ps
CPU time 9.26 seconds
Started Aug 18 06:05:57 PM PDT 24
Finished Aug 18 06:06:06 PM PDT 24
Peak memory 211340 kb
Host smart-691d51ba-7958-483e-a7fd-9cb0419d0901
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825359171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1825359171
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.73275648
Short name T407
Test name
Test status
Simulation time 884339660 ps
CPU time 9.3 seconds
Started Aug 18 06:05:59 PM PDT 24
Finished Aug 18 06:06:08 PM PDT 24
Peak memory 211504 kb
Host smart-6d9f769c-2122-4879-8fe4-ff96214af156
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73275648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.73275648
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1674185849
Short name T433
Test name
Test status
Simulation time 3623920438 ps
CPU time 41.06 seconds
Started Aug 18 06:05:55 PM PDT 24
Finished Aug 18 06:06:36 PM PDT 24
Peak memory 214584 kb
Host smart-38f292a4-8041-4a50-b108-c15ae7f28b34
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674185849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1674185849
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3158434057
Short name T108
Test name
Test status
Simulation time 346151172 ps
CPU time 8.01 seconds
Started Aug 18 06:06:07 PM PDT 24
Finished Aug 18 06:06:15 PM PDT 24
Peak memory 212080 kb
Host smart-f88d0886-5c42-40cb-8287-28a8b3f77829
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158434057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3158434057
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.501068187
Short name T422
Test name
Test status
Simulation time 826900750 ps
CPU time 11.01 seconds
Started Aug 18 06:05:55 PM PDT 24
Finished Aug 18 06:06:06 PM PDT 24
Peak memory 218172 kb
Host smart-7f6b3fae-0df6-4928-9b92-8d7ce5a59d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501068187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.501068187
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3174256468
Short name T129
Test name
Test status
Simulation time 1107630105 ps
CPU time 80.29 seconds
Started Aug 18 06:05:59 PM PDT 24
Finished Aug 18 06:07:19 PM PDT 24
Peak memory 214364 kb
Host smart-3219e688-5b54-4259-a8cc-1106e3f03497
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174256468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3174256468
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3916199758
Short name T371
Test name
Test status
Simulation time 269994548 ps
CPU time 9.49 seconds
Started Aug 18 06:06:13 PM PDT 24
Finished Aug 18 06:06:22 PM PDT 24
Peak memory 219572 kb
Host smart-8302b40b-7a93-438c-930d-f0c149166f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916199758 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3916199758
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1094740185
Short name T105
Test name
Test status
Simulation time 2047632913 ps
CPU time 13.17 seconds
Started Aug 18 06:06:05 PM PDT 24
Finished Aug 18 06:06:18 PM PDT 24
Peak memory 212184 kb
Host smart-a7ae1dfd-69d4-4bf0-8e88-308cc23a7c64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094740185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1094740185
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2687421697
Short name T396
Test name
Test status
Simulation time 724031033 ps
CPU time 36.32 seconds
Started Aug 18 06:06:06 PM PDT 24
Finished Aug 18 06:06:43 PM PDT 24
Peak memory 214536 kb
Host smart-947f8cd8-c4ac-41d2-8f20-66733a0181f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687421697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2687421697
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.336309077
Short name T399
Test name
Test status
Simulation time 254127059 ps
CPU time 9.47 seconds
Started Aug 18 06:06:14 PM PDT 24
Finished Aug 18 06:06:23 PM PDT 24
Peak memory 212032 kb
Host smart-829ea414-13d8-439a-9ab1-e1511d546ca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336309077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.336309077
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1873813902
Short name T441
Test name
Test status
Simulation time 279858078 ps
CPU time 14.03 seconds
Started Aug 18 06:06:04 PM PDT 24
Finished Aug 18 06:06:18 PM PDT 24
Peak memory 218360 kb
Host smart-33bf4a2f-26f4-4925-8828-73b98e9d5a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873813902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1873813902
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3507121882
Short name T117
Test name
Test status
Simulation time 457255300 ps
CPU time 79.7 seconds
Started Aug 18 06:06:05 PM PDT 24
Finished Aug 18 06:07:25 PM PDT 24
Peak memory 214404 kb
Host smart-d4c3f495-f2c0-4475-9d98-b5ad5edf895d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507121882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3507121882
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3790811033
Short name T362
Test name
Test status
Simulation time 1082405208 ps
CPU time 10.29 seconds
Started Aug 18 06:06:13 PM PDT 24
Finished Aug 18 06:06:23 PM PDT 24
Peak memory 217432 kb
Host smart-94fc6247-e6ca-4489-a664-2022c12071cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790811033 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3790811033
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1149039801
Short name T373
Test name
Test status
Simulation time 3528594908 ps
CPU time 9.28 seconds
Started Aug 18 06:06:14 PM PDT 24
Finished Aug 18 06:06:23 PM PDT 24
Peak memory 211712 kb
Host smart-dcb2a203-7dfe-4182-99b4-1beee8ff3d4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149039801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1149039801
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2751267946
Short name T92
Test name
Test status
Simulation time 16947101991 ps
CPU time 42.41 seconds
Started Aug 18 06:06:13 PM PDT 24
Finished Aug 18 06:06:56 PM PDT 24
Peak memory 214108 kb
Host smart-6164f64b-e8da-4648-8061-05b4b772c9b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751267946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2751267946
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4268856080
Short name T427
Test name
Test status
Simulation time 603739185 ps
CPU time 11.58 seconds
Started Aug 18 06:06:12 PM PDT 24
Finished Aug 18 06:06:24 PM PDT 24
Peak memory 211932 kb
Host smart-f776455f-bc30-4ee9-b180-06e273e2bf36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268856080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4268856080
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4278881183
Short name T426
Test name
Test status
Simulation time 279823881 ps
CPU time 12.44 seconds
Started Aug 18 06:06:13 PM PDT 24
Finished Aug 18 06:06:26 PM PDT 24
Peak memory 218064 kb
Host smart-5ac2b367-3e03-4c44-a9dd-060e0f3cd268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278881183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4278881183
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.379721415
Short name T123
Test name
Test status
Simulation time 937460531 ps
CPU time 81.36 seconds
Started Aug 18 06:06:14 PM PDT 24
Finished Aug 18 06:07:36 PM PDT 24
Peak memory 213392 kb
Host smart-492120b2-8dfd-454d-a857-f8def3f05e65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379721415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.379721415
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1864304143
Short name T411
Test name
Test status
Simulation time 517516930 ps
CPU time 9.28 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:06:31 PM PDT 24
Peak memory 214100 kb
Host smart-b1b7085a-bc12-48a1-aaaa-555a9233b92f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864304143 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1864304143
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3770590323
Short name T405
Test name
Test status
Simulation time 2063982128 ps
CPU time 9.3 seconds
Started Aug 18 06:06:17 PM PDT 24
Finished Aug 18 06:06:26 PM PDT 24
Peak memory 211712 kb
Host smart-7cdcc68f-575b-4a48-82b9-e3484ba86d85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770590323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3770590323
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1929546772
Short name T89
Test name
Test status
Simulation time 2860725998 ps
CPU time 35.22 seconds
Started Aug 18 06:06:13 PM PDT 24
Finished Aug 18 06:06:49 PM PDT 24
Peak memory 215664 kb
Host smart-10c64f33-c1fb-4f72-aa29-fc5dae2b623e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929546772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1929546772
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4260890574
Short name T415
Test name
Test status
Simulation time 945297516 ps
CPU time 13.08 seconds
Started Aug 18 06:06:23 PM PDT 24
Finished Aug 18 06:06:36 PM PDT 24
Peak memory 213212 kb
Host smart-8be72b27-e2dd-4ec4-aa44-5fc5ef1b030c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260890574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.4260890574
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2265709309
Short name T450
Test name
Test status
Simulation time 332088331 ps
CPU time 11.19 seconds
Started Aug 18 06:06:14 PM PDT 24
Finished Aug 18 06:06:25 PM PDT 24
Peak memory 218144 kb
Host smart-96a2abf5-fb80-4c64-8275-d120c62ad358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265709309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2265709309
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3325118843
Short name T403
Test name
Test status
Simulation time 183616126 ps
CPU time 9.88 seconds
Started Aug 18 06:06:23 PM PDT 24
Finished Aug 18 06:06:33 PM PDT 24
Peak memory 218500 kb
Host smart-ef177e51-3a45-448f-867b-3db3d9c6a61a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325118843 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3325118843
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2872517183
Short name T377
Test name
Test status
Simulation time 250877480 ps
CPU time 9.25 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:06:30 PM PDT 24
Peak memory 211428 kb
Host smart-d96ddeb2-ea35-4251-836d-08a6fc617b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872517183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2872517183
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.264561300
Short name T428
Test name
Test status
Simulation time 2076289033 ps
CPU time 42.55 seconds
Started Aug 18 06:06:20 PM PDT 24
Finished Aug 18 06:07:03 PM PDT 24
Peak memory 214576 kb
Host smart-d2d0eb04-84d2-4a51-99d3-6292d606b75c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264561300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.264561300
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.932923809
Short name T449
Test name
Test status
Simulation time 175130103 ps
CPU time 8.04 seconds
Started Aug 18 06:06:23 PM PDT 24
Finished Aug 18 06:06:31 PM PDT 24
Peak memory 212100 kb
Host smart-fa8b8f13-7406-48eb-a960-73a27e5223b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932923809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.932923809
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2447543729
Short name T431
Test name
Test status
Simulation time 169920252 ps
CPU time 10.84 seconds
Started Aug 18 06:06:23 PM PDT 24
Finished Aug 18 06:06:34 PM PDT 24
Peak memory 218024 kb
Host smart-38b258de-b13d-45db-9519-437ec5da9938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447543729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2447543729
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4085775697
Short name T63
Test name
Test status
Simulation time 601516458 ps
CPU time 80.24 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:07:43 PM PDT 24
Peak memory 214516 kb
Host smart-09746f58-1230-47d4-ab56-d0613364a1ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085775697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4085775697
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2376155616
Short name T390
Test name
Test status
Simulation time 945448124 ps
CPU time 10.52 seconds
Started Aug 18 06:06:23 PM PDT 24
Finished Aug 18 06:06:33 PM PDT 24
Peak memory 218520 kb
Host smart-1243a46c-0b92-45dd-bc59-f13a8c2714fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376155616 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2376155616
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1296316620
Short name T71
Test name
Test status
Simulation time 515102424 ps
CPU time 9.18 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:06:30 PM PDT 24
Peak memory 211912 kb
Host smart-e740a036-18b7-4f95-963e-27fd8477ec12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296316620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1296316620
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2913060705
Short name T86
Test name
Test status
Simulation time 6115119014 ps
CPU time 63.42 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:07:26 PM PDT 24
Peak memory 216668 kb
Host smart-8ebb4554-db20-4bc4-9afc-056708b91a05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913060705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2913060705
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3506381075
Short name T107
Test name
Test status
Simulation time 1121450486 ps
CPU time 9.34 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:06:32 PM PDT 24
Peak memory 212324 kb
Host smart-83546e46-ed85-41a5-a1e0-5c79f15c9751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506381075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3506381075
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.830559456
Short name T381
Test name
Test status
Simulation time 660756121 ps
CPU time 11.09 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:06:33 PM PDT 24
Peak memory 216944 kb
Host smart-d5e7abaf-5bfe-4671-a0e1-8b805e72e3b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830559456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.830559456
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1213200495
Short name T127
Test name
Test status
Simulation time 336742382 ps
CPU time 153.04 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:08:55 PM PDT 24
Peak memory 214844 kb
Host smart-1b05cd17-684d-4da5-8548-2f05913e202b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213200495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1213200495
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3268273961
Short name T219
Test name
Test status
Simulation time 174221528 ps
CPU time 7.81 seconds
Started Aug 18 05:22:58 PM PDT 24
Finished Aug 18 05:23:06 PM PDT 24
Peak memory 218240 kb
Host smart-c7396e72-6d04-4f65-9ae2-d2bc42fc68f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268273961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3268273961
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1746100184
Short name T255
Test name
Test status
Simulation time 23831117057 ps
CPU time 288.62 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:27:48 PM PDT 24
Peak memory 219048 kb
Host smart-957ddc8d-5d54-41a4-8d12-036697fb2129
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746100184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1746100184
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2740186811
Short name T322
Test name
Test status
Simulation time 2059830317 ps
CPU time 21.31 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:23:21 PM PDT 24
Peak memory 218768 kb
Host smart-d54b5006-e9e2-496a-bf6a-4776d6b0e131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740186811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2740186811
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2171561444
Short name T271
Test name
Test status
Simulation time 267505232 ps
CPU time 11.76 seconds
Started Aug 18 05:22:58 PM PDT 24
Finished Aug 18 05:23:10 PM PDT 24
Peak memory 218528 kb
Host smart-24d02453-ce62-4121-b213-dfe4c4f74fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171561444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2171561444
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3041859352
Short name T27
Test name
Test status
Simulation time 233939369 ps
CPU time 116.07 seconds
Started Aug 18 05:22:57 PM PDT 24
Finished Aug 18 05:24:53 PM PDT 24
Peak memory 238908 kb
Host smart-c5f411d0-2681-4716-bbbe-21c19313430f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041859352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3041859352
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3804884622
Short name T207
Test name
Test status
Simulation time 258154826 ps
CPU time 11.71 seconds
Started Aug 18 05:22:56 PM PDT 24
Finished Aug 18 05:23:08 PM PDT 24
Peak memory 218440 kb
Host smart-0242f791-2598-476b-a868-d06d39f93c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804884622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3804884622
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1468785959
Short name T80
Test name
Test status
Simulation time 348121985 ps
CPU time 23.58 seconds
Started Aug 18 05:22:56 PM PDT 24
Finished Aug 18 05:23:20 PM PDT 24
Peak memory 219064 kb
Host smart-8018016f-51c4-441e-85a1-c084019da8a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468785959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1468785959
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.933400258
Short name T5
Test name
Test status
Simulation time 14310093771 ps
CPU time 135.29 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:25:14 PM PDT 24
Peak memory 227976 kb
Host smart-ae7d8314-3345-4a20-ab61-d97b2991a9dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933400258 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.933400258
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3662580437
Short name T46
Test name
Test status
Simulation time 177987212 ps
CPU time 8.03 seconds
Started Aug 18 05:23:01 PM PDT 24
Finished Aug 18 05:23:09 PM PDT 24
Peak memory 218376 kb
Host smart-324a2107-a8c3-4677-b066-f2535a768a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662580437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3662580437
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2498871074
Short name T328
Test name
Test status
Simulation time 6957563756 ps
CPU time 245.29 seconds
Started Aug 18 05:22:58 PM PDT 24
Finished Aug 18 05:27:03 PM PDT 24
Peak memory 224608 kb
Host smart-51e2539a-9d40-45a0-9415-49cb3c06ba58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498871074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2498871074
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.488682245
Short name T180
Test name
Test status
Simulation time 740057942 ps
CPU time 21.76 seconds
Started Aug 18 05:23:01 PM PDT 24
Finished Aug 18 05:23:23 PM PDT 24
Peak memory 218584 kb
Host smart-70b25d0a-41be-4e95-a357-2ab4f86d31fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488682245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.488682245
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.480879984
Short name T168
Test name
Test status
Simulation time 999546362 ps
CPU time 15.16 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:23:14 PM PDT 24
Peak memory 219132 kb
Host smart-6bf8c78c-1b04-41f6-b5b9-083f5931ff9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480879984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.480879984
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2691641587
Short name T22
Test name
Test status
Simulation time 491256758 ps
CPU time 230.39 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:26:50 PM PDT 24
Peak memory 238372 kb
Host smart-f6f86cfb-f172-4c74-b30d-07b72848fdc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691641587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2691641587
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3131631666
Short name T35
Test name
Test status
Simulation time 9058329376 ps
CPU time 15.64 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:23:15 PM PDT 24
Peak memory 219180 kb
Host smart-00721bfb-aa5f-49bd-bcc4-8c4909bbc836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131631666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3131631666
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.37504105
Short name T327
Test name
Test status
Simulation time 847174074 ps
CPU time 41.57 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:23:41 PM PDT 24
Peak memory 219100 kb
Host smart-67051644-24a7-4a20-a33e-811b4066a3ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37504105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.rom_ctrl_stress_all.37504105
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.780759972
Short name T299
Test name
Test status
Simulation time 8137865804 ps
CPU time 168.8 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:25:48 PM PDT 24
Peak memory 235612 kb
Host smart-2839e540-90cb-434f-8a1c-2af303d8c241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780759972 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.780759972
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1793021616
Short name T24
Test name
Test status
Simulation time 528898801 ps
CPU time 9.52 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:23:28 PM PDT 24
Peak memory 218276 kb
Host smart-d3c86437-e3e9-4877-9531-7fe4102c9cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793021616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1793021616
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2259841438
Short name T275
Test name
Test status
Simulation time 12018541666 ps
CPU time 214.51 seconds
Started Aug 18 05:23:21 PM PDT 24
Finished Aug 18 05:26:55 PM PDT 24
Peak memory 217776 kb
Host smart-8bedc215-f288-4533-89b8-62195f2723e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259841438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2259841438
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.243320246
Short name T175
Test name
Test status
Simulation time 497742562 ps
CPU time 21.14 seconds
Started Aug 18 05:23:22 PM PDT 24
Finished Aug 18 05:23:43 PM PDT 24
Peak memory 218592 kb
Host smart-27a47265-549f-4661-813f-a74d49163e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243320246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.243320246
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2489691419
Short name T115
Test name
Test status
Simulation time 802610412 ps
CPU time 10.11 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:31 PM PDT 24
Peak memory 218804 kb
Host smart-9483a239-b06c-46b6-a0c3-61490c4d0f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489691419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2489691419
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3862473237
Short name T141
Test name
Test status
Simulation time 1048992249 ps
CPU time 21.96 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:23:41 PM PDT 24
Peak memory 218976 kb
Host smart-4cef480a-9914-472c-8420-1f0ad9327901
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862473237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3862473237
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1777213098
Short name T259
Test name
Test status
Simulation time 44561693436 ps
CPU time 184.55 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 235636 kb
Host smart-68cb4a56-593e-40c6-b14c-280768978f73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777213098 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1777213098
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4280314497
Short name T198
Test name
Test status
Simulation time 1306765081 ps
CPU time 9.52 seconds
Started Aug 18 05:23:22 PM PDT 24
Finished Aug 18 05:23:31 PM PDT 24
Peak memory 218324 kb
Host smart-97b0d9b8-31da-4efc-b370-e1880a4b4494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280314497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4280314497
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2670556719
Short name T99
Test name
Test status
Simulation time 8598881391 ps
CPU time 236.41 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:27:17 PM PDT 24
Peak memory 219476 kb
Host smart-c0161385-f073-4a0e-9162-faad8b0b52d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670556719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2670556719
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1899623938
Short name T183
Test name
Test status
Simulation time 579604723 ps
CPU time 21.15 seconds
Started Aug 18 05:23:22 PM PDT 24
Finished Aug 18 05:23:43 PM PDT 24
Peak memory 218788 kb
Host smart-e7b68dc5-bd04-47a2-bc75-2e2cbf751f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899623938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1899623938
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.733185740
Short name T294
Test name
Test status
Simulation time 525397421 ps
CPU time 11.37 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:23:30 PM PDT 24
Peak memory 218836 kb
Host smart-3811f60c-3ec3-49ca-b602-aefdf7404033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733185740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.733185740
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.39728363
Short name T242
Test name
Test status
Simulation time 1541982594 ps
CPU time 23.2 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:44 PM PDT 24
Peak memory 219076 kb
Host smart-cbf0d424-2fe3-4c60-98ef-e54b5857b8e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39728363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.rom_ctrl_stress_all.39728363
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.601227138
Short name T60
Test name
Test status
Simulation time 6166591448 ps
CPU time 71.4 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 227476 kb
Host smart-c6113826-4c6a-451d-8f4f-02cfe4ae9f4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601227138 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.601227138
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1075014178
Short name T277
Test name
Test status
Simulation time 1034782386 ps
CPU time 9.51 seconds
Started Aug 18 05:23:21 PM PDT 24
Finished Aug 18 05:23:30 PM PDT 24
Peak memory 218400 kb
Host smart-5c4452ed-f2dd-4600-bfd7-bccd9efbe6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075014178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1075014178
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2461391734
Short name T336
Test name
Test status
Simulation time 8623805851 ps
CPU time 254.07 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:27:34 PM PDT 24
Peak memory 236824 kb
Host smart-082a89d3-2ef7-44ed-affa-c82f93fe9e88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461391734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2461391734
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1383878738
Short name T256
Test name
Test status
Simulation time 694171641 ps
CPU time 9.69 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:30 PM PDT 24
Peak memory 218896 kb
Host smart-7d5d5cf3-c357-4609-84c5-543a8e16004c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383878738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1383878738
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2706966757
Short name T289
Test name
Test status
Simulation time 3141849203 ps
CPU time 35.24 seconds
Started Aug 18 05:23:21 PM PDT 24
Finished Aug 18 05:23:56 PM PDT 24
Peak memory 219164 kb
Host smart-96c8ca6b-45a7-481f-b89f-49ce776c7911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706966757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2706966757
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2205823898
Short name T218
Test name
Test status
Simulation time 2016631721 ps
CPU time 13.26 seconds
Started Aug 18 05:23:21 PM PDT 24
Finished Aug 18 05:23:34 PM PDT 24
Peak memory 218156 kb
Host smart-acc75f0d-2b39-4387-bb13-efd7aa2ce371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205823898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2205823898
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1300677689
Short name T45
Test name
Test status
Simulation time 4738262927 ps
CPU time 239.73 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:27:19 PM PDT 24
Peak memory 218928 kb
Host smart-73e9a168-6270-4016-836c-d1962ae36423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300677689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1300677689
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2043595212
Short name T216
Test name
Test status
Simulation time 1379201825 ps
CPU time 18.56 seconds
Started Aug 18 05:23:21 PM PDT 24
Finished Aug 18 05:23:40 PM PDT 24
Peak memory 218432 kb
Host smart-f3cc7afd-822c-4671-bb3a-b9bd10c01080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043595212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2043595212
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1716809751
Short name T297
Test name
Test status
Simulation time 274126504 ps
CPU time 9.85 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:30 PM PDT 24
Peak memory 218516 kb
Host smart-a867ad30-0dff-4214-b80c-ab45001e222f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1716809751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1716809751
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.287564079
Short name T189
Test name
Test status
Simulation time 1111296033 ps
CPU time 18.71 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:23:38 PM PDT 24
Peak memory 218948 kb
Host smart-8ee31a91-e777-4ede-93b6-75af75cc0773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287564079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.287564079
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.147737355
Short name T174
Test name
Test status
Simulation time 4278940339 ps
CPU time 48.9 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:24:09 PM PDT 24
Peak memory 224188 kb
Host smart-9023ba92-3cf7-4035-8a5f-f2d097054ec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147737355 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.147737355
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3158220758
Short name T316
Test name
Test status
Simulation time 664651812 ps
CPU time 7.96 seconds
Started Aug 18 05:23:28 PM PDT 24
Finished Aug 18 05:23:36 PM PDT 24
Peak memory 218252 kb
Host smart-09440118-e382-467c-aee1-a191e888ba91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158220758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3158220758
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1907204484
Short name T184
Test name
Test status
Simulation time 2599137855 ps
CPU time 20.97 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:41 PM PDT 24
Peak memory 218908 kb
Host smart-c280a437-0abd-4d56-b51d-9369021f1504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907204484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1907204484
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3491100257
Short name T341
Test name
Test status
Simulation time 271024621 ps
CPU time 11.35 seconds
Started Aug 18 05:23:18 PM PDT 24
Finished Aug 18 05:23:29 PM PDT 24
Peak memory 218492 kb
Host smart-dbca399d-8f12-448d-b301-98f028e89a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491100257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3491100257
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.723247633
Short name T310
Test name
Test status
Simulation time 785006095 ps
CPU time 22.71 seconds
Started Aug 18 05:23:21 PM PDT 24
Finished Aug 18 05:23:43 PM PDT 24
Peak memory 219032 kb
Host smart-d22b26d0-4a6e-487c-9d16-661a0370b449
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723247633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.723247633
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1856236673
Short name T98
Test name
Test status
Simulation time 6617650431 ps
CPU time 161.76 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:26:14 PM PDT 24
Peak memory 235644 kb
Host smart-15a8b749-47dd-4a49-9e26-6f53abaa86f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856236673 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1856236673
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3461379041
Short name T230
Test name
Test status
Simulation time 175032244 ps
CPU time 8.03 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:23:37 PM PDT 24
Peak memory 218328 kb
Host smart-54949382-09af-4925-b897-61adf103f51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461379041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3461379041
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1472017077
Short name T29
Test name
Test status
Simulation time 10362886699 ps
CPU time 288.68 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:28:21 PM PDT 24
Peak memory 234352 kb
Host smart-9ed8ed27-4c11-4837-bae6-0375d42ca8d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472017077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1472017077
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4041251092
Short name T199
Test name
Test status
Simulation time 661255610 ps
CPU time 18.26 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:23:47 PM PDT 24
Peak memory 218504 kb
Host smart-41dbad4b-474a-4929-9c29-2af2cee8b65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041251092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4041251092
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.124539684
Short name T177
Test name
Test status
Simulation time 696305036 ps
CPU time 10.5 seconds
Started Aug 18 05:23:27 PM PDT 24
Finished Aug 18 05:23:37 PM PDT 24
Peak memory 218836 kb
Host smart-0cf63106-5896-4195-beb3-b42405c35a7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124539684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.124539684
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3469286891
Short name T224
Test name
Test status
Simulation time 284589054 ps
CPU time 15.8 seconds
Started Aug 18 05:23:27 PM PDT 24
Finished Aug 18 05:23:43 PM PDT 24
Peak memory 219112 kb
Host smart-53323a1a-9a37-43d3-8eac-be7dd4b4a1db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469286891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3469286891
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2113938786
Short name T237
Test name
Test status
Simulation time 251813074 ps
CPU time 9.37 seconds
Started Aug 18 05:23:27 PM PDT 24
Finished Aug 18 05:23:36 PM PDT 24
Peak memory 218268 kb
Host smart-7f0522f0-b8bf-4da4-8595-10d8cab00826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113938786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2113938786
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.82215910
Short name T291
Test name
Test status
Simulation time 14072854343 ps
CPU time 375.18 seconds
Started Aug 18 05:23:30 PM PDT 24
Finished Aug 18 05:29:45 PM PDT 24
Peak memory 239568 kb
Host smart-18446b7b-3b21-4b4c-a188-86c1f8c4a31d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82215910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_co
rrupt_sig_fatal_chk.82215910
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3117247065
Short name T244
Test name
Test status
Simulation time 3094449319 ps
CPU time 21.33 seconds
Started Aug 18 05:23:31 PM PDT 24
Finished Aug 18 05:23:53 PM PDT 24
Peak memory 218936 kb
Host smart-cf0919a0-4643-45a0-9c51-16a4775c1f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117247065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3117247065
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2890940191
Short name T8
Test name
Test status
Simulation time 432325381 ps
CPU time 11.55 seconds
Started Aug 18 05:23:31 PM PDT 24
Finished Aug 18 05:23:43 PM PDT 24
Peak memory 218508 kb
Host smart-f5f1c7f6-8120-404f-8286-a49c76f66954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890940191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2890940191
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2984837719
Short name T332
Test name
Test status
Simulation time 539175061 ps
CPU time 32.82 seconds
Started Aug 18 05:23:30 PM PDT 24
Finished Aug 18 05:24:03 PM PDT 24
Peak memory 219116 kb
Host smart-c78f54f5-9369-4a96-81c2-ede01afa0bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984837719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2984837719
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.792969306
Short name T11
Test name
Test status
Simulation time 3518920334 ps
CPU time 202.94 seconds
Started Aug 18 05:23:30 PM PDT 24
Finished Aug 18 05:26:53 PM PDT 24
Peak memory 226512 kb
Host smart-9d51ecbc-b3fb-4c5c-8952-3de50aef6107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792969306 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.792969306
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1208677032
Short name T314
Test name
Test status
Simulation time 752602562 ps
CPU time 7.79 seconds
Started Aug 18 05:23:28 PM PDT 24
Finished Aug 18 05:23:36 PM PDT 24
Peak memory 218296 kb
Host smart-621ef3a1-d222-4895-aa1e-f7d6d2411aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208677032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1208677032
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.499872905
Short name T247
Test name
Test status
Simulation time 76485899197 ps
CPU time 336.94 seconds
Started Aug 18 05:23:31 PM PDT 24
Finished Aug 18 05:29:09 PM PDT 24
Peak memory 233576 kb
Host smart-77beb722-2834-4a3f-ae5a-c31767302669
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499872905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.499872905
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3281289950
Short name T348
Test name
Test status
Simulation time 1322241725 ps
CPU time 18.57 seconds
Started Aug 18 05:23:30 PM PDT 24
Finished Aug 18 05:23:48 PM PDT 24
Peak memory 218652 kb
Host smart-e43af50c-7671-4fa3-9bde-596d64ff4b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281289950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3281289950
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4138583560
Short name T170
Test name
Test status
Simulation time 1060679497 ps
CPU time 11.44 seconds
Started Aug 18 05:23:30 PM PDT 24
Finished Aug 18 05:23:41 PM PDT 24
Peak memory 218856 kb
Host smart-86afa826-a71a-4d85-b0af-df5155588da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138583560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4138583560
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.791579179
Short name T97
Test name
Test status
Simulation time 554070311 ps
CPU time 26.45 seconds
Started Aug 18 05:23:28 PM PDT 24
Finished Aug 18 05:23:55 PM PDT 24
Peak memory 219100 kb
Host smart-165fe57c-58aa-4950-9c02-12c55904ba0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791579179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.791579179
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2721342558
Short name T350
Test name
Test status
Simulation time 1811448887 ps
CPU time 61.9 seconds
Started Aug 18 05:23:28 PM PDT 24
Finished Aug 18 05:24:30 PM PDT 24
Peak memory 223572 kb
Host smart-713b50af-609c-4cca-955c-0b1dab5d64a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721342558 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2721342558
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1892689436
Short name T338
Test name
Test status
Simulation time 661859538 ps
CPU time 7.94 seconds
Started Aug 18 05:23:26 PM PDT 24
Finished Aug 18 05:23:34 PM PDT 24
Peak memory 218372 kb
Host smart-c6f4b5af-ca0d-49fb-b29c-60c0345fc5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892689436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1892689436
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3143981405
Short name T241
Test name
Test status
Simulation time 11269728289 ps
CPU time 318.94 seconds
Started Aug 18 05:23:31 PM PDT 24
Finished Aug 18 05:28:50 PM PDT 24
Peak memory 237668 kb
Host smart-24e5c810-3a18-4b04-af6f-85c96d559152
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143981405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3143981405
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1226651077
Short name T53
Test name
Test status
Simulation time 336948395 ps
CPU time 17.94 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:23:50 PM PDT 24
Peak memory 218400 kb
Host smart-141e474d-b9e7-410e-ba50-c73e4d6b4cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226651077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1226651077
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2274981650
Short name T267
Test name
Test status
Simulation time 182318186 ps
CPU time 9.61 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:23:42 PM PDT 24
Peak memory 218368 kb
Host smart-3761c5a1-a83d-4e88-83b1-f36cab698832
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274981650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2274981650
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3185864001
Short name T205
Test name
Test status
Simulation time 2323981344 ps
CPU time 22.81 seconds
Started Aug 18 05:23:28 PM PDT 24
Finished Aug 18 05:23:51 PM PDT 24
Peak memory 219088 kb
Host smart-2df917e3-d075-4e89-8bc0-c4d7c2251075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185864001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3185864001
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1487533626
Short name T138
Test name
Test status
Simulation time 1035638947 ps
CPU time 9.57 seconds
Started Aug 18 05:23:28 PM PDT 24
Finished Aug 18 05:23:38 PM PDT 24
Peak memory 218296 kb
Host smart-7845dec5-1b0d-41df-a927-b9d5fc72c0c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487533626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1487533626
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3455570228
Short name T186
Test name
Test status
Simulation time 2622793576 ps
CPU time 148.54 seconds
Started Aug 18 05:23:30 PM PDT 24
Finished Aug 18 05:25:58 PM PDT 24
Peak memory 239848 kb
Host smart-2ce30938-aa63-4351-999c-c2634f0b8df2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455570228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3455570228
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2160033161
Short name T355
Test name
Test status
Simulation time 516188213 ps
CPU time 21.36 seconds
Started Aug 18 05:23:30 PM PDT 24
Finished Aug 18 05:23:52 PM PDT 24
Peak memory 218484 kb
Host smart-8d58ddf7-75ac-4f70-b717-ff57b1ff7cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160033161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2160033161
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4162398084
Short name T164
Test name
Test status
Simulation time 568047138 ps
CPU time 10.06 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:23:39 PM PDT 24
Peak memory 218912 kb
Host smart-6d1f313f-0bbc-4710-87be-40d12a4cc69b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162398084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4162398084
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.156998787
Short name T234
Test name
Test status
Simulation time 11057110167 ps
CPU time 37.48 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:24:06 PM PDT 24
Peak memory 220676 kb
Host smart-6b6a5193-4227-40ae-8ed7-2202f86f0ae6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156998787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.156998787
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1065622729
Short name T302
Test name
Test status
Simulation time 18078486412 ps
CPU time 206.94 seconds
Started Aug 18 05:23:27 PM PDT 24
Finished Aug 18 05:26:54 PM PDT 24
Peak memory 235612 kb
Host smart-4e8ea7af-506a-4d4f-a634-bf0758d20d23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065622729 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1065622729
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1606578637
Short name T245
Test name
Test status
Simulation time 256648470 ps
CPU time 9.62 seconds
Started Aug 18 05:23:00 PM PDT 24
Finished Aug 18 05:23:10 PM PDT 24
Peak memory 218404 kb
Host smart-6b4be022-721d-4ea9-a939-a9daeceb60e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606578637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1606578637
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3653637633
Short name T228
Test name
Test status
Simulation time 6123911644 ps
CPU time 103.49 seconds
Started Aug 18 05:23:01 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 241060 kb
Host smart-52b19e2a-ae48-44f0-a9fb-3817e3f34ff2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653637633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3653637633
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.394741583
Short name T4
Test name
Test status
Simulation time 1381439508 ps
CPU time 18.13 seconds
Started Aug 18 05:23:01 PM PDT 24
Finished Aug 18 05:23:19 PM PDT 24
Peak memory 218836 kb
Host smart-df8a83ea-ff94-4988-b84d-5a5747a91f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394741583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.394741583
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4144563095
Short name T334
Test name
Test status
Simulation time 178828216 ps
CPU time 10.19 seconds
Started Aug 18 05:23:00 PM PDT 24
Finished Aug 18 05:23:11 PM PDT 24
Peak memory 218596 kb
Host smart-cfe80721-b794-4260-b8a5-f5dbf03ca59c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144563095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4144563095
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.955709446
Short name T28
Test name
Test status
Simulation time 2480208919 ps
CPU time 117.92 seconds
Started Aug 18 05:22:59 PM PDT 24
Finished Aug 18 05:24:58 PM PDT 24
Peak memory 239140 kb
Host smart-cbd36814-d85f-47af-8c0d-3ff7bd007ffc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955709446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.955709446
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3538922117
Short name T349
Test name
Test status
Simulation time 294477132 ps
CPU time 11.83 seconds
Started Aug 18 05:23:00 PM PDT 24
Finished Aug 18 05:23:12 PM PDT 24
Peak memory 219060 kb
Host smart-1489d8a7-caed-40f0-8a0b-4c59f7d7c30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538922117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3538922117
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2494349062
Short name T351
Test name
Test status
Simulation time 498754638 ps
CPU time 15.74 seconds
Started Aug 18 05:22:58 PM PDT 24
Finished Aug 18 05:23:14 PM PDT 24
Peak memory 219120 kb
Host smart-f96e5b0c-129e-4666-b785-899c465c7641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494349062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2494349062
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.775696542
Short name T149
Test name
Test status
Simulation time 13096660768 ps
CPU time 54.72 seconds
Started Aug 18 05:23:00 PM PDT 24
Finished Aug 18 05:23:54 PM PDT 24
Peak memory 232480 kb
Host smart-d6fb2c4b-a179-4edf-9ba1-72947a346e3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775696542 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.775696542
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2506991751
Short name T163
Test name
Test status
Simulation time 265645411 ps
CPU time 9.55 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:23:39 PM PDT 24
Peak memory 218296 kb
Host smart-8012a34f-2ce3-46b7-aa17-8017c0a89290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506991751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2506991751
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1766177011
Short name T133
Test name
Test status
Simulation time 25797306996 ps
CPU time 347.87 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:29:20 PM PDT 24
Peak memory 229404 kb
Host smart-b93d739d-7e46-48bb-a140-10778625dea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766177011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1766177011
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1478623950
Short name T257
Test name
Test status
Simulation time 336230314 ps
CPU time 18.22 seconds
Started Aug 18 05:23:27 PM PDT 24
Finished Aug 18 05:23:46 PM PDT 24
Peak memory 218564 kb
Host smart-48247bcc-4002-460a-90a7-f57dd929977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478623950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1478623950
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2209321103
Short name T268
Test name
Test status
Simulation time 261003404 ps
CPU time 11.47 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:23:41 PM PDT 24
Peak memory 218536 kb
Host smart-3ea9072d-e910-4e82-a230-922abb03aba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209321103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2209321103
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1811032402
Short name T156
Test name
Test status
Simulation time 525848859 ps
CPU time 28.09 seconds
Started Aug 18 05:23:28 PM PDT 24
Finished Aug 18 05:23:56 PM PDT 24
Peak memory 219816 kb
Host smart-139f211c-4c48-4d29-971c-8013152de766
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811032402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1811032402
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.180697049
Short name T59
Test name
Test status
Simulation time 25163162230 ps
CPU time 172.41 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:26:25 PM PDT 24
Peak memory 235592 kb
Host smart-93c3afed-2c75-492a-8918-9cc5fdff6063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180697049 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.180697049
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.641469256
Short name T220
Test name
Test status
Simulation time 250325067 ps
CPU time 9.62 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:23:38 PM PDT 24
Peak memory 218388 kb
Host smart-770dc86c-b272-4979-96b8-42c08adf5ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641469256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.641469256
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3485575299
Short name T335
Test name
Test status
Simulation time 4533076261 ps
CPU time 310.09 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:28:39 PM PDT 24
Peak memory 237524 kb
Host smart-14d1dc0d-cd77-4ed5-999d-26c0b74917df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485575299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3485575299
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3568239452
Short name T273
Test name
Test status
Simulation time 2057584711 ps
CPU time 21.32 seconds
Started Aug 18 05:23:31 PM PDT 24
Finished Aug 18 05:23:53 PM PDT 24
Peak memory 218692 kb
Host smart-e8c94fbe-0e81-4f86-8e0c-29be8df84cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568239452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3568239452
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3074494965
Short name T266
Test name
Test status
Simulation time 736239188 ps
CPU time 10 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:23:39 PM PDT 24
Peak memory 218804 kb
Host smart-208b3299-b56c-4263-9242-d45d3725351e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074494965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3074494965
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.932617049
Short name T233
Test name
Test status
Simulation time 1128903075 ps
CPU time 30.87 seconds
Started Aug 18 05:23:29 PM PDT 24
Finished Aug 18 05:24:00 PM PDT 24
Peak memory 219040 kb
Host smart-a7f93aab-9362-4b47-afed-2ec2c3344761
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932617049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.932617049
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1121696040
Short name T272
Test name
Test status
Simulation time 689368979 ps
CPU time 8.04 seconds
Started Aug 18 05:23:38 PM PDT 24
Finished Aug 18 05:23:46 PM PDT 24
Peak memory 218248 kb
Host smart-574b2772-b7a6-41fe-960c-c55883107159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121696040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1121696040
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.129646369
Short name T243
Test name
Test status
Simulation time 315268335384 ps
CPU time 371.07 seconds
Started Aug 18 05:23:36 PM PDT 24
Finished Aug 18 05:29:48 PM PDT 24
Peak memory 237184 kb
Host smart-7f1848d8-b5da-48a0-a357-a98ac5bb9395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129646369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.129646369
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2736519293
Short name T222
Test name
Test status
Simulation time 723294770 ps
CPU time 18.18 seconds
Started Aug 18 05:23:36 PM PDT 24
Finished Aug 18 05:23:55 PM PDT 24
Peak memory 218836 kb
Host smart-ee0f7c09-75ea-44b4-8af9-09f7dfbed2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736519293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2736519293
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2854528126
Short name T96
Test name
Test status
Simulation time 186179113 ps
CPU time 9.8 seconds
Started Aug 18 05:23:36 PM PDT 24
Finished Aug 18 05:23:46 PM PDT 24
Peak memory 218656 kb
Host smart-b0325279-da93-4069-bdfe-81c798e5345a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2854528126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2854528126
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1079431332
Short name T95
Test name
Test status
Simulation time 210277828 ps
CPU time 14.07 seconds
Started Aug 18 05:23:36 PM PDT 24
Finished Aug 18 05:23:50 PM PDT 24
Peak memory 219152 kb
Host smart-c772b04d-89a2-44df-8737-dcc53678f26c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079431332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1079431332
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2242710186
Short name T214
Test name
Test status
Simulation time 3252860865 ps
CPU time 196.62 seconds
Started Aug 18 05:23:47 PM PDT 24
Finished Aug 18 05:27:04 PM PDT 24
Peak memory 225156 kb
Host smart-0c5365f9-f7c2-4d5e-9ced-fea61f71c380
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242710186 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2242710186
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1243777622
Short name T193
Test name
Test status
Simulation time 636530287 ps
CPU time 7.73 seconds
Started Aug 18 05:23:36 PM PDT 24
Finished Aug 18 05:23:44 PM PDT 24
Peak memory 218256 kb
Host smart-2d9e2851-0a40-4f8b-8542-ec297a274785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243777622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1243777622
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2301663544
Short name T44
Test name
Test status
Simulation time 13393995228 ps
CPU time 273.27 seconds
Started Aug 18 05:23:38 PM PDT 24
Finished Aug 18 05:28:11 PM PDT 24
Peak memory 227564 kb
Host smart-060d54b7-f8be-43f4-82f8-c67f9bcc1fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301663544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2301663544
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2148695087
Short name T182
Test name
Test status
Simulation time 517153394 ps
CPU time 21.16 seconds
Started Aug 18 05:23:35 PM PDT 24
Finished Aug 18 05:23:57 PM PDT 24
Peak memory 218768 kb
Host smart-e6a4177f-1d81-4f11-996e-14532dcc58a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148695087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2148695087
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.650784960
Short name T194
Test name
Test status
Simulation time 713590777 ps
CPU time 9.89 seconds
Started Aug 18 05:23:37 PM PDT 24
Finished Aug 18 05:23:47 PM PDT 24
Peak memory 218720 kb
Host smart-7ed22dab-cff0-43b9-affa-ce3e2bf76d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650784960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.650784960
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3172815721
Short name T298
Test name
Test status
Simulation time 281518158 ps
CPU time 18.66 seconds
Started Aug 18 05:23:47 PM PDT 24
Finished Aug 18 05:24:06 PM PDT 24
Peak memory 219104 kb
Host smart-1abab0b3-3b0c-4179-844a-9da2e6314824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172815721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3172815721
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3862443236
Short name T2
Test name
Test status
Simulation time 6860344287 ps
CPU time 65.71 seconds
Started Aug 18 05:23:36 PM PDT 24
Finished Aug 18 05:24:41 PM PDT 24
Peak memory 227396 kb
Host smart-49fa847d-2d9c-45db-abd2-b9708fc36028
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862443236 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3862443236
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1267408085
Short name T154
Test name
Test status
Simulation time 176466539 ps
CPU time 8.05 seconds
Started Aug 18 05:23:46 PM PDT 24
Finished Aug 18 05:23:55 PM PDT 24
Peak memory 218312 kb
Host smart-cc89b768-2912-467d-b863-fa0f2c214ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267408085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1267408085
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3044158332
Short name T43
Test name
Test status
Simulation time 4456820909 ps
CPU time 254.05 seconds
Started Aug 18 05:23:37 PM PDT 24
Finished Aug 18 05:27:51 PM PDT 24
Peak memory 237028 kb
Host smart-b604d61b-58b7-4e23-badc-339be0a84d0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044158332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3044158332
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4194507893
Short name T264
Test name
Test status
Simulation time 2069163596 ps
CPU time 21.47 seconds
Started Aug 18 05:23:39 PM PDT 24
Finished Aug 18 05:24:00 PM PDT 24
Peak memory 218748 kb
Host smart-463e8bdb-bdbf-40c8-af79-2d141673c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194507893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4194507893
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3743827234
Short name T290
Test name
Test status
Simulation time 183019096 ps
CPU time 9.99 seconds
Started Aug 18 05:23:48 PM PDT 24
Finished Aug 18 05:23:58 PM PDT 24
Peak memory 218608 kb
Host smart-21926907-49f2-43b1-9b16-2dd16fee5805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743827234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3743827234
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2420633206
Short name T353
Test name
Test status
Simulation time 1330458566 ps
CPU time 57.26 seconds
Started Aug 18 05:23:47 PM PDT 24
Finished Aug 18 05:24:45 PM PDT 24
Peak memory 220720 kb
Host smart-72b7ab6e-2166-4624-a388-c053973baad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420633206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2420633206
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1820562333
Short name T169
Test name
Test status
Simulation time 7647539401 ps
CPU time 68.74 seconds
Started Aug 18 05:23:45 PM PDT 24
Finished Aug 18 05:24:54 PM PDT 24
Peak memory 235612 kb
Host smart-3a71e0d5-c46f-4ae3-a28d-09440a8a3e00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820562333 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1820562333
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1146179592
Short name T140
Test name
Test status
Simulation time 468565561 ps
CPU time 9.36 seconds
Started Aug 18 05:23:44 PM PDT 24
Finished Aug 18 05:23:54 PM PDT 24
Peak memory 217904 kb
Host smart-61bdca6f-4323-4e6f-befa-06035e703bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146179592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1146179592
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1401130178
Short name T286
Test name
Test status
Simulation time 6831620201 ps
CPU time 325.33 seconds
Started Aug 18 05:23:44 PM PDT 24
Finished Aug 18 05:29:09 PM PDT 24
Peak memory 233728 kb
Host smart-116b1fd3-62d8-483b-b2c2-d038c2b20092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401130178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1401130178
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2032158813
Short name T270
Test name
Test status
Simulation time 516839191 ps
CPU time 22.12 seconds
Started Aug 18 05:23:46 PM PDT 24
Finished Aug 18 05:24:08 PM PDT 24
Peak memory 218612 kb
Host smart-2d5cb53d-d841-4e3b-b469-fec6a7ee22ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032158813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2032158813
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.499227507
Short name T278
Test name
Test status
Simulation time 710848123 ps
CPU time 10.42 seconds
Started Aug 18 05:23:44 PM PDT 24
Finished Aug 18 05:23:55 PM PDT 24
Peak memory 218824 kb
Host smart-d44a4e78-0168-4a44-baf8-dbd2b0dcfdea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499227507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.499227507
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4033850827
Short name T176
Test name
Test status
Simulation time 743339677 ps
CPU time 11.71 seconds
Started Aug 18 05:23:46 PM PDT 24
Finished Aug 18 05:23:58 PM PDT 24
Peak memory 215108 kb
Host smart-24d19277-e00a-4718-b1c8-c79fbf1a3ba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033850827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4033850827
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.4008686170
Short name T343
Test name
Test status
Simulation time 1937119455 ps
CPU time 77.97 seconds
Started Aug 18 05:23:45 PM PDT 24
Finished Aug 18 05:25:03 PM PDT 24
Peak memory 223548 kb
Host smart-07403b01-6cfc-4a08-ba2f-2f279e8f4842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008686170 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.4008686170
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.134596090
Short name T10
Test name
Test status
Simulation time 178226468 ps
CPU time 7.86 seconds
Started Aug 18 05:23:55 PM PDT 24
Finished Aug 18 05:24:03 PM PDT 24
Peak memory 217888 kb
Host smart-7b8c71ab-e3a2-41ff-b57b-80bc84e2f2d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134596090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.134596090
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2741878542
Short name T40
Test name
Test status
Simulation time 10028163510 ps
CPU time 170.45 seconds
Started Aug 18 05:23:45 PM PDT 24
Finished Aug 18 05:26:35 PM PDT 24
Peak memory 227772 kb
Host smart-983fa12a-5bec-47d5-a137-0b2a4e38b2c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741878542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2741878542
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.42052512
Short name T147
Test name
Test status
Simulation time 2074118265 ps
CPU time 18.83 seconds
Started Aug 18 05:23:45 PM PDT 24
Finished Aug 18 05:24:05 PM PDT 24
Peak memory 218392 kb
Host smart-84efc595-07ac-445f-b9f1-1207c6fe266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42052512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.42052512
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3540130973
Short name T265
Test name
Test status
Simulation time 181343937 ps
CPU time 10.27 seconds
Started Aug 18 05:23:46 PM PDT 24
Finished Aug 18 05:23:56 PM PDT 24
Peak memory 218552 kb
Host smart-1d3aba2a-9962-49e3-a6f8-3a559411227e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3540130973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3540130973
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.403500781
Short name T150
Test name
Test status
Simulation time 1178435588 ps
CPU time 19.06 seconds
Started Aug 18 05:23:45 PM PDT 24
Finished Aug 18 05:24:05 PM PDT 24
Peak memory 219104 kb
Host smart-16d7f9f4-6c2e-4b8a-b416-f847dc14ac57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403500781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.403500781
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.877883604
Short name T145
Test name
Test status
Simulation time 2963160498 ps
CPU time 121.94 seconds
Started Aug 18 05:23:57 PM PDT 24
Finished Aug 18 05:25:59 PM PDT 24
Peak memory 232760 kb
Host smart-77e3fc84-e0e3-4fc0-a085-ba67300590f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877883604 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.877883604
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2095199407
Short name T209
Test name
Test status
Simulation time 690394846 ps
CPU time 7.72 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:10 PM PDT 24
Peak memory 218376 kb
Host smart-7237fa73-afea-451f-863e-2b32c2111486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095199407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2095199407
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1703024620
Short name T352
Test name
Test status
Simulation time 1992900629 ps
CPU time 28.53 seconds
Started Aug 18 05:23:55 PM PDT 24
Finished Aug 18 05:24:23 PM PDT 24
Peak memory 219132 kb
Host smart-05ccfe7a-00cc-48ff-a866-88302f93e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703024620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1703024620
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.628011878
Short name T249
Test name
Test status
Simulation time 1002797180 ps
CPU time 15.27 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:18 PM PDT 24
Peak memory 219348 kb
Host smart-9d0e79dc-80c5-4773-b320-27a9620dfe5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628011878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.628011878
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1856702227
Short name T295
Test name
Test status
Simulation time 4805441106 ps
CPU time 29.76 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:32 PM PDT 24
Peak memory 219120 kb
Host smart-50860bf6-9793-49d8-8ecd-d1ac783f3af6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856702227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1856702227
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.503424282
Short name T236
Test name
Test status
Simulation time 2836672689 ps
CPU time 110.35 seconds
Started Aug 18 05:24:04 PM PDT 24
Finished Aug 18 05:25:54 PM PDT 24
Peak memory 224428 kb
Host smart-be21c2b9-5c11-47d7-bc5f-79175b17edcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503424282 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.503424282
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.46496401
Short name T238
Test name
Test status
Simulation time 15265664516 ps
CPU time 380.18 seconds
Started Aug 18 05:24:01 PM PDT 24
Finished Aug 18 05:30:22 PM PDT 24
Peak memory 239980 kb
Host smart-1970da25-4c69-4100-bc46-c05dd48f3659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46496401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_co
rrupt_sig_fatal_chk.46496401
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3203273380
Short name T197
Test name
Test status
Simulation time 3865650885 ps
CPU time 30.3 seconds
Started Aug 18 05:23:57 PM PDT 24
Finished Aug 18 05:24:28 PM PDT 24
Peak memory 219212 kb
Host smart-e7433da0-8575-4d20-95f2-62a9b8074322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203273380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3203273380
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3793332880
Short name T114
Test name
Test status
Simulation time 516992968 ps
CPU time 11.34 seconds
Started Aug 18 05:24:02 PM PDT 24
Finished Aug 18 05:24:13 PM PDT 24
Peak memory 218444 kb
Host smart-df46ba26-9fc9-41e4-b790-385a2ed4d897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793332880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3793332880
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3371781656
Short name T146
Test name
Test status
Simulation time 2720183607 ps
CPU time 36.19 seconds
Started Aug 18 05:23:55 PM PDT 24
Finished Aug 18 05:24:32 PM PDT 24
Peak memory 219192 kb
Host smart-13b6f1fc-1a6b-4d1b-9ca8-9d16dbfee2f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371781656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3371781656
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2768764888
Short name T307
Test name
Test status
Simulation time 249517670 ps
CPU time 9.53 seconds
Started Aug 18 05:23:56 PM PDT 24
Finished Aug 18 05:24:05 PM PDT 24
Peak memory 218324 kb
Host smart-6d06a9a5-338f-4473-b3aa-e3535d0c392f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768764888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2768764888
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2073024889
Short name T39
Test name
Test status
Simulation time 20058931772 ps
CPU time 280.23 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:28:43 PM PDT 24
Peak memory 233488 kb
Host smart-d84846e8-6aa4-4f66-b260-36f556585ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073024889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2073024889
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2760563800
Short name T144
Test name
Test status
Simulation time 510770746 ps
CPU time 21.16 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:24 PM PDT 24
Peak memory 218324 kb
Host smart-0ee86a42-c538-4396-885c-4cc8430f477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760563800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2760563800
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3499050109
Short name T315
Test name
Test status
Simulation time 340388557 ps
CPU time 10.28 seconds
Started Aug 18 05:23:56 PM PDT 24
Finished Aug 18 05:24:07 PM PDT 24
Peak memory 218656 kb
Host smart-46b0229c-04e2-434d-860a-30f892f56f9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499050109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3499050109
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3152303672
Short name T112
Test name
Test status
Simulation time 2994741915 ps
CPU time 11.85 seconds
Started Aug 18 05:24:02 PM PDT 24
Finished Aug 18 05:24:14 PM PDT 24
Peak memory 219128 kb
Host smart-cdaa0ad4-3718-4148-b4cf-8f64c38d101e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152303672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3152303672
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1211835415
Short name T225
Test name
Test status
Simulation time 1123784193 ps
CPU time 9.29 seconds
Started Aug 18 05:23:15 PM PDT 24
Finished Aug 18 05:23:24 PM PDT 24
Peak memory 218312 kb
Host smart-db7d86bb-9325-471f-891f-2ca272be74e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211835415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1211835415
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2599193310
Short name T223
Test name
Test status
Simulation time 4527110925 ps
CPU time 246.68 seconds
Started Aug 18 05:23:11 PM PDT 24
Finished Aug 18 05:27:18 PM PDT 24
Peak memory 226448 kb
Host smart-aced7dec-d7b8-4323-9467-405e61e783ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599193310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2599193310
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3113555432
Short name T212
Test name
Test status
Simulation time 264630849 ps
CPU time 11.36 seconds
Started Aug 18 05:23:11 PM PDT 24
Finished Aug 18 05:23:22 PM PDT 24
Peak memory 218540 kb
Host smart-c50e1de3-a38c-43af-a672-c252eb2b327f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113555432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3113555432
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2363043179
Short name T301
Test name
Test status
Simulation time 3473923934 ps
CPU time 10.52 seconds
Started Aug 18 05:23:07 PM PDT 24
Finished Aug 18 05:23:18 PM PDT 24
Peak memory 219172 kb
Host smart-4e697b0d-6b35-4022-856e-f01ea5a71a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363043179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2363043179
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1711167305
Short name T254
Test name
Test status
Simulation time 373180107 ps
CPU time 23.6 seconds
Started Aug 18 05:23:13 PM PDT 24
Finished Aug 18 05:23:37 PM PDT 24
Peak memory 219016 kb
Host smart-b6ef6e47-e1b3-49ef-bcb8-8c14ff758fe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711167305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1711167305
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3094405366
Short name T61
Test name
Test status
Simulation time 1899314093 ps
CPU time 70.11 seconds
Started Aug 18 05:23:09 PM PDT 24
Finished Aug 18 05:24:20 PM PDT 24
Peak memory 222736 kb
Host smart-0fd8a3f8-c87b-450f-a07b-7b257140bf43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094405366 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3094405366
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4179270978
Short name T304
Test name
Test status
Simulation time 506204052 ps
CPU time 9.79 seconds
Started Aug 18 05:24:05 PM PDT 24
Finished Aug 18 05:24:15 PM PDT 24
Peak memory 218296 kb
Host smart-3e40a933-db16-49ea-a286-a57b08efa1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179270978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4179270978
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3108856137
Short name T130
Test name
Test status
Simulation time 1686290847 ps
CPU time 109.33 seconds
Started Aug 18 05:24:04 PM PDT 24
Finished Aug 18 05:25:53 PM PDT 24
Peak memory 236760 kb
Host smart-c330a034-07c9-46b0-ace3-1dfccadf3634
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108856137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3108856137
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3876223795
Short name T155
Test name
Test status
Simulation time 263756434 ps
CPU time 11.59 seconds
Started Aug 18 05:24:06 PM PDT 24
Finished Aug 18 05:24:17 PM PDT 24
Peak memory 218520 kb
Host smart-6668e09a-b453-456c-bd07-859168c71f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876223795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3876223795
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.561864595
Short name T81
Test name
Test status
Simulation time 1032940335 ps
CPU time 48.95 seconds
Started Aug 18 05:23:56 PM PDT 24
Finished Aug 18 05:24:45 PM PDT 24
Peak memory 219148 kb
Host smart-9b275e1a-6415-4cd5-8cec-c1334cf665c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561864595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.561864595
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1238738627
Short name T235
Test name
Test status
Simulation time 1534330627 ps
CPU time 69.15 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:25:12 PM PDT 24
Peak memory 223188 kb
Host smart-e41f1922-c589-46a6-9f79-65272940a612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238738627 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1238738627
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1915781091
Short name T167
Test name
Test status
Simulation time 1031433816 ps
CPU time 9.6 seconds
Started Aug 18 05:24:04 PM PDT 24
Finished Aug 18 05:24:14 PM PDT 24
Peak memory 218236 kb
Host smart-0d48931b-f8b6-4641-85cc-b4686a816e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915781091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1915781091
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.512859765
Short name T204
Test name
Test status
Simulation time 45187103874 ps
CPU time 132.62 seconds
Started Aug 18 05:24:06 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 217416 kb
Host smart-6ce020a7-7b45-4e48-aa04-2f1d371f845f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512859765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.512859765
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1927785758
Short name T213
Test name
Test status
Simulation time 2911004579 ps
CPU time 21.57 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:25 PM PDT 24
Peak memory 218820 kb
Host smart-42643d67-3cb6-49e1-8902-b5228277e350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927785758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1927785758
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1388693886
Short name T217
Test name
Test status
Simulation time 1230278594 ps
CPU time 11.7 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:15 PM PDT 24
Peak memory 218764 kb
Host smart-3746ca3e-7ad3-4c70-aca8-373a2f26127a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388693886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1388693886
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2580602480
Short name T52
Test name
Test status
Simulation time 365998571 ps
CPU time 23.69 seconds
Started Aug 18 05:24:05 PM PDT 24
Finished Aug 18 05:24:29 PM PDT 24
Peak memory 219036 kb
Host smart-11e531b9-2b27-4e79-9502-299cda7057de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580602480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2580602480
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2876339331
Short name T47
Test name
Test status
Simulation time 3778360373 ps
CPU time 201.09 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:27:25 PM PDT 24
Peak memory 233388 kb
Host smart-c0fe7d7a-bd0e-4a4a-93ef-3b7ef9c1b623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876339331 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2876339331
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.321233150
Short name T25
Test name
Test status
Simulation time 2475596073 ps
CPU time 9.45 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:13 PM PDT 24
Peak memory 217452 kb
Host smart-055fcc43-5917-41fb-ac33-dcb096d9afcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321233150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.321233150
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1486099750
Short name T311
Test name
Test status
Simulation time 9225764261 ps
CPU time 280.64 seconds
Started Aug 18 05:24:02 PM PDT 24
Finished Aug 18 05:28:43 PM PDT 24
Peak memory 237736 kb
Host smart-a5d21bae-a5c7-4027-b4e6-3380ade2bd30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486099750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1486099750
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1217173473
Short name T55
Test name
Test status
Simulation time 342556700 ps
CPU time 18.34 seconds
Started Aug 18 05:24:02 PM PDT 24
Finished Aug 18 05:24:21 PM PDT 24
Peak memory 218548 kb
Host smart-b8991df4-d00d-40c5-91f6-683803c30a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217173473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1217173473
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4043794675
Short name T113
Test name
Test status
Simulation time 178574913 ps
CPU time 10 seconds
Started Aug 18 05:24:05 PM PDT 24
Finished Aug 18 05:24:15 PM PDT 24
Peak memory 218516 kb
Host smart-80ca99f6-261b-400a-b83b-1e68f07ea250
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043794675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4043794675
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1482576074
Short name T34
Test name
Test status
Simulation time 1438986787 ps
CPU time 19.99 seconds
Started Aug 18 05:24:05 PM PDT 24
Finished Aug 18 05:24:25 PM PDT 24
Peak memory 218300 kb
Host smart-1f9d8860-27f8-4bda-9b58-baa707393000
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482576074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1482576074
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3847412149
Short name T159
Test name
Test status
Simulation time 9154732923 ps
CPU time 99.35 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 235632 kb
Host smart-19f35778-9104-48a9-8aae-98cdeb044462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847412149 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3847412149
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4103613474
Short name T293
Test name
Test status
Simulation time 260928455 ps
CPU time 9.45 seconds
Started Aug 18 05:24:06 PM PDT 24
Finished Aug 18 05:24:16 PM PDT 24
Peak memory 218244 kb
Host smart-da6b9210-00ee-453a-961a-503fbb22d0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103613474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4103613474
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.522075091
Short name T42
Test name
Test status
Simulation time 16701136868 ps
CPU time 275.24 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:28:39 PM PDT 24
Peak memory 224528 kb
Host smart-1728ed4e-5027-4e36-90a5-971bcb7f1b2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522075091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.522075091
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.718295343
Short name T54
Test name
Test status
Simulation time 661602388 ps
CPU time 18.07 seconds
Started Aug 18 05:24:06 PM PDT 24
Finished Aug 18 05:24:24 PM PDT 24
Peak memory 218760 kb
Host smart-2054e8d2-5725-46c2-a933-63a0eed8a8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718295343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.718295343
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1630461517
Short name T12
Test name
Test status
Simulation time 4219718330 ps
CPU time 11.46 seconds
Started Aug 18 05:24:02 PM PDT 24
Finished Aug 18 05:24:14 PM PDT 24
Peak memory 218776 kb
Host smart-9a1f0392-ec51-4096-8f1d-29e6799ffb90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630461517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1630461517
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4200761772
Short name T279
Test name
Test status
Simulation time 2125066665 ps
CPU time 27.47 seconds
Started Aug 18 05:24:05 PM PDT 24
Finished Aug 18 05:24:33 PM PDT 24
Peak memory 219044 kb
Host smart-568d3ed0-5ef0-42ae-9ceb-fe880155d2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200761772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4200761772
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.388146876
Short name T136
Test name
Test status
Simulation time 6320949242 ps
CPU time 92.48 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:25:36 PM PDT 24
Peak memory 232988 kb
Host smart-32d8effe-7f19-49d7-b3b3-d95dc19843e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388146876 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.388146876
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3513846771
Short name T187
Test name
Test status
Simulation time 4116784468 ps
CPU time 9.64 seconds
Started Aug 18 05:24:06 PM PDT 24
Finished Aug 18 05:24:16 PM PDT 24
Peak memory 218456 kb
Host smart-164fe026-96f4-4d1a-8ce6-db470c4fcf53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513846771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3513846771
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2539731698
Short name T37
Test name
Test status
Simulation time 8694558216 ps
CPU time 230.36 seconds
Started Aug 18 05:24:06 PM PDT 24
Finished Aug 18 05:27:56 PM PDT 24
Peak memory 238232 kb
Host smart-06a8cd0b-0420-4398-8d78-2e9509c5f59e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539731698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2539731698
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3531415092
Short name T226
Test name
Test status
Simulation time 333448954 ps
CPU time 18.51 seconds
Started Aug 18 05:24:06 PM PDT 24
Finished Aug 18 05:24:25 PM PDT 24
Peak memory 218576 kb
Host smart-fa9cf3f9-bb89-4fbd-8baa-123781ffae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531415092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3531415092
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3140850720
Short name T173
Test name
Test status
Simulation time 182461260 ps
CPU time 10.17 seconds
Started Aug 18 05:24:03 PM PDT 24
Finished Aug 18 05:24:13 PM PDT 24
Peak memory 218684 kb
Host smart-d493cd8d-ed50-4b22-80ed-bb7c7f05a9de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140850720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3140850720
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3729404853
Short name T143
Test name
Test status
Simulation time 346167838 ps
CPU time 7.76 seconds
Started Aug 18 05:24:16 PM PDT 24
Finished Aug 18 05:24:23 PM PDT 24
Peak memory 218344 kb
Host smart-e4d29030-f646-46b9-8af6-02730cb167ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729404853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3729404853
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3776181347
Short name T157
Test name
Test status
Simulation time 2772280359 ps
CPU time 172.08 seconds
Started Aug 18 05:24:16 PM PDT 24
Finished Aug 18 05:27:08 PM PDT 24
Peak memory 227632 kb
Host smart-3a07b399-62b4-42a4-b3e5-e5dc9b1f0a80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776181347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3776181347
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4011011906
Short name T253
Test name
Test status
Simulation time 807192578 ps
CPU time 18.55 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:24:32 PM PDT 24
Peak memory 218724 kb
Host smart-0aa425f0-fd7a-436a-ada0-9e563201e56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011011906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4011011906
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3891092699
Short name T248
Test name
Test status
Simulation time 362970498 ps
CPU time 9.77 seconds
Started Aug 18 05:24:14 PM PDT 24
Finished Aug 18 05:24:24 PM PDT 24
Peak memory 218564 kb
Host smart-eab23af6-4343-4a3c-9e5a-e50955591b2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891092699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3891092699
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2950865382
Short name T288
Test name
Test status
Simulation time 4131848378 ps
CPU time 29.9 seconds
Started Aug 18 05:24:02 PM PDT 24
Finished Aug 18 05:24:32 PM PDT 24
Peak memory 219216 kb
Host smart-a3bfeff8-15f7-45a5-bf83-2e6a5bca10e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950865382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2950865382
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.699880434
Short name T15
Test name
Test status
Simulation time 4736690352 ps
CPU time 106.41 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 224868 kb
Host smart-35a90903-78b6-465f-b3e2-93cc88d5785d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699880434 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.699880434
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4076778417
Short name T56
Test name
Test status
Simulation time 263310992 ps
CPU time 9.46 seconds
Started Aug 18 05:24:15 PM PDT 24
Finished Aug 18 05:24:24 PM PDT 24
Peak memory 218264 kb
Host smart-d40f516a-e885-498b-bf0c-5a1ae7db0603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076778417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4076778417
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2369566404
Short name T20
Test name
Test status
Simulation time 4945812779 ps
CPU time 153.24 seconds
Started Aug 18 05:24:15 PM PDT 24
Finished Aug 18 05:26:48 PM PDT 24
Peak memory 219480 kb
Host smart-2af06840-aeff-4732-b865-c04836bdc737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369566404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2369566404
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2591530091
Short name T3
Test name
Test status
Simulation time 520423400 ps
CPU time 21.28 seconds
Started Aug 18 05:24:15 PM PDT 24
Finished Aug 18 05:24:37 PM PDT 24
Peak memory 218580 kb
Host smart-10266196-b7eb-4823-a9f7-b22f52c3a0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591530091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2591530091
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2220537402
Short name T280
Test name
Test status
Simulation time 1066746769 ps
CPU time 11.5 seconds
Started Aug 18 05:24:14 PM PDT 24
Finished Aug 18 05:24:26 PM PDT 24
Peak memory 218880 kb
Host smart-192cba19-7a9e-4ab3-951d-29c273d20fb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220537402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2220537402
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4057179758
Short name T134
Test name
Test status
Simulation time 1049514887 ps
CPU time 19.33 seconds
Started Aug 18 05:24:14 PM PDT 24
Finished Aug 18 05:24:33 PM PDT 24
Peak memory 219152 kb
Host smart-bca06120-c3a3-478a-9385-dbf192c4ea36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057179758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4057179758
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4213573658
Short name T153
Test name
Test status
Simulation time 1903578998 ps
CPU time 81.87 seconds
Started Aug 18 05:24:12 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 223828 kb
Host smart-1ad91858-2ed3-49ed-ba09-25ba4f294d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213573658 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.4213573658
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3097055743
Short name T283
Test name
Test status
Simulation time 691250597 ps
CPU time 7.79 seconds
Started Aug 18 05:24:14 PM PDT 24
Finished Aug 18 05:24:21 PM PDT 24
Peak memory 218304 kb
Host smart-a303b18e-54ae-4cc6-a30c-b9cf81343186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097055743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3097055743
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2187950991
Short name T19
Test name
Test status
Simulation time 2834793820 ps
CPU time 175.95 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:27:10 PM PDT 24
Peak memory 224208 kb
Host smart-294013c1-1128-45f7-8a29-bc6bad9ec8bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187950991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2187950991
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1935949333
Short name T345
Test name
Test status
Simulation time 431540316 ps
CPU time 18.36 seconds
Started Aug 18 05:24:16 PM PDT 24
Finished Aug 18 05:24:34 PM PDT 24
Peak memory 218580 kb
Host smart-8ec7e6cf-1a17-4f5b-92e7-9997dcfc11e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935949333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1935949333
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.196962454
Short name T285
Test name
Test status
Simulation time 1032876815 ps
CPU time 11.56 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:24:24 PM PDT 24
Peak memory 218860 kb
Host smart-94eeda91-e14d-47ab-980c-edff358217ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196962454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.196962454
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.10854535
Short name T308
Test name
Test status
Simulation time 2079909239 ps
CPU time 21.72 seconds
Started Aug 18 05:24:15 PM PDT 24
Finished Aug 18 05:24:37 PM PDT 24
Peak memory 219052 kb
Host smart-bffcb249-7684-4daa-b9e8-081549e7a880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10854535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.rom_ctrl_stress_all.10854535
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3160160749
Short name T258
Test name
Test status
Simulation time 12404556284 ps
CPU time 192.1 seconds
Started Aug 18 05:24:15 PM PDT 24
Finished Aug 18 05:27:27 PM PDT 24
Peak memory 227088 kb
Host smart-69d73aff-3b5e-4a3a-9762-a11b3806a44f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160160749 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3160160749
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2436812822
Short name T50
Test name
Test status
Simulation time 174385767 ps
CPU time 7.86 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:24:21 PM PDT 24
Peak memory 218268 kb
Host smart-5be1b34b-2377-4fd5-80aa-ee8e1b2f2ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436812822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2436812822
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1668814915
Short name T318
Test name
Test status
Simulation time 19427641996 ps
CPU time 300.66 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:29:14 PM PDT 24
Peak memory 233772 kb
Host smart-7e335144-0818-4555-83e6-353473857485
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668814915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1668814915
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.624715980
Short name T158
Test name
Test status
Simulation time 753728044 ps
CPU time 18.06 seconds
Started Aug 18 05:24:15 PM PDT 24
Finished Aug 18 05:24:33 PM PDT 24
Peak memory 218556 kb
Host smart-299e476a-f582-4961-82d8-515c35e6fb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624715980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.624715980
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2039590438
Short name T191
Test name
Test status
Simulation time 368280889 ps
CPU time 9.7 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:24:22 PM PDT 24
Peak memory 218612 kb
Host smart-4cb477a3-bef5-4b23-a2db-9a83b8c26638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039590438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2039590438
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1197119010
Short name T192
Test name
Test status
Simulation time 4085602656 ps
CPU time 15.73 seconds
Started Aug 18 05:24:15 PM PDT 24
Finished Aug 18 05:24:31 PM PDT 24
Peak memory 219156 kb
Host smart-c5996335-0ee4-41ea-a441-166eec66298f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197119010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1197119010
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1359141952
Short name T101
Test name
Test status
Simulation time 8374833517 ps
CPU time 101.72 seconds
Started Aug 18 05:24:12 PM PDT 24
Finished Aug 18 05:25:54 PM PDT 24
Peak memory 225900 kb
Host smart-20ba3a72-ed72-4e6a-955a-a75aff04797c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359141952 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1359141952
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1619278524
Short name T260
Test name
Test status
Simulation time 1500858031 ps
CPU time 7.79 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:24:21 PM PDT 24
Peak memory 218352 kb
Host smart-ba5a740a-20c5-4091-ba7b-3d4dd8316c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619278524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1619278524
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1806435319
Short name T132
Test name
Test status
Simulation time 22186267746 ps
CPU time 262.6 seconds
Started Aug 18 05:24:14 PM PDT 24
Finished Aug 18 05:28:37 PM PDT 24
Peak memory 238148 kb
Host smart-72504bda-4059-4b67-b786-d8075ced0b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806435319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1806435319
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.962589560
Short name T261
Test name
Test status
Simulation time 1011559711 ps
CPU time 21.32 seconds
Started Aug 18 05:24:16 PM PDT 24
Finished Aug 18 05:24:38 PM PDT 24
Peak memory 218724 kb
Host smart-9e0a4a5a-26a1-4f63-937b-83ce7943948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962589560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.962589560
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.578615764
Short name T160
Test name
Test status
Simulation time 184091504 ps
CPU time 9.88 seconds
Started Aug 18 05:24:14 PM PDT 24
Finished Aug 18 05:24:24 PM PDT 24
Peak memory 218640 kb
Host smart-68295af2-298f-4dd4-86fb-294f2c8f3c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578615764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.578615764
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1846557257
Short name T227
Test name
Test status
Simulation time 552791586 ps
CPU time 26.18 seconds
Started Aug 18 05:24:12 PM PDT 24
Finished Aug 18 05:24:38 PM PDT 24
Peak memory 219072 kb
Host smart-0f5cab98-8c40-480f-bb96-34c1f6b59448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846557257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1846557257
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.456755482
Short name T239
Test name
Test status
Simulation time 8355429828 ps
CPU time 153.33 seconds
Started Aug 18 05:24:16 PM PDT 24
Finished Aug 18 05:26:49 PM PDT 24
Peak memory 226712 kb
Host smart-bed40b8e-ed8a-4678-b60b-f844f4e7369d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456755482 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.456755482
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4081667703
Short name T139
Test name
Test status
Simulation time 279327943 ps
CPU time 9.59 seconds
Started Aug 18 05:23:09 PM PDT 24
Finished Aug 18 05:23:19 PM PDT 24
Peak memory 218264 kb
Host smart-b4c473e4-5505-4f97-a659-047b098ae9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081667703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4081667703
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4101748063
Short name T166
Test name
Test status
Simulation time 1504180907 ps
CPU time 18.46 seconds
Started Aug 18 05:23:09 PM PDT 24
Finished Aug 18 05:23:27 PM PDT 24
Peak memory 218724 kb
Host smart-7e1350c2-6f8f-4dfd-9eb1-d6df24695496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101748063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4101748063
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.758525798
Short name T246
Test name
Test status
Simulation time 5047667538 ps
CPU time 11.59 seconds
Started Aug 18 05:23:10 PM PDT 24
Finished Aug 18 05:23:22 PM PDT 24
Peak memory 219168 kb
Host smart-c5e0e51e-8640-4309-b086-72b26bcc0ea3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758525798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.758525798
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1016641734
Short name T23
Test name
Test status
Simulation time 665867457 ps
CPU time 228.87 seconds
Started Aug 18 05:23:14 PM PDT 24
Finished Aug 18 05:27:03 PM PDT 24
Peak memory 238384 kb
Host smart-27238cdb-3498-4ba3-bbb1-54ccf727835e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016641734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1016641734
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1532978872
Short name T79
Test name
Test status
Simulation time 183149653 ps
CPU time 10.39 seconds
Started Aug 18 05:23:09 PM PDT 24
Finished Aug 18 05:23:20 PM PDT 24
Peak memory 219088 kb
Host smart-1f32e8e0-5c0c-4a57-a50f-33c49431cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532978872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1532978872
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.772578940
Short name T201
Test name
Test status
Simulation time 1011748364 ps
CPU time 15.97 seconds
Started Aug 18 05:23:13 PM PDT 24
Finished Aug 18 05:23:29 PM PDT 24
Peak memory 218104 kb
Host smart-630486ea-4f78-4121-a7e0-386e8984cb62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772578940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.772578940
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2946512055
Short name T221
Test name
Test status
Simulation time 5235375146 ps
CPU time 54.69 seconds
Started Aug 18 05:23:08 PM PDT 24
Finished Aug 18 05:24:03 PM PDT 24
Peak memory 233448 kb
Host smart-2c8a7024-bcf5-45fa-be05-5fdc636fd7ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946512055 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2946512055
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2519005921
Short name T51
Test name
Test status
Simulation time 1124675072 ps
CPU time 9.24 seconds
Started Aug 18 05:24:24 PM PDT 24
Finished Aug 18 05:24:34 PM PDT 24
Peak memory 218308 kb
Host smart-94b8568b-b76d-418d-b6ae-21b8288620ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519005921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2519005921
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3936031717
Short name T282
Test name
Test status
Simulation time 11207085183 ps
CPU time 299.61 seconds
Started Aug 18 05:24:16 PM PDT 24
Finished Aug 18 05:29:16 PM PDT 24
Peak memory 228452 kb
Host smart-cb473974-4073-4c48-93f7-d776d62252eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936031717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3936031717
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.173796396
Short name T284
Test name
Test status
Simulation time 343463654 ps
CPU time 18.29 seconds
Started Aug 18 05:24:15 PM PDT 24
Finished Aug 18 05:24:33 PM PDT 24
Peak memory 218456 kb
Host smart-7d9ea9f2-d0bd-4954-80a1-ec7443c73e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173796396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.173796396
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.261191763
Short name T202
Test name
Test status
Simulation time 1465400756 ps
CPU time 10.12 seconds
Started Aug 18 05:24:13 PM PDT 24
Finished Aug 18 05:24:24 PM PDT 24
Peak memory 218792 kb
Host smart-29c8be09-4b5b-4a0a-b986-687f7b713b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261191763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.261191763
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4001606929
Short name T300
Test name
Test status
Simulation time 583122434 ps
CPU time 16 seconds
Started Aug 18 05:24:12 PM PDT 24
Finished Aug 18 05:24:28 PM PDT 24
Peak memory 219128 kb
Host smart-a7a3e470-5104-4cbd-b90a-b3f2207c0ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001606929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4001606929
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.27055332
Short name T325
Test name
Test status
Simulation time 14322382973 ps
CPU time 56.53 seconds
Started Aug 18 05:24:25 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 233848 kb
Host smart-35a4b37a-033f-4536-aee9-ef7456b6f2f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27055332 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.27055332
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.20045125
Short name T162
Test name
Test status
Simulation time 916731751 ps
CPU time 9.32 seconds
Started Aug 18 05:24:23 PM PDT 24
Finished Aug 18 05:24:33 PM PDT 24
Peak memory 218408 kb
Host smart-525383f6-d609-445d-9c5f-357a2e6e8cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20045125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.20045125
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3608311454
Short name T100
Test name
Test status
Simulation time 13817666567 ps
CPU time 346.05 seconds
Started Aug 18 05:24:27 PM PDT 24
Finished Aug 18 05:30:13 PM PDT 24
Peak memory 241716 kb
Host smart-4cfd64f8-fa9c-45e3-972a-2c03cb945dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608311454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3608311454
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1441543073
Short name T161
Test name
Test status
Simulation time 7864436365 ps
CPU time 28.35 seconds
Started Aug 18 05:24:24 PM PDT 24
Finished Aug 18 05:24:53 PM PDT 24
Peak memory 219164 kb
Host smart-bc5dfce1-e440-4771-ae3b-748c81581229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441543073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1441543073
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1360196926
Short name T152
Test name
Test status
Simulation time 181365738 ps
CPU time 9.9 seconds
Started Aug 18 05:24:24 PM PDT 24
Finished Aug 18 05:24:34 PM PDT 24
Peak memory 218524 kb
Host smart-6c800715-9e41-49b9-8402-1345a1596ad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360196926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1360196926
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.235293247
Short name T31
Test name
Test status
Simulation time 1097152774 ps
CPU time 51.93 seconds
Started Aug 18 05:24:25 PM PDT 24
Finished Aug 18 05:25:17 PM PDT 24
Peak memory 219404 kb
Host smart-59ad52f1-8b87-4d26-ad6b-49da12542be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235293247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.235293247
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1869029184
Short name T33
Test name
Test status
Simulation time 4634655166 ps
CPU time 62.25 seconds
Started Aug 18 05:24:27 PM PDT 24
Finished Aug 18 05:25:29 PM PDT 24
Peak memory 231976 kb
Host smart-17a54dbd-de89-4efa-82ad-e919582ffc8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869029184 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1869029184
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2140105180
Short name T179
Test name
Test status
Simulation time 174470250 ps
CPU time 8.13 seconds
Started Aug 18 05:24:23 PM PDT 24
Finished Aug 18 05:24:31 PM PDT 24
Peak memory 218148 kb
Host smart-1fcb0947-e562-4232-9d80-1caa5da1c3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140105180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2140105180
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3720098310
Short name T333
Test name
Test status
Simulation time 2315486941 ps
CPU time 145.15 seconds
Started Aug 18 05:24:24 PM PDT 24
Finished Aug 18 05:26:50 PM PDT 24
Peak memory 235940 kb
Host smart-8ddade1b-b614-4047-9876-b8733095a129
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720098310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3720098310
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.771736497
Short name T331
Test name
Test status
Simulation time 1325198320 ps
CPU time 17.95 seconds
Started Aug 18 05:24:24 PM PDT 24
Finished Aug 18 05:24:42 PM PDT 24
Peak memory 218708 kb
Host smart-5170b183-4163-4715-be4a-b843ce9c4c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771736497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.771736497
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3119249429
Short name T296
Test name
Test status
Simulation time 184158166 ps
CPU time 10.38 seconds
Started Aug 18 05:24:25 PM PDT 24
Finished Aug 18 05:24:35 PM PDT 24
Peak memory 218784 kb
Host smart-3c2f448a-4e6f-4dea-9c15-5538e3fd0490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119249429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3119249429
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1500173685
Short name T77
Test name
Test status
Simulation time 2050372083 ps
CPU time 34.29 seconds
Started Aug 18 05:24:24 PM PDT 24
Finished Aug 18 05:24:58 PM PDT 24
Peak memory 219092 kb
Host smart-044f4fe7-2e6e-4790-881c-b673a7ba10d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500173685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1500173685
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1581793606
Short name T232
Test name
Test status
Simulation time 3839058993 ps
CPU time 156.37 seconds
Started Aug 18 05:24:27 PM PDT 24
Finished Aug 18 05:27:04 PM PDT 24
Peak memory 235592 kb
Host smart-8d2fd457-e6ad-48c5-bb0d-a16de6bacb41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581793606 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1581793606
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4063004607
Short name T172
Test name
Test status
Simulation time 174267325 ps
CPU time 7.78 seconds
Started Aug 18 05:24:25 PM PDT 24
Finished Aug 18 05:24:33 PM PDT 24
Peak memory 218376 kb
Host smart-477de53f-10ba-414e-8add-b94f4c366e16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063004607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4063004607
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4258529951
Short name T337
Test name
Test status
Simulation time 40135288518 ps
CPU time 224.75 seconds
Started Aug 18 05:24:23 PM PDT 24
Finished Aug 18 05:28:08 PM PDT 24
Peak memory 241968 kb
Host smart-43f54097-49af-4d9f-956a-87a1d9e2e4d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258529951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4258529951
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3908846258
Short name T26
Test name
Test status
Simulation time 2202591176 ps
CPU time 18.64 seconds
Started Aug 18 05:24:25 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 218936 kb
Host smart-d79230d9-83cc-4cd2-9f01-6b921d209503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908846258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3908846258
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1648248020
Short name T185
Test name
Test status
Simulation time 183622740 ps
CPU time 10.06 seconds
Started Aug 18 05:24:25 PM PDT 24
Finished Aug 18 05:24:35 PM PDT 24
Peak memory 218540 kb
Host smart-c2d12458-1a3a-421a-8cde-e78d1ceba5db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648248020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1648248020
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4177876075
Short name T9
Test name
Test status
Simulation time 505646877 ps
CPU time 25.66 seconds
Started Aug 18 05:24:23 PM PDT 24
Finished Aug 18 05:24:49 PM PDT 24
Peak memory 219040 kb
Host smart-a9101446-2499-42df-b420-9292b6e272c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177876075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4177876075
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4250893895
Short name T195
Test name
Test status
Simulation time 255778466 ps
CPU time 9.42 seconds
Started Aug 18 05:24:23 PM PDT 24
Finished Aug 18 05:24:33 PM PDT 24
Peak memory 218316 kb
Host smart-04a3bee6-5812-44df-a98a-5e2310cd7621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250893895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4250893895
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.247340610
Short name T346
Test name
Test status
Simulation time 5511008963 ps
CPU time 273.31 seconds
Started Aug 18 05:24:27 PM PDT 24
Finished Aug 18 05:29:01 PM PDT 24
Peak memory 225504 kb
Host smart-0d48ca9f-76e0-42d8-aa3b-04038ba8498f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247340610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.247340610
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3143495238
Short name T188
Test name
Test status
Simulation time 1376779788 ps
CPU time 18.41 seconds
Started Aug 18 05:24:24 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 218880 kb
Host smart-5b1c94a1-26c5-4bf1-ab9d-cd6b6f4d098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143495238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3143495238
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.735352602
Short name T36
Test name
Test status
Simulation time 296681015 ps
CPU time 11.63 seconds
Started Aug 18 05:24:25 PM PDT 24
Finished Aug 18 05:24:37 PM PDT 24
Peak memory 218804 kb
Host smart-9da075e5-1e7a-4573-9f3d-1ac2142d5d57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735352602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.735352602
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.650148671
Short name T196
Test name
Test status
Simulation time 1412262083 ps
CPU time 13.58 seconds
Started Aug 18 05:24:25 PM PDT 24
Finished Aug 18 05:24:39 PM PDT 24
Peak memory 219108 kb
Host smart-77ccaeab-2324-47df-9be4-12fd8f049923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650148671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.650148671
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1031447885
Short name T17
Test name
Test status
Simulation time 954477433 ps
CPU time 35.52 seconds
Started Aug 18 05:24:26 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 223332 kb
Host smart-659c4b64-dbe5-46c6-bc27-107ddae3f30d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031447885 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1031447885
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3844927693
Short name T303
Test name
Test status
Simulation time 340179899 ps
CPU time 8.22 seconds
Started Aug 18 05:24:28 PM PDT 24
Finished Aug 18 05:24:37 PM PDT 24
Peak memory 218348 kb
Host smart-5e1e7a69-968b-4423-815a-50f710579b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844927693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3844927693
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3139295593
Short name T356
Test name
Test status
Simulation time 1440147578 ps
CPU time 18.55 seconds
Started Aug 18 05:24:29 PM PDT 24
Finished Aug 18 05:24:48 PM PDT 24
Peak memory 218544 kb
Host smart-f4ea6817-bb81-457c-9668-257a33586ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139295593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3139295593
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4141580614
Short name T274
Test name
Test status
Simulation time 1422799250 ps
CPU time 11.26 seconds
Started Aug 18 05:24:26 PM PDT 24
Finished Aug 18 05:24:37 PM PDT 24
Peak memory 218804 kb
Host smart-cc967a53-d3c3-436e-b11b-6701c02250d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4141580614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4141580614
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3840836751
Short name T317
Test name
Test status
Simulation time 2208188396 ps
CPU time 29.37 seconds
Started Aug 18 05:24:27 PM PDT 24
Finished Aug 18 05:24:56 PM PDT 24
Peak memory 219148 kb
Host smart-e3f6a83b-e364-4c71-8db9-f171ac50659c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840836751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3840836751
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2982145610
Short name T178
Test name
Test status
Simulation time 5769231010 ps
CPU time 31.75 seconds
Started Aug 18 05:24:26 PM PDT 24
Finished Aug 18 05:24:57 PM PDT 24
Peak memory 227448 kb
Host smart-3da30bdc-f447-4ee3-b6d1-eb4571ddc6a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982145610 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2982145610
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1667783782
Short name T309
Test name
Test status
Simulation time 340543662 ps
CPU time 7.88 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:24:41 PM PDT 24
Peak memory 218292 kb
Host smart-11e0907c-b308-420b-9410-75b632416e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667783782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1667783782
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3716838144
Short name T94
Test name
Test status
Simulation time 19543507497 ps
CPU time 203.13 seconds
Started Aug 18 05:24:36 PM PDT 24
Finished Aug 18 05:27:59 PM PDT 24
Peak memory 237700 kb
Host smart-986cd0fc-e22f-48b0-a1f4-f28fe7e570a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716838144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3716838144
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3652071577
Short name T30
Test name
Test status
Simulation time 1012439746 ps
CPU time 21.79 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:24:55 PM PDT 24
Peak memory 218660 kb
Host smart-aacfd62a-2add-4b72-93a0-5ca9d166c141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652071577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3652071577
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3798671739
Short name T208
Test name
Test status
Simulation time 639503391 ps
CPU time 9.69 seconds
Started Aug 18 05:24:28 PM PDT 24
Finished Aug 18 05:24:38 PM PDT 24
Peak memory 218820 kb
Host smart-3c539aae-493c-48d2-b366-a25c35a46d50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798671739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3798671739
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1915037294
Short name T324
Test name
Test status
Simulation time 738520453 ps
CPU time 28.41 seconds
Started Aug 18 05:24:26 PM PDT 24
Finished Aug 18 05:24:55 PM PDT 24
Peak memory 218848 kb
Host smart-ea7706fc-57f9-4047-b533-b836e1530260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915037294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1915037294
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4257002282
Short name T151
Test name
Test status
Simulation time 14654205010 ps
CPU time 137.29 seconds
Started Aug 18 05:24:31 PM PDT 24
Finished Aug 18 05:26:48 PM PDT 24
Peak memory 227612 kb
Host smart-8b8f7e81-57b0-4993-99fa-2ed87cfee75d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257002282 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4257002282
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4203413540
Short name T211
Test name
Test status
Simulation time 168039452 ps
CPU time 8.05 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:24:41 PM PDT 24
Peak memory 218320 kb
Host smart-8957a8ce-80f7-4392-8329-974c9542aa36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203413540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4203413540
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1238360076
Short name T347
Test name
Test status
Simulation time 32970531103 ps
CPU time 374.86 seconds
Started Aug 18 05:24:32 PM PDT 24
Finished Aug 18 05:30:47 PM PDT 24
Peak memory 225408 kb
Host smart-85ed61fd-bd5b-4af3-9084-c982f17844ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238360076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1238360076
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3213424448
Short name T200
Test name
Test status
Simulation time 1323683082 ps
CPU time 18.16 seconds
Started Aug 18 05:24:32 PM PDT 24
Finished Aug 18 05:24:50 PM PDT 24
Peak memory 218840 kb
Host smart-dd571bb7-6060-4d96-8d73-9586709af981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213424448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3213424448
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.676552821
Short name T269
Test name
Test status
Simulation time 692071102 ps
CPU time 9.9 seconds
Started Aug 18 05:24:34 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 218744 kb
Host smart-3a9eec25-ab18-4413-aa6b-803e122d352a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676552821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.676552821
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.686290394
Short name T215
Test name
Test status
Simulation time 598012653 ps
CPU time 19.74 seconds
Started Aug 18 05:24:32 PM PDT 24
Finished Aug 18 05:24:52 PM PDT 24
Peak memory 219080 kb
Host smart-508f4aa9-249a-422c-8e12-d27bc0d8f0c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686290394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.686290394
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2413927775
Short name T171
Test name
Test status
Simulation time 13650971899 ps
CPU time 128.99 seconds
Started Aug 18 05:24:30 PM PDT 24
Finished Aug 18 05:26:39 PM PDT 24
Peak memory 235632 kb
Host smart-c0b584c1-64d5-4155-9155-640574daa0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413927775 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2413927775
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.813774256
Short name T281
Test name
Test status
Simulation time 2241166811 ps
CPU time 9.49 seconds
Started Aug 18 05:24:34 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 218336 kb
Host smart-8e716fa8-d065-4e96-919f-3055fce90c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813774256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.813774256
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3319614899
Short name T339
Test name
Test status
Simulation time 23021807942 ps
CPU time 295.7 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:29:29 PM PDT 24
Peak memory 238992 kb
Host smart-a4a644f5-3173-4d7b-a33a-6f72edcf9a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319614899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3319614899
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2387817991
Short name T306
Test name
Test status
Simulation time 2358507212 ps
CPU time 21.59 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:24:55 PM PDT 24
Peak memory 218836 kb
Host smart-54b65c33-d625-4b59-9b8e-87c8a5a800bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387817991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2387817991
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3575188759
Short name T321
Test name
Test status
Simulation time 268656773 ps
CPU time 11.54 seconds
Started Aug 18 05:24:32 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 218560 kb
Host smart-9e67ffc0-9564-408f-a083-84cd14155a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575188759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3575188759
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1495722219
Short name T58
Test name
Test status
Simulation time 1437320912 ps
CPU time 46.89 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:25:21 PM PDT 24
Peak memory 219656 kb
Host smart-baf4c9dc-2f95-4aee-9de3-7556b9c56088
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495722219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1495722219
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.233653149
Short name T344
Test name
Test status
Simulation time 688893608 ps
CPU time 7.99 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:24:41 PM PDT 24
Peak memory 218356 kb
Host smart-e030e179-d95f-4189-814b-07f8299202e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233653149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.233653149
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3673640069
Short name T231
Test name
Test status
Simulation time 15225838975 ps
CPU time 145.56 seconds
Started Aug 18 05:24:34 PM PDT 24
Finished Aug 18 05:26:59 PM PDT 24
Peak memory 239388 kb
Host smart-862b814e-042a-478b-8334-60790b86e1c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673640069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3673640069
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4115835573
Short name T181
Test name
Test status
Simulation time 1012831461 ps
CPU time 21.35 seconds
Started Aug 18 05:24:32 PM PDT 24
Finished Aug 18 05:24:54 PM PDT 24
Peak memory 218868 kb
Host smart-ace0ad40-ce12-4733-afb3-b4eca658f28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115835573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4115835573
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2790278439
Short name T326
Test name
Test status
Simulation time 674213189 ps
CPU time 9.82 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 218724 kb
Host smart-d2c1ce8e-f39d-416f-9586-11b2373db35e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790278439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2790278439
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.694971101
Short name T190
Test name
Test status
Simulation time 1140981089 ps
CPU time 26.87 seconds
Started Aug 18 05:24:32 PM PDT 24
Finished Aug 18 05:24:59 PM PDT 24
Peak memory 219072 kb
Host smart-d9d0e6f3-b9ee-422d-8c4c-fab5f10b2e60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694971101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.694971101
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2857263238
Short name T210
Test name
Test status
Simulation time 15959191728 ps
CPU time 195.31 seconds
Started Aug 18 05:24:34 PM PDT 24
Finished Aug 18 05:27:49 PM PDT 24
Peak memory 226416 kb
Host smart-7a4b4991-a2c4-4f2a-a103-7414f208a405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857263238 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2857263238
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.364748076
Short name T287
Test name
Test status
Simulation time 235029066 ps
CPU time 7.96 seconds
Started Aug 18 05:23:09 PM PDT 24
Finished Aug 18 05:23:17 PM PDT 24
Peak memory 218224 kb
Host smart-cf342513-c1c9-4ffb-87de-c0c836bfc5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364748076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.364748076
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2817172320
Short name T319
Test name
Test status
Simulation time 6241622202 ps
CPU time 245.63 seconds
Started Aug 18 05:23:13 PM PDT 24
Finished Aug 18 05:27:19 PM PDT 24
Peak memory 236584 kb
Host smart-f9c5f546-2afb-4e04-ae4a-66460cb66ba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817172320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2817172320
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4207334069
Short name T354
Test name
Test status
Simulation time 1983819615 ps
CPU time 21.41 seconds
Started Aug 18 05:23:13 PM PDT 24
Finished Aug 18 05:23:34 PM PDT 24
Peak memory 217976 kb
Host smart-e04f3268-8bad-4f44-a499-0d2a1bec46da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207334069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4207334069
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1811712147
Short name T320
Test name
Test status
Simulation time 177437820 ps
CPU time 9.99 seconds
Started Aug 18 05:23:08 PM PDT 24
Finished Aug 18 05:23:18 PM PDT 24
Peak memory 218816 kb
Host smart-f80e1585-48f1-48b3-9cbd-ca642352d291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811712147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1811712147
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4248902252
Short name T1
Test name
Test status
Simulation time 260233477 ps
CPU time 11.5 seconds
Started Aug 18 05:23:09 PM PDT 24
Finished Aug 18 05:23:20 PM PDT 24
Peak memory 218464 kb
Host smart-ec02a9b5-0f0c-4979-95e3-c2847c49933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248902252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4248902252
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1956913996
Short name T252
Test name
Test status
Simulation time 1074484043 ps
CPU time 14.54 seconds
Started Aug 18 05:23:06 PM PDT 24
Finished Aug 18 05:23:21 PM PDT 24
Peak memory 219052 kb
Host smart-7c62d9b2-eff9-4ca1-9013-2ec486f20dd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956913996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1956913996
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2898610396
Short name T137
Test name
Test status
Simulation time 5577360079 ps
CPU time 61.61 seconds
Started Aug 18 05:23:10 PM PDT 24
Finished Aug 18 05:24:11 PM PDT 24
Peak memory 233620 kb
Host smart-0f2e8676-7e48-4656-8da3-ed826f1e9cb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898610396 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2898610396
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4138033598
Short name T48
Test name
Test status
Simulation time 1377714759 ps
CPU time 9.45 seconds
Started Aug 18 05:23:06 PM PDT 24
Finished Aug 18 05:23:16 PM PDT 24
Peak memory 217976 kb
Host smart-1d3418e4-6510-4f1a-baf3-b46f0c4c197a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138033598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4138033598
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2110376897
Short name T329
Test name
Test status
Simulation time 3782671028 ps
CPU time 200.65 seconds
Started Aug 18 05:23:08 PM PDT 24
Finished Aug 18 05:26:28 PM PDT 24
Peak memory 230996 kb
Host smart-8255fd7f-386c-4c3a-a20f-b773c9f2818a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110376897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2110376897
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3972159454
Short name T250
Test name
Test status
Simulation time 2066245094 ps
CPU time 21.76 seconds
Started Aug 18 05:23:08 PM PDT 24
Finished Aug 18 05:23:30 PM PDT 24
Peak memory 218656 kb
Host smart-9f37293a-7f00-4f11-86b7-9f33db369862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972159454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3972159454
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2526585921
Short name T148
Test name
Test status
Simulation time 181109926 ps
CPU time 9.73 seconds
Started Aug 18 05:23:11 PM PDT 24
Finished Aug 18 05:23:21 PM PDT 24
Peak memory 219044 kb
Host smart-4e08a63d-10f9-4069-877b-7103b34608f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526585921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2526585921
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3080027296
Short name T78
Test name
Test status
Simulation time 429518966 ps
CPU time 10.29 seconds
Started Aug 18 05:23:09 PM PDT 24
Finished Aug 18 05:23:20 PM PDT 24
Peak memory 219104 kb
Host smart-cc464e11-73a5-4353-8052-5fdf0f9b6e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080027296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3080027296
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2781231182
Short name T67
Test name
Test status
Simulation time 2383325438 ps
CPU time 39.98 seconds
Started Aug 18 05:23:08 PM PDT 24
Finished Aug 18 05:23:48 PM PDT 24
Peak memory 219160 kb
Host smart-d643e3a9-fe33-4e7c-ab9c-f18023e3c85f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781231182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2781231182
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2865991538
Short name T135
Test name
Test status
Simulation time 10174606228 ps
CPU time 99.79 seconds
Started Aug 18 05:23:10 PM PDT 24
Finished Aug 18 05:24:50 PM PDT 24
Peak memory 228340 kb
Host smart-4e05430b-a6b8-4f91-9bf2-80c43ecac7bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865991538 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2865991538
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1502058715
Short name T276
Test name
Test status
Simulation time 332428963 ps
CPU time 7.75 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:23:27 PM PDT 24
Peak memory 218284 kb
Host smart-708f1af5-b431-484d-9151-eda26357b644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502058715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1502058715
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1187333913
Short name T305
Test name
Test status
Simulation time 5502329167 ps
CPU time 142.2 seconds
Started Aug 18 05:23:22 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 236404 kb
Host smart-f4311825-c59f-4109-a9f3-4cd4d5e7c340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187333913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1187333913
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1279079677
Short name T251
Test name
Test status
Simulation time 346315190 ps
CPU time 18.36 seconds
Started Aug 18 05:23:22 PM PDT 24
Finished Aug 18 05:23:41 PM PDT 24
Peak memory 217692 kb
Host smart-c80cc5d5-103c-41d5-9f73-cc63af81a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279079677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1279079677
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3469054969
Short name T203
Test name
Test status
Simulation time 1267704914 ps
CPU time 11.23 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:31 PM PDT 24
Peak memory 218888 kb
Host smart-7434d0cd-fc67-4ff0-85f4-f7ae353fb9aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469054969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3469054969
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2426217932
Short name T165
Test name
Test status
Simulation time 827604197 ps
CPU time 10.18 seconds
Started Aug 18 05:23:14 PM PDT 24
Finished Aug 18 05:23:24 PM PDT 24
Peak memory 218212 kb
Host smart-c1c15307-6b13-41d6-be6b-7a71ca4347b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426217932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2426217932
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3689263787
Short name T313
Test name
Test status
Simulation time 558617204 ps
CPU time 33.9 seconds
Started Aug 18 05:23:09 PM PDT 24
Finished Aug 18 05:23:43 PM PDT 24
Peak memory 219108 kb
Host smart-fb95eecc-0087-486a-9fe4-b6ed630f5711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689263787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3689263787
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2943823384
Short name T312
Test name
Test status
Simulation time 377815888 ps
CPU time 20.87 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:41 PM PDT 24
Peak memory 222924 kb
Host smart-fddf5695-239b-4b5c-89f9-619c43e90c54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943823384 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2943823384
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3432448758
Short name T330
Test name
Test status
Simulation time 664378567 ps
CPU time 7.8 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:23:40 PM PDT 24
Peak memory 218368 kb
Host smart-a45fb88c-2530-471b-8735-5a4bcdaad8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432448758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3432448758
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1880842192
Short name T131
Test name
Test status
Simulation time 7987830710 ps
CPU time 226 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:27:05 PM PDT 24
Peak memory 218524 kb
Host smart-26e32b2d-e4fb-4a59-a72e-80b5274eb13b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880842192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1880842192
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3538866212
Short name T323
Test name
Test status
Simulation time 4119939543 ps
CPU time 29.32 seconds
Started Aug 18 05:23:22 PM PDT 24
Finished Aug 18 05:23:51 PM PDT 24
Peak memory 219168 kb
Host smart-0741c76e-3ffc-4e45-a2aa-af113e248be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538866212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3538866212
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4254273544
Short name T32
Test name
Test status
Simulation time 188642221 ps
CPU time 10.27 seconds
Started Aug 18 05:23:21 PM PDT 24
Finished Aug 18 05:23:32 PM PDT 24
Peak memory 219092 kb
Host smart-502dbd6c-ce31-4357-8405-e282ab672717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254273544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4254273544
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1540051042
Short name T292
Test name
Test status
Simulation time 3130383060 ps
CPU time 57.72 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:24:18 PM PDT 24
Peak memory 220704 kb
Host smart-fc0de8b0-4a6c-4fa1-9c11-f361e6d4aeae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540051042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1540051042
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1967563921
Short name T263
Test name
Test status
Simulation time 28048189585 ps
CPU time 273.15 seconds
Started Aug 18 05:23:32 PM PDT 24
Finished Aug 18 05:28:05 PM PDT 24
Peak memory 235656 kb
Host smart-3a3e5fee-8aed-4e71-a205-3c92b2a59fe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967563921 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1967563921
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4001339180
Short name T340
Test name
Test status
Simulation time 1027868551 ps
CPU time 9.03 seconds
Started Aug 18 05:23:22 PM PDT 24
Finished Aug 18 05:23:31 PM PDT 24
Peak memory 217904 kb
Host smart-d08b0584-7202-474d-bf00-da6122968508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001339180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4001339180
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2753697410
Short name T262
Test name
Test status
Simulation time 11449213954 ps
CPU time 175.88 seconds
Started Aug 18 05:23:22 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 240368 kb
Host smart-a3d2f6a8-4420-47ad-bb79-b4b2c6394136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753697410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2753697410
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1206024254
Short name T142
Test name
Test status
Simulation time 6617873065 ps
CPU time 18.48 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:23:37 PM PDT 24
Peak memory 218920 kb
Host smart-be5f78de-e6ae-4b2e-bcc2-f3105b573eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206024254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1206024254
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2308536319
Short name T240
Test name
Test status
Simulation time 1013824011 ps
CPU time 9.74 seconds
Started Aug 18 05:23:19 PM PDT 24
Finished Aug 18 05:23:29 PM PDT 24
Peak memory 218736 kb
Host smart-50887858-18d5-4e42-9415-205de247be6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308536319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2308536319
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.830270536
Short name T229
Test name
Test status
Simulation time 183235646 ps
CPU time 9.73 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:30 PM PDT 24
Peak memory 219088 kb
Host smart-da94162a-1fe6-47c4-8973-220c36a3cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830270536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.830270536
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.794428519
Short name T82
Test name
Test status
Simulation time 689169867 ps
CPU time 26.94 seconds
Started Aug 18 05:23:20 PM PDT 24
Finished Aug 18 05:23:47 PM PDT 24
Peak memory 219112 kb
Host smart-7d19cd02-5476-40d2-acf2-1c3dd7636b98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794428519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.794428519
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.985360986
Short name T206
Test name
Test status
Simulation time 6957197618 ps
CPU time 91.37 seconds
Started Aug 18 05:23:21 PM PDT 24
Finished Aug 18 05:24:52 PM PDT 24
Peak memory 224620 kb
Host smart-453ef34b-c9b7-4033-bb42-4a9811bd89dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985360986 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.985360986
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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