Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

313736

1

T1

9

T2

10761

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	107054	1			T1	94		T2	3270		T5	60
values[0x0]	117725	1			T2	4050		T10	564		T12	1778
values[0x1]	122075	1			T2	4228		T10	625		T12	1866

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15418	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

331436

1

T1

56

T2

11154

T5

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1893	1			T2	54		T10	5		T11	2
valid_sources[0x01]	1418	1			T2	44		T10	7		T46	1
valid_sources[0x02]	1265	1			T2	42		T10	5		T11	1
valid_sources[0x03]	1363	1			T1	2		T2	52		T10	4
valid_sources[0x04]	2089	1			T2	46		T10	3		T12	25
valid_sources[0x05]	1553	1			T2	55		T5	4		T9	1
valid_sources[0x06]	1307	1			T2	36		T10	4		T11	3
valid_sources[0x07]	1541	1			T2	43		T10	5		T12	24
valid_sources[0x08]	1262	1			T2	47		T9	2		T10	9
valid_sources[0x09]	1620	1			T1	1		T2	56		T10	9
valid_sources[0x0a]	1286	1			T2	39		T10	10		T11	2
valid_sources[0x0b]	1219	1			T2	44		T8	12		T9	1
valid_sources[0x0c]	1291	1			T2	40		T10	11		T46	1
valid_sources[0x0d]	1235	1			T2	38		T10	9		T11	2
valid_sources[0x0e]	1330	1			T2	47		T9	3		T10	10
valid_sources[0x0f]	1318	1			T2	42		T9	1		T10	8
valid_sources[0x10]	1188	1			T1	1		T2	32		T10	8
valid_sources[0x11]	1346	1			T1	3		T2	44		T9	1
valid_sources[0x12]	1448	1			T2	52		T9	1		T10	3
valid_sources[0x13]	1309	1			T2	44		T9	1		T10	3
valid_sources[0x14]	1232	1			T2	44		T9	2		T10	8
valid_sources[0x15]	1375	1			T2	41		T10	4		T62	1
valid_sources[0x16]	1276	1			T2	41		T10	3		T12	5
valid_sources[0x17]	1153	1			T2	48		T10	8		T12	16
valid_sources[0x18]	1301	1			T2	31		T8	18		T10	8
valid_sources[0x19]	1227	1			T2	41		T11	1		T14	7
valid_sources[0x1a]	1730	1			T2	51		T9	1		T10	7
valid_sources[0x1b]	1288	1			T2	40		T9	2		T10	9
valid_sources[0x1c]	1263	1			T2	58		T10	4		T12	16
valid_sources[0x1d]	1208	1			T2	44		T10	2		T11	2
valid_sources[0x1e]	1717	1			T2	34		T5	3		T6	1
valid_sources[0x1f]	1212	1			T2	52		T10	7		T14	1
valid_sources[0x20]	1365	1			T2	47		T10	6		T46	1
valid_sources[0x21]	1306	1			T2	40		T8	2		T9	3
valid_sources[0x22]	1330	1			T2	36		T9	2		T10	7
valid_sources[0x23]	1254	1			T2	48		T5	3		T10	10
valid_sources[0x24]	1668	1			T2	49		T9	1		T10	1
valid_sources[0x25]	1508	1			T2	43		T8	14		T9	2
valid_sources[0x26]	1592	1			T2	36		T9	2		T10	5
valid_sources[0x27]	1747	1			T1	3		T2	62		T5	1
valid_sources[0x28]	1267	1			T2	36		T5	5		T10	7
valid_sources[0x29]	1310	1			T2	48		T9	2		T10	9
valid_sources[0x2a]	1206	1			T1	2		T2	36		T6	1
valid_sources[0x2b]	2168	1			T2	44		T9	1		T10	7
valid_sources[0x2c]	1324	1			T1	1		T2	45		T10	7
valid_sources[0x2d]	1524	1			T2	47		T5	3		T10	8
valid_sources[0x2e]	1306	1			T2	27		T9	1		T10	7
valid_sources[0x2f]	1294	1			T2	38		T6	1		T10	4
valid_sources[0x30]	1365	1			T2	54		T10	6		T16	78
valid_sources[0x31]	1159	1			T2	56		T10	9		T11	1
valid_sources[0x32]	1285	1			T2	46		T5	3		T10	5
valid_sources[0x33]	1554	1			T1	1		T2	63		T10	6
valid_sources[0x34]	1186	1			T2	33		T9	3		T10	7
valid_sources[0x35]	1296	1			T2	32		T8	11		T10	7
valid_sources[0x36]	1109	1			T2	48		T9	2		T10	13
valid_sources[0x37]	1291	1			T1	1		T2	46		T10	1
valid_sources[0x38]	1176	1			T2	37		T9	1		T10	4
valid_sources[0x39]	1167	1			T2	44		T10	4		T12	22
valid_sources[0x3a]	1180	1			T1	1		T2	39		T10	5
valid_sources[0x3b]	1268	1			T1	1		T2	50		T10	5
valid_sources[0x3c]	1419	1			T2	41		T9	1		T10	8
valid_sources[0x3d]	1204	1			T2	36		T9	1		T10	6
valid_sources[0x3e]	1331	1			T1	5		T2	47		T5	1
valid_sources[0x3f]	1254	1			T2	34		T9	1		T10	5
valid_sources[0x40]	1430	1			T2	33		T10	7		T12	19
valid_sources[0x41]	1297	1			T2	43		T9	1		T10	8
valid_sources[0x42]	1262	1			T2	70		T10	9		T11	1
valid_sources[0x43]	1276	1			T2	47		T9	1		T10	7
valid_sources[0x44]	1510	1			T2	40		T9	1		T10	7
valid_sources[0x45]	1368	1			T2	51		T9	1		T10	9
valid_sources[0x46]	1254	1			T2	54		T10	6		T12	18
valid_sources[0x47]	1154	1			T2	45		T9	2		T10	8
valid_sources[0x48]	1217	1			T2	48		T10	8		T11	2
valid_sources[0x49]	1575	1			T2	43		T9	1		T10	12
valid_sources[0x4a]	1316	1			T2	53		T10	8		T11	2
valid_sources[0x4b]	1166	1			T2	39		T9	1		T10	7
valid_sources[0x4c]	1360	1			T2	38		T9	2		T10	9
valid_sources[0x4d]	1203	1			T2	49		T9	2		T10	3
valid_sources[0x4e]	1205	1			T2	42		T8	3		T10	5
valid_sources[0x4f]	1188	1			T2	52		T9	1		T10	5
valid_sources[0x50]	1138	1			T2	40		T9	1		T10	8
valid_sources[0x51]	1327	1			T2	40		T6	1		T10	5
valid_sources[0x52]	1361	1			T2	57		T10	3		T11	1
valid_sources[0x53]	1188	1			T2	64		T8	9		T9	1
valid_sources[0x54]	1309	1			T2	45		T10	7		T11	1
valid_sources[0x55]	1358	1			T1	1		T2	49		T10	4
valid_sources[0x56]	1395	1			T2	41		T10	7		T12	20
valid_sources[0x57]	1248	1			T2	64		T5	1		T9	2
valid_sources[0x58]	1384	1			T1	3		T2	44		T9	3
valid_sources[0x59]	1281	1			T1	1		T2	50		T10	7
valid_sources[0x5a]	1398	1			T2	38		T10	10		T12	25
valid_sources[0x5b]	1263	1			T2	42		T9	3		T10	6
valid_sources[0x5c]	1275	1			T2	58		T10	6		T12	24
valid_sources[0x5d]	1248	1			T2	41		T10	11		T11	2
valid_sources[0x5e]	1701	1			T2	55		T9	2		T10	12
valid_sources[0x5f]	1106	1			T2	46		T5	4		T10	6
valid_sources[0x60]	1558	1			T2	43		T10	4		T11	2
valid_sources[0x61]	1365	1			T1	5		T2	43		T10	9
valid_sources[0x62]	1353	1			T2	55		T9	1		T10	11
valid_sources[0x63]	1227	1			T2	49		T9	2		T10	4
valid_sources[0x64]	1550	1			T2	50		T10	12		T12	14
valid_sources[0x65]	1217	1			T2	46		T9	1		T10	6
valid_sources[0x66]	1364	1			T2	48		T10	6		T46	1
valid_sources[0x67]	1375	1			T1	1		T2	40		T9	2
valid_sources[0x68]	1296	1			T1	1		T2	49		T9	1
valid_sources[0x69]	1326	1			T2	44		T10	7		T12	14
valid_sources[0x6a]	1175	1			T2	42		T9	1		T10	5
valid_sources[0x6b]	1287	1			T2	51		T9	1		T10	4
valid_sources[0x6c]	1289	1			T2	53		T9	1		T10	9
valid_sources[0x6d]	1183	1			T2	51		T8	19		T10	4
valid_sources[0x6e]	1276	1			T2	50		T9	2		T10	8
valid_sources[0x6f]	1399	1			T2	49		T5	2		T9	1
valid_sources[0x70]	1219	1			T2	48		T9	1		T10	12
valid_sources[0x71]	1116	1			T2	48		T9	1		T10	3
valid_sources[0x72]	1328	1			T2	47		T10	9		T11	2
valid_sources[0x73]	1310	1			T2	49		T10	2		T62	2
valid_sources[0x74]	1251	1			T2	55		T9	4		T10	10
valid_sources[0x75]	1376	1			T1	2		T2	58		T10	10
valid_sources[0x76]	1142	1			T2	37		T10	11		T11	2
valid_sources[0x77]	1271	1			T2	43		T9	1		T10	9
valid_sources[0x78]	1192	1			T2	43		T9	2		T10	10
valid_sources[0x79]	1227	1			T2	41		T10	6		T11	2
valid_sources[0x7a]	1384	1			T2	54		T10	7		T11	2
valid_sources[0x7b]	1389	1			T2	59		T9	1		T10	4
valid_sources[0x7c]	1492	1			T1	2		T2	41		T10	4
valid_sources[0x7d]	1247	1			T2	37		T10	9		T12	26
valid_sources[0x7e]	1340	1			T2	42		T10	5		T12	7
valid_sources[0x7f]	1616	1			T1	3		T2	46		T10	8
valid_sources[0x80]	1219	1			T2	42		T9	1		T10	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80317

1

T1

9

T2

2768

T5

3

values[0x0]

all_enables

biggest_size

116678

1

T2

4017

T10

560

T12

1765

values[0x1]

all_enables

biggest_size

116741

1

T2

3976

T10

595

T12

1779

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30823	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

269400

1

T2

8885

T3

18

T5

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80984	1			T2	2614		T3	41		T4	1
values[0x0]	102418	1			T2	3370		T7	11		T10	673
values[0x1]	116821	1			T2	3951		T7	5		T10	754

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

283932

1

T2

9441

T3

21

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	978	1			T2	31		T21	1		T47	55
valid_sources[0x01]	1099	1			T2	35		T12	32		T48	1
valid_sources[0x02]	1197	1			T2	37		T12	133		T47	1
valid_sources[0x03]	1368	1			T2	40		T48	1		T28	30
valid_sources[0x04]	929	1			T2	47		T37	1		T28	32
valid_sources[0x05]	1610	1			T2	45		T13	17		T38	1
valid_sources[0x06]	1198	1			T2	42		T28	21		T31	1
valid_sources[0x07]	1244	1			T2	42		T48	1		T28	22
valid_sources[0x08]	954	1			T2	31		T59	1		T48	19
valid_sources[0x09]	1010	1			T2	41		T5	1		T43	2
valid_sources[0x0a]	1268	1			T2	41		T28	20		T50	16
valid_sources[0x0b]	1402	1			T2	39		T6	1		T27	2
valid_sources[0x0c]	889	1			T2	28		T10	1		T48	28
valid_sources[0x0d]	1429	1			T2	39		T6	1		T10	4
valid_sources[0x0e]	1183	1			T2	46		T28	45		T49	1
valid_sources[0x0f]	1022	1			T2	41		T12	3		T37	1
valid_sources[0x10]	1202	1			T2	42		T48	5		T28	39
valid_sources[0x11]	861	1			T2	43		T28	19		T49	4
valid_sources[0x12]	1017	1			T2	29		T28	15		T49	1
valid_sources[0x13]	1113	1			T2	54		T12	44		T28	28
valid_sources[0x14]	1169	1			T2	22		T10	1		T48	3
valid_sources[0x15]	1068	1			T2	38		T7	1		T22	1
valid_sources[0x16]	1067	1			T2	53		T12	92		T28	34
valid_sources[0x17]	1143	1			T2	40		T48	12		T28	22
valid_sources[0x18]	1000	1			T2	39		T10	29		T61	1
valid_sources[0x19]	935	1			T2	31		T12	89		T28	33
valid_sources[0x1a]	1524	1			T2	32		T10	1		T47	63
valid_sources[0x1b]	1184	1			T2	40		T4	1		T6	1
valid_sources[0x1c]	1164	1			T2	25		T10	2		T48	75
valid_sources[0x1d]	1062	1			T2	23		T28	27		T29	2
valid_sources[0x1e]	1274	1			T2	42		T12	84		T28	27
valid_sources[0x1f]	920	1			T2	32		T48	15		T28	27
valid_sources[0x20]	1158	1			T2	39		T6	1		T7	2
valid_sources[0x21]	1345	1			T2	44		T17	11		T12	1
valid_sources[0x22]	898	1			T2	35		T126	2		T48	1
valid_sources[0x23]	1271	1			T2	39		T17	4		T12	128
valid_sources[0x24]	1302	1			T2	59		T38	1		T48	127
valid_sources[0x25]	1308	1			T2	60		T12	4		T28	24
valid_sources[0x26]	1050	1			T2	25		T6	1		T36	2
valid_sources[0x27]	1066	1			T2	46		T28	18		T50	13
valid_sources[0x28]	1231	1			T2	34		T48	3		T28	13
valid_sources[0x29]	1213	1			T2	31		T12	6		T71	32
valid_sources[0x2a]	1159	1			T2	34		T126	2		T48	1
valid_sources[0x2b]	1831	1			T2	58		T5	2		T12	92
valid_sources[0x2c]	1304	1			T2	24		T6	1		T21	1
valid_sources[0x2d]	1140	1			T2	47		T5	1		T10	57
valid_sources[0x2e]	1103	1			T2	39		T12	4		T48	2
valid_sources[0x2f]	1403	1			T2	27		T5	1		T10	166
valid_sources[0x30]	1016	1			T2	40		T5	3		T28	24
valid_sources[0x31]	1158	1			T2	55		T6	1		T10	180
valid_sources[0x32]	1357	1			T2	43		T7	1		T61	1
valid_sources[0x33]	909	1			T2	24		T28	34		T35	1
valid_sources[0x34]	1050	1			T2	37		T59	1		T48	1
valid_sources[0x35]	1022	1			T2	31		T6	1		T48	1
valid_sources[0x36]	1107	1			T2	27		T5	4		T7	1
valid_sources[0x37]	1104	1			T2	32		T12	2		T61	1
valid_sources[0x38]	1269	1			T2	44		T28	35		T73	2
valid_sources[0x39]	1157	1			T2	39		T6	1		T23	1
valid_sources[0x3a]	1342	1			T2	35		T36	1		T48	2
valid_sources[0x3b]	1048	1			T2	45		T10	1		T62	16
valid_sources[0x3c]	1206	1			T2	35		T59	1		T48	7
valid_sources[0x3d]	1166	1			T2	40		T12	173		T48	1
valid_sources[0x3e]	801	1			T2	25		T5	1		T48	4
valid_sources[0x3f]	1276	1			T2	30		T48	101		T28	23
valid_sources[0x40]	1649	1			T2	47		T10	191		T28	40
valid_sources[0x41]	1190	1			T2	38		T6	1		T28	18
valid_sources[0x42]	1263	1			T2	40		T28	35		T35	1
valid_sources[0x43]	1096	1			T2	40		T105	16		T61	1
valid_sources[0x44]	1016	1			T2	32		T28	25		T32	2
valid_sources[0x45]	897	1			T2	31		T6	1		T7	1
valid_sources[0x46]	1166	1			T2	44		T10	147		T28	32
valid_sources[0x47]	993	1			T2	41		T10	1		T37	1
valid_sources[0x48]	1062	1			T2	45		T37	1		T28	27
valid_sources[0x49]	1480	1			T2	47		T7	1		T12	134
valid_sources[0x4a]	1032	1			T2	37		T61	1		T48	4
valid_sources[0x4b]	943	1			T2	56		T28	24		T49	2
valid_sources[0x4c]	1047	1			T2	51		T48	2		T28	36
valid_sources[0x4d]	1069	1			T2	51		T5	1		T10	33
valid_sources[0x4e]	1317	1			T2	20		T28	17		T49	1
valid_sources[0x4f]	1336	1			T2	38		T127	1		T28	25
valid_sources[0x50]	1336	1			T2	41		T7	1		T48	1
valid_sources[0x51]	907	1			T2	24		T22	1		T48	1
valid_sources[0x52]	902	1			T2	31		T5	1		T6	1
valid_sources[0x53]	1207	1			T2	24		T6	2		T12	5
valid_sources[0x54]	1275	1			T2	41		T12	175		T60	1
valid_sources[0x55]	1251	1			T2	41		T22	1		T28	23
valid_sources[0x56]	1220	1			T2	29		T28	42		T50	15
valid_sources[0x57]	888	1			T2	30		T10	1		T48	1
valid_sources[0x58]	1314	1			T2	49		T48	106		T28	46
valid_sources[0x59]	1618	1			T2	36		T21	2		T48	179
valid_sources[0x5a]	1045	1			T2	35		T38	1		T28	26
valid_sources[0x5b]	887	1			T2	24		T28	35		T128	1
valid_sources[0x5c]	1527	1			T2	56		T10	171		T24	1
valid_sources[0x5d]	1056	1			T2	41		T14	6		T48	1
valid_sources[0x5e]	1848	1			T2	33		T60	2		T48	1
valid_sources[0x5f]	872	1			T2	35		T126	2		T48	2
valid_sources[0x60]	1154	1			T2	48		T37	1		T48	180
valid_sources[0x61]	1213	1			T2	31		T48	3		T28	25
valid_sources[0x62]	1483	1			T2	48		T10	1		T36	3
valid_sources[0x63]	1227	1			T2	47		T28	23		T49	3
valid_sources[0x64]	1129	1			T2	56		T48	1		T28	31
valid_sources[0x65]	1263	1			T2	38		T5	1		T37	1
valid_sources[0x66]	1080	1			T2	35		T48	12		T28	21
valid_sources[0x67]	1045	1			T2	48		T22	2		T48	2
valid_sources[0x68]	971	1			T2	39		T10	2		T61	1
valid_sources[0x69]	1072	1			T2	26		T47	18		T28	24
valid_sources[0x6a]	1387	1			T2	53		T12	282		T48	258
valid_sources[0x6b]	1083	1			T2	42		T10	1		T28	31
valid_sources[0x6c]	1471	1			T2	25		T12	153		T126	3
valid_sources[0x6d]	1306	1			T2	59		T6	1		T10	1
valid_sources[0x6e]	893	1			T2	37		T37	1		T28	36
valid_sources[0x6f]	1329	1			T2	35		T48	4		T28	20
valid_sources[0x70]	1239	1			T2	36		T48	2		T28	25
valid_sources[0x71]	1354	1			T2	42		T12	128		T28	26
valid_sources[0x72]	1116	1			T2	35		T37	1		T28	36
valid_sources[0x73]	1255	1			T2	32		T3	41		T21	1
valid_sources[0x74]	1604	1			T2	44		T5	1		T12	4
valid_sources[0x75]	1145	1			T2	45		T7	1		T28	25
valid_sources[0x76]	1653	1			T2	40		T5	1		T60	1
valid_sources[0x77]	1144	1			T2	30		T127	5		T28	20
valid_sources[0x78]	1427	1			T2	31		T5	1		T12	237
valid_sources[0x79]	949	1			T2	42		T46	3		T28	40
valid_sources[0x7a]	1534	1			T2	50		T126	1		T28	34
valid_sources[0x7b]	974	1			T2	54		T6	1		T10	1
valid_sources[0x7c]	945	1			T2	44		T10	3		T43	2
valid_sources[0x7d]	1287	1			T2	43		T10	3		T17	2
valid_sources[0x7e]	1489	1			T2	44		T6	1		T12	128
valid_sources[0x7f]	1218	1			T2	36		T127	1		T27	2
valid_sources[0x80]	1246	1			T2	45		T21	2		T36	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69688

1

T2

2364

T3

18

T5

17

values[0x0]

all_enables

biggest_size

99956

1

T2

3289

T7

5

T10

665

values[0x1]

all_enables

biggest_size

99756

1

T2

3232

T7

1

T10

677