Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

573599

1

T1

85

T2

23059

T5

57

full_word

363998

1

T1

9

T2

12867

T5

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	937317	1			T1	94		T2	35926		T5	60
auto[TlIntgErrCmd]	91	1			T53	4		T54	5		T55	3
auto[TlIntgErrData]	86	1			T53	8		T54	6		T55	4
auto[TlIntgErrBoth]	103	1			T53	8		T54	9		T55	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168510

1

T1

94

T2

5873

T5

60

auto[1]

769087

1

T2

30053

T10

3013

T12

12593

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	80828	1			T1	85		T2	2802		T5	57
auto[TlIntgErrNone]	partial	auto[1]	492512	1			T2	20257		T10	1732		T12	8345
auto[TlIntgErrNone]	full_word	auto[0]	87557	1			T1	9		T2	3071		T5	3
auto[TlIntgErrNone]	full_word	auto[1]	276420	1			T2	9796		T10	1281		T12	4248
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T53	2		T54	3		T55	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T53	2		T54	2		T115	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T114	1		T109	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T55	1		T117	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T53	4		T54	1		T55	2
auto[TlIntgErrData]	partial	auto[1]	37	1			T53	4		T54	5		T55	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T55	1		T108	2		T118	2
auto[TlIntgErrData]	full_word	auto[1]	2	1			T114	1		T117	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T53	3		T54	2		T55	2
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T53	5		T54	7		T55	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T110	1		T113	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T110	1		T112	1		T118	1