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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.89 92.13 97.68 100.00 98.28 98.05 98.83


Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T303 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1613779426 Aug 23 11:26:03 PM UTC 24 Aug 23 11:26:14 PM UTC 24 209258807 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.297180652 Aug 23 11:25:54 PM UTC 24 Aug 23 11:26:15 PM UTC 24 2148504741 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3304951884 Aug 23 11:23:17 PM UTC 24 Aug 23 11:26:17 PM UTC 24 7393568953 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.872626276 Aug 23 11:26:06 PM UTC 24 Aug 23 11:26:18 PM UTC 24 263827126 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1859414840 Aug 23 11:24:48 PM UTC 24 Aug 23 11:26:21 PM UTC 24 20526274861 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2035974258 Aug 23 11:25:25 PM UTC 24 Aug 23 11:26:26 PM UTC 24 4052625633 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.426997956 Aug 23 11:26:18 PM UTC 24 Aug 23 11:26:28 PM UTC 24 497093782 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3140745641 Aug 23 11:25:49 PM UTC 24 Aug 23 11:26:29 PM UTC 24 2952044260 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.2280716509 Aug 23 11:26:22 PM UTC 24 Aug 23 11:26:32 PM UTC 24 176771866 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3816064140 Aug 23 11:26:15 PM UTC 24 Aug 23 11:26:34 PM UTC 24 1226321266 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3537138317 Aug 23 11:23:15 PM UTC 24 Aug 23 11:26:37 PM UTC 24 13271778889 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2235584533 Aug 23 11:22:53 PM UTC 24 Aug 23 11:26:41 PM UTC 24 65624714910 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1744317128 Aug 23 11:22:01 PM UTC 24 Aug 23 11:26:41 PM UTC 24 5893242229 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.319992615 Aug 23 11:26:33 PM UTC 24 Aug 23 11:26:42 PM UTC 24 690334346 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.802205637 Aug 23 11:23:43 PM UTC 24 Aug 23 11:26:43 PM UTC 24 18054718690 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2229071916 Aug 23 11:26:18 PM UTC 24 Aug 23 11:26:43 PM UTC 24 1056283873 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1320326160 Aug 23 11:26:37 PM UTC 24 Aug 23 11:26:48 PM UTC 24 688481795 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3183025749 Aug 23 11:26:28 PM UTC 24 Aug 23 11:26:49 PM UTC 24 3529751755 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1381313345 Aug 23 11:26:44 PM UTC 24 Aug 23 11:26:52 PM UTC 24 339180391 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3031084562 Aug 23 11:23:37 PM UTC 24 Aug 23 11:26:55 PM UTC 24 43120597215 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.811377292 Aug 23 11:26:49 PM UTC 24 Aug 23 11:27:01 PM UTC 24 530905385 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2023113492 Aug 23 11:23:27 PM UTC 24 Aug 23 11:27:01 PM UTC 24 14745486496 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3056529620 Aug 23 11:26:16 PM UTC 24 Aug 23 11:27:02 PM UTC 24 3454534688 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.537213826 Aug 23 11:26:42 PM UTC 24 Aug 23 11:27:02 PM UTC 24 4120561961 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3144317641 Aug 23 11:26:45 PM UTC 24 Aug 23 11:27:03 PM UTC 24 203741608 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.2462177830 Aug 23 11:27:01 PM UTC 24 Aug 23 11:27:11 PM UTC 24 260151903 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.321344688 Aug 23 11:26:53 PM UTC 24 Aug 23 11:27:11 PM UTC 24 1379064194 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3224377270 Aug 23 11:24:16 PM UTC 24 Aug 23 11:27:15 PM UTC 24 32279146341 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.4042507403 Aug 23 11:26:34 PM UTC 24 Aug 23 11:27:16 PM UTC 24 2478749752 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1370631062 Aug 23 11:23:33 PM UTC 24 Aug 23 11:27:18 PM UTC 24 7107365373 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.875884255 Aug 23 11:27:03 PM UTC 24 Aug 23 11:27:18 PM UTC 24 1529099062 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1437329739 Aug 23 11:27:11 PM UTC 24 Aug 23 11:27:21 PM UTC 24 254019252 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.675563983 Aug 23 11:27:03 PM UTC 24 Aug 23 11:27:24 PM UTC 24 2601585622 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1942586452 Aug 23 11:27:15 PM UTC 24 Aug 23 11:27:27 PM UTC 24 1017369431 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1310823594 Aug 23 11:25:44 PM UTC 24 Aug 23 11:27:30 PM UTC 24 12480759414 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.115789325 Aug 23 11:24:36 PM UTC 24 Aug 23 11:27:30 PM UTC 24 13644870218 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1902772609 Aug 23 11:27:12 PM UTC 24 Aug 23 11:27:34 PM UTC 24 5178171418 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.625947579 Aug 23 11:27:21 PM UTC 24 Aug 23 11:27:35 PM UTC 24 1971355900 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3882132112 Aug 23 11:27:08 PM UTC 24 Aug 23 11:27:35 PM UTC 24 700210073 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.186144982 Aug 23 11:27:19 PM UTC 24 Aug 23 11:28:55 PM UTC 24 5424093579 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.4210720420 Aug 23 11:27:18 PM UTC 24 Aug 23 11:27:39 PM UTC 24 2062162157 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.860648076 Aug 23 11:27:02 PM UTC 24 Aug 23 11:27:42 PM UTC 24 732174248 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1880268389 Aug 23 11:24:12 PM UTC 24 Aug 23 11:27:44 PM UTC 24 7405639125 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3204716127 Aug 23 11:26:56 PM UTC 24 Aug 23 11:27:46 PM UTC 24 5968953394 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1255250892 Aug 23 11:22:19 PM UTC 24 Aug 23 11:27:47 PM UTC 24 18517362958 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.879272883 Aug 23 11:23:58 PM UTC 24 Aug 23 11:27:56 PM UTC 24 20174606688 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1670867440 Aug 23 11:24:21 PM UTC 24 Aug 23 11:28:07 PM UTC 24 4785777187 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4113745714 Aug 23 11:24:44 PM UTC 24 Aug 23 11:28:09 PM UTC 24 3778237345 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3015187807 Aug 23 11:25:00 PM UTC 24 Aug 23 11:28:21 PM UTC 24 13722498260 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1467463104 Aug 23 11:24:54 PM UTC 24 Aug 23 11:28:30 PM UTC 24 34190081101 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.790146784 Aug 23 11:25:23 PM UTC 24 Aug 23 11:28:30 PM UTC 24 18308500097 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2785220314 Aug 23 11:24:33 PM UTC 24 Aug 23 11:28:36 PM UTC 24 8076286912 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1052337811 Aug 23 11:25:58 PM UTC 24 Aug 23 11:28:42 PM UTC 24 4576449275 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2723289051 Aug 23 11:26:50 PM UTC 24 Aug 23 11:28:43 PM UTC 24 10538749939 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.813582846 Aug 23 11:26:42 PM UTC 24 Aug 23 11:29:36 PM UTC 24 27822150952 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2100101759 Aug 23 11:25:12 PM UTC 24 Aug 23 11:29:38 PM UTC 24 14334333726 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.437150681 Aug 23 11:26:29 PM UTC 24 Aug 23 11:29:44 PM UTC 24 10615344806 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3823952865 Aug 23 11:26:27 PM UTC 24 Aug 23 11:29:51 PM UTC 24 4427371497 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1554259645 Aug 23 11:25:53 PM UTC 24 Aug 23 11:29:54 PM UTC 24 5246767083 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4078032781 Aug 23 11:27:03 PM UTC 24 Aug 23 11:30:29 PM UTC 24 9645343678 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1158922064 Aug 23 11:26:12 PM UTC 24 Aug 23 11:30:34 PM UTC 24 21589611454 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.309666733 Aug 23 11:25:34 PM UTC 24 Aug 23 11:30:35 PM UTC 24 6211784601 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3558964546 Aug 23 11:27:17 PM UTC 24 Aug 23 11:30:40 PM UTC 24 8888947392 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2376162312 Aug 23 11:27:31 PM UTC 24 Aug 23 11:27:39 PM UTC 24 172505397 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.859757974 Aug 23 11:27:28 PM UTC 24 Aug 23 11:27:41 PM UTC 24 1463813091 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.348317379 Aug 23 11:27:36 PM UTC 24 Aug 23 11:27:45 PM UTC 24 1077943118 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1385713490 Aug 23 11:27:40 PM UTC 24 Aug 23 11:27:48 PM UTC 24 171660965 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2824901149 Aug 23 11:27:40 PM UTC 24 Aug 23 11:27:48 PM UTC 24 169622239 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2076733924 Aug 23 11:27:36 PM UTC 24 Aug 23 11:27:49 PM UTC 24 5790403028 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.191236679 Aug 23 11:27:40 PM UTC 24 Aug 23 11:27:49 PM UTC 24 262984546 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1060609655 Aug 23 11:27:41 PM UTC 24 Aug 23 11:27:50 PM UTC 24 185179179 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.105317949 Aug 23 11:27:36 PM UTC 24 Aug 23 11:27:55 PM UTC 24 1018710168 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2643699247 Aug 23 11:27:47 PM UTC 24 Aug 23 11:27:56 PM UTC 24 489391281 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2359981103 Aug 23 11:27:47 PM UTC 24 Aug 23 11:27:57 PM UTC 24 1455560002 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2349941506 Aug 23 11:27:49 PM UTC 24 Aug 23 11:27:58 PM UTC 24 691336555 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1532244823 Aug 23 11:27:49 PM UTC 24 Aug 23 11:27:59 PM UTC 24 1076555905 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3279848733 Aug 23 11:27:45 PM UTC 24 Aug 23 11:28:00 PM UTC 24 517757679 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3912039962 Aug 23 11:27:50 PM UTC 24 Aug 23 11:28:00 PM UTC 24 2065182371 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3257135798 Aug 23 11:27:50 PM UTC 24 Aug 23 11:28:00 PM UTC 24 988931339 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2627192665 Aug 23 11:27:49 PM UTC 24 Aug 23 11:28:04 PM UTC 24 3337456428 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1728920889 Aug 23 11:27:56 PM UTC 24 Aug 23 11:28:05 PM UTC 24 170673796 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.166571021 Aug 23 11:27:58 PM UTC 24 Aug 23 11:28:08 PM UTC 24 994195856 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2976423441 Aug 23 11:28:01 PM UTC 24 Aug 23 11:28:09 PM UTC 24 174483836 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3350003351 Aug 23 11:27:57 PM UTC 24 Aug 23 11:28:10 PM UTC 24 259486304 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2686511888 Aug 23 11:27:59 PM UTC 24 Aug 23 11:28:12 PM UTC 24 1007025430 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1946428485 Aug 23 11:28:00 PM UTC 24 Aug 23 11:28:13 PM UTC 24 514239078 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1631630759 Aug 23 11:28:01 PM UTC 24 Aug 23 11:28:14 PM UTC 24 2043017652 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1233464792 Aug 23 11:28:05 PM UTC 24 Aug 23 11:28:14 PM UTC 24 1030094536 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4158327374 Aug 23 11:28:08 PM UTC 24 Aug 23 11:28:16 PM UTC 24 367580048 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.586816566 Aug 23 11:28:06 PM UTC 24 Aug 23 11:28:19 PM UTC 24 1029873452 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1500317820 Aug 23 11:28:11 PM UTC 24 Aug 23 11:28:19 PM UTC 24 339400373 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2043304946 Aug 23 11:28:13 PM UTC 24 Aug 23 11:28:21 PM UTC 24 167698109 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1715368636 Aug 23 11:28:14 PM UTC 24 Aug 23 11:28:22 PM UTC 24 1653278983 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.760588752 Aug 23 11:28:10 PM UTC 24 Aug 23 11:28:22 PM UTC 24 346994635 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2112367483 Aug 23 11:27:24 PM UTC 24 Aug 23 11:28:24 PM UTC 24 3055607903 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.808016157 Aug 23 11:28:15 PM UTC 24 Aug 23 11:28:25 PM UTC 24 250099382 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2932000597 Aug 23 11:27:43 PM UTC 24 Aug 23 11:28:25 PM UTC 24 1019163711 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2575964851 Aug 23 11:28:17 PM UTC 24 Aug 23 11:28:25 PM UTC 24 661153108 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.512988596 Aug 23 11:28:14 PM UTC 24 Aug 23 11:28:27 PM UTC 24 256457045 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2257310105 Aug 23 11:28:20 PM UTC 24 Aug 23 11:28:28 PM UTC 24 168485998 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1071402619 Aug 23 11:28:20 PM UTC 24 Aug 23 11:28:31 PM UTC 24 2607541049 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3311269188 Aug 23 11:28:23 PM UTC 24 Aug 23 11:28:33 PM UTC 24 280058825 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.764688309 Aug 23 11:28:24 PM UTC 24 Aug 23 11:28:33 PM UTC 24 332539504 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.328432085 Aug 23 11:28:25 PM UTC 24 Aug 23 11:28:34 PM UTC 24 176900798 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2690038753 Aug 23 11:28:22 PM UTC 24 Aug 23 11:28:36 PM UTC 24 496847156 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3273517461 Aug 23 11:28:26 PM UTC 24 Aug 23 11:28:36 PM UTC 24 617352082 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1880706246 Aug 23 11:28:27 PM UTC 24 Aug 23 11:28:37 PM UTC 24 452148892 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.814490131 Aug 23 11:28:29 PM UTC 24 Aug 23 11:28:38 PM UTC 24 689683990 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1434654632 Aug 23 11:28:25 PM UTC 24 Aug 23 11:28:40 PM UTC 24 241199330 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.432687556 Aug 23 11:28:31 PM UTC 24 Aug 23 11:28:40 PM UTC 24 1927307700 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3441152062 Aug 23 11:28:34 PM UTC 24 Aug 23 11:28:42 PM UTC 24 168097190 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1160078985 Aug 23 11:28:35 PM UTC 24 Aug 23 11:28:44 PM UTC 24 527181706 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2207343016 Aug 23 11:28:37 PM UTC 24 Aug 23 11:28:47 PM UTC 24 1034089572 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.354932592 Aug 23 11:28:33 PM UTC 24 Aug 23 11:28:47 PM UTC 24 1374185919 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3278714005 Aug 23 11:28:39 PM UTC 24 Aug 23 11:28:47 PM UTC 24 174194541 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.367640423 Aug 23 11:28:37 PM UTC 24 Aug 23 11:28:49 PM UTC 24 1034756893 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4013851062 Aug 23 11:28:41 PM UTC 24 Aug 23 11:28:51 PM UTC 24 259929029 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1401666675 Aug 23 11:28:41 PM UTC 24 Aug 23 11:28:53 PM UTC 24 1233073437 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.8671068 Aug 23 11:28:45 PM UTC 24 Aug 23 11:28:55 PM UTC 24 1903820003 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2325750544 Aug 23 11:28:43 PM UTC 24 Aug 23 11:28:56 PM UTC 24 508067290 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.356641474 Aug 23 11:27:56 PM UTC 24 Aug 23 11:28:56 PM UTC 24 6094798095 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3892077482 Aug 23 11:28:47 PM UTC 24 Aug 23 11:28:56 PM UTC 24 794591849 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.577173096 Aug 23 11:28:47 PM UTC 24 Aug 23 11:28:57 PM UTC 24 496505791 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1256420455 Aug 23 11:27:46 PM UTC 24 Aug 23 11:29:00 PM UTC 24 467135063 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1767915224 Aug 23 11:28:22 PM UTC 24 Aug 23 11:29:03 PM UTC 24 4234663758 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.201692261 Aug 23 11:28:53 PM UTC 24 Aug 23 11:29:03 PM UTC 24 851504303 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3897860506 Aug 23 11:28:50 PM UTC 24 Aug 23 11:29:03 PM UTC 24 590870621 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3729254576 Aug 23 11:28:55 PM UTC 24 Aug 23 11:29:04 PM UTC 24 3329515006 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2978490125 Aug 23 11:28:55 PM UTC 24 Aug 23 11:29:05 PM UTC 24 1897361604 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3812339796 Aug 23 11:28:58 PM UTC 24 Aug 23 11:29:06 PM UTC 24 1830231618 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.619638414 Aug 23 11:28:31 PM UTC 24 Aug 23 11:29:06 PM UTC 24 1381182861 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3339737025 Aug 23 11:28:56 PM UTC 24 Aug 23 11:29:09 PM UTC 24 176258732 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2749503817 Aug 23 11:28:37 PM UTC 24 Aug 23 11:29:12 PM UTC 24 703935943 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.532869645 Aug 23 11:29:01 PM UTC 24 Aug 23 11:29:14 PM UTC 24 981225394 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1261244418 Aug 23 11:29:04 PM UTC 24 Aug 23 11:29:14 PM UTC 24 1105583628 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1638988168 Aug 23 11:29:06 PM UTC 24 Aug 23 11:29:14 PM UTC 24 174495578 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3993258805 Aug 23 11:29:07 PM UTC 24 Aug 23 11:29:16 PM UTC 24 707808819 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3639401355 Aug 23 11:29:04 PM UTC 24 Aug 23 11:29:16 PM UTC 24 167617662 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3957586521 Aug 23 11:29:07 PM UTC 24 Aug 23 11:29:21 PM UTC 24 1016541288 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2283506381 Aug 23 11:29:15 PM UTC 24 Aug 23 11:29:23 PM UTC 24 1031956177 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.919828141 Aug 23 11:29:12 PM UTC 24 Aug 23 11:29:25 PM UTC 24 256863932 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.203451697 Aug 23 11:29:15 PM UTC 24 Aug 23 11:29:25 PM UTC 24 505970599 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3017592483 Aug 23 11:29:16 PM UTC 24 Aug 23 11:29:25 PM UTC 24 1154729128 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.137981057 Aug 23 11:28:10 PM UTC 24 Aug 23 11:29:25 PM UTC 24 538470366 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.316725825 Aug 23 11:28:09 PM UTC 24 Aug 23 11:29:28 PM UTC 24 6174988667 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3044258970 Aug 23 11:29:25 PM UTC 24 Aug 23 11:29:34 PM UTC 24 339206191 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3750811710 Aug 23 11:29:25 PM UTC 24 Aug 23 11:29:35 PM UTC 24 257031166 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.213515988 Aug 23 11:29:25 PM UTC 24 Aug 23 11:29:36 PM UTC 24 521978482 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2942164618 Aug 23 11:29:21 PM UTC 24 Aug 23 11:29:36 PM UTC 24 1036728182 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1562503268 Aug 23 11:28:23 PM UTC 24 Aug 23 11:29:38 PM UTC 24 648833907 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1231305366 Aug 23 11:28:48 PM UTC 24 Aug 23 11:29:40 PM UTC 24 1095130644 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2930190084 Aug 23 11:29:29 PM UTC 24 Aug 23 11:29:41 PM UTC 24 252346541 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3495309037 Aug 23 11:28:43 PM UTC 24 Aug 23 11:29:43 PM UTC 24 7617541351 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4212139010 Aug 23 11:29:35 PM UTC 24 Aug 23 11:29:44 PM UTC 24 2353856131 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2410108017 Aug 23 11:29:37 PM UTC 24 Aug 23 11:29:45 PM UTC 24 167607239 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.628134918 Aug 23 11:29:11 PM UTC 24 Aug 23 11:29:46 PM UTC 24 2640591349 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.450584199 Aug 23 11:29:37 PM UTC 24 Aug 23 11:29:46 PM UTC 24 526760355 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.683522931 Aug 23 11:28:34 PM UTC 24 Aug 23 11:29:47 PM UTC 24 859629923 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3407236003 Aug 23 11:28:56 PM UTC 24 Aug 23 11:29:48 PM UTC 24 2020669555 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.262100632 Aug 23 11:29:39 PM UTC 24 Aug 23 11:29:50 PM UTC 24 824610720 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.957830467 Aug 23 11:29:41 PM UTC 24 Aug 23 11:29:50 PM UTC 24 251923082 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.133243365 Aug 23 11:29:42 PM UTC 24 Aug 23 11:29:51 PM UTC 24 564315609 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3543543141 Aug 23 11:29:17 PM UTC 24 Aug 23 11:29:52 PM UTC 24 2235237866 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2383262296 Aug 23 11:29:44 PM UTC 24 Aug 23 11:29:54 PM UTC 24 1028466080 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2673672807 Aug 23 11:27:31 PM UTC 24 Aug 23 11:29:54 PM UTC 24 1103796059 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3362420617 Aug 23 11:29:45 PM UTC 24 Aug 23 11:29:56 PM UTC 24 717832639 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1621151845 Aug 23 11:29:47 PM UTC 24 Aug 23 11:29:57 PM UTC 24 259857851 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4109884092 Aug 23 11:29:48 PM UTC 24 Aug 23 11:29:58 PM UTC 24 921584846 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3798820145 Aug 23 11:28:44 PM UTC 24 Aug 23 11:29:58 PM UTC 24 1276943375 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2015042094 Aug 23 11:29:47 PM UTC 24 Aug 23 11:30:00 PM UTC 24 1027383339 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.743777972 Aug 23 11:29:51 PM UTC 24 Aug 23 11:30:01 PM UTC 24 884025689 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4241372990 Aug 23 11:29:26 PM UTC 24 Aug 23 11:30:01 PM UTC 24 2867131492 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1795903770 Aug 23 11:29:52 PM UTC 24 Aug 23 11:30:02 PM UTC 24 249723883 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3152672432 Aug 23 11:29:04 PM UTC 24 Aug 23 11:30:03 PM UTC 24 6363313097 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1095544853 Aug 23 11:29:53 PM UTC 24 Aug 23 11:30:03 PM UTC 24 189844771 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.854826157 Aug 23 11:29:51 PM UTC 24 Aug 23 11:30:04 PM UTC 24 257801172 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3587396852 Aug 23 11:29:57 PM UTC 24 Aug 23 11:30:05 PM UTC 24 340077576 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3107658527 Aug 23 11:28:51 PM UTC 24 Aug 23 11:30:06 PM UTC 24 248150521 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.649643998 Aug 23 11:29:59 PM UTC 24 Aug 23 11:30:07 PM UTC 24 342109908 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.907277240 Aug 23 11:29:58 PM UTC 24 Aug 23 11:30:07 PM UTC 24 255492229 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3741419202 Aug 23 11:29:55 PM UTC 24 Aug 23 11:30:10 PM UTC 24 255720766 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2129440176 Aug 23 11:30:02 PM UTC 24 Aug 23 11:30:11 PM UTC 24 988469205 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3103897924 Aug 23 11:30:03 PM UTC 24 Aug 23 11:30:13 PM UTC 24 1054003305 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2256303946 Aug 23 11:30:06 PM UTC 24 Aug 23 11:30:14 PM UTC 24 168381097 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3772781707 Aug 23 11:30:03 PM UTC 24 Aug 23 11:30:15 PM UTC 24 2451733542 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2821206973 Aug 23 11:27:57 PM UTC 24 Aug 23 11:30:16 PM UTC 24 278023836 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.454403315 Aug 23 11:30:08 PM UTC 24 Aug 23 11:30:17 PM UTC 24 249469170 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1187312176 Aug 23 11:30:08 PM UTC 24 Aug 23 11:30:18 PM UTC 24 1031734273 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1546544883 Aug 23 11:30:05 PM UTC 24 Aug 23 11:30:18 PM UTC 24 255237704 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2672631599 Aug 23 11:29:45 PM UTC 24 Aug 23 11:30:25 PM UTC 24 4220509903 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1188311304 Aug 23 11:29:37 PM UTC 24 Aug 23 11:30:28 PM UTC 24 2152816269 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1019653831 Aug 23 11:29:14 PM UTC 24 Aug 23 11:30:29 PM UTC 24 3485710924 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2646551786 Aug 23 11:29:49 PM UTC 24 Aug 23 11:30:29 PM UTC 24 1073997829 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.576560800 Aug 23 11:29:59 PM UTC 24 Aug 23 11:30:39 PM UTC 24 3621381208 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2412302271 Aug 23 11:29:24 PM UTC 24 Aug 23 11:30:39 PM UTC 24 1026854057 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2770476661 Aug 23 11:30:04 PM UTC 24 Aug 23 11:30:44 PM UTC 24 1065391203 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2286890958 Aug 23 11:29:54 PM UTC 24 Aug 23 11:30:47 PM UTC 24 8575844617 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3568196071 Aug 23 11:29:34 PM UTC 24 Aug 23 11:30:49 PM UTC 24 1251767034 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3164164136 Aug 23 11:29:39 PM UTC 24 Aug 23 11:30:53 PM UTC 24 259466318 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3678831407 Aug 23 11:28:38 PM UTC 24 Aug 23 11:31:00 PM UTC 24 5037834782 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2921496150 Aug 23 11:29:51 PM UTC 24 Aug 23 11:31:07 PM UTC 24 758419315 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1829024542 Aug 23 11:29:55 PM UTC 24 Aug 23 11:31:11 PM UTC 24 358960934 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2067023581 Aug 23 11:30:02 PM UTC 24 Aug 23 11:31:18 PM UTC 24 336215754 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3182931392 Aug 23 11:28:56 PM UTC 24 Aug 23 11:31:19 PM UTC 24 600161050 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1542359554 Aug 23 11:30:05 PM UTC 24 Aug 23 11:31:20 PM UTC 24 2311637068 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3576690430 Aug 23 11:29:05 PM UTC 24 Aug 23 11:31:26 PM UTC 24 1876330004 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2262016215 Aug 23 11:29:46 PM UTC 24 Aug 23 11:32:07 PM UTC 24 1529151834 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2505273555
Short name T4
Test name
Test status
Simulation time 2135120831 ps
CPU time 21.3 seconds
Started Aug 23 11:17:35 PM UTC 24
Finished Aug 23 11:17:58 PM UTC 24
Peak memory 228704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250527355
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.2505273555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2632750167
Short name T13
Test name
Test status
Simulation time 1948304153 ps
CPU time 36.08 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:27 PM UTC 24
Peak memory 232868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2632750167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2632750167
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3887921624
Short name T26
Test name
Test status
Simulation time 2797966420 ps
CPU time 154.35 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:20:26 PM UTC 24
Peak memory 243936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887921624 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.3887921624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.883960503
Short name T11
Test name
Test status
Simulation time 1375544649 ps
CPU time 17.22 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:07 PM UTC 24
Peak memory 228788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883960503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.883960503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4090426193
Short name T64
Test name
Test status
Simulation time 1910916718 ps
CPU time 69.49 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:19:00 PM UTC 24
Peak memory 232628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4090426193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.rom_ctrl_stress_all_with_rand_reset.4090426193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2673672807
Short name T131
Test name
Test status
Simulation time 1103796059 ps
CPU time 140.76 seconds
Started Aug 23 11:27:31 PM UTC 24
Finished Aug 23 11:29:54 PM UTC 24
Peak memory 225920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673672807 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.2673672807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.244299821
Short name T51
Test name
Test status
Simulation time 5686495750 ps
CPU time 171.78 seconds
Started Aug 23 11:18:35 PM UTC 24
Finished Aug 23 11:21:30 PM UTC 24
Peak memory 245864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244299821 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.244299821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.4113404189
Short name T16
Test name
Test status
Simulation time 189254114 ps
CPU time 9.98 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:01 PM UTC 24
Peak memory 228640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113404189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4113404189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1385426365
Short name T18
Test name
Test status
Simulation time 5035134059 ps
CPU time 49.55 seconds
Started Aug 23 11:18:30 PM UTC 24
Finished Aug 23 11:19:21 PM UTC 24
Peak memory 239076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1385426365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1385426365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3379112045
Short name T12
Test name
Test status
Simulation time 689213566 ps
CPU time 17.24 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:08 PM UTC 24
Peak memory 228640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379112045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3379112045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2946017259
Short name T39
Test name
Test status
Simulation time 873270092 ps
CPU time 215.59 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:21:28 PM UTC 24
Peak memory 258508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946017259 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2946017259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2076733924
Short name T80
Test name
Test status
Simulation time 5790403028 ps
CPU time 11.75 seconds
Started Aug 23 11:27:36 PM UTC 24
Finished Aug 23 11:27:49 PM UTC 24
Peak memory 223924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076733924 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2076733924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1135391694
Short name T83
Test name
Test status
Simulation time 1086604712 ps
CPU time 12.19 seconds
Started Aug 23 11:18:23 PM UTC 24
Finished Aug 23 11:18:36 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135391694 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1135391694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3678831407
Short name T132
Test name
Test status
Simulation time 5037834782 ps
CPU time 140.15 seconds
Started Aug 23 11:28:38 PM UTC 24
Finished Aug 23 11:31:00 PM UTC 24
Peak memory 226048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678831407 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.3678831407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.12163444
Short name T24
Test name
Test status
Simulation time 3819520363 ps
CPU time 95.55 seconds
Started Aug 23 11:18:02 PM UTC 24
Finished Aug 23 11:19:40 PM UTC 24
Peak memory 257424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12163444 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.12163444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.316725825
Short name T100
Test name
Test status
Simulation time 6174988667 ps
CPU time 77.67 seconds
Started Aug 23 11:28:09 PM UTC 24
Finished Aug 23 11:29:28 PM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316725825 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.316725825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3182931392
Short name T138
Test name
Test status
Simulation time 600161050 ps
CPU time 140.13 seconds
Started Aug 23 11:28:56 PM UTC 24
Finished Aug 23 11:31:19 PM UTC 24
Peak memory 225920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182931392 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.3182931392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3960409963
Short name T7
Test name
Test status
Simulation time 1604109443 ps
CPU time 9.68 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:00 PM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960409963 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3960409963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.778672738
Short name T54
Test name
Test status
Simulation time 5497083133 ps
CPU time 19.57 seconds
Started Aug 23 11:18:19 PM UTC 24
Finished Aug 23 11:18:39 PM UTC 24
Peak memory 228892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778672738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.778672738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2112367483
Short name T117
Test name
Test status
Simulation time 3055607903 ps
CPU time 57.96 seconds
Started Aug 23 11:27:24 PM UTC 24
Finished Aug 23 11:28:24 PM UTC 24
Peak memory 226004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112367483 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.2112367483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1019653831
Short name T140
Test name
Test status
Simulation time 3485710924 ps
CPU time 73.19 seconds
Started Aug 23 11:29:14 PM UTC 24
Finished Aug 23 11:30:29 PM UTC 24
Peak memory 226104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019653831 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.1019653831
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2821206973
Short name T136
Test name
Test status
Simulation time 278023836 ps
CPU time 136.64 seconds
Started Aug 23 11:27:57 PM UTC 24
Finished Aug 23 11:30:16 PM UTC 24
Peak memory 225916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821206973 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.2821206973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.791597083
Short name T48
Test name
Test status
Simulation time 19582710679 ps
CPU time 209.7 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:21:22 PM UTC 24
Peak memory 256404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791597083 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.791597083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3482430906
Short name T106
Test name
Test status
Simulation time 1084247497 ps
CPU time 10.84 seconds
Started Aug 23 11:21:26 PM UTC 24
Finished Aug 23 11:21:38 PM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482430906 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3482430906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3026185672
Short name T19
Test name
Test status
Simulation time 6717259715 ps
CPU time 122.02 seconds
Started Aug 23 11:23:47 PM UTC 24
Finished Aug 23 11:25:51 PM UTC 24
Peak memory 246468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3026185672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3026185672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.4191552752
Short name T44
Test name
Test status
Simulation time 432877283 ps
CPU time 17.26 seconds
Started Aug 23 11:19:25 PM UTC 24
Finished Aug 23 11:19:43 PM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191552752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4191552752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.191236679
Short name T122
Test name
Test status
Simulation time 262984546 ps
CPU time 8.47 seconds
Started Aug 23 11:27:40 PM UTC 24
Finished Aug 23 11:27:49 PM UTC 24
Peak memory 221880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191236679 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.191236679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2824901149
Short name T79
Test name
Test status
Simulation time 169622239 ps
CPU time 7.59 seconds
Started Aug 23 11:27:40 PM UTC 24
Finished Aug 23 11:27:48 PM UTC 24
Peak memory 221944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824901149 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.2824901149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.105317949
Short name T123
Test name
Test status
Simulation time 1018710168 ps
CPU time 18 seconds
Started Aug 23 11:27:36 PM UTC 24
Finished Aug 23 11:27:55 PM UTC 24
Peak memory 223864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105317949 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.105317949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1060609655
Short name T367
Test name
Test status
Simulation time 185179179 ps
CPU time 7.77 seconds
Started Aug 23 11:27:41 PM UTC 24
Finished Aug 23 11:27:50 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1060609655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
om_ctrl_csr_mem_rw_with_rand_reset.1060609655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.348317379
Short name T366
Test name
Test status
Simulation time 1077943118 ps
CPU time 8.47 seconds
Started Aug 23 11:27:36 PM UTC 24
Finished Aug 23 11:27:45 PM UTC 24
Peak memory 221744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348317379 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.348317379
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2376162312
Short name T364
Test name
Test status
Simulation time 172505397 ps
CPU time 7.15 seconds
Started Aug 23 11:27:31 PM UTC 24
Finished Aug 23 11:27:39 PM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376162312 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.2376162312
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1385713490
Short name T78
Test name
Test status
Simulation time 171660965 ps
CPU time 7.14 seconds
Started Aug 23 11:27:40 PM UTC 24
Finished Aug 23 11:27:48 PM UTC 24
Peak memory 221800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385713490 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.1385713490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.859757974
Short name T365
Test name
Test status
Simulation time 1463813091 ps
CPU time 11.78 seconds
Started Aug 23 11:27:28 PM UTC 24
Finished Aug 23 11:27:41 PM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859757974 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.859757974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3912039962
Short name T125
Test name
Test status
Simulation time 2065182371 ps
CPU time 8.45 seconds
Started Aug 23 11:27:50 PM UTC 24
Finished Aug 23 11:28:00 PM UTC 24
Peak memory 221944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912039962 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.3912039962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2349941506
Short name T84
Test name
Test status
Simulation time 691336555 ps
CPU time 7.34 seconds
Started Aug 23 11:27:49 PM UTC 24
Finished Aug 23 11:27:58 PM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349941506 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.2349941506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2627192665
Short name T126
Test name
Test status
Simulation time 3337456428 ps
CPU time 13.5 seconds
Started Aug 23 11:27:49 PM UTC 24
Finished Aug 23 11:28:04 PM UTC 24
Peak memory 223704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627192665 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.2627192665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1728920889
Short name T371
Test name
Test status
Simulation time 170673796 ps
CPU time 7.51 seconds
Started Aug 23 11:27:56 PM UTC 24
Finished Aug 23 11:28:05 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1728920889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
om_ctrl_csr_mem_rw_with_rand_reset.1728920889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1532244823
Short name T124
Test name
Test status
Simulation time 1076555905 ps
CPU time 8.34 seconds
Started Aug 23 11:27:49 PM UTC 24
Finished Aug 23 11:27:59 PM UTC 24
Peak memory 221432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532244823 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1532244823
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2359981103
Short name T369
Test name
Test status
Simulation time 1455560002 ps
CPU time 8.33 seconds
Started Aug 23 11:27:47 PM UTC 24
Finished Aug 23 11:27:57 PM UTC 24
Peak memory 221624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359981103 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.2359981103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2643699247
Short name T368
Test name
Test status
Simulation time 489391281 ps
CPU time 7.12 seconds
Started Aug 23 11:27:47 PM UTC 24
Finished Aug 23 11:27:56 PM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643699247 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.2643699247
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2932000597
Short name T89
Test name
Test status
Simulation time 1019163711 ps
CPU time 40.39 seconds
Started Aug 23 11:27:43 PM UTC 24
Finished Aug 23 11:28:25 PM UTC 24
Peak memory 225940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932000597 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.2932000597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3257135798
Short name T85
Test name
Test status
Simulation time 988931339 ps
CPU time 8.53 seconds
Started Aug 23 11:27:50 PM UTC 24
Finished Aug 23 11:28:00 PM UTC 24
Peak memory 223848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257135798 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.3257135798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3279848733
Short name T370
Test name
Test status
Simulation time 517757679 ps
CPU time 13.32 seconds
Started Aug 23 11:27:45 PM UTC 24
Finished Aug 23 11:28:00 PM UTC 24
Peak memory 228132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279848733 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3279848733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1256420455
Short name T75
Test name
Test status
Simulation time 467135063 ps
CPU time 72.28 seconds
Started Aug 23 11:27:46 PM UTC 24
Finished Aug 23 11:29:00 PM UTC 24
Peak memory 225916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256420455 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.1256420455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3993258805
Short name T409
Test name
Test status
Simulation time 707808819 ps
CPU time 7.41 seconds
Started Aug 23 11:29:07 PM UTC 24
Finished Aug 23 11:29:16 PM UTC 24
Peak memory 226008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3993258805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rom_ctrl_csr_mem_rw_with_rand_reset.3993258805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1638988168
Short name T408
Test name
Test status
Simulation time 174495578 ps
CPU time 7.18 seconds
Started Aug 23 11:29:06 PM UTC 24
Finished Aug 23 11:29:14 PM UTC 24
Peak memory 221876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638988168 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1638988168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3152672432
Short name T435
Test name
Test status
Simulation time 6363313097 ps
CPU time 57.35 seconds
Started Aug 23 11:29:04 PM UTC 24
Finished Aug 23 11:30:03 PM UTC 24
Peak memory 226000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152672432 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.3152672432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3957586521
Short name T411
Test name
Test status
Simulation time 1016541288 ps
CPU time 12.09 seconds
Started Aug 23 11:29:07 PM UTC 24
Finished Aug 23 11:29:21 PM UTC 24
Peak memory 221780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957586521 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.3957586521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3639401355
Short name T410
Test name
Test status
Simulation time 167617662 ps
CPU time 11.05 seconds
Started Aug 23 11:29:04 PM UTC 24
Finished Aug 23 11:29:16 PM UTC 24
Peak memory 227920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639401355 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3639401355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3576690430
Short name T457
Test name
Test status
Simulation time 1876330004 ps
CPU time 139.33 seconds
Started Aug 23 11:29:05 PM UTC 24
Finished Aug 23 11:31:26 PM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576690430 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.3576690430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3017592483
Short name T414
Test name
Test status
Simulation time 1154729128 ps
CPU time 7.38 seconds
Started Aug 23 11:29:16 PM UTC 24
Finished Aug 23 11:29:25 PM UTC 24
Peak memory 227948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3017592483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rom_ctrl_csr_mem_rw_with_rand_reset.3017592483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.203451697
Short name T99
Test name
Test status
Simulation time 505970599 ps
CPU time 8.48 seconds
Started Aug 23 11:29:15 PM UTC 24
Finished Aug 23 11:29:25 PM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203451697 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.203451697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.628134918
Short name T103
Test name
Test status
Simulation time 2640591349 ps
CPU time 34.07 seconds
Started Aug 23 11:29:11 PM UTC 24
Finished Aug 23 11:29:46 PM UTC 24
Peak memory 226000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628134918 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.628134918
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2283506381
Short name T412
Test name
Test status
Simulation time 1031956177 ps
CPU time 7.16 seconds
Started Aug 23 11:29:15 PM UTC 24
Finished Aug 23 11:29:23 PM UTC 24
Peak memory 221808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283506381 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.2283506381
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.919828141
Short name T413
Test name
Test status
Simulation time 256863932 ps
CPU time 11.29 seconds
Started Aug 23 11:29:12 PM UTC 24
Finished Aug 23 11:29:25 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919828141 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.919828141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.213515988
Short name T417
Test name
Test status
Simulation time 521978482 ps
CPU time 8.82 seconds
Started Aug 23 11:29:25 PM UTC 24
Finished Aug 23 11:29:36 PM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=213515988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.r
om_ctrl_csr_mem_rw_with_rand_reset.213515988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3044258970
Short name T415
Test name
Test status
Simulation time 339206191 ps
CPU time 7.06 seconds
Started Aug 23 11:29:25 PM UTC 24
Finished Aug 23 11:29:34 PM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044258970 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3044258970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3543543141
Short name T427
Test name
Test status
Simulation time 2235237866 ps
CPU time 33.95 seconds
Started Aug 23 11:29:17 PM UTC 24
Finished Aug 23 11:29:52 PM UTC 24
Peak memory 223952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543543141 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.3543543141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3750811710
Short name T416
Test name
Test status
Simulation time 257031166 ps
CPU time 8.44 seconds
Started Aug 23 11:29:25 PM UTC 24
Finished Aug 23 11:29:35 PM UTC 24
Peak memory 221808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750811710 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.3750811710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2942164618
Short name T418
Test name
Test status
Simulation time 1036728182 ps
CPU time 13.07 seconds
Started Aug 23 11:29:21 PM UTC 24
Finished Aug 23 11:29:36 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942164618 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2942164618
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2412302271
Short name T137
Test name
Test status
Simulation time 1026854057 ps
CPU time 72.65 seconds
Started Aug 23 11:29:24 PM UTC 24
Finished Aug 23 11:30:39 PM UTC 24
Peak memory 223864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412302271 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.2412302271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.450584199
Short name T423
Test name
Test status
Simulation time 526760355 ps
CPU time 8.74 seconds
Started Aug 23 11:29:37 PM UTC 24
Finished Aug 23 11:29:46 PM UTC 24
Peak memory 229300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=450584199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.r
om_ctrl_csr_mem_rw_with_rand_reset.450584199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4212139010
Short name T421
Test name
Test status
Simulation time 2353856131 ps
CPU time 7.18 seconds
Started Aug 23 11:29:35 PM UTC 24
Finished Aug 23 11:29:44 PM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212139010 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4212139010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4241372990
Short name T102
Test name
Test status
Simulation time 2867131492 ps
CPU time 33.52 seconds
Started Aug 23 11:29:26 PM UTC 24
Finished Aug 23 11:30:01 PM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241372990 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.4241372990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2410108017
Short name T422
Test name
Test status
Simulation time 167607239 ps
CPU time 7.15 seconds
Started Aug 23 11:29:37 PM UTC 24
Finished Aug 23 11:29:45 PM UTC 24
Peak memory 221808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410108017 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.2410108017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2930190084
Short name T419
Test name
Test status
Simulation time 252346541 ps
CPU time 10.98 seconds
Started Aug 23 11:29:29 PM UTC 24
Finished Aug 23 11:29:41 PM UTC 24
Peak memory 228056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930190084 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2930190084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3568196071
Short name T454
Test name
Test status
Simulation time 1251767034 ps
CPU time 72.99 seconds
Started Aug 23 11:29:34 PM UTC 24
Finished Aug 23 11:30:49 PM UTC 24
Peak memory 225912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568196071 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.3568196071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2383262296
Short name T428
Test name
Test status
Simulation time 1028466080 ps
CPU time 8.89 seconds
Started Aug 23 11:29:44 PM UTC 24
Finished Aug 23 11:29:54 PM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2383262296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rom_ctrl_csr_mem_rw_with_rand_reset.2383262296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.957830467
Short name T425
Test name
Test status
Simulation time 251923082 ps
CPU time 8.62 seconds
Started Aug 23 11:29:41 PM UTC 24
Finished Aug 23 11:29:50 PM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957830467 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.957830467
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1188311304
Short name T449
Test name
Test status
Simulation time 2152816269 ps
CPU time 49.93 seconds
Started Aug 23 11:29:37 PM UTC 24
Finished Aug 23 11:30:28 PM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188311304 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.1188311304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.133243365
Short name T426
Test name
Test status
Simulation time 564315609 ps
CPU time 8.59 seconds
Started Aug 23 11:29:42 PM UTC 24
Finished Aug 23 11:29:51 PM UTC 24
Peak memory 223868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133243365 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.133243365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.262100632
Short name T424
Test name
Test status
Simulation time 824610720 ps
CPU time 10.29 seconds
Started Aug 23 11:29:39 PM UTC 24
Finished Aug 23 11:29:50 PM UTC 24
Peak memory 228740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262100632 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.262100632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3164164136
Short name T134
Test name
Test status
Simulation time 259466318 ps
CPU time 72.88 seconds
Started Aug 23 11:29:39 PM UTC 24
Finished Aug 23 11:30:53 PM UTC 24
Peak memory 223992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164164136 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.3164164136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4109884092
Short name T431
Test name
Test status
Simulation time 921584846 ps
CPU time 8.42 seconds
Started Aug 23 11:29:48 PM UTC 24
Finished Aug 23 11:29:58 PM UTC 24
Peak memory 225964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4109884092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rom_ctrl_csr_mem_rw_with_rand_reset.4109884092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1621151845
Short name T430
Test name
Test status
Simulation time 259857851 ps
CPU time 8.72 seconds
Started Aug 23 11:29:47 PM UTC 24
Finished Aug 23 11:29:57 PM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621151845 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1621151845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2672631599
Short name T448
Test name
Test status
Simulation time 4220509903 ps
CPU time 38.67 seconds
Started Aug 23 11:29:45 PM UTC 24
Finished Aug 23 11:30:25 PM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672631599 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.2672631599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2015042094
Short name T432
Test name
Test status
Simulation time 1027383339 ps
CPU time 12.08 seconds
Started Aug 23 11:29:47 PM UTC 24
Finished Aug 23 11:30:00 PM UTC 24
Peak memory 223856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015042094 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.2015042094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3362420617
Short name T429
Test name
Test status
Simulation time 717832639 ps
CPU time 9.86 seconds
Started Aug 23 11:29:45 PM UTC 24
Finished Aug 23 11:29:56 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362420617 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3362420617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2262016215
Short name T135
Test name
Test status
Simulation time 1529151834 ps
CPU time 138.58 seconds
Started Aug 23 11:29:46 PM UTC 24
Finished Aug 23 11:32:07 PM UTC 24
Peak memory 225912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262016215 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.2262016215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1095544853
Short name T436
Test name
Test status
Simulation time 189844771 ps
CPU time 8.43 seconds
Started Aug 23 11:29:53 PM UTC 24
Finished Aug 23 11:30:03 PM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1095544853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rom_ctrl_csr_mem_rw_with_rand_reset.1095544853
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.743777972
Short name T433
Test name
Test status
Simulation time 884025689 ps
CPU time 8.73 seconds
Started Aug 23 11:29:51 PM UTC 24
Finished Aug 23 11:30:01 PM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743777972 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.743777972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2646551786
Short name T450
Test name
Test status
Simulation time 1073997829 ps
CPU time 38.75 seconds
Started Aug 23 11:29:49 PM UTC 24
Finished Aug 23 11:30:29 PM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646551786 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.2646551786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1795903770
Short name T434
Test name
Test status
Simulation time 249723883 ps
CPU time 8.58 seconds
Started Aug 23 11:29:52 PM UTC 24
Finished Aug 23 11:30:02 PM UTC 24
Peak memory 221808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795903770 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.1795903770
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.854826157
Short name T437
Test name
Test status
Simulation time 257801172 ps
CPU time 11.7 seconds
Started Aug 23 11:29:51 PM UTC 24
Finished Aug 23 11:30:04 PM UTC 24
Peak memory 227708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854826157 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.854826157
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2921496150
Short name T455
Test name
Test status
Simulation time 758419315 ps
CPU time 73.56 seconds
Started Aug 23 11:29:51 PM UTC 24
Finished Aug 23 11:31:07 PM UTC 24
Peak memory 225520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921496150 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.2921496150
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.649643998
Short name T438
Test name
Test status
Simulation time 342109908 ps
CPU time 7.32 seconds
Started Aug 23 11:29:59 PM UTC 24
Finished Aug 23 11:30:07 PM UTC 24
Peak memory 225976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=649643998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.r
om_ctrl_csr_mem_rw_with_rand_reset.649643998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3587396852
Short name T105
Test name
Test status
Simulation time 340077576 ps
CPU time 7.05 seconds
Started Aug 23 11:29:57 PM UTC 24
Finished Aug 23 11:30:05 PM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587396852 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3587396852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2286890958
Short name T453
Test name
Test status
Simulation time 8575844617 ps
CPU time 50.69 seconds
Started Aug 23 11:29:54 PM UTC 24
Finished Aug 23 11:30:47 PM UTC 24
Peak memory 226000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286890958 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.2286890958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.907277240
Short name T439
Test name
Test status
Simulation time 255492229 ps
CPU time 8.49 seconds
Started Aug 23 11:29:58 PM UTC 24
Finished Aug 23 11:30:07 PM UTC 24
Peak memory 223868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907277240 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.907277240
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3741419202
Short name T440
Test name
Test status
Simulation time 255720766 ps
CPU time 13.38 seconds
Started Aug 23 11:29:55 PM UTC 24
Finished Aug 23 11:30:10 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741419202 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3741419202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1829024542
Short name T133
Test name
Test status
Simulation time 358960934 ps
CPU time 73.96 seconds
Started Aug 23 11:29:55 PM UTC 24
Finished Aug 23 11:31:11 PM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829024542 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.1829024542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3103897924
Short name T442
Test name
Test status
Simulation time 1054003305 ps
CPU time 8.56 seconds
Started Aug 23 11:30:03 PM UTC 24
Finished Aug 23 11:30:13 PM UTC 24
Peak memory 225964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3103897924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rom_ctrl_csr_mem_rw_with_rand_reset.3103897924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2129440176
Short name T441
Test name
Test status
Simulation time 988469205 ps
CPU time 8.34 seconds
Started Aug 23 11:30:02 PM UTC 24
Finished Aug 23 11:30:11 PM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129440176 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2129440176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.576560800
Short name T451
Test name
Test status
Simulation time 3621381208 ps
CPU time 38.73 seconds
Started Aug 23 11:29:59 PM UTC 24
Finished Aug 23 11:30:39 PM UTC 24
Peak memory 226000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576560800 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.576560800
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3772781707
Short name T444
Test name
Test status
Simulation time 2451733542 ps
CPU time 10.61 seconds
Started Aug 23 11:30:03 PM UTC 24
Finished Aug 23 11:30:15 PM UTC 24
Peak memory 223920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772781707 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.3772781707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2067023581
Short name T456
Test name
Test status
Simulation time 336215754 ps
CPU time 74.45 seconds
Started Aug 23 11:30:02 PM UTC 24
Finished Aug 23 11:31:18 PM UTC 24
Peak memory 224056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067023581 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.2067023581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.454403315
Short name T445
Test name
Test status
Simulation time 249469170 ps
CPU time 7.54 seconds
Started Aug 23 11:30:08 PM UTC 24
Finished Aug 23 11:30:17 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=454403315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.r
om_ctrl_csr_mem_rw_with_rand_reset.454403315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2256303946
Short name T443
Test name
Test status
Simulation time 168381097 ps
CPU time 7.12 seconds
Started Aug 23 11:30:06 PM UTC 24
Finished Aug 23 11:30:14 PM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256303946 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2256303946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2770476661
Short name T452
Test name
Test status
Simulation time 1065391203 ps
CPU time 38.27 seconds
Started Aug 23 11:30:04 PM UTC 24
Finished Aug 23 11:30:44 PM UTC 24
Peak memory 225936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770476661 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.2770476661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1187312176
Short name T446
Test name
Test status
Simulation time 1031734273 ps
CPU time 8.8 seconds
Started Aug 23 11:30:08 PM UTC 24
Finished Aug 23 11:30:18 PM UTC 24
Peak memory 223856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187312176 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.1187312176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1546544883
Short name T447
Test name
Test status
Simulation time 255237704 ps
CPU time 12.19 seconds
Started Aug 23 11:30:05 PM UTC 24
Finished Aug 23 11:30:18 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546544883 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1546544883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1542359554
Short name T139
Test name
Test status
Simulation time 2311637068 ps
CPU time 73.12 seconds
Started Aug 23 11:30:05 PM UTC 24
Finished Aug 23 11:31:20 PM UTC 24
Peak memory 223856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542359554 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.1542359554
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1233464792
Short name T87
Test name
Test status
Simulation time 1030094536 ps
CPU time 8.46 seconds
Started Aug 23 11:28:05 PM UTC 24
Finished Aug 23 11:28:14 PM UTC 24
Peak memory 221752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233464792 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.1233464792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2976423441
Short name T373
Test name
Test status
Simulation time 174483836 ps
CPU time 7.37 seconds
Started Aug 23 11:28:01 PM UTC 24
Finished Aug 23 11:28:09 PM UTC 24
Peak memory 221944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976423441 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.2976423441
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1946428485
Short name T86
Test name
Test status
Simulation time 514239078 ps
CPU time 11.55 seconds
Started Aug 23 11:28:00 PM UTC 24
Finished Aug 23 11:28:13 PM UTC 24
Peak memory 221444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946428485 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.1946428485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4158327374
Short name T376
Test name
Test status
Simulation time 367580048 ps
CPU time 7.46 seconds
Started Aug 23 11:28:08 PM UTC 24
Finished Aug 23 11:28:16 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4158327374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
om_ctrl_csr_mem_rw_with_rand_reset.4158327374
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1631630759
Short name T116
Test name
Test status
Simulation time 2043017652 ps
CPU time 11.96 seconds
Started Aug 23 11:28:01 PM UTC 24
Finished Aug 23 11:28:14 PM UTC 24
Peak memory 223988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631630759 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1631630759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2686511888
Short name T375
Test name
Test status
Simulation time 1007025430 ps
CPU time 11.6 seconds
Started Aug 23 11:27:59 PM UTC 24
Finished Aug 23 11:28:12 PM UTC 24
Peak memory 221616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686511888 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.2686511888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.166571021
Short name T372
Test name
Test status
Simulation time 994195856 ps
CPU time 8.33 seconds
Started Aug 23 11:27:58 PM UTC 24
Finished Aug 23 11:28:08 PM UTC 24
Peak memory 221676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166571021 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.166571021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.356641474
Short name T94
Test name
Test status
Simulation time 6094798095 ps
CPU time 58.01 seconds
Started Aug 23 11:27:56 PM UTC 24
Finished Aug 23 11:28:56 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356641474 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.356641474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.586816566
Short name T88
Test name
Test status
Simulation time 1029873452 ps
CPU time 12.13 seconds
Started Aug 23 11:28:06 PM UTC 24
Finished Aug 23 11:28:19 PM UTC 24
Peak memory 221820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586816566 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.586816566
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3350003351
Short name T374
Test name
Test status
Simulation time 259486304 ps
CPU time 11.3 seconds
Started Aug 23 11:27:57 PM UTC 24
Finished Aug 23 11:28:10 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350003351 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3350003351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2575964851
Short name T382
Test name
Test status
Simulation time 661153108 ps
CPU time 7.18 seconds
Started Aug 23 11:28:17 PM UTC 24
Finished Aug 23 11:28:25 PM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575964851 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.2575964851
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.808016157
Short name T381
Test name
Test status
Simulation time 250099382 ps
CPU time 8.52 seconds
Started Aug 23 11:28:15 PM UTC 24
Finished Aug 23 11:28:25 PM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808016157 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.808016157
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.512988596
Short name T383
Test name
Test status
Simulation time 256457045 ps
CPU time 11.64 seconds
Started Aug 23 11:28:14 PM UTC 24
Finished Aug 23 11:28:27 PM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512988596 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.512988596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1071402619
Short name T384
Test name
Test status
Simulation time 2607541049 ps
CPU time 10.15 seconds
Started Aug 23 11:28:20 PM UTC 24
Finished Aug 23 11:28:31 PM UTC 24
Peak memory 227732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1071402619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
om_ctrl_csr_mem_rw_with_rand_reset.1071402619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1715368636
Short name T379
Test name
Test status
Simulation time 1653278983 ps
CPU time 7.15 seconds
Started Aug 23 11:28:14 PM UTC 24
Finished Aug 23 11:28:22 PM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715368636 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1715368636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2043304946
Short name T378
Test name
Test status
Simulation time 167698109 ps
CPU time 7.07 seconds
Started Aug 23 11:28:13 PM UTC 24
Finished Aug 23 11:28:21 PM UTC 24
Peak memory 221744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043304946 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.2043304946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1500317820
Short name T377
Test name
Test status
Simulation time 339400373 ps
CPU time 7.19 seconds
Started Aug 23 11:28:11 PM UTC 24
Finished Aug 23 11:28:19 PM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500317820 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.1500317820
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2257310105
Short name T118
Test name
Test status
Simulation time 168485998 ps
CPU time 7.17 seconds
Started Aug 23 11:28:20 PM UTC 24
Finished Aug 23 11:28:28 PM UTC 24
Peak memory 221652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257310105 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.2257310105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.760588752
Short name T380
Test name
Test status
Simulation time 346994635 ps
CPU time 11.53 seconds
Started Aug 23 11:28:10 PM UTC 24
Finished Aug 23 11:28:22 PM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760588752 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.760588752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.137981057
Short name T76
Test name
Test status
Simulation time 538470366 ps
CPU time 73.37 seconds
Started Aug 23 11:28:10 PM UTC 24
Finished Aug 23 11:29:25 PM UTC 24
Peak memory 223860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137981057 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.137981057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1880706246
Short name T389
Test name
Test status
Simulation time 452148892 ps
CPU time 8.27 seconds
Started Aug 23 11:28:27 PM UTC 24
Finished Aug 23 11:28:37 PM UTC 24
Peak memory 222008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880706246 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.1880706246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3273517461
Short name T388
Test name
Test status
Simulation time 617352082 ps
CPU time 8.66 seconds
Started Aug 23 11:28:26 PM UTC 24
Finished Aug 23 11:28:36 PM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273517461 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.3273517461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1434654632
Short name T390
Test name
Test status
Simulation time 241199330 ps
CPU time 13.57 seconds
Started Aug 23 11:28:25 PM UTC 24
Finished Aug 23 11:28:40 PM UTC 24
Peak memory 221880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434654632 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.1434654632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.432687556
Short name T391
Test name
Test status
Simulation time 1927307700 ps
CPU time 8.7 seconds
Started Aug 23 11:28:31 PM UTC 24
Finished Aug 23 11:28:40 PM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=432687556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ro
m_ctrl_csr_mem_rw_with_rand_reset.432687556
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.328432085
Short name T90
Test name
Test status
Simulation time 176900798 ps
CPU time 7.14 seconds
Started Aug 23 11:28:25 PM UTC 24
Finished Aug 23 11:28:34 PM UTC 24
Peak memory 222012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328432085 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.328432085
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.764688309
Short name T386
Test name
Test status
Simulation time 332539504 ps
CPU time 7.34 seconds
Started Aug 23 11:28:24 PM UTC 24
Finished Aug 23 11:28:33 PM UTC 24
Peak memory 221616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764688309 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.764688309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3311269188
Short name T385
Test name
Test status
Simulation time 280058825 ps
CPU time 8.28 seconds
Started Aug 23 11:28:23 PM UTC 24
Finished Aug 23 11:28:33 PM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311269188 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.3311269188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1767915224
Short name T95
Test name
Test status
Simulation time 4234663758 ps
CPU time 39 seconds
Started Aug 23 11:28:22 PM UTC 24
Finished Aug 23 11:29:03 PM UTC 24
Peak memory 226004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767915224 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.1767915224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.814490131
Short name T119
Test name
Test status
Simulation time 689683990 ps
CPU time 7.18 seconds
Started Aug 23 11:28:29 PM UTC 24
Finished Aug 23 11:28:38 PM UTC 24
Peak memory 222016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814490131 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.814490131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2690038753
Short name T387
Test name
Test status
Simulation time 496847156 ps
CPU time 12.29 seconds
Started Aug 23 11:28:22 PM UTC 24
Finished Aug 23 11:28:36 PM UTC 24
Peak memory 228056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690038753 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2690038753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1562503268
Short name T77
Test name
Test status
Simulation time 648833907 ps
CPU time 73.25 seconds
Started Aug 23 11:28:23 PM UTC 24
Finished Aug 23 11:29:38 PM UTC 24
Peak memory 229436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562503268 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.1562503268
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2207343016
Short name T392
Test name
Test status
Simulation time 1034089572 ps
CPU time 8.89 seconds
Started Aug 23 11:28:37 PM UTC 24
Finished Aug 23 11:28:47 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2207343016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
om_ctrl_csr_mem_rw_with_rand_reset.2207343016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3441152062
Short name T91
Test name
Test status
Simulation time 168097190 ps
CPU time 7.34 seconds
Started Aug 23 11:28:34 PM UTC 24
Finished Aug 23 11:28:42 PM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441152062 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3441152062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.619638414
Short name T97
Test name
Test status
Simulation time 1381182861 ps
CPU time 33.85 seconds
Started Aug 23 11:28:31 PM UTC 24
Finished Aug 23 11:29:06 PM UTC 24
Peak memory 225944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619638414 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.619638414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1160078985
Short name T120
Test name
Test status
Simulation time 527181706 ps
CPU time 8.49 seconds
Started Aug 23 11:28:35 PM UTC 24
Finished Aug 23 11:28:44 PM UTC 24
Peak memory 223848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160078985 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.1160078985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.354932592
Short name T393
Test name
Test status
Simulation time 1374185919 ps
CPU time 12.94 seconds
Started Aug 23 11:28:33 PM UTC 24
Finished Aug 23 11:28:47 PM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354932592 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.354932592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.683522931
Short name T130
Test name
Test status
Simulation time 859629923 ps
CPU time 71.58 seconds
Started Aug 23 11:28:34 PM UTC 24
Finished Aug 23 11:29:47 PM UTC 24
Peak memory 225840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683522931 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.683522931
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4013851062
Short name T396
Test name
Test status
Simulation time 259929029 ps
CPU time 8.8 seconds
Started Aug 23 11:28:41 PM UTC 24
Finished Aug 23 11:28:51 PM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4013851062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
om_ctrl_csr_mem_rw_with_rand_reset.4013851062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3278714005
Short name T394
Test name
Test status
Simulation time 174194541 ps
CPU time 7.29 seconds
Started Aug 23 11:28:39 PM UTC 24
Finished Aug 23 11:28:47 PM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278714005 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3278714005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2749503817
Short name T98
Test name
Test status
Simulation time 703935943 ps
CPU time 33.43 seconds
Started Aug 23 11:28:37 PM UTC 24
Finished Aug 23 11:29:12 PM UTC 24
Peak memory 224024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749503817 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.2749503817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1401666675
Short name T397
Test name
Test status
Simulation time 1233073437 ps
CPU time 10.59 seconds
Started Aug 23 11:28:41 PM UTC 24
Finished Aug 23 11:28:53 PM UTC 24
Peak memory 223508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401666675 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.1401666675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.367640423
Short name T395
Test name
Test status
Simulation time 1034756893 ps
CPU time 11.34 seconds
Started Aug 23 11:28:37 PM UTC 24
Finished Aug 23 11:28:49 PM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367640423 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.367640423
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3892077482
Short name T399
Test name
Test status
Simulation time 794591849 ps
CPU time 7.85 seconds
Started Aug 23 11:28:47 PM UTC 24
Finished Aug 23 11:28:56 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3892077482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
om_ctrl_csr_mem_rw_with_rand_reset.3892077482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.8671068
Short name T92
Test name
Test status
Simulation time 1903820003 ps
CPU time 8.41 seconds
Started Aug 23 11:28:45 PM UTC 24
Finished Aug 23 11:28:55 PM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8671068 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.8671068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3495309037
Short name T420
Test name
Test status
Simulation time 7617541351 ps
CPU time 57.94 seconds
Started Aug 23 11:28:43 PM UTC 24
Finished Aug 23 11:29:43 PM UTC 24
Peak memory 227968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495309037 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.3495309037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.577173096
Short name T400
Test name
Test status
Simulation time 496505791 ps
CPU time 8.56 seconds
Started Aug 23 11:28:47 PM UTC 24
Finished Aug 23 11:28:57 PM UTC 24
Peak memory 221820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577173096 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.577173096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2325750544
Short name T398
Test name
Test status
Simulation time 508067290 ps
CPU time 11.43 seconds
Started Aug 23 11:28:43 PM UTC 24
Finished Aug 23 11:28:56 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325750544 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2325750544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3798820145
Short name T141
Test name
Test status
Simulation time 1276943375 ps
CPU time 72.52 seconds
Started Aug 23 11:28:44 PM UTC 24
Finished Aug 23 11:29:58 PM UTC 24
Peak memory 223936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798820145 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.3798820145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3729254576
Short name T402
Test name
Test status
Simulation time 3329515006 ps
CPU time 7.16 seconds
Started Aug 23 11:28:55 PM UTC 24
Finished Aug 23 11:29:04 PM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3729254576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
om_ctrl_csr_mem_rw_with_rand_reset.3729254576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.201692261
Short name T96
Test name
Test status
Simulation time 851504303 ps
CPU time 8.56 seconds
Started Aug 23 11:28:53 PM UTC 24
Finished Aug 23 11:29:03 PM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201692261 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.201692261
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1231305366
Short name T104
Test name
Test status
Simulation time 1095130644 ps
CPU time 50.59 seconds
Started Aug 23 11:28:48 PM UTC 24
Finished Aug 23 11:29:40 PM UTC 24
Peak memory 225940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231305366 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.1231305366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2978490125
Short name T403
Test name
Test status
Simulation time 1897361604 ps
CPU time 8.51 seconds
Started Aug 23 11:28:55 PM UTC 24
Finished Aug 23 11:29:05 PM UTC 24
Peak memory 221932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978490125 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.2978490125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3897860506
Short name T401
Test name
Test status
Simulation time 590870621 ps
CPU time 11.68 seconds
Started Aug 23 11:28:50 PM UTC 24
Finished Aug 23 11:29:03 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897860506 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3897860506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3107658527
Short name T142
Test name
Test status
Simulation time 248150521 ps
CPU time 72.62 seconds
Started Aug 23 11:28:51 PM UTC 24
Finished Aug 23 11:30:06 PM UTC 24
Peak memory 225984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107658527 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.3107658527
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1261244418
Short name T407
Test name
Test status
Simulation time 1105583628 ps
CPU time 9.16 seconds
Started Aug 23 11:29:04 PM UTC 24
Finished Aug 23 11:29:14 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1261244418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
om_ctrl_csr_mem_rw_with_rand_reset.1261244418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3812339796
Short name T404
Test name
Test status
Simulation time 1830231618 ps
CPU time 7.03 seconds
Started Aug 23 11:28:58 PM UTC 24
Finished Aug 23 11:29:06 PM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812339796 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3812339796
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3407236003
Short name T101
Test name
Test status
Simulation time 2020669555 ps
CPU time 50.31 seconds
Started Aug 23 11:28:56 PM UTC 24
Finished Aug 23 11:29:48 PM UTC 24
Peak memory 225940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407236003 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.3407236003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.532869645
Short name T406
Test name
Test status
Simulation time 981225394 ps
CPU time 11.88 seconds
Started Aug 23 11:29:01 PM UTC 24
Finished Aug 23 11:29:14 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532869645 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.532869645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3339737025
Short name T405
Test name
Test status
Simulation time 176258732 ps
CPU time 11.85 seconds
Started Aug 23 11:28:56 PM UTC 24
Finished Aug 23 11:29:09 PM UTC 24
Peak memory 228184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339737025 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3339737025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1767819684
Short name T2
Test name
Test status
Simulation time 474788188 ps
CPU time 7.27 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:17:57 PM UTC 24
Peak memory 228232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767819684 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1767819684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.172791256
Short name T10
Test name
Test status
Simulation time 2844894077 ps
CPU time 10.66 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:01 PM UTC 24
Peak memory 228440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172791256 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.172791256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.229453331
Short name T1
Test name
Test status
Simulation time 1856366042 ps
CPU time 14.6 seconds
Started Aug 23 11:17:35 PM UTC 24
Finished Aug 23 11:17:51 PM UTC 24
Peak memory 228376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229453331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64k
B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.229453331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1651834283
Short name T3
Test name
Test status
Simulation time 591765705 ps
CPU time 7.35 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:17:58 PM UTC 24
Peak memory 227840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651834283 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1651834283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3021692680
Short name T143
Test name
Test status
Simulation time 3490517754 ps
CPU time 224.42 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:21:37 PM UTC 24
Peak memory 257440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021692680 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.3021692680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1859370212
Short name T27
Test name
Test status
Simulation time 1510892011 ps
CPU time 106.53 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:19:38 PM UTC 24
Peak memory 259456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859370212 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1859370212
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.1594338339
Short name T6
Test name
Test status
Simulation time 415200456 ps
CPU time 9.36 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:00 PM UTC 24
Peak memory 225476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594338339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1594338339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1692682097
Short name T34
Test name
Test status
Simulation time 374711346 ps
CPU time 21.4 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:12 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169268209
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.1692682097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.3115203517
Short name T153
Test name
Test status
Simulation time 192976756 ps
CPU time 7.29 seconds
Started Aug 23 11:18:48 PM UTC 24
Finished Aug 23 11:18:57 PM UTC 24
Peak memory 228048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115203517 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3115203517
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1076374131
Short name T204
Test name
Test status
Simulation time 65025200899 ps
CPU time 211.56 seconds
Started Aug 23 11:18:47 PM UTC 24
Finished Aug 23 11:22:22 PM UTC 24
Peak memory 257440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076374131 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.1076374131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3128317418
Short name T156
Test name
Test status
Simulation time 347131267 ps
CPU time 17.55 seconds
Started Aug 23 11:18:47 PM UTC 24
Finished Aug 23 11:19:06 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128317418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3128317418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.803436553
Short name T129
Test name
Test status
Simulation time 908360377 ps
CPU time 9.24 seconds
Started Aug 23 11:18:41 PM UTC 24
Finished Aug 23 11:18:52 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803436553 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.803436553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.4055758611
Short name T155
Test name
Test status
Simulation time 3372235204 ps
CPU time 21.86 seconds
Started Aug 23 11:18:40 PM UTC 24
Finished Aug 23 11:19:03 PM UTC 24
Peak memory 228536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405575861
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.4055758611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3575040431
Short name T177
Test name
Test status
Simulation time 3113500170 ps
CPU time 132.03 seconds
Started Aug 23 11:18:47 PM UTC 24
Finished Aug 23 11:21:02 PM UTC 24
Peak memory 234792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3575040431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3575040431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1962779758
Short name T59
Test name
Test status
Simulation time 249170811 ps
CPU time 8.48 seconds
Started Aug 23 11:18:59 PM UTC 24
Finished Aug 23 11:19:08 PM UTC 24
Peak memory 227784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962779758 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1962779758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.524738859
Short name T61
Test name
Test status
Simulation time 7092786270 ps
CPU time 216.71 seconds
Started Aug 23 11:18:51 PM UTC 24
Finished Aug 23 11:22:31 PM UTC 24
Peak memory 228528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524738859 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.524738859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.880619290
Short name T157
Test name
Test status
Simulation time 508286407 ps
CPU time 20.76 seconds
Started Aug 23 11:18:53 PM UTC 24
Finished Aug 23 11:19:15 PM UTC 24
Peak memory 225524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880619290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.880619290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1546523915
Short name T154
Test name
Test status
Simulation time 177199300 ps
CPU time 9.38 seconds
Started Aug 23 11:18:51 PM UTC 24
Finished Aug 23 11:19:02 PM UTC 24
Peak memory 228040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546523915 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1546523915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.2430643991
Short name T148
Test name
Test status
Simulation time 545329975 ps
CPU time 23.83 seconds
Started Aug 23 11:18:49 PM UTC 24
Finished Aug 23 11:19:15 PM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243064399
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.2430643991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.4013174362
Short name T185
Test name
Test status
Simulation time 8479307471 ps
CPU time 143.38 seconds
Started Aug 23 11:18:58 PM UTC 24
Finished Aug 23 11:21:24 PM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4013174362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.4013174362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3764965892
Short name T159
Test name
Test status
Simulation time 661729652 ps
CPU time 7.69 seconds
Started Aug 23 11:19:15 PM UTC 24
Finished Aug 23 11:19:24 PM UTC 24
Peak memory 227608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764965892 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3764965892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2099815762
Short name T220
Test name
Test status
Simulation time 4173693864 ps
CPU time 247.07 seconds
Started Aug 23 11:19:04 PM UTC 24
Finished Aug 23 11:23:14 PM UTC 24
Peak memory 247036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099815762 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.2099815762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3193101277
Short name T162
Test name
Test status
Simulation time 2609305107 ps
CPU time 19.96 seconds
Started Aug 23 11:19:07 PM UTC 24
Finished Aug 23 11:19:28 PM UTC 24
Peak memory 225780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193101277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3193101277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1508979462
Short name T158
Test name
Test status
Simulation time 1443978846 ps
CPU time 10.85 seconds
Started Aug 23 11:19:03 PM UTC 24
Finished Aug 23 11:19:15 PM UTC 24
Peak memory 228576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508979462 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1508979462
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.635848787
Short name T161
Test name
Test status
Simulation time 359093008 ps
CPU time 24.79 seconds
Started Aug 23 11:19:01 PM UTC 24
Finished Aug 23 11:19:27 PM UTC 24
Peak memory 228820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635848787
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.635848787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.107146256
Short name T188
Test name
Test status
Simulation time 16470546392 ps
CPU time 134.62 seconds
Started Aug 23 11:19:09 PM UTC 24
Finished Aug 23 11:21:26 PM UTC 24
Peak memory 239196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=107146256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.rom_ctrl_stress_all_with_rand_reset.107146256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3031945878
Short name T43
Test name
Test status
Simulation time 2657541480 ps
CPU time 12.81 seconds
Started Aug 23 11:19:27 PM UTC 24
Finished Aug 23 11:19:41 PM UTC 24
Peak memory 227936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031945878 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3031945878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1520084759
Short name T63
Test name
Test status
Simulation time 2932687666 ps
CPU time 131.54 seconds
Started Aug 23 11:19:22 PM UTC 24
Finished Aug 23 11:21:36 PM UTC 24
Peak memory 257516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520084759 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.1520084759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.331522430
Short name T160
Test name
Test status
Simulation time 257293664 ps
CPU time 10.37 seconds
Started Aug 23 11:19:15 PM UTC 24
Finished Aug 23 11:19:27 PM UTC 24
Peak memory 228084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331522430 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.331522430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.553905074
Short name T41
Test name
Test status
Simulation time 2074529927 ps
CPU time 21.97 seconds
Started Aug 23 11:19:15 PM UTC 24
Finished Aug 23 11:19:38 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553905074
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.553905074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3948728977
Short name T69
Test name
Test status
Simulation time 2784824843 ps
CPU time 91.94 seconds
Started Aug 23 11:19:26 PM UTC 24
Finished Aug 23 11:21:00 PM UTC 24
Peak memory 232932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3948728977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3948728977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.392987281
Short name T45
Test name
Test status
Simulation time 174238593 ps
CPU time 7.26 seconds
Started Aug 23 11:19:40 PM UTC 24
Finished Aug 23 11:19:49 PM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392987281 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.392987281
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2779292465
Short name T213
Test name
Test status
Simulation time 3116049822 ps
CPU time 194.53 seconds
Started Aug 23 11:19:38 PM UTC 24
Finished Aug 23 11:22:56 PM UTC 24
Peak memory 259488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779292465 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.2779292465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3229525286
Short name T163
Test name
Test status
Simulation time 1771985546 ps
CPU time 19.63 seconds
Started Aug 23 11:19:38 PM UTC 24
Finished Aug 23 11:19:59 PM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229525286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3229525286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1369614533
Short name T42
Test name
Test status
Simulation time 689178500 ps
CPU time 9.1 seconds
Started Aug 23 11:19:29 PM UTC 24
Finished Aug 23 11:19:40 PM UTC 24
Peak memory 228340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369614533 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1369614533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3410767326
Short name T46
Test name
Test status
Simulation time 1435378338 ps
CPU time 21.48 seconds
Started Aug 23 11:19:27 PM UTC 24
Finished Aug 23 11:19:50 PM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341076732
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.3410767326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.956355991
Short name T190
Test name
Test status
Simulation time 15857660235 ps
CPU time 108.16 seconds
Started Aug 23 11:19:39 PM UTC 24
Finished Aug 23 11:21:30 PM UTC 24
Peak memory 234972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=956355991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.rom_ctrl_stress_all_with_rand_reset.956355991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2216420493
Short name T164
Test name
Test status
Simulation time 174996841 ps
CPU time 7.17 seconds
Started Aug 23 11:19:59 PM UTC 24
Finished Aug 23 11:20:07 PM UTC 24
Peak memory 227624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216420493 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2216420493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2997344140
Short name T208
Test name
Test status
Simulation time 15655315867 ps
CPU time 172.85 seconds
Started Aug 23 11:19:44 PM UTC 24
Finished Aug 23 11:22:40 PM UTC 24
Peak memory 259616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997344140 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.2997344140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1837636872
Short name T60
Test name
Test status
Simulation time 1503965207 ps
CPU time 17.3 seconds
Started Aug 23 11:19:50 PM UTC 24
Finished Aug 23 11:20:08 PM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837636872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1837636872
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3220829337
Short name T47
Test name
Test status
Simulation time 1006098517 ps
CPU time 14.1 seconds
Started Aug 23 11:19:42 PM UTC 24
Finished Aug 23 11:19:58 PM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220829337 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3220829337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.416006652
Short name T165
Test name
Test status
Simulation time 560865936 ps
CPU time 25.66 seconds
Started Aug 23 11:19:40 PM UTC 24
Finished Aug 23 11:20:07 PM UTC 24
Peak memory 228836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416006652
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.416006652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2325715053
Short name T180
Test name
Test status
Simulation time 7288452932 ps
CPU time 77.2 seconds
Started Aug 23 11:19:51 PM UTC 24
Finished Aug 23 11:21:10 PM UTC 24
Peak memory 246344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2325715053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2325715053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1043095782
Short name T169
Test name
Test status
Simulation time 250540914 ps
CPU time 8.52 seconds
Started Aug 23 11:20:19 PM UTC 24
Finished Aug 23 11:20:29 PM UTC 24
Peak memory 227476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043095782 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1043095782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2853178004
Short name T241
Test name
Test status
Simulation time 4849364865 ps
CPU time 215.96 seconds
Started Aug 23 11:20:08 PM UTC 24
Finished Aug 23 11:23:47 PM UTC 24
Peak memory 259596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853178004 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.2853178004
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1762383669
Short name T168
Test name
Test status
Simulation time 346044203 ps
CPU time 17.2 seconds
Started Aug 23 11:20:09 PM UTC 24
Finished Aug 23 11:20:27 PM UTC 24
Peak memory 228080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762383669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1762383669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.2715187557
Short name T167
Test name
Test status
Simulation time 269870397 ps
CPU time 10.85 seconds
Started Aug 23 11:20:08 PM UTC 24
Finished Aug 23 11:20:20 PM UTC 24
Peak memory 228380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715187557 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2715187557
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1849401189
Short name T166
Test name
Test status
Simulation time 299395515 ps
CPU time 17.64 seconds
Started Aug 23 11:20:00 PM UTC 24
Finished Aug 23 11:20:19 PM UTC 24
Peak memory 228840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184940118
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.1849401189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1701716808
Short name T189
Test name
Test status
Simulation time 24768359201 ps
CPU time 67.35 seconds
Started Aug 23 11:20:19 PM UTC 24
Finished Aug 23 11:21:28 PM UTC 24
Peak memory 241116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1701716808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1701716808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1880889035
Short name T172
Test name
Test status
Simulation time 1029943734 ps
CPU time 8.52 seconds
Started Aug 23 11:20:30 PM UTC 24
Finished Aug 23 11:20:40 PM UTC 24
Peak memory 227936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880889035 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1880889035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.777101248
Short name T280
Test name
Test status
Simulation time 12257779138 ps
CPU time 280.48 seconds
Started Aug 23 11:20:27 PM UTC 24
Finished Aug 23 11:25:12 PM UTC 24
Peak memory 256428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777101248 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.777101248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1837331608
Short name T173
Test name
Test status
Simulation time 2200143521 ps
CPU time 17.37 seconds
Started Aug 23 11:20:28 PM UTC 24
Finished Aug 23 11:20:47 PM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837331608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1837331608
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3909456421
Short name T170
Test name
Test status
Simulation time 358147471 ps
CPU time 9.13 seconds
Started Aug 23 11:20:20 PM UTC 24
Finished Aug 23 11:20:30 PM UTC 24
Peak memory 228108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909456421 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3909456421
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.148198208
Short name T171
Test name
Test status
Simulation time 1460509377 ps
CPU time 17.39 seconds
Started Aug 23 11:20:19 PM UTC 24
Finished Aug 23 11:20:37 PM UTC 24
Peak memory 225452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148198208
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.148198208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2959217413
Short name T232
Test name
Test status
Simulation time 3817373241 ps
CPU time 179.31 seconds
Started Aug 23 11:20:29 PM UTC 24
Finished Aug 23 11:23:31 PM UTC 24
Peak memory 246600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2959217413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2959217413
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.881701363
Short name T178
Test name
Test status
Simulation time 689333797 ps
CPU time 7.23 seconds
Started Aug 23 11:20:54 PM UTC 24
Finished Aug 23 11:21:03 PM UTC 24
Peak memory 228012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881701363 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.881701363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.254905125
Short name T288
Test name
Test status
Simulation time 20411661450 ps
CPU time 281.28 seconds
Started Aug 23 11:20:40 PM UTC 24
Finished Aug 23 11:25:25 PM UTC 24
Peak memory 259488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254905125 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.254905125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.492915022
Short name T179
Test name
Test status
Simulation time 1376021002 ps
CPU time 17.25 seconds
Started Aug 23 11:20:47 PM UTC 24
Finished Aug 23 11:21:06 PM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492915022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.492915022
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.139363666
Short name T174
Test name
Test status
Simulation time 1034287282 ps
CPU time 13.92 seconds
Started Aug 23 11:20:38 PM UTC 24
Finished Aug 23 11:20:53 PM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139363666 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.139363666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.1608906874
Short name T175
Test name
Test status
Simulation time 546683843 ps
CPU time 24.77 seconds
Started Aug 23 11:20:31 PM UTC 24
Finished Aug 23 11:20:57 PM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160890687
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.1608906874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2097689511
Short name T182
Test name
Test status
Simulation time 1787885309 ps
CPU time 24.76 seconds
Started Aug 23 11:20:48 PM UTC 24
Finished Aug 23 11:21:15 PM UTC 24
Peak memory 230812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2097689511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2097689511
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.812866725
Short name T183
Test name
Test status
Simulation time 4950984560 ps
CPU time 8.66 seconds
Started Aug 23 11:21:11 PM UTC 24
Finished Aug 23 11:21:20 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812866725 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.812866725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.28920394
Short name T253
Test name
Test status
Simulation time 8208606656 ps
CPU time 189.58 seconds
Started Aug 23 11:21:03 PM UTC 24
Finished Aug 23 11:24:15 PM UTC 24
Peak memory 257564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28920394 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.28920394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3303834166
Short name T186
Test name
Test status
Simulation time 7079216068 ps
CPU time 19.98 seconds
Started Aug 23 11:21:04 PM UTC 24
Finished Aug 23 11:21:25 PM UTC 24
Peak memory 227700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303834166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3303834166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2087825565
Short name T181
Test name
Test status
Simulation time 262142431 ps
CPU time 10.68 seconds
Started Aug 23 11:21:00 PM UTC 24
Finished Aug 23 11:21:12 PM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087825565 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2087825565
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2695836445
Short name T184
Test name
Test status
Simulation time 785454227 ps
CPU time 21.68 seconds
Started Aug 23 11:20:58 PM UTC 24
Finished Aug 23 11:21:21 PM UTC 24
Peak memory 228840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269583644
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.2695836445
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.251351383
Short name T218
Test name
Test status
Simulation time 4883340864 ps
CPU time 117.96 seconds
Started Aug 23 11:21:07 PM UTC 24
Finished Aug 23 11:23:07 PM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=251351383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.rom_ctrl_stress_all_with_rand_reset.251351383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.2695458566
Short name T5
Test name
Test status
Simulation time 884374377 ps
CPU time 8.55 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:17:59 PM UTC 24
Peak memory 227784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695458566 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2695458566
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2834831620
Short name T30
Test name
Test status
Simulation time 3303979393 ps
CPU time 17.46 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:08 PM UTC 24
Peak memory 228700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834831620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2834831620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1394142441
Short name T22
Test name
Test status
Simulation time 263711161 ps
CPU time 10.6 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:01 PM UTC 24
Peak memory 228224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394142441 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1394142441
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1367129085
Short name T29
Test name
Test status
Simulation time 374008640 ps
CPU time 204.39 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:21:17 PM UTC 24
Peak memory 258520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367129085 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1367129085
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1741536213
Short name T8
Test name
Test status
Simulation time 179683969 ps
CPU time 9.53 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:00 PM UTC 24
Peak memory 225364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741536213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1741536213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1250477225
Short name T37
Test name
Test status
Simulation time 2095302484 ps
CPU time 24.86 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:16 PM UTC 24
Peak memory 228900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125047722
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.1250477225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1788924367
Short name T15
Test name
Test status
Simulation time 30282944999 ps
CPU time 55.5 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:47 PM UTC 24
Peak memory 245508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1788924367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1788924367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.986662422
Short name T191
Test name
Test status
Simulation time 661832377 ps
CPU time 7.23 seconds
Started Aug 23 11:21:23 PM UTC 24
Finished Aug 23 11:21:31 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986662422 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.986662422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3131879617
Short name T231
Test name
Test status
Simulation time 1878430602 ps
CPU time 130.69 seconds
Started Aug 23 11:21:18 PM UTC 24
Finished Aug 23 11:23:31 PM UTC 24
Peak memory 257400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131879617 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.3131879617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.126257906
Short name T107
Test name
Test status
Simulation time 1377984758 ps
CPU time 17.18 seconds
Started Aug 23 11:21:21 PM UTC 24
Finished Aug 23 11:21:39 PM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126257906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.126257906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2782650099
Short name T187
Test name
Test status
Simulation time 190581677 ps
CPU time 9.37 seconds
Started Aug 23 11:21:16 PM UTC 24
Finished Aug 23 11:21:26 PM UTC 24
Peak memory 228040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782650099 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2782650099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3626168236
Short name T109
Test name
Test status
Simulation time 8502932587 ps
CPU time 30.66 seconds
Started Aug 23 11:21:13 PM UTC 24
Finished Aug 23 11:21:45 PM UTC 24
Peak memory 228904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362616823
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.3626168236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1916162799
Short name T145
Test name
Test status
Simulation time 5482685492 ps
CPU time 181.23 seconds
Started Aug 23 11:21:22 PM UTC 24
Finished Aug 23 11:24:26 PM UTC 24
Peak memory 246540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1916162799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1916162799
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.622490996
Short name T193
Test name
Test status
Simulation time 1897314477 ps
CPU time 8.6 seconds
Started Aug 23 11:21:28 PM UTC 24
Finished Aug 23 11:21:38 PM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622490996 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.622490996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4152313501
Short name T216
Test name
Test status
Simulation time 6267631816 ps
CPU time 96.78 seconds
Started Aug 23 11:21:27 PM UTC 24
Finished Aug 23 11:23:06 PM UTC 24
Peak memory 257188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152313501 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.4152313501
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1955941343
Short name T111
Test name
Test status
Simulation time 1664856281 ps
CPU time 17.36 seconds
Started Aug 23 11:21:27 PM UTC 24
Finished Aug 23 11:21:46 PM UTC 24
Peak memory 228892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955941343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1955941343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2368069573
Short name T192
Test name
Test status
Simulation time 546874757 ps
CPU time 11.17 seconds
Started Aug 23 11:21:24 PM UTC 24
Finished Aug 23 11:21:36 PM UTC 24
Peak memory 228708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236806957
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.2368069573
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2339672191
Short name T237
Test name
Test status
Simulation time 3560025557 ps
CPU time 127.5 seconds
Started Aug 23 11:21:28 PM UTC 24
Finished Aug 23 11:23:38 PM UTC 24
Peak memory 239132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2339672191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2339672191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.993109208
Short name T110
Test name
Test status
Simulation time 172742448 ps
CPU time 7.24 seconds
Started Aug 23 11:21:36 PM UTC 24
Finished Aug 23 11:21:45 PM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993109208 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.993109208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2864874740
Short name T233
Test name
Test status
Simulation time 4043891707 ps
CPU time 119.05 seconds
Started Aug 23 11:21:30 PM UTC 24
Finished Aug 23 11:23:32 PM UTC 24
Peak memory 245900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864874740 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.2864874740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3535720563
Short name T115
Test name
Test status
Simulation time 496508783 ps
CPU time 19.84 seconds
Started Aug 23 11:21:32 PM UTC 24
Finished Aug 23 11:21:54 PM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535720563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3535720563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2900219596
Short name T108
Test name
Test status
Simulation time 2936273485 ps
CPU time 9.59 seconds
Started Aug 23 11:21:30 PM UTC 24
Finished Aug 23 11:21:41 PM UTC 24
Peak memory 228456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900219596 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2900219596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2140982759
Short name T114
Test name
Test status
Simulation time 3747796189 ps
CPU time 21.63 seconds
Started Aug 23 11:21:29 PM UTC 24
Finished Aug 23 11:21:52 PM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214098275
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.2140982759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1421480672
Short name T230
Test name
Test status
Simulation time 8632973393 ps
CPU time 113.63 seconds
Started Aug 23 11:21:34 PM UTC 24
Finished Aug 23 11:23:30 PM UTC 24
Peak memory 245912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1421480672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1421480672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.291144340
Short name T113
Test name
Test status
Simulation time 1102203806 ps
CPU time 7.34 seconds
Started Aug 23 11:21:42 PM UTC 24
Finished Aug 23 11:21:50 PM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291144340 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.291144340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1721032053
Short name T286
Test name
Test status
Simulation time 15300914636 ps
CPU time 221.26 seconds
Started Aug 23 11:21:39 PM UTC 24
Finished Aug 23 11:25:23 PM UTC 24
Peak memory 259488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721032053 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.1721032053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3891672976
Short name T195
Test name
Test status
Simulation time 3533501602 ps
CPU time 20.05 seconds
Started Aug 23 11:21:39 PM UTC 24
Finished Aug 23 11:22:00 PM UTC 24
Peak memory 228700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891672976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3891672976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.848429031
Short name T112
Test name
Test status
Simulation time 186547066 ps
CPU time 9.38 seconds
Started Aug 23 11:21:38 PM UTC 24
Finished Aug 23 11:21:48 PM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848429031 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.848429031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2471315454
Short name T199
Test name
Test status
Simulation time 810880631 ps
CPU time 30.97 seconds
Started Aug 23 11:21:38 PM UTC 24
Finished Aug 23 11:22:10 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247131545
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.2471315454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2478042673
Short name T259
Test name
Test status
Simulation time 11963292077 ps
CPU time 165.13 seconds
Started Aug 23 11:21:40 PM UTC 24
Finished Aug 23 11:24:27 PM UTC 24
Peak memory 241116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2478042673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2478042673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.1531422411
Short name T196
Test name
Test status
Simulation time 1036281738 ps
CPU time 7.31 seconds
Started Aug 23 11:21:53 PM UTC 24
Finished Aug 23 11:22:01 PM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531422411 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1531422411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1146228529
Short name T255
Test name
Test status
Simulation time 3163862708 ps
CPU time 150.32 seconds
Started Aug 23 11:21:47 PM UTC 24
Finished Aug 23 11:24:20 PM UTC 24
Peak memory 259616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146228529 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.1146228529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3496709825
Short name T200
Test name
Test status
Simulation time 2056021933 ps
CPU time 20.05 seconds
Started Aug 23 11:21:49 PM UTC 24
Finished Aug 23 11:22:10 PM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496709825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3496709825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3415891315
Short name T194
Test name
Test status
Simulation time 759852198 ps
CPU time 9.33 seconds
Started Aug 23 11:21:46 PM UTC 24
Finished Aug 23 11:21:56 PM UTC 24
Peak memory 228392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415891315 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3415891315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2361646868
Short name T198
Test name
Test status
Simulation time 373256992 ps
CPU time 21.75 seconds
Started Aug 23 11:21:46 PM UTC 24
Finished Aug 23 11:22:09 PM UTC 24
Peak memory 228840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236164686
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.2361646868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1017039755
Short name T215
Test name
Test status
Simulation time 3392729140 ps
CPU time 71.15 seconds
Started Aug 23 11:21:51 PM UTC 24
Finished Aug 23 11:23:04 PM UTC 24
Peak memory 232988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1017039755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1017039755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1170026707
Short name T201
Test name
Test status
Simulation time 1033006068 ps
CPU time 8.45 seconds
Started Aug 23 11:22:09 PM UTC 24
Finished Aug 23 11:22:19 PM UTC 24
Peak memory 227808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170026707 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1170026707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1744317128
Short name T315
Test name
Test status
Simulation time 5893242229 ps
CPU time 275.93 seconds
Started Aug 23 11:22:01 PM UTC 24
Finished Aug 23 11:26:41 PM UTC 24
Peak memory 246608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744317128 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.1744317128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3785892757
Short name T202
Test name
Test status
Simulation time 333818707 ps
CPU time 17.82 seconds
Started Aug 23 11:22:02 PM UTC 24
Finished Aug 23 11:22:21 PM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785892757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3785892757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.45096266
Short name T197
Test name
Test status
Simulation time 352560204 ps
CPU time 9.18 seconds
Started Aug 23 11:21:57 PM UTC 24
Finished Aug 23 11:22:07 PM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45096266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.45096266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2800326928
Short name T205
Test name
Test status
Simulation time 563575664 ps
CPU time 34.12 seconds
Started Aug 23 11:21:55 PM UTC 24
Finished Aug 23 11:22:30 PM UTC 24
Peak memory 228840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280032692
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.2800326928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2782175386
Short name T295
Test name
Test status
Simulation time 5940241628 ps
CPU time 216.42 seconds
Started Aug 23 11:22:08 PM UTC 24
Finished Aug 23 11:25:48 PM UTC 24
Peak memory 246540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2782175386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2782175386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.777002245
Short name T206
Test name
Test status
Simulation time 479178932 ps
CPU time 8.55 seconds
Started Aug 23 11:22:22 PM UTC 24
Finished Aug 23 11:22:32 PM UTC 24
Peak memory 228288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777002245 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.777002245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1255250892
Short name T345
Test name
Test status
Simulation time 18517362958 ps
CPU time 323.05 seconds
Started Aug 23 11:22:19 PM UTC 24
Finished Aug 23 11:27:47 PM UTC 24
Peak memory 257568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255250892 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.1255250892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2273747558
Short name T210
Test name
Test status
Simulation time 2753440842 ps
CPU time 19.85 seconds
Started Aug 23 11:22:22 PM UTC 24
Finished Aug 23 11:22:44 PM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273747558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2273747558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2060135432
Short name T203
Test name
Test status
Simulation time 367422627 ps
CPU time 9.27 seconds
Started Aug 23 11:22:11 PM UTC 24
Finished Aug 23 11:22:22 PM UTC 24
Peak memory 228040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060135432 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2060135432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2149413730
Short name T207
Test name
Test status
Simulation time 778361269 ps
CPU time 24.98 seconds
Started Aug 23 11:22:10 PM UTC 24
Finished Aug 23 11:22:37 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214941373
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.2149413730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2479240189
Short name T144
Test name
Test status
Simulation time 2911262430 ps
CPU time 98.49 seconds
Started Aug 23 11:22:22 PM UTC 24
Finished Aug 23 11:24:03 PM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2479240189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2479240189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3254582419
Short name T212
Test name
Test status
Simulation time 660685756 ps
CPU time 7.26 seconds
Started Aug 23 11:22:44 PM UTC 24
Finished Aug 23 11:22:52 PM UTC 24
Peak memory 228056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254582419 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3254582419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1444557341
Short name T252
Test name
Test status
Simulation time 1779787142 ps
CPU time 99.09 seconds
Started Aug 23 11:22:34 PM UTC 24
Finished Aug 23 11:24:15 PM UTC 24
Peak memory 244040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444557341 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.1444557341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3996420415
Short name T214
Test name
Test status
Simulation time 1504539914 ps
CPU time 17.75 seconds
Started Aug 23 11:22:38 PM UTC 24
Finished Aug 23 11:22:57 PM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996420415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3996420415
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.1217270338
Short name T209
Test name
Test status
Simulation time 698737934 ps
CPU time 9.42 seconds
Started Aug 23 11:22:33 PM UTC 24
Finished Aug 23 11:22:43 PM UTC 24
Peak memory 228340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217270338 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1217270338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2117652476
Short name T176
Test name
Test status
Simulation time 1699608195 ps
CPU time 22.51 seconds
Started Aug 23 11:22:32 PM UTC 24
Finished Aug 23 11:22:56 PM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211765247
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.2117652476
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3564543018
Short name T285
Test name
Test status
Simulation time 18144410926 ps
CPU time 159.12 seconds
Started Aug 23 11:22:41 PM UTC 24
Finished Aug 23 11:25:23 PM UTC 24
Peak memory 239132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3564543018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3564543018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3628417828
Short name T217
Test name
Test status
Simulation time 325087891 ps
CPU time 8.58 seconds
Started Aug 23 11:22:57 PM UTC 24
Finished Aug 23 11:23:07 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628417828 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3628417828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2235584533
Short name T314
Test name
Test status
Simulation time 65624714910 ps
CPU time 224.55 seconds
Started Aug 23 11:22:53 PM UTC 24
Finished Aug 23 11:26:41 PM UTC 24
Peak memory 247188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235584533 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.2235584533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.794192506
Short name T223
Test name
Test status
Simulation time 2145501292 ps
CPU time 19.84 seconds
Started Aug 23 11:22:56 PM UTC 24
Finished Aug 23 11:23:17 PM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794192506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.794192506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2146633781
Short name T121
Test name
Test status
Simulation time 3953855909 ps
CPU time 14.49 seconds
Started Aug 23 11:22:52 PM UTC 24
Finished Aug 23 11:23:08 PM UTC 24
Peak memory 228624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146633781 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2146633781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3601246393
Short name T222
Test name
Test status
Simulation time 7054549668 ps
CPU time 30.51 seconds
Started Aug 23 11:22:45 PM UTC 24
Finished Aug 23 11:23:17 PM UTC 24
Peak memory 228632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360124639
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.3601246393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1908339652
Short name T250
Test name
Test status
Simulation time 2135245873 ps
CPU time 73.68 seconds
Started Aug 23 11:22:56 PM UTC 24
Finished Aug 23 11:24:11 PM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1908339652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1908339652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1216461837
Short name T224
Test name
Test status
Simulation time 514087989 ps
CPU time 8.63 seconds
Started Aug 23 11:23:08 PM UTC 24
Finished Aug 23 11:23:18 PM UTC 24
Peak memory 227476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216461837 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1216461837
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.267766139
Short name T272
Test name
Test status
Simulation time 1555500637 ps
CPU time 102.84 seconds
Started Aug 23 11:23:06 PM UTC 24
Finished Aug 23 11:24:51 PM UTC 24
Peak memory 259004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267766139 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.267766139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1840668314
Short name T227
Test name
Test status
Simulation time 1744686583 ps
CPU time 17.72 seconds
Started Aug 23 11:23:07 PM UTC 24
Finished Aug 23 11:23:26 PM UTC 24
Peak memory 228416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840668314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1840668314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3871921803
Short name T221
Test name
Test status
Simulation time 366257159 ps
CPU time 9.59 seconds
Started Aug 23 11:23:04 PM UTC 24
Finished Aug 23 11:23:15 PM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871921803 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3871921803
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.343280736
Short name T225
Test name
Test status
Simulation time 747138044 ps
CPU time 21.5 seconds
Started Aug 23 11:22:57 PM UTC 24
Finished Aug 23 11:23:20 PM UTC 24
Peak memory 228756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343280736
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.343280736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3413086862
Short name T301
Test name
Test status
Simulation time 16042661729 ps
CPU time 175.19 seconds
Started Aug 23 11:23:07 PM UTC 24
Finished Aug 23 11:26:05 PM UTC 24
Peak memory 246604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3413086862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3413086862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1375734617
Short name T9
Test name
Test status
Simulation time 171464455 ps
CPU time 7.27 seconds
Started Aug 23 11:17:52 PM UTC 24
Finished Aug 23 11:18:00 PM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375734617 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1375734617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3515707993
Short name T49
Test name
Test status
Simulation time 8801681891 ps
CPU time 216.08 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:21:29 PM UTC 24
Peak memory 246092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515707993 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.3515707993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2372666096
Short name T35
Test name
Test status
Simulation time 517102187 ps
CPU time 19.89 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:11 PM UTC 24
Peak memory 228640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372666096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2372666096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2162814190
Short name T23
Test name
Test status
Simulation time 270985958 ps
CPU time 10.61 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:01 PM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162814190 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2162814190
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.1625899824
Short name T28
Test name
Test status
Simulation time 231360845 ps
CPU time 104.87 seconds
Started Aug 23 11:17:51 PM UTC 24
Finished Aug 23 11:19:38 PM UTC 24
Peak memory 254424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625899824 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1625899824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.617208961
Short name T33
Test name
Test status
Simulation time 1018422998 ps
CPU time 20.55 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:18:11 PM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617208961
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.617208961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.328593416
Short name T65
Test name
Test status
Simulation time 7077060843 ps
CPU time 93.75 seconds
Started Aug 23 11:17:49 PM UTC 24
Finished Aug 23 11:19:25 PM UTC 24
Peak memory 245916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=328593416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.rom_ctrl_stress_all_with_rand_reset.328593416
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.4082917130
Short name T229
Test name
Test status
Simulation time 516341678 ps
CPU time 8.6 seconds
Started Aug 23 11:23:19 PM UTC 24
Finished Aug 23 11:23:28 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082917130 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4082917130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3537138317
Short name T313
Test name
Test status
Simulation time 13271778889 ps
CPU time 198.72 seconds
Started Aug 23 11:23:15 PM UTC 24
Finished Aug 23 11:26:37 PM UTC 24
Peak memory 257268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537138317 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.3537138317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3655167992
Short name T235
Test name
Test status
Simulation time 346156706 ps
CPU time 17.22 seconds
Started Aug 23 11:23:17 PM UTC 24
Finished Aug 23 11:23:36 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655167992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3655167992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.4277329768
Short name T228
Test name
Test status
Simulation time 676996491 ps
CPU time 10.44 seconds
Started Aug 23 11:23:15 PM UTC 24
Finished Aug 23 11:23:27 PM UTC 24
Peak memory 228332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277329768 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4277329768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.415725735
Short name T226
Test name
Test status
Simulation time 776196363 ps
CPU time 12.86 seconds
Started Aug 23 11:23:10 PM UTC 24
Finished Aug 23 11:23:24 PM UTC 24
Peak memory 228752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415725735
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.415725735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3304951884
Short name T305
Test name
Test status
Simulation time 7393568953 ps
CPU time 177.22 seconds
Started Aug 23 11:23:17 PM UTC 24
Finished Aug 23 11:26:17 PM UTC 24
Peak memory 235292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3304951884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3304951884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1419774822
Short name T238
Test name
Test status
Simulation time 826011879 ps
CPU time 7.18 seconds
Started Aug 23 11:23:31 PM UTC 24
Finished Aug 23 11:23:39 PM UTC 24
Peak memory 228032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419774822 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1419774822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2023113492
Short name T324
Test name
Test status
Simulation time 14745486496 ps
CPU time 211.16 seconds
Started Aug 23 11:23:27 PM UTC 24
Finished Aug 23 11:27:01 PM UTC 24
Peak memory 259512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023113492 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.2023113492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3938206325
Short name T242
Test name
Test status
Simulation time 2060931043 ps
CPU time 19.9 seconds
Started Aug 23 11:23:28 PM UTC 24
Finished Aug 23 11:23:49 PM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938206325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3938206325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.543823259
Short name T236
Test name
Test status
Simulation time 565741920 ps
CPU time 10.33 seconds
Started Aug 23 11:23:25 PM UTC 24
Finished Aug 23 11:23:36 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543823259 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.543823259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1699965883
Short name T234
Test name
Test status
Simulation time 826031834 ps
CPU time 13.29 seconds
Started Aug 23 11:23:21 PM UTC 24
Finished Aug 23 11:23:35 PM UTC 24
Peak memory 228708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169996588
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.1699965883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.989385072
Short name T269
Test name
Test status
Simulation time 6506190574 ps
CPU time 77.58 seconds
Started Aug 23 11:23:29 PM UTC 24
Finished Aug 23 11:24:48 PM UTC 24
Peak memory 239260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=989385072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_stress_all_with_rand_reset.989385072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.299201290
Short name T240
Test name
Test status
Simulation time 993572885 ps
CPU time 8.62 seconds
Started Aug 23 11:23:37 PM UTC 24
Finished Aug 23 11:23:47 PM UTC 24
Peak memory 228192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299201290 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.299201290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1370631062
Short name T331
Test name
Test status
Simulation time 7107365373 ps
CPU time 221.55 seconds
Started Aug 23 11:23:33 PM UTC 24
Finished Aug 23 11:27:18 PM UTC 24
Peak memory 227896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370631062 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.1370631062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.423601910
Short name T244
Test name
Test status
Simulation time 3014193329 ps
CPU time 17.34 seconds
Started Aug 23 11:23:36 PM UTC 24
Finished Aug 23 11:23:54 PM UTC 24
Peak memory 228956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423601910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.423601910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.1085272585
Short name T239
Test name
Test status
Simulation time 683289686 ps
CPU time 9.18 seconds
Started Aug 23 11:23:32 PM UTC 24
Finished Aug 23 11:23:42 PM UTC 24
Peak memory 228392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085272585 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1085272585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.4007890467
Short name T247
Test name
Test status
Simulation time 388713985 ps
CPU time 28 seconds
Started Aug 23 11:23:32 PM UTC 24
Finished Aug 23 11:24:01 PM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400789046
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.4007890467
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3031084562
Short name T322
Test name
Test status
Simulation time 43120597215 ps
CPU time 195.02 seconds
Started Aug 23 11:23:37 PM UTC 24
Finished Aug 23 11:26:55 PM UTC 24
Peak memory 243164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3031084562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3031084562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2484137869
Short name T246
Test name
Test status
Simulation time 884927091 ps
CPU time 8.47 seconds
Started Aug 23 11:23:49 PM UTC 24
Finished Aug 23 11:23:59 PM UTC 24
Peak memory 227760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484137869 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2484137869
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.802205637
Short name T317
Test name
Test status
Simulation time 18054718690 ps
CPU time 176.68 seconds
Started Aug 23 11:23:43 PM UTC 24
Finished Aug 23 11:26:43 PM UTC 24
Peak memory 256384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802205637 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.802205637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2849200296
Short name T249
Test name
Test status
Simulation time 1030806570 ps
CPU time 20.01 seconds
Started Aug 23 11:23:47 PM UTC 24
Finished Aug 23 11:24:08 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849200296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2849200296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1018401330
Short name T243
Test name
Test status
Simulation time 754081550 ps
CPU time 10.4 seconds
Started Aug 23 11:23:40 PM UTC 24
Finished Aug 23 11:23:52 PM UTC 24
Peak memory 228376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018401330 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1018401330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2240915793
Short name T260
Test name
Test status
Simulation time 2126081347 ps
CPU time 47.24 seconds
Started Aug 23 11:23:39 PM UTC 24
Finished Aug 23 11:24:28 PM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224091579
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.2240915793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1193314781
Short name T251
Test name
Test status
Simulation time 250945711 ps
CPU time 8.62 seconds
Started Aug 23 11:24:04 PM UTC 24
Finished Aug 23 11:24:13 PM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193314781 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1193314781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.879272883
Short name T346
Test name
Test status
Simulation time 20174606688 ps
CPU time 234.76 seconds
Started Aug 23 11:23:58 PM UTC 24
Finished Aug 23 11:27:56 PM UTC 24
Peak memory 259024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879272883 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.879272883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.4053513437
Short name T256
Test name
Test status
Simulation time 1975235828 ps
CPU time 19.78 seconds
Started Aug 23 11:23:59 PM UTC 24
Finished Aug 23 11:24:20 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053513437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4053513437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2882622363
Short name T248
Test name
Test status
Simulation time 546663036 ps
CPU time 10.6 seconds
Started Aug 23 11:23:55 PM UTC 24
Finished Aug 23 11:24:07 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882622363 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2882622363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.3231336537
Short name T254
Test name
Test status
Simulation time 1542988854 ps
CPU time 21.52 seconds
Started Aug 23 11:23:52 PM UTC 24
Finished Aug 23 11:24:15 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323133653
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.3231336537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2105385039
Short name T265
Test name
Test status
Simulation time 2142744839 ps
CPU time 36.8 seconds
Started Aug 23 11:24:02 PM UTC 24
Finished Aug 23 11:24:40 PM UTC 24
Peak memory 230812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2105385039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2105385039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3604403682
Short name T258
Test name
Test status
Simulation time 2255405857 ps
CPU time 8.45 seconds
Started Aug 23 11:24:16 PM UTC 24
Finished Aug 23 11:24:25 PM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604403682 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3604403682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1880268389
Short name T343
Test name
Test status
Simulation time 7405639125 ps
CPU time 209.22 seconds
Started Aug 23 11:24:12 PM UTC 24
Finished Aug 23 11:27:44 PM UTC 24
Peak memory 243652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880268389 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.1880268389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1866039805
Short name T267
Test name
Test status
Simulation time 24517517794 ps
CPU time 28.49 seconds
Started Aug 23 11:24:14 PM UTC 24
Finished Aug 23 11:24:44 PM UTC 24
Peak memory 228696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866039805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1866039805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3029117345
Short name T257
Test name
Test status
Simulation time 548489733 ps
CPU time 10.75 seconds
Started Aug 23 11:24:09 PM UTC 24
Finished Aug 23 11:24:21 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029117345 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3029117345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1099157782
Short name T262
Test name
Test status
Simulation time 733576336 ps
CPU time 24.45 seconds
Started Aug 23 11:24:08 PM UTC 24
Finished Aug 23 11:24:33 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109915778
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.1099157782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3224377270
Short name T20
Test name
Test status
Simulation time 32279146341 ps
CPU time 176.35 seconds
Started Aug 23 11:24:16 PM UTC 24
Finished Aug 23 11:27:15 PM UTC 24
Peak memory 238156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3224377270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3224377270
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1931083529
Short name T263
Test name
Test status
Simulation time 751218657 ps
CPU time 7.09 seconds
Started Aug 23 11:24:27 PM UTC 24
Finished Aug 23 11:24:35 PM UTC 24
Peak memory 227752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931083529 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1931083529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1670867440
Short name T347
Test name
Test status
Simulation time 4785777187 ps
CPU time 222.67 seconds
Started Aug 23 11:24:21 PM UTC 24
Finished Aug 23 11:28:07 PM UTC 24
Peak memory 259616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670867440 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.1670867440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1364765920
Short name T266
Test name
Test status
Simulation time 677529464 ps
CPU time 17.35 seconds
Started Aug 23 11:24:22 PM UTC 24
Finished Aug 23 11:24:41 PM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364765920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1364765920
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.430156268
Short name T261
Test name
Test status
Simulation time 272441138 ps
CPU time 10.58 seconds
Started Aug 23 11:24:20 PM UTC 24
Finished Aug 23 11:24:32 PM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430156268 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.430156268
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2404178745
Short name T271
Test name
Test status
Simulation time 528534411 ps
CPU time 32.67 seconds
Started Aug 23 11:24:16 PM UTC 24
Finished Aug 23 11:24:50 PM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240417874
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.2404178745
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3249165594
Short name T282
Test name
Test status
Simulation time 5677193544 ps
CPU time 48.04 seconds
Started Aug 23 11:24:26 PM UTC 24
Finished Aug 23 11:25:16 PM UTC 24
Peak memory 235164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3249165594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3249165594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.936872537
Short name T268
Test name
Test status
Simulation time 167337484 ps
CPU time 7.28 seconds
Started Aug 23 11:24:39 PM UTC 24
Finished Aug 23 11:24:48 PM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936872537 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.936872537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2785220314
Short name T352
Test name
Test status
Simulation time 8076286912 ps
CPU time 239.25 seconds
Started Aug 23 11:24:33 PM UTC 24
Finished Aug 23 11:28:36 PM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785220314 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.2785220314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.4020595711
Short name T273
Test name
Test status
Simulation time 333943548 ps
CPU time 17.43 seconds
Started Aug 23 11:24:34 PM UTC 24
Finished Aug 23 11:24:53 PM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020595711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4020595711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.181933922
Short name T264
Test name
Test status
Simulation time 190973530 ps
CPU time 9.49 seconds
Started Aug 23 11:24:28 PM UTC 24
Finished Aug 23 11:24:39 PM UTC 24
Peak memory 228292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181933922 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.181933922
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2298693210
Short name T270
Test name
Test status
Simulation time 285538429 ps
CPU time 20.33 seconds
Started Aug 23 11:24:28 PM UTC 24
Finished Aug 23 11:24:50 PM UTC 24
Peak memory 228496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229869321
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.2298693210
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.115789325
Short name T337
Test name
Test status
Simulation time 13644870218 ps
CPU time 170.61 seconds
Started Aug 23 11:24:36 PM UTC 24
Finished Aug 23 11:27:30 PM UTC 24
Peak memory 246344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=115789325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.rom_ctrl_stress_all_with_rand_reset.115789325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1356403122
Short name T275
Test name
Test status
Simulation time 167563968 ps
CPU time 7.26 seconds
Started Aug 23 11:24:50 PM UTC 24
Finished Aug 23 11:24:59 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356403122 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1356403122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4113745714
Short name T348
Test name
Test status
Simulation time 3778237345 ps
CPU time 201.66 seconds
Started Aug 23 11:24:44 PM UTC 24
Finished Aug 23 11:28:09 PM UTC 24
Peak memory 246192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113745714 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.4113745714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3989408953
Short name T278
Test name
Test status
Simulation time 1979701204 ps
CPU time 20.11 seconds
Started Aug 23 11:24:48 PM UTC 24
Finished Aug 23 11:25:10 PM UTC 24
Peak memory 225716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989408953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3989408953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2238382784
Short name T274
Test name
Test status
Simulation time 1069589582 ps
CPU time 10.8 seconds
Started Aug 23 11:24:41 PM UTC 24
Finished Aug 23 11:24:53 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238382784 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2238382784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2332265734
Short name T277
Test name
Test status
Simulation time 383766509 ps
CPU time 25.28 seconds
Started Aug 23 11:24:40 PM UTC 24
Finished Aug 23 11:25:07 PM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233226573
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.2332265734
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1859414840
Short name T307
Test name
Test status
Simulation time 20526274861 ps
CPU time 91.01 seconds
Started Aug 23 11:24:48 PM UTC 24
Finished Aug 23 11:26:21 PM UTC 24
Peak memory 246072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1859414840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1859414840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.1686604677
Short name T279
Test name
Test status
Simulation time 688219851 ps
CPU time 7.15 seconds
Started Aug 23 11:25:03 PM UTC 24
Finished Aug 23 11:25:11 PM UTC 24
Peak memory 227476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686604677 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1686604677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1467463104
Short name T350
Test name
Test status
Simulation time 34190081101 ps
CPU time 213.03 seconds
Started Aug 23 11:24:54 PM UTC 24
Finished Aug 23 11:28:30 PM UTC 24
Peak memory 228616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467463104 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.1467463104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.826572159
Short name T281
Test name
Test status
Simulation time 1377085088 ps
CPU time 17.42 seconds
Started Aug 23 11:24:54 PM UTC 24
Finished Aug 23 11:25:12 PM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826572159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.826572159
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3658402333
Short name T276
Test name
Test status
Simulation time 175337101 ps
CPU time 9.22 seconds
Started Aug 23 11:24:52 PM UTC 24
Finished Aug 23 11:25:02 PM UTC 24
Peak memory 228168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658402333 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3658402333
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.1981721383
Short name T283
Test name
Test status
Simulation time 2188069489 ps
CPU time 27.44 seconds
Started Aug 23 11:24:51 PM UTC 24
Finished Aug 23 11:25:19 PM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198172138
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.1981721383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3015187807
Short name T349
Test name
Test status
Simulation time 13722498260 ps
CPU time 198.3 seconds
Started Aug 23 11:25:00 PM UTC 24
Finished Aug 23 11:28:21 PM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3015187807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3015187807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2817875898
Short name T31
Test name
Test status
Simulation time 249620084 ps
CPU time 8.46 seconds
Started Aug 23 11:18:02 PM UTC 24
Finished Aug 23 11:18:11 PM UTC 24
Peak memory 227300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817875898 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2817875898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.873088116
Short name T50
Test name
Test status
Simulation time 4682815825 ps
CPU time 291.99 seconds
Started Aug 23 11:18:00 PM UTC 24
Finished Aug 23 11:22:56 PM UTC 24
Peak memory 258724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873088116 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.873088116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.884624341
Short name T38
Test name
Test status
Simulation time 2062138528 ps
CPU time 19.9 seconds
Started Aug 23 11:18:02 PM UTC 24
Finished Aug 23 11:18:23 PM UTC 24
Peak memory 227724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884624341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.884624341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.961242989
Short name T57
Test name
Test status
Simulation time 726317146 ps
CPU time 9.42 seconds
Started Aug 23 11:18:00 PM UTC 24
Finished Aug 23 11:18:10 PM UTC 24
Peak memory 228412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961242989 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.961242989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1338001273
Short name T40
Test name
Test status
Simulation time 1436612244 ps
CPU time 209.14 seconds
Started Aug 23 11:18:02 PM UTC 24
Finished Aug 23 11:21:34 PM UTC 24
Peak memory 257480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338001273 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1338001273
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.2910128735
Short name T21
Test name
Test status
Simulation time 272060881 ps
CPU time 10.68 seconds
Started Aug 23 11:17:58 PM UTC 24
Finished Aug 23 11:18:09 PM UTC 24
Peak memory 228572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910128735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2910128735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.557631725
Short name T17
Test name
Test status
Simulation time 285961543 ps
CPU time 14.95 seconds
Started Aug 23 11:18:00 PM UTC 24
Finished Aug 23 11:18:16 PM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557631725
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.557631725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4124188069
Short name T14
Test name
Test status
Simulation time 3187267947 ps
CPU time 31.44 seconds
Started Aug 23 11:18:02 PM UTC 24
Finished Aug 23 11:18:35 PM UTC 24
Peak memory 232664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4124188069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.4124188069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1730501916
Short name T287
Test name
Test status
Simulation time 691039601 ps
CPU time 7.21 seconds
Started Aug 23 11:25:16 PM UTC 24
Finished Aug 23 11:25:24 PM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730501916 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1730501916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2100101759
Short name T356
Test name
Test status
Simulation time 14334333726 ps
CPU time 262.35 seconds
Started Aug 23 11:25:12 PM UTC 24
Finished Aug 23 11:29:38 PM UTC 24
Peak memory 256304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100101759 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.2100101759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2881063394
Short name T290
Test name
Test status
Simulation time 1326761782 ps
CPU time 17.23 seconds
Started Aug 23 11:25:13 PM UTC 24
Finished Aug 23 11:25:31 PM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881063394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2881063394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2301137043
Short name T284
Test name
Test status
Simulation time 2534462437 ps
CPU time 10.52 seconds
Started Aug 23 11:25:11 PM UTC 24
Finished Aug 23 11:25:23 PM UTC 24
Peak memory 228388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301137043 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2301137043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3130583334
Short name T289
Test name
Test status
Simulation time 1802012840 ps
CPU time 18.9 seconds
Started Aug 23 11:25:08 PM UTC 24
Finished Aug 23 11:25:28 PM UTC 24
Peak memory 228500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313058333
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.3130583334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2021968093
Short name T292
Test name
Test status
Simulation time 691497403 ps
CPU time 7.27 seconds
Started Aug 23 11:25:26 PM UTC 24
Finished Aug 23 11:25:35 PM UTC 24
Peak memory 227832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021968093 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2021968093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.790146784
Short name T351
Test name
Test status
Simulation time 18308500097 ps
CPU time 184.22 seconds
Started Aug 23 11:25:23 PM UTC 24
Finished Aug 23 11:28:30 PM UTC 24
Peak memory 228880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790146784 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.790146784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2043577694
Short name T293
Test name
Test status
Simulation time 678601954 ps
CPU time 17.19 seconds
Started Aug 23 11:25:24 PM UTC 24
Finished Aug 23 11:25:43 PM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043577694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2043577694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1720373899
Short name T291
Test name
Test status
Simulation time 177480600 ps
CPU time 9.27 seconds
Started Aug 23 11:25:23 PM UTC 24
Finished Aug 23 11:25:34 PM UTC 24
Peak memory 228168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720373899 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1720373899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2034676083
Short name T296
Test name
Test status
Simulation time 545424877 ps
CPU time 27.54 seconds
Started Aug 23 11:25:20 PM UTC 24
Finished Aug 23 11:25:49 PM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203467608
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.2034676083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2035974258
Short name T308
Test name
Test status
Simulation time 4052625633 ps
CPU time 59.28 seconds
Started Aug 23 11:25:25 PM UTC 24
Finished Aug 23 11:26:26 PM UTC 24
Peak memory 239064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2035974258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2035974258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3874139520
Short name T297
Test name
Test status
Simulation time 1376232838 ps
CPU time 7.13 seconds
Started Aug 23 11:25:45 PM UTC 24
Finished Aug 23 11:25:53 PM UTC 24
Peak memory 228232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874139520 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3874139520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.309666733
Short name T362
Test name
Test status
Simulation time 6211784601 ps
CPU time 297.12 seconds
Started Aug 23 11:25:34 PM UTC 24
Finished Aug 23 11:30:35 PM UTC 24
Peak memory 246188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309666733 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.309666733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3931588737
Short name T298
Test name
Test status
Simulation time 973228305 ps
CPU time 20.01 seconds
Started Aug 23 11:25:35 PM UTC 24
Finished Aug 23 11:25:57 PM UTC 24
Peak memory 228956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931588737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3931588737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.1093916674
Short name T294
Test name
Test status
Simulation time 268779765 ps
CPU time 10.51 seconds
Started Aug 23 11:25:32 PM UTC 24
Finished Aug 23 11:25:44 PM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093916674 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1093916674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.2358850723
Short name T300
Test name
Test status
Simulation time 389501079 ps
CPU time 31.92 seconds
Started Aug 23 11:25:28 PM UTC 24
Finished Aug 23 11:26:02 PM UTC 24
Peak memory 228836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235885072
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.2358850723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1310823594
Short name T336
Test name
Test status
Simulation time 12480759414 ps
CPU time 104.02 seconds
Started Aug 23 11:25:44 PM UTC 24
Finished Aug 23 11:27:30 PM UTC 24
Peak memory 239068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1310823594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1310823594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.810511223
Short name T302
Test name
Test status
Simulation time 1078985826 ps
CPU time 8.63 seconds
Started Aug 23 11:26:01 PM UTC 24
Finished Aug 23 11:26:11 PM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810511223 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.810511223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1554259645
Short name T359
Test name
Test status
Simulation time 5246767083 ps
CPU time 238.36 seconds
Started Aug 23 11:25:53 PM UTC 24
Finished Aug 23 11:29:54 PM UTC 24
Peak memory 246064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554259645 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.1554259645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.297180652
Short name T304
Test name
Test status
Simulation time 2148504741 ps
CPU time 19.96 seconds
Started Aug 23 11:25:54 PM UTC 24
Finished Aug 23 11:26:15 PM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297180652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.297180652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1573080137
Short name T299
Test name
Test status
Simulation time 356463571 ps
CPU time 9.23 seconds
Started Aug 23 11:25:50 PM UTC 24
Finished Aug 23 11:26:00 PM UTC 24
Peak memory 228392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573080137 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1573080137
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3140745641
Short name T310
Test name
Test status
Simulation time 2952044260 ps
CPU time 38.72 seconds
Started Aug 23 11:25:49 PM UTC 24
Finished Aug 23 11:26:29 PM UTC 24
Peak memory 228712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314074564
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.3140745641
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1052337811
Short name T353
Test name
Test status
Simulation time 4576449275 ps
CPU time 161.53 seconds
Started Aug 23 11:25:58 PM UTC 24
Finished Aug 23 11:28:42 PM UTC 24
Peak memory 235244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1052337811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1052337811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.426997956
Short name T309
Test name
Test status
Simulation time 497093782 ps
CPU time 8.45 seconds
Started Aug 23 11:26:18 PM UTC 24
Finished Aug 23 11:26:28 PM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426997956 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.426997956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1158922064
Short name T361
Test name
Test status
Simulation time 21589611454 ps
CPU time 258.14 seconds
Started Aug 23 11:26:12 PM UTC 24
Finished Aug 23 11:30:34 PM UTC 24
Peak memory 259444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158922064 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.1158922064
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3816064140
Short name T312
Test name
Test status
Simulation time 1226321266 ps
CPU time 17.34 seconds
Started Aug 23 11:26:15 PM UTC 24
Finished Aug 23 11:26:34 PM UTC 24
Peak memory 228240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816064140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3816064140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.872626276
Short name T306
Test name
Test status
Simulation time 263827126 ps
CPU time 10.58 seconds
Started Aug 23 11:26:06 PM UTC 24
Finished Aug 23 11:26:18 PM UTC 24
Peak memory 228508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872626276 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.872626276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1613779426
Short name T303
Test name
Test status
Simulation time 209258807 ps
CPU time 9.81 seconds
Started Aug 23 11:26:03 PM UTC 24
Finished Aug 23 11:26:14 PM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161377942
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.1613779426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3056529620
Short name T325
Test name
Test status
Simulation time 3454534688 ps
CPU time 44.28 seconds
Started Aug 23 11:26:16 PM UTC 24
Finished Aug 23 11:27:02 PM UTC 24
Peak memory 230876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3056529620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3056529620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.319992615
Short name T316
Test name
Test status
Simulation time 690334346 ps
CPU time 7.13 seconds
Started Aug 23 11:26:33 PM UTC 24
Finished Aug 23 11:26:42 PM UTC 24
Peak memory 227840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319992615 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.319992615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3823952865
Short name T358
Test name
Test status
Simulation time 4427371497 ps
CPU time 200.74 seconds
Started Aug 23 11:26:27 PM UTC 24
Finished Aug 23 11:29:51 PM UTC 24
Peak memory 257440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823952865 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.3823952865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3183025749
Short name T320
Test name
Test status
Simulation time 3529751755 ps
CPU time 19.67 seconds
Started Aug 23 11:26:28 PM UTC 24
Finished Aug 23 11:26:49 PM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183025749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3183025749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.2280716509
Short name T311
Test name
Test status
Simulation time 176771866 ps
CPU time 9.14 seconds
Started Aug 23 11:26:22 PM UTC 24
Finished Aug 23 11:26:32 PM UTC 24
Peak memory 228168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280716509 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2280716509
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2229071916
Short name T318
Test name
Test status
Simulation time 1056283873 ps
CPU time 23.97 seconds
Started Aug 23 11:26:18 PM UTC 24
Finished Aug 23 11:26:43 PM UTC 24
Peak memory 228644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222907191
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.2229071916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.437150681
Short name T357
Test name
Test status
Simulation time 10615344806 ps
CPU time 191.99 seconds
Started Aug 23 11:26:29 PM UTC 24
Finished Aug 23 11:29:44 PM UTC 24
Peak memory 246604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=437150681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_stress_all_with_rand_reset.437150681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1381313345
Short name T321
Test name
Test status
Simulation time 339180391 ps
CPU time 7.25 seconds
Started Aug 23 11:26:44 PM UTC 24
Finished Aug 23 11:26:52 PM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381313345 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1381313345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.813582846
Short name T355
Test name
Test status
Simulation time 27822150952 ps
CPU time 171.64 seconds
Started Aug 23 11:26:42 PM UTC 24
Finished Aug 23 11:29:36 PM UTC 24
Peak memory 259484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813582846 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.813582846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.537213826
Short name T326
Test name
Test status
Simulation time 4120561961 ps
CPU time 19.69 seconds
Started Aug 23 11:26:42 PM UTC 24
Finished Aug 23 11:27:02 PM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537213826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.537213826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1320326160
Short name T319
Test name
Test status
Simulation time 688481795 ps
CPU time 9.34 seconds
Started Aug 23 11:26:37 PM UTC 24
Finished Aug 23 11:26:48 PM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320326160 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1320326160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.4042507403
Short name T330
Test name
Test status
Simulation time 2478749752 ps
CPU time 40.48 seconds
Started Aug 23 11:26:34 PM UTC 24
Finished Aug 23 11:27:16 PM UTC 24
Peak memory 230760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404250740
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.4042507403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.2462177830
Short name T328
Test name
Test status
Simulation time 260151903 ps
CPU time 8.68 seconds
Started Aug 23 11:27:01 PM UTC 24
Finished Aug 23 11:27:11 PM UTC 24
Peak memory 227476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462177830 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2462177830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2723289051
Short name T354
Test name
Test status
Simulation time 10538749939 ps
CPU time 111.62 seconds
Started Aug 23 11:26:50 PM UTC 24
Finished Aug 23 11:28:43 PM UTC 24
Peak memory 228552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723289051 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.2723289051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.321344688
Short name T329
Test name
Test status
Simulation time 1379064194 ps
CPU time 17.3 seconds
Started Aug 23 11:26:53 PM UTC 24
Finished Aug 23 11:27:11 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321344688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.321344688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.811377292
Short name T323
Test name
Test status
Simulation time 530905385 ps
CPU time 10.75 seconds
Started Aug 23 11:26:49 PM UTC 24
Finished Aug 23 11:27:01 PM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811377292 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.811377292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3144317641
Short name T327
Test name
Test status
Simulation time 203741608 ps
CPU time 16.67 seconds
Started Aug 23 11:26:45 PM UTC 24
Finished Aug 23 11:27:03 PM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314431764
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.3144317641
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3204716127
Short name T344
Test name
Test status
Simulation time 5968953394 ps
CPU time 48.97 seconds
Started Aug 23 11:26:56 PM UTC 24
Finished Aug 23 11:27:46 PM UTC 24
Peak memory 230876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3204716127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3204716127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1437329739
Short name T333
Test name
Test status
Simulation time 254019252 ps
CPU time 8.66 seconds
Started Aug 23 11:27:11 PM UTC 24
Finished Aug 23 11:27:21 PM UTC 24
Peak memory 227668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437329739 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1437329739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4078032781
Short name T360
Test name
Test status
Simulation time 9645343678 ps
CPU time 203.27 seconds
Started Aug 23 11:27:03 PM UTC 24
Finished Aug 23 11:30:29 PM UTC 24
Peak memory 228536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078032781 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.4078032781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.675563983
Short name T334
Test name
Test status
Simulation time 2601585622 ps
CPU time 19.66 seconds
Started Aug 23 11:27:03 PM UTC 24
Finished Aug 23 11:27:24 PM UTC 24
Peak memory 228892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675563983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.675563983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.875884255
Short name T332
Test name
Test status
Simulation time 1529099062 ps
CPU time 14 seconds
Started Aug 23 11:27:03 PM UTC 24
Finished Aug 23 11:27:18 PM UTC 24
Peak memory 228460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875884255 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.875884255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.860648076
Short name T342
Test name
Test status
Simulation time 732174248 ps
CPU time 38.77 seconds
Started Aug 23 11:27:02 PM UTC 24
Finished Aug 23 11:27:42 PM UTC 24
Peak memory 228708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860648076
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.860648076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3882132112
Short name T340
Test name
Test status
Simulation time 700210073 ps
CPU time 25.87 seconds
Started Aug 23 11:27:08 PM UTC 24
Finished Aug 23 11:27:35 PM UTC 24
Peak memory 232924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3882132112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3882132112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.625947579
Short name T339
Test name
Test status
Simulation time 1971355900 ps
CPU time 12.33 seconds
Started Aug 23 11:27:21 PM UTC 24
Finished Aug 23 11:27:35 PM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625947579 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.625947579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3558964546
Short name T363
Test name
Test status
Simulation time 8888947392 ps
CPU time 199.52 seconds
Started Aug 23 11:27:17 PM UTC 24
Finished Aug 23 11:30:40 PM UTC 24
Peak memory 227964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558964546 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.3558964546
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.4210720420
Short name T341
Test name
Test status
Simulation time 2062162157 ps
CPU time 19.74 seconds
Started Aug 23 11:27:18 PM UTC 24
Finished Aug 23 11:27:39 PM UTC 24
Peak memory 228096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210720420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4210720420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1942586452
Short name T335
Test name
Test status
Simulation time 1017369431 ps
CPU time 10.48 seconds
Started Aug 23 11:27:15 PM UTC 24
Finished Aug 23 11:27:27 PM UTC 24
Peak memory 228064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942586452 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1942586452
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1902772609
Short name T338
Test name
Test status
Simulation time 5178171418 ps
CPU time 20.97 seconds
Started Aug 23 11:27:12 PM UTC 24
Finished Aug 23 11:27:34 PM UTC 24
Peak memory 227504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190277260
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.1902772609
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.186144982
Short name T146
Test name
Test status
Simulation time 5424093579 ps
CPU time 93.63 seconds
Started Aug 23 11:27:19 PM UTC 24
Finished Aug 23 11:28:55 PM UTC 24
Peak memory 239068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=186144982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.rom_ctrl_stress_all_with_rand_reset.186144982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2238994153
Short name T81
Test name
Test status
Simulation time 1034686768 ps
CPU time 8.69 seconds
Started Aug 23 11:18:08 PM UTC 24
Finished Aug 23 11:18:18 PM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238994153 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2238994153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1621309161
Short name T52
Test name
Test status
Simulation time 2061152445 ps
CPU time 20.27 seconds
Started Aug 23 11:18:08 PM UTC 24
Finished Aug 23 11:18:30 PM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621309161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1621309161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.2464378251
Short name T58
Test name
Test status
Simulation time 530959273 ps
CPU time 10.48 seconds
Started Aug 23 11:18:02 PM UTC 24
Finished Aug 23 11:18:14 PM UTC 24
Peak memory 228044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464378251 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2464378251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2950816750
Short name T32
Test name
Test status
Simulation time 521093976 ps
CPU time 10.76 seconds
Started Aug 23 11:18:02 PM UTC 24
Finished Aug 23 11:18:14 PM UTC 24
Peak memory 224668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950816750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2950816750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3520206020
Short name T36
Test name
Test status
Simulation time 555604923 ps
CPU time 30.1 seconds
Started Aug 23 11:18:02 PM UTC 24
Finished Aug 23 11:18:33 PM UTC 24
Peak memory 228708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352020602
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.3520206020
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.240552532
Short name T66
Test name
Test status
Simulation time 3554036219 ps
CPU time 128.06 seconds
Started Aug 23 11:18:08 PM UTC 24
Finished Aug 23 11:20:18 PM UTC 24
Peak memory 234972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=240552532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.rom_ctrl_stress_all_with_rand_reset.240552532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2459388159
Short name T82
Test name
Test status
Simulation time 4953028843 ps
CPU time 8.65 seconds
Started Aug 23 11:18:12 PM UTC 24
Finished Aug 23 11:18:22 PM UTC 24
Peak memory 227804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459388159 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2459388159
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.369311269
Short name T25
Test name
Test status
Simulation time 8367293508 ps
CPU time 124.34 seconds
Started Aug 23 11:18:11 PM UTC 24
Finished Aug 23 11:20:18 PM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369311269 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.369311269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1350746572
Short name T53
Test name
Test status
Simulation time 497741013 ps
CPU time 19.59 seconds
Started Aug 23 11:18:12 PM UTC 24
Finished Aug 23 11:18:33 PM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350746572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1350746572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2738236515
Short name T147
Test name
Test status
Simulation time 536299636 ps
CPU time 10.58 seconds
Started Aug 23 11:18:11 PM UTC 24
Finished Aug 23 11:18:23 PM UTC 24
Peak memory 228176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738236515 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2738236515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2948958663
Short name T62
Test name
Test status
Simulation time 187432739 ps
CPU time 9.68 seconds
Started Aug 23 11:18:09 PM UTC 24
Finished Aug 23 11:18:20 PM UTC 24
Peak memory 225468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948958663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2948958663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2853788187
Short name T74
Test name
Test status
Simulation time 1827433823 ps
CPU time 23.04 seconds
Started Aug 23 11:18:10 PM UTC 24
Finished Aug 23 11:18:35 PM UTC 24
Peak memory 228644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285378818
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.2853788187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1070140337
Short name T211
Test name
Test status
Simulation time 11535262597 ps
CPU time 274.73 seconds
Started Aug 23 11:18:12 PM UTC 24
Finished Aug 23 11:22:51 PM UTC 24
Peak memory 245220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1070140337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1070140337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2132114335
Short name T219
Test name
Test status
Simulation time 17973251152 ps
CPU time 289.08 seconds
Started Aug 23 11:18:17 PM UTC 24
Finished Aug 23 11:23:09 PM UTC 24
Peak memory 257552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132114335 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.2132114335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3056078470
Short name T71
Test name
Test status
Simulation time 516254974 ps
CPU time 10.57 seconds
Started Aug 23 11:18:17 PM UTC 24
Finished Aug 23 11:18:28 PM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056078470 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3056078470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.59603666
Short name T70
Test name
Test status
Simulation time 277061738 ps
CPU time 11.27 seconds
Started Aug 23 11:18:14 PM UTC 24
Finished Aug 23 11:18:27 PM UTC 24
Peak memory 228524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59603666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_
TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.59603666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.787944130
Short name T72
Test name
Test status
Simulation time 205618754 ps
CPU time 13.42 seconds
Started Aug 23 11:18:14 PM UTC 24
Finished Aug 23 11:18:29 PM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787944130
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.787944130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1593571858
Short name T67
Test name
Test status
Simulation time 3750206205 ps
CPU time 126.12 seconds
Started Aug 23 11:18:21 PM UTC 24
Finished Aug 23 11:20:29 PM UTC 24
Peak memory 235044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1593571858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1593571858
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.2868572280
Short name T151
Test name
Test status
Simulation time 296423562 ps
CPU time 8.58 seconds
Started Aug 23 11:18:31 PM UTC 24
Finished Aug 23 11:18:41 PM UTC 24
Peak memory 227936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868572280 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2868572280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.846608868
Short name T245
Test name
Test status
Simulation time 66392075329 ps
CPU time 325.39 seconds
Started Aug 23 11:18:28 PM UTC 24
Finished Aug 23 11:23:57 PM UTC 24
Peak memory 246064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846608868 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.846608868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.4031897455
Short name T55
Test name
Test status
Simulation time 661503474 ps
CPU time 17.41 seconds
Started Aug 23 11:18:29 PM UTC 24
Finished Aug 23 11:18:47 PM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031897455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4031897455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3696696478
Short name T150
Test name
Test status
Simulation time 1071383282 ps
CPU time 10.48 seconds
Started Aug 23 11:18:28 PM UTC 24
Finished Aug 23 11:18:39 PM UTC 24
Peak memory 228688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696696478 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3696696478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2470539473
Short name T73
Test name
Test status
Simulation time 183818697 ps
CPU time 9.59 seconds
Started Aug 23 11:18:24 PM UTC 24
Finished Aug 23 11:18:34 PM UTC 24
Peak memory 225580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470539473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2470539473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.674920237
Short name T152
Test name
Test status
Simulation time 394670243 ps
CPU time 25.17 seconds
Started Aug 23 11:18:24 PM UTC 24
Finished Aug 23 11:18:50 PM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674920237
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.674920237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.227309287
Short name T149
Test name
Test status
Simulation time 255443957 ps
CPU time 8.96 seconds
Started Aug 23 11:18:40 PM UTC 24
Finished Aug 23 11:18:50 PM UTC 24
Peak memory 227964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227309287 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.227309287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2736094766
Short name T56
Test name
Test status
Simulation time 2741571003 ps
CPU time 20.18 seconds
Started Aug 23 11:18:36 PM UTC 24
Finished Aug 23 11:18:57 PM UTC 24
Peak memory 228700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736094766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2736094766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.1239512318
Short name T127
Test name
Test status
Simulation time 264541581 ps
CPU time 10.43 seconds
Started Aug 23 11:18:35 PM UTC 24
Finished Aug 23 11:18:47 PM UTC 24
Peak memory 228256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239512318 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1239512318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2079611879
Short name T93
Test name
Test status
Simulation time 268402066 ps
CPU time 11.59 seconds
Started Aug 23 11:18:34 PM UTC 24
Finished Aug 23 11:18:47 PM UTC 24
Peak memory 228512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079611879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2079611879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.719167266
Short name T128
Test name
Test status
Simulation time 241375468 ps
CPU time 13 seconds
Started Aug 23 11:18:34 PM UTC 24
Finished Aug 23 11:18:48 PM UTC 24
Peak memory 228752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719167266
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.719167266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2803336388
Short name T68
Test name
Test status
Simulation time 15219647274 ps
CPU time 128.04 seconds
Started Aug 23 11:18:37 PM UTC 24
Finished Aug 23 11:20:47 PM UTC 24
Peak memory 246356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2803336388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2803336388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest
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