Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.89 92.13 97.68 100.00 98.28 98.05 98.83


Total tests in report: 457
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.85 64.85 92.58 92.58 70.37 70.37 50.72 50.72 40.00 40.00 89.31 89.31 93.85 93.85 17.10 17.10 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2505273555
79.87 15.02 95.93 3.35 83.71 13.34 75.99 25.26 40.00 0.00 92.41 3.10 95.65 1.80 75.41 58.31 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2632750167
85.67 5.80 96.05 0.12 86.24 2.53 78.14 2.15 73.33 33.33 93.10 0.69 95.80 0.15 77.05 1.64 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3887921624
90.34 4.67 96.65 0.60 87.36 1.12 84.76 6.62 93.33 20.00 96.21 3.10 96.10 0.30 77.99 0.94 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.883960503
93.03 2.69 96.65 0.00 87.50 0.14 91.70 6.95 93.33 0.00 96.21 0.00 96.10 0.00 89.70 11.71 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4090426193
94.15 1.12 96.89 0.24 88.20 0.70 91.70 0.00 93.33 0.00 97.24 1.03 96.10 0.00 95.55 5.85 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2673672807
95.18 1.03 96.89 0.00 88.62 0.42 91.85 0.15 100.00 6.67 97.24 0.00 96.10 0.00 95.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.244299821
95.75 0.57 96.89 0.00 90.45 1.83 93.18 1.32 100.00 0.00 97.93 0.69 96.25 0.15 95.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.4113404189
96.10 0.34 96.89 0.00 90.59 0.14 95.45 2.27 100.00 0.00 97.93 0.00 96.25 0.00 95.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1385426365
96.31 0.22 96.89 0.00 90.73 0.14 96.48 1.02 100.00 0.00 98.28 0.34 96.25 0.00 95.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3379112045
96.51 0.20 96.89 0.00 91.29 0.56 96.53 0.05 100.00 0.00 98.28 0.00 96.55 0.30 96.02 0.47 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2946017259
96.68 0.17 96.89 0.00 91.43 0.14 96.53 0.00 100.00 0.00 98.28 0.00 97.60 1.05 96.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2076733924
96.81 0.13 96.89 0.00 91.99 0.56 96.63 0.10 100.00 0.00 98.28 0.00 97.60 0.00 96.25 0.23 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1135391694
96.91 0.10 96.89 0.00 91.99 0.00 96.63 0.00 100.00 0.00 98.28 0.00 97.60 0.00 96.96 0.70 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3678831407
97.01 0.10 96.89 0.00 91.99 0.00 97.33 0.70 100.00 0.00 98.28 0.00 97.60 0.00 96.96 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.12163444
97.08 0.08 96.89 0.00 91.99 0.00 97.33 0.00 100.00 0.00 98.28 0.00 97.90 0.30 97.19 0.23 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.316725825
97.15 0.07 96.89 0.00 91.99 0.00 97.33 0.00 100.00 0.00 98.28 0.00 97.90 0.00 97.66 0.47 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3182931392
97.19 0.04 96.89 0.00 91.99 0.00 97.38 0.05 100.00 0.00 98.28 0.00 97.90 0.00 97.89 0.23 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3960409963
97.23 0.04 96.89 0.00 91.99 0.00 97.65 0.27 100.00 0.00 98.28 0.00 97.90 0.00 97.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.778672738
97.26 0.03 96.89 0.00 91.99 0.00 97.65 0.00 100.00 0.00 98.28 0.00 97.90 0.00 98.13 0.23 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2112367483
97.30 0.03 96.89 0.00 91.99 0.00 97.65 0.00 100.00 0.00 98.28 0.00 97.90 0.00 98.36 0.23 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1019653831
97.33 0.03 96.89 0.00 91.99 0.00 97.65 0.00 100.00 0.00 98.28 0.00 97.90 0.00 98.59 0.23 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2821206973
97.36 0.03 96.89 0.00 91.99 0.00 97.65 0.00 100.00 0.00 98.28 0.00 97.90 0.00 98.83 0.23 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.791597083
97.38 0.02 96.89 0.00 91.99 0.00 97.65 0.00 100.00 0.00 98.28 0.00 98.05 0.15 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3482430906
97.40 0.02 96.89 0.00 92.13 0.14 97.65 0.00 100.00 0.00 98.28 0.00 98.05 0.00 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3026185672
97.41 0.01 96.89 0.00 92.13 0.00 97.68 0.02 100.00 0.00 98.28 0.00 98.05 0.00 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.4191552752

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.191236679
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2824901149
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.105317949
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1060609655
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.348317379
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2376162312
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1385713490
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.859757974
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3912039962
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2349941506
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2627192665
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1728920889
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1532244823
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2359981103
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2643699247
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2932000597
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3257135798
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3279848733
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1256420455
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3993258805
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1638988168
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3152672432
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3957586521
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3639401355
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3576690430
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3017592483
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.203451697
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.628134918
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2283506381
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.919828141
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.213515988
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3044258970
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3543543141
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3750811710
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2942164618
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2412302271
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.450584199
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4212139010
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4241372990
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2410108017
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2930190084
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3568196071
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2383262296
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.957830467
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1188311304
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.133243365
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.262100632
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3164164136
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4109884092
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1621151845
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2672631599
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2015042094
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3362420617
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2262016215
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1095544853
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.743777972
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2646551786
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1795903770
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.854826157
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2921496150
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.649643998
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3587396852
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2286890958
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.907277240
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3741419202
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1829024542
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3103897924
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2129440176
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.576560800
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3772781707
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2067023581
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.454403315
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2256303946
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2770476661
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1187312176
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1546544883
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1542359554
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1233464792
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2976423441
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1946428485
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4158327374
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1631630759
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/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2238994153
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/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2803336388



Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.229453331 Aug 23 11:17:35 PM UTC 24 Aug 23 11:17:51 PM UTC 24 1856366042 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1767819684 Aug 23 11:17:49 PM UTC 24 Aug 23 11:17:57 PM UTC 24 474788188 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1651834283 Aug 23 11:17:49 PM UTC 24 Aug 23 11:17:58 PM UTC 24 591765705 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2505273555 Aug 23 11:17:35 PM UTC 24 Aug 23 11:17:58 PM UTC 24 2135120831 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.2695458566 Aug 23 11:17:49 PM UTC 24 Aug 23 11:17:59 PM UTC 24 884374377 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.1594338339 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:00 PM UTC 24 415200456 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3960409963 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:00 PM UTC 24 1604109443 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1741536213 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:00 PM UTC 24 179683969 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1375734617 Aug 23 11:17:52 PM UTC 24 Aug 23 11:18:00 PM UTC 24 171464455 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.172791256 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:01 PM UTC 24 2844894077 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.4113404189 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:01 PM UTC 24 189254114 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1394142441 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:01 PM UTC 24 263711161 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2162814190 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:01 PM UTC 24 270985958 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.883960503 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:07 PM UTC 24 1375544649 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3379112045 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:08 PM UTC 24 689213566 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2834831620 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:08 PM UTC 24 3303979393 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.2910128735 Aug 23 11:17:58 PM UTC 24 Aug 23 11:18:09 PM UTC 24 272060881 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.961242989 Aug 23 11:18:00 PM UTC 24 Aug 23 11:18:10 PM UTC 24 726317146 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2372666096 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:11 PM UTC 24 517102187 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.617208961 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:11 PM UTC 24 1018422998 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2817875898 Aug 23 11:18:02 PM UTC 24 Aug 23 11:18:11 PM UTC 24 249620084 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1692682097 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:12 PM UTC 24 374711346 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.2464378251 Aug 23 11:18:02 PM UTC 24 Aug 23 11:18:14 PM UTC 24 530959273 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2950816750 Aug 23 11:18:02 PM UTC 24 Aug 23 11:18:14 PM UTC 24 521093976 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1250477225 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:16 PM UTC 24 2095302484 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.557631725 Aug 23 11:18:00 PM UTC 24 Aug 23 11:18:16 PM UTC 24 285961543 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2238994153 Aug 23 11:18:08 PM UTC 24 Aug 23 11:18:18 PM UTC 24 1034686768 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2948958663 Aug 23 11:18:09 PM UTC 24 Aug 23 11:18:20 PM UTC 24 187432739 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2459388159 Aug 23 11:18:12 PM UTC 24 Aug 23 11:18:22 PM UTC 24 4953028843 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.884624341 Aug 23 11:18:02 PM UTC 24 Aug 23 11:18:23 PM UTC 24 2062138528 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2738236515 Aug 23 11:18:11 PM UTC 24 Aug 23 11:18:23 PM UTC 24 536299636 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2632750167 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:27 PM UTC 24 1948304153 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.59603666 Aug 23 11:18:14 PM UTC 24 Aug 23 11:18:27 PM UTC 24 277061738 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3056078470 Aug 23 11:18:17 PM UTC 24 Aug 23 11:18:28 PM UTC 24 516254974 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.787944130 Aug 23 11:18:14 PM UTC 24 Aug 23 11:18:29 PM UTC 24 205618754 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1621309161 Aug 23 11:18:08 PM UTC 24 Aug 23 11:18:30 PM UTC 24 2061152445 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1350746572 Aug 23 11:18:12 PM UTC 24 Aug 23 11:18:33 PM UTC 24 497741013 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3520206020 Aug 23 11:18:02 PM UTC 24 Aug 23 11:18:33 PM UTC 24 555604923 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2470539473 Aug 23 11:18:24 PM UTC 24 Aug 23 11:18:34 PM UTC 24 183818697 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2853788187 Aug 23 11:18:10 PM UTC 24 Aug 23 11:18:35 PM UTC 24 1827433823 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4124188069 Aug 23 11:18:02 PM UTC 24 Aug 23 11:18:35 PM UTC 24 3187267947 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1135391694 Aug 23 11:18:23 PM UTC 24 Aug 23 11:18:36 PM UTC 24 1086604712 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3696696478 Aug 23 11:18:28 PM UTC 24 Aug 23 11:18:39 PM UTC 24 1071383282 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.778672738 Aug 23 11:18:19 PM UTC 24 Aug 23 11:18:39 PM UTC 24 5497083133 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.2868572280 Aug 23 11:18:31 PM UTC 24 Aug 23 11:18:41 PM UTC 24 296423562 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1788924367 Aug 23 11:17:49 PM UTC 24 Aug 23 11:18:47 PM UTC 24 30282944999 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.1239512318 Aug 23 11:18:35 PM UTC 24 Aug 23 11:18:47 PM UTC 24 264541581 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2079611879 Aug 23 11:18:34 PM UTC 24 Aug 23 11:18:47 PM UTC 24 268402066 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.4031897455 Aug 23 11:18:29 PM UTC 24 Aug 23 11:18:47 PM UTC 24 661503474 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.719167266 Aug 23 11:18:34 PM UTC 24 Aug 23 11:18:48 PM UTC 24 241375468 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.674920237 Aug 23 11:18:24 PM UTC 24 Aug 23 11:18:50 PM UTC 24 394670243 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.227309287 Aug 23 11:18:40 PM UTC 24 Aug 23 11:18:50 PM UTC 24 255443957 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.803436553 Aug 23 11:18:41 PM UTC 24 Aug 23 11:18:52 PM UTC 24 908360377 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.3115203517 Aug 23 11:18:48 PM UTC 24 Aug 23 11:18:57 PM UTC 24 192976756 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2736094766 Aug 23 11:18:36 PM UTC 24 Aug 23 11:18:57 PM UTC 24 2741571003 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4090426193 Aug 23 11:17:49 PM UTC 24 Aug 23 11:19:00 PM UTC 24 1910916718 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1546523915 Aug 23 11:18:51 PM UTC 24 Aug 23 11:19:02 PM UTC 24 177199300 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.4055758611 Aug 23 11:18:40 PM UTC 24 Aug 23 11:19:03 PM UTC 24 3372235204 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3128317418 Aug 23 11:18:47 PM UTC 24 Aug 23 11:19:06 PM UTC 24 347131267 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1962779758 Aug 23 11:18:59 PM UTC 24 Aug 23 11:19:08 PM UTC 24 249170811 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.880619290 Aug 23 11:18:53 PM UTC 24 Aug 23 11:19:15 PM UTC 24 508286407 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.2430643991 Aug 23 11:18:49 PM UTC 24 Aug 23 11:19:15 PM UTC 24 545329975 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1508979462 Aug 23 11:19:03 PM UTC 24 Aug 23 11:19:15 PM UTC 24 1443978846 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1385426365 Aug 23 11:18:30 PM UTC 24 Aug 23 11:19:21 PM UTC 24 5035134059 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3764965892 Aug 23 11:19:15 PM UTC 24 Aug 23 11:19:24 PM UTC 24 661729652 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.328593416 Aug 23 11:17:49 PM UTC 24 Aug 23 11:19:25 PM UTC 24 7077060843 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.331522430 Aug 23 11:19:15 PM UTC 24 Aug 23 11:19:27 PM UTC 24 257293664 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.635848787 Aug 23 11:19:01 PM UTC 24 Aug 23 11:19:27 PM UTC 24 359093008 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3193101277 Aug 23 11:19:07 PM UTC 24 Aug 23 11:19:28 PM UTC 24 2609305107 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1859370212 Aug 23 11:17:49 PM UTC 24 Aug 23 11:19:38 PM UTC 24 1510892011 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.1625899824 Aug 23 11:17:51 PM UTC 24 Aug 23 11:19:38 PM UTC 24 231360845 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.553905074 Aug 23 11:19:15 PM UTC 24 Aug 23 11:19:38 PM UTC 24 2074529927 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1369614533 Aug 23 11:19:29 PM UTC 24 Aug 23 11:19:40 PM UTC 24 689178500 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.12163444 Aug 23 11:18:02 PM UTC 24 Aug 23 11:19:40 PM UTC 24 3819520363 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3031945878 Aug 23 11:19:27 PM UTC 24 Aug 23 11:19:41 PM UTC 24 2657541480 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.4191552752 Aug 23 11:19:25 PM UTC 24 Aug 23 11:19:43 PM UTC 24 432877283 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.392987281 Aug 23 11:19:40 PM UTC 24 Aug 23 11:19:49 PM UTC 24 174238593 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3410767326 Aug 23 11:19:27 PM UTC 24 Aug 23 11:19:50 PM UTC 24 1435378338 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3220829337 Aug 23 11:19:42 PM UTC 24 Aug 23 11:19:58 PM UTC 24 1006098517 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3229525286 Aug 23 11:19:38 PM UTC 24 Aug 23 11:19:59 PM UTC 24 1771985546 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2216420493 Aug 23 11:19:59 PM UTC 24 Aug 23 11:20:07 PM UTC 24 174996841 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.416006652 Aug 23 11:19:40 PM UTC 24 Aug 23 11:20:07 PM UTC 24 560865936 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1837636872 Aug 23 11:19:50 PM UTC 24 Aug 23 11:20:08 PM UTC 24 1503965207 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.369311269 Aug 23 11:18:11 PM UTC 24 Aug 23 11:20:18 PM UTC 24 8367293508 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.240552532 Aug 23 11:18:08 PM UTC 24 Aug 23 11:20:18 PM UTC 24 3554036219 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1849401189 Aug 23 11:20:00 PM UTC 24 Aug 23 11:20:19 PM UTC 24 299395515 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.2715187557 Aug 23 11:20:08 PM UTC 24 Aug 23 11:20:20 PM UTC 24 269870397 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3887921624 Aug 23 11:17:49 PM UTC 24 Aug 23 11:20:26 PM UTC 24 2797966420 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1762383669 Aug 23 11:20:09 PM UTC 24 Aug 23 11:20:27 PM UTC 24 346044203 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1043095782 Aug 23 11:20:19 PM UTC 24 Aug 23 11:20:29 PM UTC 24 250540914 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1593571858 Aug 23 11:18:21 PM UTC 24 Aug 23 11:20:29 PM UTC 24 3750206205 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3909456421 Aug 23 11:20:20 PM UTC 24 Aug 23 11:20:30 PM UTC 24 358147471 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.148198208 Aug 23 11:20:19 PM UTC 24 Aug 23 11:20:37 PM UTC 24 1460509377 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1880889035 Aug 23 11:20:30 PM UTC 24 Aug 23 11:20:40 PM UTC 24 1029943734 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1837331608 Aug 23 11:20:28 PM UTC 24 Aug 23 11:20:47 PM UTC 24 2200143521 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2803336388 Aug 23 11:18:37 PM UTC 24 Aug 23 11:20:47 PM UTC 24 15219647274 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.139363666 Aug 23 11:20:38 PM UTC 24 Aug 23 11:20:53 PM UTC 24 1034287282 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.1608906874 Aug 23 11:20:31 PM UTC 24 Aug 23 11:20:57 PM UTC 24 546683843 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2117652476 Aug 23 11:22:32 PM UTC 24 Aug 23 11:22:56 PM UTC 24 1699608195 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3948728977 Aug 23 11:19:26 PM UTC 24 Aug 23 11:21:00 PM UTC 24 2784824843 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3575040431 Aug 23 11:18:47 PM UTC 24 Aug 23 11:21:02 PM UTC 24 3113500170 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.881701363 Aug 23 11:20:54 PM UTC 24 Aug 23 11:21:03 PM UTC 24 689333797 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.492915022 Aug 23 11:20:47 PM UTC 24 Aug 23 11:21:06 PM UTC 24 1376021002 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2325715053 Aug 23 11:19:51 PM UTC 24 Aug 23 11:21:10 PM UTC 24 7288452932 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2087825565 Aug 23 11:21:00 PM UTC 24 Aug 23 11:21:12 PM UTC 24 262142431 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2097689511 Aug 23 11:20:48 PM UTC 24 Aug 23 11:21:15 PM UTC 24 1787885309 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1367129085 Aug 23 11:17:49 PM UTC 24 Aug 23 11:21:17 PM UTC 24 374008640 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.812866725 Aug 23 11:21:11 PM UTC 24 Aug 23 11:21:20 PM UTC 24 4950984560 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2695836445 Aug 23 11:20:58 PM UTC 24 Aug 23 11:21:21 PM UTC 24 785454227 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.791597083 Aug 23 11:17:49 PM UTC 24 Aug 23 11:21:22 PM UTC 24 19582710679 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.4013174362 Aug 23 11:18:58 PM UTC 24 Aug 23 11:21:24 PM UTC 24 8479307471 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3303834166 Aug 23 11:21:04 PM UTC 24 Aug 23 11:21:25 PM UTC 24 7079216068 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2782650099 Aug 23 11:21:16 PM UTC 24 Aug 23 11:21:26 PM UTC 24 190581677 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.107146256 Aug 23 11:19:09 PM UTC 24 Aug 23 11:21:26 PM UTC 24 16470546392 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2946017259 Aug 23 11:17:49 PM UTC 24 Aug 23 11:21:28 PM UTC 24 873270092 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1701716808 Aug 23 11:20:19 PM UTC 24 Aug 23 11:21:28 PM UTC 24 24768359201 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3515707993 Aug 23 11:17:49 PM UTC 24 Aug 23 11:21:29 PM UTC 24 8801681891 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.873088116 Aug 23 11:18:00 PM UTC 24 Aug 23 11:22:56 PM UTC 24 4682815825 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.244299821 Aug 23 11:18:35 PM UTC 24 Aug 23 11:21:30 PM UTC 24 5686495750 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.956355991 Aug 23 11:19:39 PM UTC 24 Aug 23 11:21:30 PM UTC 24 15857660235 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.986662422 Aug 23 11:21:23 PM UTC 24 Aug 23 11:21:31 PM UTC 24 661832377 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1338001273 Aug 23 11:18:02 PM UTC 24 Aug 23 11:21:34 PM UTC 24 1436612244 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1520084759 Aug 23 11:19:22 PM UTC 24 Aug 23 11:21:36 PM UTC 24 2932687666 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2368069573 Aug 23 11:21:24 PM UTC 24 Aug 23 11:21:36 PM UTC 24 546874757 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3021692680 Aug 23 11:17:49 PM UTC 24 Aug 23 11:21:37 PM UTC 24 3490517754 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.622490996 Aug 23 11:21:28 PM UTC 24 Aug 23 11:21:38 PM UTC 24 1897314477 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3482430906 Aug 23 11:21:26 PM UTC 24 Aug 23 11:21:38 PM UTC 24 1084247497 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.126257906 Aug 23 11:21:21 PM UTC 24 Aug 23 11:21:39 PM UTC 24 1377984758 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2900219596 Aug 23 11:21:30 PM UTC 24 Aug 23 11:21:41 PM UTC 24 2936273485 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3626168236 Aug 23 11:21:13 PM UTC 24 Aug 23 11:21:45 PM UTC 24 8502932587 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.993109208 Aug 23 11:21:36 PM UTC 24 Aug 23 11:21:45 PM UTC 24 172742448 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1955941343 Aug 23 11:21:27 PM UTC 24 Aug 23 11:21:46 PM UTC 24 1664856281 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.848429031 Aug 23 11:21:38 PM UTC 24 Aug 23 11:21:48 PM UTC 24 186547066 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.291144340 Aug 23 11:21:42 PM UTC 24 Aug 23 11:21:50 PM UTC 24 1102203806 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2140982759 Aug 23 11:21:29 PM UTC 24 Aug 23 11:21:52 PM UTC 24 3747796189 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3535720563 Aug 23 11:21:32 PM UTC 24 Aug 23 11:21:54 PM UTC 24 496508783 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3415891315 Aug 23 11:21:46 PM UTC 24 Aug 23 11:21:56 PM UTC 24 759852198 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3891672976 Aug 23 11:21:39 PM UTC 24 Aug 23 11:22:00 PM UTC 24 3533501602 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.1531422411 Aug 23 11:21:53 PM UTC 24 Aug 23 11:22:01 PM UTC 24 1036281738 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.45096266 Aug 23 11:21:57 PM UTC 24 Aug 23 11:22:07 PM UTC 24 352560204 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2361646868 Aug 23 11:21:46 PM UTC 24 Aug 23 11:22:09 PM UTC 24 373256992 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2471315454 Aug 23 11:21:38 PM UTC 24 Aug 23 11:22:10 PM UTC 24 810880631 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3496709825 Aug 23 11:21:49 PM UTC 24 Aug 23 11:22:10 PM UTC 24 2056021933 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1170026707 Aug 23 11:22:09 PM UTC 24 Aug 23 11:22:19 PM UTC 24 1033006068 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3785892757 Aug 23 11:22:02 PM UTC 24 Aug 23 11:22:21 PM UTC 24 333818707 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2060135432 Aug 23 11:22:11 PM UTC 24 Aug 23 11:22:22 PM UTC 24 367422627 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1076374131 Aug 23 11:18:47 PM UTC 24 Aug 23 11:22:22 PM UTC 24 65025200899 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2800326928 Aug 23 11:21:55 PM UTC 24 Aug 23 11:22:30 PM UTC 24 563575664 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.524738859 Aug 23 11:18:51 PM UTC 24 Aug 23 11:22:31 PM UTC 24 7092786270 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.777002245 Aug 23 11:22:22 PM UTC 24 Aug 23 11:22:32 PM UTC 24 479178932 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2149413730 Aug 23 11:22:10 PM UTC 24 Aug 23 11:22:37 PM UTC 24 778361269 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2997344140 Aug 23 11:19:44 PM UTC 24 Aug 23 11:22:40 PM UTC 24 15655315867 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.1217270338 Aug 23 11:22:33 PM UTC 24 Aug 23 11:22:43 PM UTC 24 698737934 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2273747558 Aug 23 11:22:22 PM UTC 24 Aug 23 11:22:44 PM UTC 24 2753440842 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1070140337 Aug 23 11:18:12 PM UTC 24 Aug 23 11:22:51 PM UTC 24 11535262597 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3254582419 Aug 23 11:22:44 PM UTC 24 Aug 23 11:22:52 PM UTC 24 660685756 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2779292465 Aug 23 11:19:38 PM UTC 24 Aug 23 11:22:56 PM UTC 24 3116049822 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3996420415 Aug 23 11:22:38 PM UTC 24 Aug 23 11:22:57 PM UTC 24 1504539914 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1017039755 Aug 23 11:21:51 PM UTC 24 Aug 23 11:23:04 PM UTC 24 3392729140 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4152313501 Aug 23 11:21:27 PM UTC 24 Aug 23 11:23:06 PM UTC 24 6267631816 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3628417828 Aug 23 11:22:57 PM UTC 24 Aug 23 11:23:07 PM UTC 24 325087891 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.251351383 Aug 23 11:21:07 PM UTC 24 Aug 23 11:23:07 PM UTC 24 4883340864 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2146633781 Aug 23 11:22:52 PM UTC 24 Aug 23 11:23:08 PM UTC 24 3953855909 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2132114335 Aug 23 11:18:17 PM UTC 24 Aug 23 11:23:09 PM UTC 24 17973251152 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2099815762 Aug 23 11:19:04 PM UTC 24 Aug 23 11:23:14 PM UTC 24 4173693864 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3871921803 Aug 23 11:23:04 PM UTC 24 Aug 23 11:23:15 PM UTC 24 366257159 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3601246393 Aug 23 11:22:45 PM UTC 24 Aug 23 11:23:17 PM UTC 24 7054549668 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.794192506 Aug 23 11:22:56 PM UTC 24 Aug 23 11:23:17 PM UTC 24 2145501292 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1216461837 Aug 23 11:23:08 PM UTC 24 Aug 23 11:23:18 PM UTC 24 514087989 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.343280736 Aug 23 11:22:57 PM UTC 24 Aug 23 11:23:20 PM UTC 24 747138044 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.415725735 Aug 23 11:23:10 PM UTC 24 Aug 23 11:23:24 PM UTC 24 776196363 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1840668314 Aug 23 11:23:07 PM UTC 24 Aug 23 11:23:26 PM UTC 24 1744686583 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.4277329768 Aug 23 11:23:15 PM UTC 24 Aug 23 11:23:27 PM UTC 24 676996491 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.4082917130 Aug 23 11:23:19 PM UTC 24 Aug 23 11:23:28 PM UTC 24 516341678 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1421480672 Aug 23 11:21:34 PM UTC 24 Aug 23 11:23:30 PM UTC 24 8632973393 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3131879617 Aug 23 11:21:18 PM UTC 24 Aug 23 11:23:31 PM UTC 24 1878430602 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2959217413 Aug 23 11:20:29 PM UTC 24 Aug 23 11:23:31 PM UTC 24 3817373241 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2864874740 Aug 23 11:21:30 PM UTC 24 Aug 23 11:23:32 PM UTC 24 4043891707 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1699965883 Aug 23 11:23:21 PM UTC 24 Aug 23 11:23:35 PM UTC 24 826031834 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3655167992 Aug 23 11:23:17 PM UTC 24 Aug 23 11:23:36 PM UTC 24 346156706 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.543823259 Aug 23 11:23:25 PM UTC 24 Aug 23 11:23:36 PM UTC 24 565741920 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2339672191 Aug 23 11:21:28 PM UTC 24 Aug 23 11:23:38 PM UTC 24 3560025557 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1419774822 Aug 23 11:23:31 PM UTC 24 Aug 23 11:23:39 PM UTC 24 826011879 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.1085272585 Aug 23 11:23:32 PM UTC 24 Aug 23 11:23:42 PM UTC 24 683289686 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.299201290 Aug 23 11:23:37 PM UTC 24 Aug 23 11:23:47 PM UTC 24 993572885 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2853178004 Aug 23 11:20:08 PM UTC 24 Aug 23 11:23:47 PM UTC 24 4849364865 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3938206325 Aug 23 11:23:28 PM UTC 24 Aug 23 11:23:49 PM UTC 24 2060931043 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1018401330 Aug 23 11:23:40 PM UTC 24 Aug 23 11:23:52 PM UTC 24 754081550 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.423601910 Aug 23 11:23:36 PM UTC 24 Aug 23 11:23:54 PM UTC 24 3014193329 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.846608868 Aug 23 11:18:28 PM UTC 24 Aug 23 11:23:57 PM UTC 24 66392075329 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2484137869 Aug 23 11:23:49 PM UTC 24 Aug 23 11:23:59 PM UTC 24 884927091 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.4007890467 Aug 23 11:23:32 PM UTC 24 Aug 23 11:24:01 PM UTC 24 388713985 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2479240189 Aug 23 11:22:22 PM UTC 24 Aug 23 11:24:03 PM UTC 24 2911262430 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2882622363 Aug 23 11:23:55 PM UTC 24 Aug 23 11:24:07 PM UTC 24 546663036 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2849200296 Aug 23 11:23:47 PM UTC 24 Aug 23 11:24:08 PM UTC 24 1030806570 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1908339652 Aug 23 11:22:56 PM UTC 24 Aug 23 11:24:11 PM UTC 24 2135245873 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1193314781 Aug 23 11:24:04 PM UTC 24 Aug 23 11:24:13 PM UTC 24 250945711 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1444557341 Aug 23 11:22:34 PM UTC 24 Aug 23 11:24:15 PM UTC 24 1779787142 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.28920394 Aug 23 11:21:03 PM UTC 24 Aug 23 11:24:15 PM UTC 24 8208606656 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.3231336537 Aug 23 11:23:52 PM UTC 24 Aug 23 11:24:15 PM UTC 24 1542988854 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1146228529 Aug 23 11:21:47 PM UTC 24 Aug 23 11:24:20 PM UTC 24 3163862708 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.4053513437 Aug 23 11:23:59 PM UTC 24 Aug 23 11:24:20 PM UTC 24 1975235828 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3029117345 Aug 23 11:24:09 PM UTC 24 Aug 23 11:24:21 PM UTC 24 548489733 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3604403682 Aug 23 11:24:16 PM UTC 24 Aug 23 11:24:25 PM UTC 24 2255405857 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1916162799 Aug 23 11:21:22 PM UTC 24 Aug 23 11:24:26 PM UTC 24 5482685492 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2478042673 Aug 23 11:21:40 PM UTC 24 Aug 23 11:24:27 PM UTC 24 11963292077 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2240915793 Aug 23 11:23:39 PM UTC 24 Aug 23 11:24:28 PM UTC 24 2126081347 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.430156268 Aug 23 11:24:20 PM UTC 24 Aug 23 11:24:32 PM UTC 24 272441138 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1099157782 Aug 23 11:24:08 PM UTC 24 Aug 23 11:24:33 PM UTC 24 733576336 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1931083529 Aug 23 11:24:27 PM UTC 24 Aug 23 11:24:35 PM UTC 24 751218657 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.181933922 Aug 23 11:24:28 PM UTC 24 Aug 23 11:24:39 PM UTC 24 190973530 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2105385039 Aug 23 11:24:02 PM UTC 24 Aug 23 11:24:40 PM UTC 24 2142744839 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1364765920 Aug 23 11:24:22 PM UTC 24 Aug 23 11:24:41 PM UTC 24 677529464 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1866039805 Aug 23 11:24:14 PM UTC 24 Aug 23 11:24:44 PM UTC 24 24517517794 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.936872537 Aug 23 11:24:39 PM UTC 24 Aug 23 11:24:48 PM UTC 24 167337484 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.989385072 Aug 23 11:23:29 PM UTC 24 Aug 23 11:24:48 PM UTC 24 6506190574 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2298693210 Aug 23 11:24:28 PM UTC 24 Aug 23 11:24:50 PM UTC 24 285538429 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2404178745 Aug 23 11:24:16 PM UTC 24 Aug 23 11:24:50 PM UTC 24 528534411 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.267766139 Aug 23 11:23:06 PM UTC 24 Aug 23 11:24:51 PM UTC 24 1555500637 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.4020595711 Aug 23 11:24:34 PM UTC 24 Aug 23 11:24:53 PM UTC 24 333943548 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2238382784 Aug 23 11:24:41 PM UTC 24 Aug 23 11:24:53 PM UTC 24 1069589582 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1356403122 Aug 23 11:24:50 PM UTC 24 Aug 23 11:24:59 PM UTC 24 167563968 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3658402333 Aug 23 11:24:52 PM UTC 24 Aug 23 11:25:02 PM UTC 24 175337101 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2332265734 Aug 23 11:24:40 PM UTC 24 Aug 23 11:25:07 PM UTC 24 383766509 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3989408953 Aug 23 11:24:48 PM UTC 24 Aug 23 11:25:10 PM UTC 24 1979701204 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.1686604677 Aug 23 11:25:03 PM UTC 24 Aug 23 11:25:11 PM UTC 24 688219851 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.777101248 Aug 23 11:20:27 PM UTC 24 Aug 23 11:25:12 PM UTC 24 12257779138 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.826572159 Aug 23 11:24:54 PM UTC 24 Aug 23 11:25:12 PM UTC 24 1377085088 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3249165594 Aug 23 11:24:26 PM UTC 24 Aug 23 11:25:16 PM UTC 24 5677193544 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.1981721383 Aug 23 11:24:51 PM UTC 24 Aug 23 11:25:19 PM UTC 24 2188069489 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2301137043 Aug 23 11:25:11 PM UTC 24 Aug 23 11:25:23 PM UTC 24 2534462437 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3564543018 Aug 23 11:22:41 PM UTC 24 Aug 23 11:25:23 PM UTC 24 18144410926 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1721032053 Aug 23 11:21:39 PM UTC 24 Aug 23 11:25:23 PM UTC 24 15300914636 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1730501916 Aug 23 11:25:16 PM UTC 24 Aug 23 11:25:24 PM UTC 24 691039601 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.254905125 Aug 23 11:20:40 PM UTC 24 Aug 23 11:25:25 PM UTC 24 20411661450 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3130583334 Aug 23 11:25:08 PM UTC 24 Aug 23 11:25:28 PM UTC 24 1802012840 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2881063394 Aug 23 11:25:13 PM UTC 24 Aug 23 11:25:31 PM UTC 24 1326761782 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1720373899 Aug 23 11:25:23 PM UTC 24 Aug 23 11:25:34 PM UTC 24 177480600 ps
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