Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

295803

1

T2

4

T3

3

T6

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	101867	1			T2	43		T3	102		T6	232
values[0x0]	111358	1			T11	315		T16	22		T17	1583
values[0x1]	114684	1			T11	328		T16	30		T17	1653

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

312825

1

T2

24

T3

62

T6

134

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1618	1			T3	1		T11	6		T14	3
valid_sources[0x01]	1013	1			T11	2		T119	2		T120	1
valid_sources[0x02]	1747	1			T3	1		T11	1		T12	1
valid_sources[0x03]	958	1			T11	1		T118	2		T142	4
valid_sources[0x04]	1602	1			T11	2		T13	1		T119	1
valid_sources[0x05]	989	1			T2	1		T11	3		T122	1
valid_sources[0x06]	1085	1			T3	2		T11	2		T12	6
valid_sources[0x07]	1195	1			T11	5		T13	1		T118	3
valid_sources[0x08]	1251	1			T2	1		T8	3		T122	2
valid_sources[0x09]	2227	1			T3	1		T11	6		T13	1
valid_sources[0x0a]	1066	1			T11	2		T143	1		T142	4
valid_sources[0x0b]	960	1			T3	2		T122	1		T118	1
valid_sources[0x0c]	973	1			T3	1		T11	8		T13	1
valid_sources[0x0d]	1561	1			T11	4		T122	1		T118	3
valid_sources[0x0e]	1117	1			T3	1		T11	1		T122	1
valid_sources[0x0f]	1214	1			T6	36		T122	3		T118	3
valid_sources[0x10]	1091	1			T13	2		T122	1		T118	4
valid_sources[0x11]	1097	1			T118	6		T142	1		T144	1
valid_sources[0x12]	1046	1			T62	1		T19	1		T145	1
valid_sources[0x13]	1100	1			T62	2		T118	2		T120	3
valid_sources[0x14]	1099	1			T11	4		T13	1		T122	1
valid_sources[0x15]	1365	1			T11	10		T14	10		T122	1
valid_sources[0x16]	1317	1			T11	1		T143	2		T120	1
valid_sources[0x17]	1086	1			T118	3		T120	1		T142	1
valid_sources[0x18]	1341	1			T13	2		T143	1		T120	1
valid_sources[0x19]	1437	1			T11	17		T122	1		T118	4
valid_sources[0x1a]	1274	1			T11	3		T122	1		T19	1
valid_sources[0x1b]	1095	1			T2	2		T3	2		T7	11
valid_sources[0x1c]	978	1			T3	1		T10	2		T11	1
valid_sources[0x1d]	988	1			T11	1		T13	1		T118	1
valid_sources[0x1e]	996	1			T3	1		T117	39		T142	2
valid_sources[0x1f]	1720	1			T2	2		T118	1		T119	1
valid_sources[0x20]	1066	1			T3	1		T118	7		T19	1
valid_sources[0x21]	1025	1			T11	2		T118	2		T120	9
valid_sources[0x22]	1314	1			T7	7		T11	11		T119	5
valid_sources[0x23]	1240	1			T13	1		T15	1		T122	1
valid_sources[0x24]	1653	1			T2	2		T11	6		T12	2
valid_sources[0x25]	1162	1			T3	1		T7	8		T11	2
valid_sources[0x26]	1371	1			T7	5		T122	2		T143	1
valid_sources[0x27]	1099	1			T2	1		T12	14		T122	1
valid_sources[0x28]	1503	1			T3	2		T11	1		T122	2
valid_sources[0x29]	2180	1			T11	3		T118	2		T119	2
valid_sources[0x2a]	1193	1			T11	3		T118	1		T145	2
valid_sources[0x2b]	899	1			T13	1		T122	1		T118	2
valid_sources[0x2c]	1254	1			T3	1		T118	3		T142	3
valid_sources[0x2d]	1105	1			T3	1		T11	2		T12	6
valid_sources[0x2e]	997	1			T19	1		T142	2		T144	3
valid_sources[0x2f]	1095	1			T11	2		T122	1		T19	1
valid_sources[0x30]	1351	1			T10	5		T122	1		T118	5
valid_sources[0x31]	1140	1			T10	10		T11	1		T143	2
valid_sources[0x32]	1153	1			T11	3		T118	3		T19	1
valid_sources[0x33]	1816	1			T11	1		T122	1		T119	5
valid_sources[0x34]	1636	1			T6	23		T11	9		T13	1
valid_sources[0x35]	971	1			T15	1		T118	3		T120	2
valid_sources[0x36]	1193	1			T11	4		T19	2		T143	2
valid_sources[0x37]	999	1			T2	4		T3	1		T122	1
valid_sources[0x38]	1460	1			T14	21		T143	1		T120	1
valid_sources[0x39]	1003	1			T11	15		T118	1		T143	2
valid_sources[0x3a]	1839	1			T11	1		T122	2		T118	1
valid_sources[0x3b]	953	1			T8	1		T11	1		T118	1
valid_sources[0x3c]	2190	1			T11	8		T118	5		T120	7
valid_sources[0x3d]	1213	1			T3	2		T8	1		T11	3
valid_sources[0x3e]	2124	1			T12	3		T118	8		T120	1
valid_sources[0x3f]	1213	1			T3	1		T122	1		T118	1
valid_sources[0x40]	1541	1			T8	1		T118	1		T119	2
valid_sources[0x41]	1195	1			T143	2		T119	1		T120	1
valid_sources[0x42]	1506	1			T11	5		T122	2		T19	1
valid_sources[0x43]	962	1			T2	1		T11	8		T122	1
valid_sources[0x44]	1940	1			T11	3		T118	10		T142	2
valid_sources[0x45]	937	1			T11	2		T120	7		T142	2
valid_sources[0x46]	1008	1			T11	6		T118	1		T143	2
valid_sources[0x47]	880	1			T3	2		T118	3		T142	1
valid_sources[0x48]	2889	1			T11	11		T120	1		T142	1
valid_sources[0x49]	1373	1			T11	3		T120	1		T142	1
valid_sources[0x4a]	1175	1			T8	2		T11	9		T122	1
valid_sources[0x4b]	988	1			T11	1		T118	2		T120	2
valid_sources[0x4c]	2282	1			T11	2		T122	2		T118	2
valid_sources[0x4d]	1099	1			T122	2		T118	1		T119	2
valid_sources[0x4e]	965	1			T11	2		T118	2		T143	1
valid_sources[0x4f]	1063	1			T122	1		T143	1		T142	1
valid_sources[0x50]	1270	1			T118	1		T143	2		T120	2
valid_sources[0x51]	1302	1			T3	1		T11	3		T118	1
valid_sources[0x52]	1127	1			T3	1		T11	3		T19	1
valid_sources[0x53]	1664	1			T118	1		T143	4		T120	3
valid_sources[0x54]	1622	1			T3	3		T11	4		T62	2
valid_sources[0x55]	1098	1			T3	1		T117	86		T118	1
valid_sources[0x56]	1231	1			T6	32		T122	1		T119	2
valid_sources[0x57]	1120	1			T2	1		T3	1		T119	1
valid_sources[0x58]	1194	1			T2	2		T13	2		T122	1
valid_sources[0x59]	1218	1			T11	1		T122	1		T118	1
valid_sources[0x5a]	1258	1			T11	1		T62	3		T142	1
valid_sources[0x5b]	1625	1			T8	1		T11	2		T15	1
valid_sources[0x5c]	1089	1			T3	2		T11	15		T19	1
valid_sources[0x5d]	1555	1			T2	2		T11	4		T118	1
valid_sources[0x5e]	979	1			T3	3		T7	15		T11	7
valid_sources[0x5f]	1130	1			T11	1		T13	1		T19	1
valid_sources[0x60]	1815	1			T122	1		T118	2		T119	1
valid_sources[0x61]	1565	1			T3	1		T11	1		T122	1
valid_sources[0x62]	951	1			T8	1		T11	8		T15	1
valid_sources[0x63]	1406	1			T3	1		T8	2		T11	3
valid_sources[0x64]	1689	1			T122	1		T120	4		T142	2
valid_sources[0x65]	1027	1			T11	1		T118	3		T120	3
valid_sources[0x66]	1175	1			T3	1		T11	10		T13	1
valid_sources[0x67]	1110	1			T11	4		T122	1		T62	4
valid_sources[0x68]	1352	1			T117	19		T143	1		T120	1
valid_sources[0x69]	2178	1			T62	1		T143	4		T119	1
valid_sources[0x6a]	1901	1			T3	1		T7	8		T11	1
valid_sources[0x6b]	938	1			T3	1		T11	13		T62	4
valid_sources[0x6c]	958	1			T3	9		T118	2		T120	1
valid_sources[0x6d]	1333	1			T10	9		T11	2		T19	2
valid_sources[0x6e]	960	1			T2	4		T11	3		T119	5
valid_sources[0x6f]	1449	1			T3	2		T11	13		T12	5
valid_sources[0x70]	1289	1			T3	2		T119	4		T120	2
valid_sources[0x71]	1074	1			T14	5		T122	1		T118	5
valid_sources[0x72]	1158	1			T7	18		T142	3		T144	3
valid_sources[0x73]	1637	1			T2	4		T119	1		T120	1
valid_sources[0x74]	1031	1			T10	1		T11	13		T118	2
valid_sources[0x75]	1444	1			T3	1		T122	1		T118	1
valid_sources[0x76]	1172	1			T6	33		T11	2		T122	1
valid_sources[0x77]	2566	1			T3	1		T14	12		T145	1
valid_sources[0x78]	1201	1			T11	2		T15	1		T122	1
valid_sources[0x79]	1406	1			T3	2		T10	4		T11	17
valid_sources[0x7a]	1342	1			T11	3		T122	1		T143	1
valid_sources[0x7b]	1264	1			T11	1		T13	1		T119	1
valid_sources[0x7c]	1208	1			T118	3		T120	1		T142	1
valid_sources[0x7d]	960	1			T11	2		T118	1		T119	1
valid_sources[0x7e]	1896	1			T11	1		T120	2		T142	2
valid_sources[0x7f]	1031	1			T3	1		T10	1		T143	1
valid_sources[0x80]	1710	1			T3	1		T11	6		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75670

1

T2

4

T3

3

T6

21

values[0x0]

all_enables

biggest_size

110400

1

T11

314

T16

21

T17

1569

values[0x1]

all_enables

biggest_size

109733

1

T11

320

T16

30

T17

1592

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30823	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

266929

1

T1

1

T2

7

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80286	1			T2	16		T4	1		T8	16
values[0x0]	101691	1			T1	4		T5	4		T11	740
values[0x1]	115775	1			T1	3		T5	2		T11	838

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

281413

1

T1

3

T2

9

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	878	1			T11	6		T34	4		T91	1
valid_sources[0x01]	899	1			T146	2		T90	1		T16	7
valid_sources[0x02]	1330	1			T11	2		T147	1		T91	1
valid_sources[0x03]	1670	1			T11	15		T77	3		T91	1
valid_sources[0x04]	960	1			T11	10		T148	11		T91	2
valid_sources[0x05]	921	1			T11	1		T16	2		T149	1
valid_sources[0x06]	1161	1			T91	1		T17	33		T22	8
valid_sources[0x07]	1052	1			T11	14		T16	6		T149	1
valid_sources[0x08]	1010	1			T11	2		T60	1		T150	1
valid_sources[0x09]	887	1			T11	4		T16	1		T151	1
valid_sources[0x0a]	987	1			T11	2		T152	1		T16	1
valid_sources[0x0b]	1552	1			T10	1		T11	17		T60	1
valid_sources[0x0c]	1381	1			T153	2		T16	2		T154	1
valid_sources[0x0d]	1147	1			T155	1		T91	1		T154	2
valid_sources[0x0e]	1047	1			T156	3		T16	1		T17	17
valid_sources[0x0f]	1123	1			T11	1		T91	1		T16	3
valid_sources[0x10]	909	1			T11	22		T155	1		T91	1
valid_sources[0x11]	1124	1			T10	1		T34	1		T157	1
valid_sources[0x12]	1127	1			T13	2		T158	2		T16	1
valid_sources[0x13]	955	1			T152	1		T16	31		T17	21
valid_sources[0x14]	1125	1			T11	1		T16	1		T159	1
valid_sources[0x15]	947	1			T2	1		T34	1		T16	9
valid_sources[0x16]	1051	1			T160	8		T159	1		T17	42
valid_sources[0x17]	848	1			T10	1		T11	4		T17	31
valid_sources[0x18]	1183	1			T11	21		T57	1		T91	1
valid_sources[0x19]	1135	1			T11	20		T19	8		T150	2
valid_sources[0x1a]	1282	1			T34	1		T17	7		T21	1
valid_sources[0x1b]	1089	1			T11	9		T16	15		T161	1
valid_sources[0x1c]	1379	1			T8	2		T10	2		T11	25
valid_sources[0x1d]	1354	1			T11	25		T13	7		T162	2
valid_sources[0x1e]	1216	1			T16	5		T17	10		T21	110
valid_sources[0x1f]	1082	1			T16	2		T17	5		T21	4
valid_sources[0x20]	1164	1			T11	17		T34	2		T91	1
valid_sources[0x21]	1150	1			T11	4		T77	1		T147	1
valid_sources[0x22]	833	1			T8	1		T11	16		T158	2
valid_sources[0x23]	1502	1			T11	3		T16	15		T151	2
valid_sources[0x24]	1155	1			T16	4		T163	2		T17	9
valid_sources[0x25]	1191	1			T11	7		T16	4		T17	5
valid_sources[0x26]	1451	1			T11	6		T164	6		T16	1
valid_sources[0x27]	1437	1			T90	1		T71	2		T161	1
valid_sources[0x28]	857	1			T11	1		T90	1		T16	8
valid_sources[0x29]	1092	1			T11	25		T91	1		T16	2
valid_sources[0x2a]	867	1			T152	1		T16	2		T17	11
valid_sources[0x2b]	1082	1			T11	12		T91	1		T17	21
valid_sources[0x2c]	1115	1			T11	18		T88	16		T16	5
valid_sources[0x2d]	1050	1			T16	1		T149	1		T159	1
valid_sources[0x2e]	1207	1			T11	4		T16	10		T149	1
valid_sources[0x2f]	1443	1			T11	5		T145	1		T91	1
valid_sources[0x30]	1007	1			T11	2		T16	5		T151	1
valid_sources[0x31]	858	1			T145	1		T16	2		T159	1
valid_sources[0x32]	1429	1			T11	10		T158	1		T91	1
valid_sources[0x33]	939	1			T150	1		T160	9		T165	18
valid_sources[0x34]	947	1			T2	1		T11	17		T66	1
valid_sources[0x35]	1146	1			T11	1		T166	3		T159	1
valid_sources[0x36]	997	1			T11	8		T167	16		T151	1
valid_sources[0x37]	1379	1			T11	2		T17	14		T22	5
valid_sources[0x38]	1351	1			T11	6		T36	1		T91	1
valid_sources[0x39]	1050	1			T8	1		T11	4		T12	32
valid_sources[0x3a]	958	1			T2	1		T11	1		T89	16
valid_sources[0x3b]	1546	1			T11	29		T91	1		T16	19
valid_sources[0x3c]	1043	1			T11	1		T16	2		T17	5
valid_sources[0x3d]	1241	1			T18	10		T16	3		T162	2
valid_sources[0x3e]	1037	1			T11	8		T152	1		T146	1
valid_sources[0x3f]	1578	1			T11	1		T90	1		T16	2
valid_sources[0x40]	1528	1			T11	27		T90	1		T159	2
valid_sources[0x41]	1042	1			T11	19		T158	2		T91	3
valid_sources[0x42]	936	1			T145	1		T17	60		T21	2
valid_sources[0x43]	1449	1			T11	10		T16	6		T159	2
valid_sources[0x44]	933	1			T16	4		T17	6		T42	117
valid_sources[0x45]	1650	1			T11	14		T150	8		T16	1
valid_sources[0x46]	1303	1			T11	22		T159	1		T17	23
valid_sources[0x47]	924	1			T16	5		T17	2		T22	5
valid_sources[0x48]	1386	1			T10	1		T11	1		T150	1
valid_sources[0x49]	1084	1			T11	1		T150	13		T91	1
valid_sources[0x4a]	1249	1			T34	2		T91	1		T16	8
valid_sources[0x4b]	1185	1			T11	16		T33	1		T60	1
valid_sources[0x4c]	1349	1			T8	2		T11	20		T16	1
valid_sources[0x4d]	1312	1			T11	1		T34	5		T168	1
valid_sources[0x4e]	885	1			T33	1		T91	1		T16	5
valid_sources[0x4f]	1151	1			T16	3		T162	4		T17	33
valid_sources[0x50]	1300	1			T11	2		T91	1		T16	1
valid_sources[0x51]	1103	1			T10	2		T11	1		T16	2
valid_sources[0x52]	1292	1			T10	1		T11	2		T16	5
valid_sources[0x53]	1162	1			T11	28		T159	1		T17	19
valid_sources[0x54]	1224	1			T2	1		T11	12		T17	26
valid_sources[0x55]	871	1			T2	1		T10	1		T11	7
valid_sources[0x56]	1098	1			T11	16		T67	3		T169	1
valid_sources[0x57]	1432	1			T8	1		T10	1		T11	4
valid_sources[0x58]	1192	1			T11	3		T91	1		T170	1
valid_sources[0x59]	1181	1			T11	22		T16	6		T17	1
valid_sources[0x5a]	1169	1			T11	45		T77	3		T91	1
valid_sources[0x5b]	1332	1			T150	4		T16	2		T17	27
valid_sources[0x5c]	1514	1			T10	1		T11	26		T33	1
valid_sources[0x5d]	1152	1			T11	3		T16	2		T17	7
valid_sources[0x5e]	857	1			T11	4		T91	1		T149	1
valid_sources[0x5f]	1090	1			T11	1		T16	15		T159	2
valid_sources[0x60]	1460	1			T16	9		T161	1		T160	5
valid_sources[0x61]	935	1			T11	6		T16	1		T162	1
valid_sources[0x62]	977	1			T11	21		T34	1		T146	1
valid_sources[0x63]	1436	1			T11	9		T155	1		T162	1
valid_sources[0x64]	1323	1			T11	5		T145	1		T151	2
valid_sources[0x65]	994	1			T11	1		T16	3		T17	5
valid_sources[0x66]	987	1			T11	8		T37	1		T34	3
valid_sources[0x67]	1236	1			T11	3		T19	3		T169	1
valid_sources[0x68]	1313	1			T11	1		T171	2		T149	1
valid_sources[0x69]	1065	1			T11	31		T16	9		T17	15
valid_sources[0x6a]	1114	1			T11	6		T90	1		T16	4
valid_sources[0x6b]	893	1			T11	2		T90	1		T91	2
valid_sources[0x6c]	811	1			T11	3		T155	1		T16	1
valid_sources[0x6d]	1037	1			T91	1		T16	4		T71	2
valid_sources[0x6e]	1237	1			T11	8		T16	1		T17	3
valid_sources[0x6f]	975	1			T11	2		T90	1		T91	1
valid_sources[0x70]	1248	1			T11	21		T172	32		T16	7
valid_sources[0x71]	940	1			T11	5		T16	8		T173	4
valid_sources[0x72]	1199	1			T8	1		T10	2		T11	15
valid_sources[0x73]	986	1			T145	1		T16	2		T149	1
valid_sources[0x74]	1135	1			T11	1		T56	1		T154	1
valid_sources[0x75]	1210	1			T4	1		T11	2		T146	1
valid_sources[0x76]	1035	1			T2	1		T11	2		T16	11
valid_sources[0x77]	1279	1			T11	2		T91	1		T16	2
valid_sources[0x78]	1291	1			T16	3		T174	1		T160	1
valid_sources[0x79]	1199	1			T8	1		T10	1		T11	4
valid_sources[0x7a]	1083	1			T60	1		T17	5		T22	4
valid_sources[0x7b]	1258	1			T11	4		T76	2		T91	1
valid_sources[0x7c]	924	1			T2	1		T8	1		T11	21
valid_sources[0x7d]	991	1			T11	2		T91	1		T17	3
valid_sources[0x7e]	1145	1			T11	7		T91	1		T22	6
valid_sources[0x7f]	974	1			T16	9		T161	1		T159	1
valid_sources[0x80]	1021	1			T11	2		T13	2		T91	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68961

1

T2

7

T4

1

T8

8

values[0x0]

all_enables

biggest_size

99163

1

T1

1

T5

2

T11

717

values[0x1]

all_enables

biggest_size

98805

1

T11

733

T18

2

T75

1