| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.53 | 96.89 | 92.56 | 97.68 | 100.00 | 98.62 | 97.90 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 64.28 | 64.28 | 92.58 | 92.58 | 68.54 | 68.54 | 52.97 | 52.97 | 40.00 | 40.00 | 89.31 | 89.31 | 93.70 | 93.70 | 12.88 | 12.88 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2252085061 |
| 79.88 | 15.59 | 96.29 | 3.71 | 85.96 | 17.42 | 63.79 | 10.82 | 53.33 | 13.33 | 94.48 | 5.17 | 95.50 | 1.80 | 69.79 | 56.91 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1596608295 |
| 84.29 | 4.42 | 96.41 | 0.12 | 88.34 | 2.39 | 63.99 | 0.20 | 80.00 | 26.67 | 95.17 | 0.69 | 95.65 | 0.15 | 70.49 | 0.70 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1725570084 |
| 87.17 | 2.88 | 96.65 | 0.24 | 89.04 | 0.70 | 73.56 | 9.57 | 86.67 | 6.67 | 96.90 | 1.72 | 95.95 | 0.30 | 71.43 | 0.94 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3812009838 |
| 89.29 | 2.12 | 96.65 | 0.00 | 89.33 | 0.28 | 78.99 | 5.42 | 86.67 | 0.00 | 96.90 | 0.00 | 95.95 | 0.00 | 80.56 | 9.13 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3529371916 |
| 91.12 | 1.83 | 96.65 | 0.00 | 89.47 | 0.14 | 84.66 | 5.67 | 93.33 | 6.67 | 97.24 | 0.34 | 95.95 | 0.00 | 80.56 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1740324336 |
| 92.26 | 1.14 | 96.65 | 0.00 | 89.47 | 0.00 | 88.18 | 3.52 | 93.33 | 0.00 | 97.24 | 0.00 | 95.95 | 0.00 | 85.01 | 4.45 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.4208640256 |
| 93.31 | 1.05 | 96.89 | 0.24 | 90.17 | 0.70 | 88.18 | 0.00 | 93.33 | 0.00 | 98.28 | 1.03 | 95.95 | 0.00 | 90.40 | 5.39 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3618547074 |
| 94.34 | 1.03 | 96.89 | 0.00 | 90.45 | 0.28 | 88.18 | 0.00 | 100.00 | 6.67 | 98.28 | 0.00 | 95.95 | 0.00 | 90.63 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1254883384 |
| 95.13 | 0.79 | 96.89 | 0.00 | 90.45 | 0.00 | 93.30 | 5.12 | 100.00 | 0.00 | 98.28 | 0.00 | 96.10 | 0.15 | 90.87 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1113554872 |
| 95.63 | 0.50 | 96.89 | 0.00 | 90.45 | 0.00 | 93.30 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 96.10 | 0.00 | 94.38 | 3.51 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.299916832 |
| 95.99 | 0.36 | 96.89 | 0.00 | 90.45 | 0.00 | 95.35 | 2.05 | 100.00 | 0.00 | 98.28 | 0.00 | 96.10 | 0.00 | 94.85 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3925127116 |
| 96.24 | 0.25 | 96.89 | 0.00 | 91.01 | 0.56 | 95.55 | 0.20 | 100.00 | 0.00 | 98.28 | 0.00 | 96.40 | 0.30 | 95.55 | 0.70 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.924033991 |
| 96.39 | 0.15 | 96.89 | 0.00 | 91.01 | 0.00 | 95.55 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.00 | 0.60 | 96.02 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2021252610 |
| 96.53 | 0.14 | 96.89 | 0.00 | 91.01 | 0.00 | 96.30 | 0.75 | 100.00 | 0.00 | 98.28 | 0.00 | 97.00 | 0.00 | 96.25 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2388980194 |
| 96.67 | 0.13 | 96.89 | 0.00 | 91.01 | 0.00 | 96.30 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.00 | 0.00 | 97.19 | 0.94 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3986260582 |
| 96.80 | 0.13 | 96.89 | 0.00 | 91.57 | 0.56 | 96.65 | 0.35 | 100.00 | 0.00 | 98.28 | 0.00 | 97.00 | 0.00 | 97.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1514303689 |
| 96.91 | 0.11 | 96.89 | 0.00 | 91.99 | 0.42 | 96.65 | 0.00 | 100.00 | 0.00 | 98.62 | 0.34 | 97.00 | 0.00 | 97.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1792796857 |
| 97.01 | 0.10 | 96.89 | 0.00 | 91.99 | 0.00 | 96.65 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.00 | 0.00 | 97.89 | 0.70 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2343542438 |
| 97.10 | 0.09 | 96.89 | 0.00 | 91.99 | 0.00 | 96.83 | 0.17 | 100.00 | 0.00 | 98.62 | 0.00 | 97.00 | 0.00 | 98.36 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1866896037 |
| 97.18 | 0.09 | 96.89 | 0.00 | 91.99 | 0.00 | 96.83 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.60 | 0.60 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3616376498 |
| 97.25 | 0.07 | 96.89 | 0.00 | 91.99 | 0.00 | 96.83 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.60 | 0.00 | 98.83 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2562529545 |
| 97.31 | 0.06 | 96.89 | 0.00 | 91.99 | 0.00 | 97.23 | 0.40 | 100.00 | 0.00 | 98.62 | 0.00 | 97.60 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.607926127 |
| 97.35 | 0.04 | 96.89 | 0.00 | 92.13 | 0.14 | 97.23 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.75 | 0.15 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2412170953 |
| 97.39 | 0.04 | 96.89 | 0.00 | 92.42 | 0.28 | 97.23 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.75 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3636262383 |
| 97.42 | 0.03 | 96.89 | 0.00 | 92.42 | 0.00 | 97.23 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.75 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1728394181 |
| 97.46 | 0.03 | 96.89 | 0.00 | 92.42 | 0.00 | 97.45 | 0.22 | 100.00 | 0.00 | 98.62 | 0.00 | 97.75 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1519132072 |
| 97.48 | 0.02 | 96.89 | 0.00 | 92.42 | 0.00 | 97.45 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2211336916 |
| 97.50 | 0.02 | 96.89 | 0.00 | 92.56 | 0.14 | 97.45 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.923489750 |
| 97.52 | 0.02 | 96.89 | 0.00 | 92.56 | 0.00 | 97.58 | 0.12 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3751153809 |
| 97.53 | 0.01 | 96.89 | 0.00 | 92.56 | 0.00 | 97.68 | 0.10 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.4063047855 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1414441225 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3471915144 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3857348229 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1608077601 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2403235108 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2567204518 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2070994684 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2492905563 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4142363459 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4145346852 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4025846424 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1003312649 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2418620254 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3401200282 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2135987835 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.827337790 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.906450312 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2271098656 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.992376450 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1909681764 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1714274065 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4142586708 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.140200904 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3589150318 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3063896668 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1320570261 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4096560828 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1506324615 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3873527773 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2855140982 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3295049096 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1010450944 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1437414894 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1295979681 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4243248788 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.151201185 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.315679257 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4025222228 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.80784794 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4248020349 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.289727079 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1385255043 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3054842539 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2134390832 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3612824231 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3966378228 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.107595631 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3434826586 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1685840196 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.956977330 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1820174023 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2925122850 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.967609447 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3817627157 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.279655612 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1228146828 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2280762676 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3762644024 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.624406255 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2501939317 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2682394996 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2729758058 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.546090714 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2299284366 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1824328805 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4288431288 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1806005990 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1439505694 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1544329053 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.105011911 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4246391852 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1584157613 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.340104175 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3411225365 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.407849048 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.572927297 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.349163208 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4011719475 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1464221644 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1845596205 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3776686385 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3206097452 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.24751385 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1982734932 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4269716961 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1985126970 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3627382181 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.124331864 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3307484815 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.258541114 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1219614297 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.173070373 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.203766523 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1773190943 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2607742067 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.907990750 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3804012971 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3988096063 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.832597918 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1344762642 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2264210918 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4043458361 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1633268555 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.591873795 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1884917805 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1626254659 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2757086489 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.745198993 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.192599955 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3220402755 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.187984625 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1448107815 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1849932204 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.505596531 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.177331989 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.60311192 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3576683777 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4000306297 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3806130338 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3392392773 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.250547459 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1033884165 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3092352315 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2164462399 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4086691436 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.862080537 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4129739023 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4062764852 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2682676549 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2376822304 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.528112672 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1305725620 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2164862732 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1355199293 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.816342032 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3876061712 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1147685267 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4206235139 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1036285170 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.922824126 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3438078128 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3378714744 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.4207456957 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.67218398 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2414848241 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3462943311 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2674699832 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1825702712 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1539597942 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2215561360 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1270599156 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2739502217 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.4052279779 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2440243756 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2195693576 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2990488984 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.277707770 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3404414267 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3593008044 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.3072661533 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2243543877 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.88254309 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1317550437 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.644769450 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.927855589 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.510141037 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2792365950 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.306989644 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1316859163 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1330053180 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.862067756 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.4254479302 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.530975082 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.195788326 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.4240667048 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3375506104 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3547940448 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2748314332 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2145698572 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.842444281 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.593054772 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2293810939 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3062646432 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2625011930 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1965517864 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1754763303 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2353384635 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1964366524 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3622751853 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2049876988 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3476842033 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3028892804 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.340414308 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.441001212 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2483028540 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.288862629 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3428510675 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2434872460 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2104136512 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1671154868 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1604195732 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3085003606 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3530149359 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2684565048 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2488934802 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2935891354 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3806555691 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.414557628 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3918503841 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2891593676 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1437294363 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.3331914554 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2019351347 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.65673797 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3730269141 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.2620096892 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2331788308 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.40867460 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3653124904 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2139003952 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.580506170 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.643264951 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3703642155 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3267551770 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3452991473 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4097211990 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2404227097 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1400678853 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3833199448 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2248826656 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3387856566 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1931651328 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2318528161 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1659332349 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3705036761 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2866616172 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1413962596 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3432565282 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2710756473 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1966375160 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.4206147369 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.465274307 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4193065613 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.639650837 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2602271954 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2142565618 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.3485326098 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.675411086 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4200084502 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.1258462691 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2160100549 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.2019688354 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1483947633 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3558673381 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3394949891 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.496924106 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2229158831 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3290377889 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3329155046 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2267216123 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.545289892 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2962917510 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2914127679 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.840396349 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3754982279 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1815975070 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2702303330 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.213162010 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1744680057 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3816937673 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2077594481 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3533182242 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.745397833 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3227325686 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3894163149 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1361347867 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.4057844654 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2183186438 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2534698415 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2481013759 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1525790326 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3248523911 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2684569542 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2106367895 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.895737314 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.531057436 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3394635853 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.341632378 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.4195391038 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1460432178 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2839564613 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1195276523 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3731479814 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2820088635 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.4145680359 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.13700444 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2905548780 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3235923867 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.46710055 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3758864480 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2558013705 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.187743384 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2245612694 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3388597042 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3216718780 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1795396877 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1599299399 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1644165443 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2200017981 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1908814702 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2722601545 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2181167710 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.887648313 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2207719634 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3510221456 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.4021492320 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.894525494 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.4048482939 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.74836944 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.775195835 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1550582160 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3504593536 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1660160113 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.707044419 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1611947364 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3921647516 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3309173571 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.3203276406 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.365701249 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3307785617 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.88181060 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1492499052 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2936554355 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1581300529 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.2682676025 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3876897325 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2035683194 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.339410695 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2296250450 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.420869126 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3714109741 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3721063408 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.788458751 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2420995358 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1835608766 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2073084928 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3483516732 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3983922701 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.994784744 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1141279377 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3698299525 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3072279977 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2126492736 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3583570045 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.4152530679 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2992506473 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3616981950 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2051286873 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.308840856 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3677561710 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3011814372 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3334131555 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1069105971 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.4087489366 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1418386800 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1234709975 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.340583777 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.4057941170 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.140437043 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4173956603 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1987129601 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1977882112 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1174392381 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3944137625 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.911289406 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3946044886 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4209677654 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.2965909693 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1218359976 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.4106145770 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1684958716 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.4291299123 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3457773445 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.978167022 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3969359711 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3821478418 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2498559154 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3205101846 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1733561731 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.809209131 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.764227395 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.391202245 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2090011598 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2336625662 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3969426629 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.2182252903 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1976163452 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2495932393 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3492282643 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3805516653 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1916539441 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3229891388 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.670078753 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3741063699 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.87489026 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1571745998 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1009510586 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1990112774 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.2885255286 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3785686393 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3420826885 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2952146308 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1629949439 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4035449421 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2078063944 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1790048705 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3989873124 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2321866604 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1185974717 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2103821816 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3053882112 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3013673199 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2826619805 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4247845848 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.386488185 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4206235139 | Aug 25 04:10:18 AM UTC 24 | Aug 25 04:10:27 AM UTC 24 | 1646345715 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.922824126 | Aug 25 04:10:18 AM UTC 24 | Aug 25 04:10:30 AM UTC 24 | 698411678 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2211336916 | Aug 25 04:10:18 AM UTC 24 | Aug 25 04:10:31 AM UTC 24 | 1022203646 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.607926127 | Aug 25 04:10:18 AM UTC 24 | Aug 25 04:10:37 AM UTC 24 | 1502044644 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3438078128 | Aug 25 04:10:26 AM UTC 24 | Aug 25 04:10:38 AM UTC 24 | 688056165 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2434872460 | Aug 25 04:10:27 AM UTC 24 | Aug 25 04:10:39 AM UTC 24 | 376736950 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3378714744 | Aug 25 04:10:22 AM UTC 24 | Aug 25 04:10:39 AM UTC 24 | 310937639 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1671154868 | Aug 25 04:10:26 AM UTC 24 | Aug 25 04:10:40 AM UTC 24 | 179055498 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3812009838 | Aug 25 04:10:27 AM UTC 24 | Aug 25 04:10:47 AM UTC 24 | 346854435 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2252085061 | Aug 25 04:10:22 AM UTC 24 | Aug 25 04:10:48 AM UTC 24 | 550994194 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1596608295 | Aug 25 04:10:18 AM UTC 24 | Aug 25 04:10:58 AM UTC 24 | 5278482324 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1965517864 | Aug 25 04:11:33 AM UTC 24 | Aug 25 04:11:46 AM UTC 24 | 347264974 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1113554872 | Aug 25 04:10:18 AM UTC 24 | Aug 25 04:11:01 AM UTC 24 | 544574395 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2495932393 | Aug 25 04:10:47 AM UTC 24 | Aug 25 04:11:05 AM UTC 24 | 1334116057 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1916539441 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:08 AM UTC 24 | 169476619 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2336625662 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:09 AM UTC 24 | 260613481 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1976163452 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:10 AM UTC 24 | 705668764 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1514303689 | Aug 25 04:10:31 AM UTC 24 | Aug 25 04:11:10 AM UTC 24 | 1643936084 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1270599156 | Aug 25 04:11:07 AM UTC 24 | Aug 25 04:11:46 AM UTC 24 | 5500643840 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3420826885 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:11 AM UTC 24 | 184517158 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3741063699 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:12 AM UTC 24 | 1064043259 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3785686393 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:12 AM UTC 24 | 691080117 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1815975070 | Aug 25 04:10:31 AM UTC 24 | Aug 25 04:11:12 AM UTC 24 | 176730168 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.87489026 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:13 AM UTC 24 | 271901594 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.840396349 | Aug 25 04:10:34 AM UTC 24 | Aug 25 04:11:15 AM UTC 24 | 183109085 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.545289892 | Aug 25 04:10:37 AM UTC 24 | Aug 25 04:11:15 AM UTC 24 | 346005748 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.3203276406 | Aug 25 04:10:43 AM UTC 24 | Aug 25 04:11:15 AM UTC 24 | 1271560930 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1492499052 | Aug 25 04:10:37 AM UTC 24 | Aug 25 04:11:18 AM UTC 24 | 179480625 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1740324336 | Aug 25 04:10:56 AM UTC 24 | Aug 25 04:11:19 AM UTC 24 | 333925376 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.2885255286 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:20 AM UTC 24 | 1654538215 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1185974717 | Aug 25 04:11:01 AM UTC 24 | Aug 25 04:11:21 AM UTC 24 | 172925546 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.670078753 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:21 AM UTC 24 | 1576825128 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4035449421 | Aug 25 04:10:56 AM UTC 24 | Aug 25 04:11:22 AM UTC 24 | 1648962716 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3053882112 | Aug 25 04:10:58 AM UTC 24 | Aug 25 04:11:23 AM UTC 24 | 1982124234 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1790048705 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:24 AM UTC 24 | 495162297 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1009510586 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:24 AM UTC 24 | 989328392 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1539597942 | Aug 25 04:11:09 AM UTC 24 | Aug 25 04:11:25 AM UTC 24 | 993608904 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.2182252903 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:25 AM UTC 24 | 2473494860 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3989873124 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:26 AM UTC 24 | 186110894 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3925127116 | Aug 25 04:10:26 AM UTC 24 | Aug 25 04:11:26 AM UTC 24 | 3292163972 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.4052279779 | Aug 25 04:11:10 AM UTC 24 | Aug 25 04:11:28 AM UTC 24 | 4109102993 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3013673199 | Aug 25 04:10:56 AM UTC 24 | Aug 25 04:11:28 AM UTC 24 | 266253048 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.67218398 | Aug 25 04:11:07 AM UTC 24 | Aug 25 04:11:28 AM UTC 24 | 250607845 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2440243756 | Aug 25 04:11:09 AM UTC 24 | Aug 25 04:11:29 AM UTC 24 | 1071774427 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.510141037 | Aug 25 04:11:13 AM UTC 24 | Aug 25 04:11:30 AM UTC 24 | 348083265 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2826619805 | Aug 25 04:10:56 AM UTC 24 | Aug 25 04:11:30 AM UTC 24 | 347906884 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.299916832 | Aug 25 04:11:07 AM UTC 24 | Aug 25 04:11:30 AM UTC 24 | 189569174 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.3072661533 | Aug 25 04:11:10 AM UTC 24 | Aug 25 04:11:30 AM UTC 24 | 528581714 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3307785617 | Aug 25 04:10:40 AM UTC 24 | Aug 25 04:11:31 AM UTC 24 | 6601836049 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.277707770 | Aug 25 04:11:12 AM UTC 24 | Aug 25 04:11:31 AM UTC 24 | 992846714 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3462943311 | Aug 25 04:11:05 AM UTC 24 | Aug 25 04:11:31 AM UTC 24 | 187426788 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1317550437 | Aug 25 04:11:16 AM UTC 24 | Aug 25 04:11:32 AM UTC 24 | 510056377 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2702303330 | Aug 25 04:10:32 AM UTC 24 | Aug 25 04:11:32 AM UTC 24 | 1035562418 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2914127679 | Aug 25 04:10:34 AM UTC 24 | Aug 25 04:11:34 AM UTC 24 | 6600350051 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1519132072 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:34 AM UTC 24 | 512713366 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.88181060 | Aug 25 04:10:38 AM UTC 24 | Aug 25 04:11:34 AM UTC 24 | 3664726820 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.862067756 | Aug 25 04:11:19 AM UTC 24 | Aug 25 04:11:35 AM UTC 24 | 183049908 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2321866604 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:36 AM UTC 24 | 1059312690 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4247845848 | Aug 25 04:10:56 AM UTC 24 | Aug 25 04:11:37 AM UTC 24 | 558010935 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.306989644 | Aug 25 04:11:23 AM UTC 24 | Aug 25 04:11:38 AM UTC 24 | 989222172 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.530975082 | Aug 25 04:11:26 AM UTC 24 | Aug 25 04:11:40 AM UTC 24 | 260869256 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2293810939 | Aug 25 04:11:26 AM UTC 24 | Aug 25 04:11:40 AM UTC 24 | 516713483 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2792365950 | Aug 25 04:11:13 AM UTC 24 | Aug 25 04:11:41 AM UTC 24 | 1115238572 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2936554355 | Aug 25 04:10:38 AM UTC 24 | Aug 25 04:11:44 AM UTC 24 | 373377455 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3085003606 | Aug 25 04:11:38 AM UTC 24 | Aug 25 04:11:54 AM UTC 24 | 4129275028 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3375506104 | Aug 25 04:11:24 AM UTC 24 | Aug 25 04:11:42 AM UTC 24 | 268147762 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3547940448 | Aug 25 04:11:24 AM UTC 24 | Aug 25 04:11:43 AM UTC 24 | 1397283969 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.4063047855 | Aug 25 04:11:09 AM UTC 24 | Aug 25 04:11:44 AM UTC 24 | 1326278561 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2145698572 | Aug 25 04:11:30 AM UTC 24 | Aug 25 04:11:45 AM UTC 24 | 249184370 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3751153809 | Aug 25 04:11:07 AM UTC 24 | Aug 25 04:11:47 AM UTC 24 | 507024357 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1330053180 | Aug 25 04:11:20 AM UTC 24 | Aug 25 04:11:47 AM UTC 24 | 332568420 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3492282643 | Aug 25 04:10:49 AM UTC 24 | Aug 25 04:11:48 AM UTC 24 | 1547713378 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2195693576 | Aug 25 04:11:09 AM UTC 24 | Aug 25 04:11:49 AM UTC 24 | 2100492349 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3593008044 | Aug 25 04:11:11 AM UTC 24 | Aug 25 04:11:50 AM UTC 24 | 1973135027 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2952146308 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:11:50 AM UTC 24 | 2110034940 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3476842033 | Aug 25 04:11:36 AM UTC 24 | Aug 25 04:11:51 AM UTC 24 | 261101409 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2243543877 | Aug 25 04:11:10 AM UTC 24 | Aug 25 04:11:52 AM UTC 24 | 1452198613 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.4208640256 | Aug 25 04:11:07 AM UTC 24 | Aug 25 04:11:53 AM UTC 24 | 2218501554 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.927855589 | Aug 25 04:11:16 AM UTC 24 | Aug 25 04:11:53 AM UTC 24 | 4515151011 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.441001212 | Aug 25 04:11:33 AM UTC 24 | Aug 25 04:11:53 AM UTC 24 | 1022224098 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.386488185 | Aug 25 04:10:59 AM UTC 24 | Aug 25 04:11:53 AM UTC 24 | 4122237935 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2488934802 | Aug 25 04:11:36 AM UTC 24 | Aug 25 04:11:54 AM UTC 24 | 260733227 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.4240667048 | Aug 25 04:11:24 AM UTC 24 | Aug 25 04:11:55 AM UTC 24 | 346508327 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1964366524 | Aug 25 04:11:30 AM UTC 24 | Aug 25 04:11:56 AM UTC 24 | 5497760547 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1437294363 | Aug 25 04:11:39 AM UTC 24 | Aug 25 04:11:56 AM UTC 24 | 187015561 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.414557628 | Aug 25 04:11:43 AM UTC 24 | Aug 25 04:11:58 AM UTC 24 | 852909313 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3062646432 | Aug 25 04:11:26 AM UTC 24 | Aug 25 04:11:59 AM UTC 24 | 1065029014 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.65673797 | Aug 25 04:11:47 AM UTC 24 | Aug 25 04:12:00 AM UTC 24 | 688899891 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3622751853 | Aug 25 04:11:30 AM UTC 24 | Aug 25 04:12:01 AM UTC 24 | 520215440 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.593054772 | Aug 25 04:11:28 AM UTC 24 | Aug 25 04:12:01 AM UTC 24 | 3295604316 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.340414308 | Aug 25 04:11:33 AM UTC 24 | Aug 25 04:12:01 AM UTC 24 | 332433017 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2674699832 | Aug 25 04:11:01 AM UTC 24 | Aug 25 04:12:03 AM UTC 24 | 3942910948 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3703642155 | Aug 25 04:11:48 AM UTC 24 | Aug 25 04:12:04 AM UTC 24 | 271614301 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2331788308 | Aug 25 04:11:45 AM UTC 24 | Aug 25 04:12:05 AM UTC 24 | 267353389 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2353384635 | Aug 25 04:11:30 AM UTC 24 | Aug 25 04:12:05 AM UTC 24 | 516487132 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2139003952 | Aug 25 04:11:50 AM UTC 24 | Aug 25 04:12:06 AM UTC 24 | 2736321738 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.3331914554 | Aug 25 04:11:38 AM UTC 24 | Aug 25 04:12:07 AM UTC 24 | 212830616 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2388980194 | Aug 25 04:11:18 AM UTC 24 | Aug 25 04:12:07 AM UTC 24 | 2066228311 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2935891354 | Aug 25 04:11:36 AM UTC 24 | Aug 25 04:12:08 AM UTC 24 | 536170680 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2891593676 | Aug 25 04:11:40 AM UTC 24 | Aug 25 04:12:09 AM UTC 24 | 335777489 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4097211990 | Aug 25 04:11:54 AM UTC 24 | Aug 25 04:12:09 AM UTC 24 | 259611548 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3267551770 | Aug 25 04:11:47 AM UTC 24 | Aug 25 04:12:10 AM UTC 24 | 394150915 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3833199448 | Aug 25 04:11:52 AM UTC 24 | Aug 25 04:12:11 AM UTC 24 | 1100153506 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2684565048 | Aug 25 04:11:36 AM UTC 24 | Aug 25 04:12:11 AM UTC 24 | 517396593 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3705036761 | Aug 25 04:11:55 AM UTC 24 | Aug 25 04:12:15 AM UTC 24 | 1217815409 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1931651328 | Aug 25 04:11:59 AM UTC 24 | Aug 25 04:12:15 AM UTC 24 | 258071846 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.2620096892 | Aug 25 04:11:46 AM UTC 24 | Aug 25 04:12:19 AM UTC 24 | 4938660730 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.4206147369 | Aug 25 04:12:01 AM UTC 24 | Aug 25 04:12:21 AM UTC 24 | 1342524396 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2483028540 | Aug 25 04:11:33 AM UTC 24 | Aug 25 04:12:22 AM UTC 24 | 510480445 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.639650837 | Aug 25 04:12:08 AM UTC 24 | Aug 25 04:12:24 AM UTC 24 | 296150740 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1659332349 | Aug 25 04:11:57 AM UTC 24 | Aug 25 04:12:25 AM UTC 24 | 1379419689 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2866616172 | Aug 25 04:11:55 AM UTC 24 | Aug 25 04:12:26 AM UTC 24 | 302107026 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3432565282 | Aug 25 04:12:03 AM UTC 24 | Aug 25 04:12:26 AM UTC 24 | 1016180134 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.643264951 | Aug 25 04:11:50 AM UTC 24 | Aug 25 04:12:26 AM UTC 24 | 2600219285 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.1258462691 | Aug 25 04:12:12 AM UTC 24 | Aug 25 04:12:26 AM UTC 24 | 331784074 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.3485326098 | Aug 25 04:12:06 AM UTC 24 | Aug 25 04:12:27 AM UTC 24 | 4522867502 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.40867460 | Aug 25 04:11:44 AM UTC 24 | Aug 25 04:12:27 AM UTC 24 | 542227341 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1400678853 | Aug 25 04:11:54 AM UTC 24 | Aug 25 04:12:28 AM UTC 24 | 1985832002 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2248826656 | Aug 25 04:11:52 AM UTC 24 | Aug 25 04:12:29 AM UTC 24 | 364909236 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1483947633 | Aug 25 04:12:10 AM UTC 24 | Aug 25 04:12:30 AM UTC 24 | 513755847 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3329155046 | Aug 25 04:12:15 AM UTC 24 | Aug 25 04:12:31 AM UTC 24 | 1961121424 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3529371916 | Aug 25 04:10:24 AM UTC 24 | Aug 25 04:12:33 AM UTC 24 | 5876186442 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.288862629 | Aug 25 04:11:33 AM UTC 24 | Aug 25 04:12:36 AM UTC 24 | 970054775 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1966375160 | Aug 25 04:12:02 AM UTC 24 | Aug 25 04:12:36 AM UTC 24 | 512949322 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.465274307 | Aug 25 04:11:59 AM UTC 24 | Aug 25 04:12:37 AM UTC 24 | 524470281 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2142565618 | Aug 25 04:12:07 AM UTC 24 | Aug 25 04:12:40 AM UTC 24 | 350845124 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.496924106 | Aug 25 04:12:24 AM UTC 24 | Aug 25 04:12:41 AM UTC 24 | 255183361 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1744680057 | Aug 25 04:12:28 AM UTC 24 | Aug 25 04:12:42 AM UTC 24 | 173542900 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.2019688354 | Aug 25 04:12:11 AM UTC 24 | Aug 25 04:12:43 AM UTC 24 | 2538822462 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1866896037 | Aug 25 04:11:16 AM UTC 24 | Aug 25 04:12:43 AM UTC 24 | 1346425102 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.675411086 | Aug 25 04:12:04 AM UTC 24 | Aug 25 04:12:44 AM UTC 24 | 2143185702 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2183186438 | Aug 25 04:12:29 AM UTC 24 | Aug 25 04:12:45 AM UTC 24 | 1430470971 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1581300529 | Aug 25 04:10:41 AM UTC 24 | Aug 25 04:12:46 AM UTC 24 | 8634626234 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3533182242 | Aug 25 04:12:27 AM UTC 24 | Aug 25 04:12:46 AM UTC 24 | 917702728 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3894163149 | Aug 25 04:12:33 AM UTC 24 | Aug 25 04:12:46 AM UTC 24 | 212487416 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1036285170 | Aug 25 04:10:18 AM UTC 24 | Aug 25 04:12:50 AM UTC 24 | 354293788 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1604195732 | Aug 25 04:10:27 AM UTC 24 | Aug 25 04:12:51 AM UTC 24 | 4890019105 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3290377889 | Aug 25 04:12:21 AM UTC 24 | Aug 25 04:12:51 AM UTC 24 | 345988306 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2267216123 | Aug 25 04:12:15 AM UTC 24 | Aug 25 04:12:52 AM UTC 24 | 2069894013 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.745397833 | Aug 25 04:12:26 AM UTC 24 | Aug 25 04:12:56 AM UTC 24 | 582642356 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2684569542 | Aug 25 04:12:37 AM UTC 24 | Aug 25 04:12:56 AM UTC 24 | 3173280506 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2077594481 | Aug 25 04:12:28 AM UTC 24 | Aug 25 04:12:57 AM UTC 24 | 332285685 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1525790326 | Aug 25 04:12:43 AM UTC 24 | Aug 25 04:12:59 AM UTC 24 | 254848654 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.531057436 | Aug 25 04:12:47 AM UTC 24 | Aug 25 04:13:01 AM UTC 24 | 729850942 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.4195391038 | Aug 25 04:12:44 AM UTC 24 | Aug 25 04:13:04 AM UTC 24 | 515465349 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.4057844654 | Aug 25 04:12:31 AM UTC 24 | Aug 25 04:13:04 AM UTC 24 | 335487070 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3558673381 | Aug 25 04:12:10 AM UTC 24 | Aug 25 04:13:07 AM UTC 24 | 1746299705 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1571745998 | Aug 25 04:10:52 AM UTC 24 | Aug 25 04:13:09 AM UTC 24 | 9471845714 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.4145680359 | Aug 25 04:12:51 AM UTC 24 | Aug 25 04:13:11 AM UTC 24 | 989473479 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1195276523 | Aug 25 04:12:56 AM UTC 24 | Aug 25 04:13:11 AM UTC 24 | 4926273502 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2534698415 | Aug 25 04:12:28 AM UTC 24 | Aug 25 04:13:12 AM UTC 24 | 1032361492 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2558013705 | Aug 25 04:12:57 AM UTC 24 | Aug 25 04:13:16 AM UTC 24 | 1021245851 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3235923867 | Aug 25 04:13:05 AM UTC 24 | Aug 25 04:13:17 AM UTC 24 | 170456944 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.341632378 | Aug 25 04:12:46 AM UTC 24 | Aug 25 04:13:17 AM UTC 24 | 718821559 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.213162010 | Aug 25 04:10:36 AM UTC 24 | Aug 25 04:13:18 AM UTC 24 | 2699753526 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2106367895 | Aug 25 04:12:36 AM UTC 24 | Aug 25 04:13:20 AM UTC 24 | 1559012909 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1460432178 | Aug 25 04:12:44 AM UTC 24 | Aug 25 04:13:21 AM UTC 24 | 516533350 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.187743384 | Aug 25 04:12:57 AM UTC 24 | Aug 25 04:13:21 AM UTC 24 | 300540437 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4200084502 | Aug 25 04:12:08 AM UTC 24 | Aug 25 04:13:24 AM UTC 24 | 13732228787 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2820088635 | Aug 25 04:12:52 AM UTC 24 | Aug 25 04:13:25 AM UTC 24 | 512380505 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3388597042 | Aug 25 04:13:13 AM UTC 24 | Aug 25 04:13:26 AM UTC 24 | 1269181600 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1599299399 | Aug 25 04:13:10 AM UTC 24 | Aug 25 04:13:27 AM UTC 24 | 716051752 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3653124904 | Aug 25 04:11:47 AM UTC 24 | Aug 25 04:13:29 AM UTC 24 | 1844580390 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3758864480 | Aug 25 04:13:03 AM UTC 24 | Aug 25 04:13:31 AM UTC 24 | 944496563 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1644165443 | Aug 25 04:13:08 AM UTC 24 | Aug 25 04:13:31 AM UTC 24 | 199729846 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.887648313 | Aug 25 04:13:17 AM UTC 24 | Aug 25 04:13:34 AM UTC 24 | 729484715 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1908814702 | Aug 25 04:13:22 AM UTC 24 | Aug 25 04:13:35 AM UTC 24 | 972322954 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.13700444 | Aug 25 04:12:47 AM UTC 24 | Aug 25 04:13:37 AM UTC 24 | 1076666867 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.4254479302 | Aug 25 04:11:23 AM UTC 24 | Aug 25 04:13:43 AM UTC 24 | 12041581485 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.4021492320 | Aug 25 04:13:30 AM UTC 24 | Aug 25 04:13:43 AM UTC 24 | 688437117 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.74836944 | Aug 25 04:13:25 AM UTC 24 | Aug 25 04:13:43 AM UTC 24 | 270098538 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1795396877 | Aug 25 04:13:12 AM UTC 24 | Aug 25 04:13:47 AM UTC 24 | 1030444926 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2181167710 | Aug 25 04:13:18 AM UTC 24 | Aug 25 04:13:49 AM UTC 24 | 342713082 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.895737314 | Aug 25 04:12:42 AM UTC 24 | Aug 25 04:13:49 AM UTC 24 | 3597799693 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2207719634 | Aug 25 04:13:17 AM UTC 24 | Aug 25 04:13:50 AM UTC 24 | 354034708 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1611947364 | Aug 25 04:13:32 AM UTC 24 | Aug 25 04:13:51 AM UTC 24 | 4239043265 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.924033991 | Aug 25 04:10:41 AM UTC 24 | Aug 25 04:13:51 AM UTC 24 | 1240827823 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3918503841 | Aug 25 04:11:40 AM UTC 24 | Aug 25 04:15:43 AM UTC 24 | 1996525006 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3504593536 | Aug 25 04:13:43 AM UTC 24 | Aug 25 04:13:56 AM UTC 24 | 1376767220 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3921647516 | Aug 25 04:13:32 AM UTC 24 | Aug 25 04:13:57 AM UTC 24 | 3416265023 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.4048482939 | Aug 25 04:13:28 AM UTC 24 | Aug 25 04:14:00 AM UTC 24 | 1012284426 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.339410695 | Aug 25 04:13:44 AM UTC 24 | Aug 25 04:14:02 AM UTC 24 | 699677727 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3806555691 | Aug 25 04:11:38 AM UTC 24 | Aug 25 04:14:02 AM UTC 24 | 27292971233 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.2682676025 | Aug 25 04:13:51 AM UTC 24 | Aug 25 04:14:04 AM UTC 24 | 394850875 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2019351347 | Aug 25 04:11:43 AM UTC 24 | Aug 25 04:14:08 AM UTC 24 | 6318829849 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.788458751 | Aug 25 04:13:52 AM UTC 24 | Aug 25 04:14:08 AM UTC 24 | 182388679 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.707044419 | Aug 25 04:13:36 AM UTC 24 | Aug 25 04:14:09 AM UTC 24 | 1011374910 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2481013759 | Aug 25 04:12:32 AM UTC 24 | Aug 25 04:14:13 AM UTC 24 | 21195320337 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2420995358 | Aug 25 04:13:52 AM UTC 24 | Aug 25 04:14:13 AM UTC 24 | 222105017 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2104136512 | Aug 25 04:10:30 AM UTC 24 | Aug 25 04:14:14 AM UTC 24 | 465895991 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.420869126 | Aug 25 04:14:01 AM UTC 24 | Aug 25 04:14:14 AM UTC 24 | 688821034 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.775195835 | Aug 25 04:13:22 AM UTC 24 | Aug 25 04:14:19 AM UTC 24 | 1143369098 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1792796857 | Aug 25 04:12:22 AM UTC 24 | Aug 25 04:14:19 AM UTC 24 | 6512293968 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3387856566 | Aug 25 04:11:54 AM UTC 24 | Aug 25 04:14:19 AM UTC 24 | 6115669335 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.994784744 | Aug 25 04:14:03 AM UTC 24 | Aug 25 04:14:21 AM UTC 24 | 175093828 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2035683194 | Aug 25 04:13:49 AM UTC 24 | Aug 25 04:14:23 AM UTC 24 | 496537655 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2073084928 | Aug 25 04:14:10 AM UTC 24 | Aug 25 04:14:26 AM UTC 24 | 508537303 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3510221456 | Aug 25 04:13:21 AM UTC 24 | Aug 25 04:14:28 AM UTC 24 | 5231685015 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1141279377 | Aug 25 04:14:02 AM UTC 24 | Aug 25 04:14:28 AM UTC 24 | 291052358 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2078063944 | Aug 25 04:10:53 AM UTC 24 | Aug 25 04:14:28 AM UTC 24 | 2482183070 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3721063408 | Aug 25 04:13:57 AM UTC 24 | Aug 25 04:14:30 AM UTC 24 | 2074856309 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1413962596 | Aug 25 04:11:57 AM UTC 24 | Aug 25 04:14:30 AM UTC 24 | 11754623027 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.4152530679 | Aug 25 04:14:14 AM UTC 24 | Aug 25 04:14:31 AM UTC 24 | 175640440 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2296250450 | Aug 25 04:13:43 AM UTC 24 | Aug 25 04:14:36 AM UTC 24 | 791173300 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3983922701 | Aug 25 04:14:08 AM UTC 24 | Aug 25 04:14:37 AM UTC 24 | 333943604 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3011814372 | Aug 25 04:14:22 AM UTC 24 | Aug 25 04:14:38 AM UTC 24 | 181593688 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3334131555 | Aug 25 04:14:21 AM UTC 24 | Aug 25 04:14:44 AM UTC 24 | 861864265 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3072279977 | Aug 25 04:14:20 AM UTC 24 | Aug 25 04:14:44 AM UTC 24 | 19722079747 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2051286873 | Aug 25 04:14:29 AM UTC 24 | Aug 25 04:14:45 AM UTC 24 | 1118917205 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2748314332 | Aug 25 04:11:26 AM UTC 24 | Aug 25 04:14:46 AM UTC 24 | 2861570089 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3583570045 | Aug 25 04:14:15 AM UTC 24 | Aug 25 04:14:47 AM UTC 24 | 5520704777 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.340583777 | Aug 25 04:14:31 AM UTC 24 | Aug 25 04:14:48 AM UTC 24 | 426142747 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.4087489366 | Aug 25 04:14:38 AM UTC 24 | Aug 25 04:14:53 AM UTC 24 | 1033149365 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3677561710 | Aug 25 04:14:27 AM UTC 24 | Aug 25 04:15:01 AM UTC 24 | 1009610297 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1174392381 | Aug 25 04:14:45 AM UTC 24 | Aug 25 04:15:02 AM UTC 24 | 176886949 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4173956603 | Aug 25 04:14:48 AM UTC 24 | Aug 25 04:15:03 AM UTC 24 | 2479426350 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.4057941170 | Aug 25 04:14:29 AM UTC 24 | Aug 25 04:15:05 AM UTC 24 | 2216213389 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1234709975 | Aug 25 04:14:32 AM UTC 24 | Aug 25 04:15:06 AM UTC 24 | 1053767219 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2992506473 | Aug 25 04:14:14 AM UTC 24 | Aug 25 04:15:08 AM UTC 24 | 1551600033 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1316859163 | Aug 25 04:11:20 AM UTC 24 | Aug 25 04:15:11 AM UTC 24 | 12046979985 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1218359976 | Aug 25 04:14:54 AM UTC 24 | Aug 25 04:15:12 AM UTC 24 | 183144642 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3946044886 | Aug 25 04:15:05 AM UTC 24 | Aug 25 04:15:19 AM UTC 24 | 340863820 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3969359711 | Aug 25 04:15:07 AM UTC 24 | Aug 25 04:15:21 AM UTC 24 | 186357266 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1977882112 | Aug 25 04:14:46 AM UTC 24 | Aug 25 04:15:21 AM UTC 24 | 2056547818 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2245612694 | Aug 25 04:13:05 AM UTC 24 | Aug 25 04:15:28 AM UTC 24 | 1920518160 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1725570084 | Aug 25 04:10:22 AM UTC 24 | Aug 25 04:15:28 AM UTC 24 | 8703175318 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.4291299123 | Aug 25 04:15:13 AM UTC 24 | Aug 25 04:15:29 AM UTC 24 | 1297593408 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2990488984 | Aug 25 04:11:10 AM UTC 24 | Aug 25 04:15:29 AM UTC 24 | 6452912754 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.4106145770 | Aug 25 04:14:49 AM UTC 24 | Aug 25 04:15:32 AM UTC 24 | 1239372509 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3944137625 | Aug 25 04:14:39 AM UTC 24 | Aug 25 04:15:37 AM UTC 24 | 833358936 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.764227395 | Aug 25 04:15:22 AM UTC 24 | Aug 25 04:15:38 AM UTC 24 | 354139347 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.2965909693 | Aug 25 04:15:02 AM UTC 24 | Aug 25 04:15:38 AM UTC 24 | 4940760197 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.88254309 | Aug 25 04:11:12 AM UTC 24 | Aug 25 04:15:41 AM UTC 24 | 16636266130 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3530149359 | Aug 25 04:11:36 AM UTC 24 | Aug 25 04:15:46 AM UTC 24 | 5210829888 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2049876988 | Aug 25 04:11:31 AM UTC 24 | Aug 25 04:15:43 AM UTC 24 | 22704027458 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3309173571 | Aug 25 04:13:38 AM UTC 24 | Aug 25 04:15:48 AM UTC 24 | 19150151714 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3205101846 | Aug 25 04:15:29 AM UTC 24 | Aug 25 04:15:51 AM UTC 24 | 3760505498 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2200017981 | Aug 25 04:13:13 AM UTC 24 | Aug 25 04:15:54 AM UTC 24 | 11928189796 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2625011930 | Aug 25 04:11:28 AM UTC 24 | Aug 25 04:15:55 AM UTC 24 | 3329895970 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3394949891 | Aug 25 04:12:12 AM UTC 24 | Aug 25 04:15:56 AM UTC 24 | 13015552756 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3698299525 | Aug 25 04:14:09 AM UTC 24 | Aug 25 04:15:57 AM UTC 24 | 16848919548 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1254883384 | Aug 25 04:10:18 AM UTC 24 | Aug 25 04:15:59 AM UTC 24 | 52804769124 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3821478418 | Aug 25 04:15:05 AM UTC 24 | Aug 25 04:16:00 AM UTC 24 | 7849759351 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.4207456957 | Aug 25 04:10:25 AM UTC 24 | Aug 25 04:16:01 AM UTC 24 | 1083425268 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.809209131 | Aug 25 04:15:25 AM UTC 24 | Aug 25 04:16:01 AM UTC 24 | 1980393844 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.978167022 | Aug 25 04:15:11 AM UTC 24 | Aug 25 04:16:02 AM UTC 24 | 39445192389 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2839564613 | Aug 25 04:12:46 AM UTC 24 | Aug 25 04:16:06 AM UTC 24 | 15094276762 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2962917510 | Aug 25 04:10:34 AM UTC 24 | Aug 25 04:16:08 AM UTC 24 | 10884435650 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2229158831 | Aug 25 04:12:19 AM UTC 24 | Aug 25 04:16:11 AM UTC 24 | 29654938726 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2739502217 | Aug 25 04:11:07 AM UTC 24 | Aug 25 04:16:12 AM UTC 24 | 20583690445 ps |
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