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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.53 96.89 92.56 97.68 100.00 98.62 97.90 99.06


Total test records in report: 456
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T314 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.391202245 Aug 25 04:15:20 AM UTC 24 Aug 25 04:16:15 AM UTC 24 809395552 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1835608766 Aug 25 04:13:58 AM UTC 24 Aug 25 04:16:16 AM UTC 24 3893131390 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2602271954 Aug 25 04:12:07 AM UTC 24 Aug 25 04:16:18 AM UTC 24 1924048732 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1825702712 Aug 25 04:11:07 AM UTC 24 Aug 25 04:16:19 AM UTC 24 24954090905 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2498559154 Aug 25 04:15:13 AM UTC 24 Aug 25 04:16:21 AM UTC 24 1152528899 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3805516653 Aug 25 04:10:52 AM UTC 24 Aug 25 04:16:29 AM UTC 24 8424781427 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2905548780 Aug 25 04:12:52 AM UTC 24 Aug 25 04:16:29 AM UTC 24 2870168712 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1684958716 Aug 25 04:15:04 AM UTC 24 Aug 25 04:16:30 AM UTC 24 1395003003 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2215561360 Aug 25 04:11:07 AM UTC 24 Aug 25 04:16:34 AM UTC 24 12158421304 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3452991473 Aug 25 04:11:50 AM UTC 24 Aug 25 04:16:39 AM UTC 24 18132078983 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3636262383 Aug 25 04:11:09 AM UTC 24 Aug 25 04:16:42 AM UTC 24 3501374901 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2090011598 Aug 25 04:15:29 AM UTC 24 Aug 25 04:16:44 AM UTC 24 12780868410 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4193065613 Aug 25 04:12:02 AM UTC 24 Aug 25 04:16:47 AM UTC 24 5058449978 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3969426629 Aug 25 04:10:52 AM UTC 24 Aug 25 04:16:48 AM UTC 24 3748003335 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3248523911 Aug 25 04:12:38 AM UTC 24 Aug 25 04:16:58 AM UTC 24 2382372514 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3754982279 Aug 25 04:10:37 AM UTC 24 Aug 25 04:16:59 AM UTC 24 382375914 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2722601545 Aug 25 04:13:18 AM UTC 24 Aug 25 04:17:01 AM UTC 24 28219964975 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2710756473 Aug 25 04:12:02 AM UTC 24 Aug 25 04:17:02 AM UTC 24 17386707304 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3216718780 Aug 25 04:13:11 AM UTC 24 Aug 25 04:17:02 AM UTC 24 2445270580 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.308840856 Aug 25 04:14:24 AM UTC 24 Aug 25 04:17:02 AM UTC 24 10098980167 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.842444281 Aug 25 04:11:28 AM UTC 24 Aug 25 04:17:07 AM UTC 24 4356618181 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2404227097 Aug 25 04:11:53 AM UTC 24 Aug 25 04:17:07 AM UTC 24 11177245257 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3714109741 Aug 25 04:13:57 AM UTC 24 Aug 25 04:17:23 AM UTC 24 3872879055 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3229891388 Aug 25 04:10:52 AM UTC 24 Aug 25 04:17:38 AM UTC 24 3589233098 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2414848241 Aug 25 04:11:07 AM UTC 24 Aug 25 04:17:39 AM UTC 24 3590655493 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.580506170 Aug 25 04:11:49 AM UTC 24 Aug 25 04:17:42 AM UTC 24 3517224397 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.644769450 Aug 25 04:11:13 AM UTC 24 Aug 25 04:17:43 AM UTC 24 9116461647 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3816937673 Aug 25 04:12:27 AM UTC 24 Aug 25 04:17:44 AM UTC 24 5120685429 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.923489750 Aug 25 04:13:50 AM UTC 24 Aug 25 04:18:01 AM UTC 24 14908345054 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1629949439 Aug 25 04:10:52 AM UTC 24 Aug 25 04:18:05 AM UTC 24 5770095694 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3404414267 Aug 25 04:11:11 AM UTC 24 Aug 25 04:18:12 AM UTC 24 12357386721 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3731479814 Aug 25 04:12:51 AM UTC 24 Aug 25 04:18:15 AM UTC 24 4434771424 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.911289406 Aug 25 04:14:47 AM UTC 24 Aug 25 04:18:17 AM UTC 24 3902988586 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3428510675 Aug 25 04:10:27 AM UTC 24 Aug 25 04:18:20 AM UTC 24 9746719769 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3730269141 Aug 25 04:11:45 AM UTC 24 Aug 25 04:18:27 AM UTC 24 4117872767 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.140437043 Aug 25 04:14:37 AM UTC 24 Aug 25 04:18:28 AM UTC 24 14899271314 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1069105971 Aug 25 04:14:28 AM UTC 24 Aug 25 04:18:30 AM UTC 24 3300987692 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3394635853 Aug 25 04:12:45 AM UTC 24 Aug 25 04:18:42 AM UTC 24 3950367052 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3457773445 Aug 25 04:15:08 AM UTC 24 Aug 25 04:18:46 AM UTC 24 3973297592 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2103821816 Aug 25 04:10:56 AM UTC 24 Aug 25 04:19:15 AM UTC 24 6854952444 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4209677654 Aug 25 04:15:02 AM UTC 24 Aug 25 04:19:40 AM UTC 24 15792252270 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1660160113 Aug 25 04:13:35 AM UTC 24 Aug 25 04:19:46 AM UTC 24 4233321871 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.46710055 Aug 25 04:13:00 AM UTC 24 Aug 25 04:20:02 AM UTC 24 13034881176 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2160100549 Aug 25 04:12:10 AM UTC 24 Aug 25 04:20:11 AM UTC 24 46462203301 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3227325686 Aug 25 04:12:28 AM UTC 24 Aug 25 04:20:12 AM UTC 24 10625998518 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3028892804 Aug 25 04:11:33 AM UTC 24 Aug 25 04:20:13 AM UTC 24 6803271545 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.195788326 Aug 25 04:11:24 AM UTC 24 Aug 25 04:20:15 AM UTC 24 18496706575 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3483516732 Aug 25 04:14:04 AM UTC 24 Aug 25 04:20:40 AM UTC 24 5022600521 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2318528161 Aug 25 04:11:56 AM UTC 24 Aug 25 04:20:56 AM UTC 24 23016620109 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.365701249 Aug 25 04:10:40 AM UTC 24 Aug 25 04:20:57 AM UTC 24 77388082005 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1733561731 Aug 25 04:15:22 AM UTC 24 Aug 25 04:21:00 AM UTC 24 5807537124 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3616981950 Aug 25 04:14:20 AM UTC 24 Aug 25 04:21:09 AM UTC 24 22295326209 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3876897325 Aug 25 04:13:48 AM UTC 24 Aug 25 04:21:29 AM UTC 24 9006093310 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1754763303 Aug 25 04:11:30 AM UTC 24 Aug 25 04:21:32 AM UTC 24 22230974590 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1550582160 Aug 25 04:13:28 AM UTC 24 Aug 25 04:21:34 AM UTC 24 24721258294 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1990112774 Aug 25 04:10:52 AM UTC 24 Aug 25 04:21:49 AM UTC 24 45809709876 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1418386800 Aug 25 04:14:31 AM UTC 24 Aug 25 04:21:50 AM UTC 24 16799506209 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2126492736 Aug 25 04:14:15 AM UTC 24 Aug 25 04:22:23 AM UTC 24 40209253175 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1987129601 Aug 25 04:14:45 AM UTC 24 Aug 25 04:22:33 AM UTC 24 11823615503 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1361347867 Aug 25 04:12:30 AM UTC 24 Aug 25 04:25:11 AM UTC 24 19617011648 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.894525494 Aug 25 04:13:26 AM UTC 24 Aug 25 04:27:40 AM UTC 24 132597004553 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2567204518 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:18 AM UTC 24 577501983 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4011719475 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:18 AM UTC 24 338804607 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2607742067 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:18 AM UTC 24 174619789 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.258541114 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:18 AM UTC 24 922402594 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2412170953 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:18 AM UTC 24 1025447394 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.24751385 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:18 AM UTC 24 1078767894 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3206097452 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:19 AM UTC 24 323655715 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1982734932 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:19 AM UTC 24 485079691 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2403235108 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:19 AM UTC 24 251795493 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1464221644 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:19 AM UTC 24 950722794 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4142363459 Aug 25 02:22:01 AM UTC 24 Aug 25 02:22:19 AM UTC 24 987988904 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.203766523 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:19 AM UTC 24 252570073 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1773190943 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:19 AM UTC 24 1185426493 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1985126970 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:19 AM UTC 24 4952344768 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3776686385 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:20 AM UTC 24 1003474479 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3627382181 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:20 AM UTC 24 551117176 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.591873795 Aug 25 02:22:13 AM UTC 24 Aug 25 02:22:22 AM UTC 24 687615651 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1845596205 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:22 AM UTC 24 254691895 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1633268555 Aug 25 02:22:13 AM UTC 24 Aug 25 02:22:24 AM UTC 24 993044412 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3988096063 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:24 AM UTC 24 313129801 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1884917805 Aug 25 02:22:13 AM UTC 24 Aug 25 02:22:24 AM UTC 24 260318260 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3307484815 Aug 25 02:22:11 AM UTC 24 Aug 25 02:22:24 AM UTC 24 170701507 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1344762642 Aug 25 02:22:13 AM UTC 24 Aug 25 02:22:24 AM UTC 24 260315630 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3804012971 Aug 25 02:22:11 AM UTC 24 Aug 25 02:22:25 AM UTC 24 174402480 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1219614297 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:26 AM UTC 24 704561496 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4043458361 Aug 25 02:22:13 AM UTC 24 Aug 25 02:22:26 AM UTC 24 266420554 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.173070373 Aug 25 02:22:11 AM UTC 24 Aug 25 02:22:27 AM UTC 24 356612536 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3857348229 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:27 AM UTC 24 4119558100 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1414441225 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:27 AM UTC 24 167587950 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2757086489 Aug 25 02:22:13 AM UTC 24 Aug 25 02:22:27 AM UTC 24 338566691 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.745198993 Aug 25 02:22:11 AM UTC 24 Aug 25 02:22:29 AM UTC 24 346229300 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2135987835 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:30 AM UTC 24 181011592 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.832597918 Aug 25 02:22:13 AM UTC 24 Aug 25 02:22:31 AM UTC 24 3926835589 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1033884165 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:31 AM UTC 24 635765938 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3471915144 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:31 AM UTC 24 3527538114 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3616376498 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:31 AM UTC 24 249420709 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4129739023 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:31 AM UTC 24 171312165 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1608077601 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:31 AM UTC 24 1071765295 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.192599955 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:32 AM UTC 24 186540193 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.992376450 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:32 AM UTC 24 209826863 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2492905563 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:32 AM UTC 24 260659146 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3220402755 Aug 25 02:22:18 AM UTC 24 Aug 25 02:22:33 AM UTC 24 780379317 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2164462399 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:33 AM UTC 24 339020408 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2264210918 Aug 25 02:22:13 AM UTC 24 Aug 25 02:22:34 AM UTC 24 171948766 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.60311192 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:34 AM UTC 24 1496994726 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1448107815 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:35 AM UTC 24 508021007 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2682676549 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:36 AM UTC 24 690950630 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2271098656 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:36 AM UTC 24 518047954 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1003312649 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:36 AM UTC 24 288814017 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.827337790 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:36 AM UTC 24 250531403 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3401200282 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:37 AM UTC 24 356785958 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.250547459 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:37 AM UTC 24 1807888655 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1849932204 Aug 25 02:22:18 AM UTC 24 Aug 25 02:22:37 AM UTC 24 691079113 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.862080537 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:37 AM UTC 24 259275275 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4086691436 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:37 AM UTC 24 171037508 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1714274065 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:38 AM UTC 24 690838590 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.177331989 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:38 AM UTC 24 1153793843 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2418620254 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:39 AM UTC 24 2498078622 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4000306297 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:39 AM UTC 24 721091825 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1320570261 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:40 AM UTC 24 995717400 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2164862732 Aug 25 02:22:25 AM UTC 24 Aug 25 02:22:40 AM UTC 24 250175609 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3063896668 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:41 AM UTC 24 503633636 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1506324615 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:41 AM UTC 24 852369181 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3876061712 Aug 25 02:22:22 AM UTC 24 Aug 25 02:22:41 AM UTC 24 663625352 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1305725620 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:41 AM UTC 24 542128321 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2376822304 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:42 AM UTC 24 252883993 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3295049096 Aug 25 02:22:28 AM UTC 24 Aug 25 02:22:42 AM UTC 24 346766621 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3806130338 Aug 25 02:22:21 AM UTC 24 Aug 25 02:22:42 AM UTC 24 172619172 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1010450944 Aug 25 02:22:28 AM UTC 24 Aug 25 02:22:43 AM UTC 24 496806243 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2134390832 Aug 25 02:22:31 AM UTC 24 Aug 25 02:22:43 AM UTC 24 169778888 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4025222228 Aug 25 02:22:28 AM UTC 24 Aug 25 02:22:43 AM UTC 24 248454278 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4248020349 Aug 25 02:22:28 AM UTC 24 Aug 25 02:22:43 AM UTC 24 2757208471 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.816342032 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:44 AM UTC 24 1022247983 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.315679257 Aug 25 02:22:30 AM UTC 24 Aug 25 02:22:45 AM UTC 24 707492412 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.140200904 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:45 AM UTC 24 719677680 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4243248788 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:45 AM UTC 24 250136098 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4142586708 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:45 AM UTC 24 269906555 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3966378228 Aug 25 02:22:32 AM UTC 24 Aug 25 02:22:45 AM UTC 24 720903561 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1685840196 Aug 25 02:22:33 AM UTC 24 Aug 25 02:22:46 AM UTC 24 332971660 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1909681764 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:46 AM UTC 24 8950612142 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4025846424 Aug 25 02:22:05 AM UTC 24 Aug 25 02:22:46 AM UTC 24 1006558832 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3873527773 Aug 25 02:22:26 AM UTC 24 Aug 25 02:22:46 AM UTC 24 1898142475 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3054842539 Aug 25 02:22:32 AM UTC 24 Aug 25 02:22:47 AM UTC 24 180848745 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1295979681 Aug 25 02:22:28 AM UTC 24 Aug 25 02:22:47 AM UTC 24 179023023 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.279655612 Aug 25 02:22:36 AM UTC 24 Aug 25 02:22:49 AM UTC 24 720334608 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3434826586 Aug 25 02:22:34 AM UTC 24 Aug 25 02:22:50 AM UTC 24 904576432 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1820174023 Aug 25 02:22:33 AM UTC 24 Aug 25 02:22:50 AM UTC 24 334861503 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1806005990 Aug 25 02:22:39 AM UTC 24 Aug 25 02:22:51 AM UTC 24 3294286227 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.107595631 Aug 25 02:22:31 AM UTC 24 Aug 25 02:22:51 AM UTC 24 338794147 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2501939317 Aug 25 02:22:38 AM UTC 24 Aug 25 02:22:51 AM UTC 24 185392555 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3817627157 Aug 25 02:22:37 AM UTC 24 Aug 25 02:22:52 AM UTC 24 834812314 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.907990750 Aug 25 02:22:09 AM UTC 24 Aug 25 02:22:52 AM UTC 24 2746989897 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2925122850 Aug 25 02:22:32 AM UTC 24 Aug 25 02:22:52 AM UTC 24 174678428 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2682394996 Aug 25 02:22:38 AM UTC 24 Aug 25 02:22:53 AM UTC 24 1764578271 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1584157613 Aug 25 02:22:43 AM UTC 24 Aug 25 02:22:54 AM UTC 24 183202739 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.546090714 Aug 25 02:22:38 AM UTC 24 Aug 25 02:22:54 AM UTC 24 507203667 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.340104175 Aug 25 02:22:42 AM UTC 24 Aug 25 02:22:55 AM UTC 24 687587049 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3762644024 Aug 25 02:22:35 AM UTC 24 Aug 25 02:22:55 AM UTC 24 990091820 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1544329053 Aug 25 02:22:40 AM UTC 24 Aug 25 02:22:55 AM UTC 24 1121309883 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4288431288 Aug 25 02:22:40 AM UTC 24 Aug 25 02:22:56 AM UTC 24 263973393 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.105011911 Aug 25 02:22:39 AM UTC 24 Aug 25 02:22:56 AM UTC 24 663282821 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2280762676 Aug 25 02:22:37 AM UTC 24 Aug 25 02:22:57 AM UTC 24 274497189 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.289727079 Aug 25 02:22:28 AM UTC 24 Aug 25 02:22:58 AM UTC 24 986437873 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2299284366 Aug 25 02:22:38 AM UTC 24 Aug 25 02:23:00 AM UTC 24 249657007 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.572927297 Aug 25 02:22:42 AM UTC 24 Aug 25 02:23:01 AM UTC 24 1501060107 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.407849048 Aug 25 02:22:42 AM UTC 24 Aug 25 02:23:01 AM UTC 24 5176506008 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.187984625 Aug 25 02:22:14 AM UTC 24 Aug 25 02:23:04 AM UTC 24 687883328 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.906450312 Aug 25 02:22:05 AM UTC 24 Aug 25 02:23:10 AM UTC 24 1384573069 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4269716961 Aug 25 02:22:05 AM UTC 24 Aug 25 02:23:21 AM UTC 24 6089278540 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1437414894 Aug 25 02:22:26 AM UTC 24 Aug 25 02:23:22 AM UTC 24 721128448 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2070994684 Aug 25 02:22:01 AM UTC 24 Aug 25 02:23:27 AM UTC 24 5851593716 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.80784794 Aug 25 02:22:28 AM UTC 24 Aug 25 02:23:33 AM UTC 24 1040455617 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1439505694 Aug 25 02:22:38 AM UTC 24 Aug 25 02:23:38 AM UTC 24 1351415193 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1355199293 Aug 25 02:22:22 AM UTC 24 Aug 25 02:23:43 AM UTC 24 1039910188 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3092352315 Aug 25 02:22:21 AM UTC 24 Aug 25 02:23:44 AM UTC 24 1055242928 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3411225365 Aug 25 02:22:42 AM UTC 24 Aug 25 02:23:46 AM UTC 24 14488135319 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1626254659 Aug 25 02:22:11 AM UTC 24 Aug 25 02:23:47 AM UTC 24 1594760046 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2021252610 Aug 25 02:22:26 AM UTC 24 Aug 25 02:23:48 AM UTC 24 2147753369 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.124331864 Aug 25 02:22:08 AM UTC 24 Aug 25 02:23:53 AM UTC 24 635322785 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4145346852 Aug 25 02:22:05 AM UTC 24 Aug 25 02:23:55 AM UTC 24 2332480205 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4062764852 Aug 25 02:22:21 AM UTC 24 Aug 25 02:23:56 AM UTC 24 1554642132 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3576683777 Aug 25 02:22:21 AM UTC 24 Aug 25 02:23:56 AM UTC 24 3175211573 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4096560828 Aug 25 02:22:26 AM UTC 24 Aug 25 02:23:58 AM UTC 24 1568220428 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2729758058 Aug 25 02:22:37 AM UTC 24 Aug 25 02:23:59 AM UTC 24 1313570548 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3612824231 Aug 25 02:22:30 AM UTC 24 Aug 25 02:24:01 AM UTC 24 6090903783 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.956977330 Aug 25 02:22:32 AM UTC 24 Aug 25 02:24:12 AM UTC 24 6090503257 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.505596531 Aug 25 02:22:18 AM UTC 24 Aug 25 02:24:17 AM UTC 24 3922413059 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3392392773 Aug 25 02:22:21 AM UTC 24 Aug 25 02:24:18 AM UTC 24 965699121 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3618547074 Aug 25 02:22:05 AM UTC 24 Aug 25 02:24:20 AM UTC 24 637371612 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1385255043 Aug 25 02:22:28 AM UTC 24 Aug 25 02:24:32 AM UTC 24 325878789 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.967609447 Aug 25 02:22:32 AM UTC 24 Aug 25 02:24:38 AM UTC 24 1246650599 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3986260582 Aug 25 02:22:31 AM UTC 24 Aug 25 02:24:45 AM UTC 24 338555866 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1228146828 Aug 25 02:22:34 AM UTC 24 Aug 25 02:24:45 AM UTC 24 6663707909 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.624406255 Aug 25 02:22:35 AM UTC 24 Aug 25 02:24:50 AM UTC 24 324383104 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1824328805 Aug 25 02:22:38 AM UTC 24 Aug 25 02:24:57 AM UTC 24 267055306 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.528112672 Aug 25 02:22:21 AM UTC 24 Aug 25 02:26:02 AM UTC 24 491763727 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2343542438 Aug 25 02:22:21 AM UTC 24 Aug 25 02:26:02 AM UTC 24 353155293 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.349163208 Aug 25 02:22:42 AM UTC 24 Aug 25 02:26:04 AM UTC 24 2166847729 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2562529545 Aug 25 02:22:09 AM UTC 24 Aug 25 02:26:08 AM UTC 24 691570186 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1728394181 Aug 25 02:22:13 AM UTC 24 Aug 25 02:26:18 AM UTC 24 705577244 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3589150318 Aug 25 02:22:26 AM UTC 24 Aug 25 02:26:26 AM UTC 24 1539168547 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1147685267 Aug 25 02:22:22 AM UTC 24 Aug 25 02:26:27 AM UTC 24 1421408660 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2855140982 Aug 25 02:22:26 AM UTC 24 Aug 25 02:26:27 AM UTC 24 1128708880 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.151201185 Aug 25 02:22:26 AM UTC 24 Aug 25 02:26:32 AM UTC 24 401183220 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4246391852 Aug 25 02:22:39 AM UTC 24 Aug 25 02:26:43 AM UTC 24 1907796074 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2252085061
Short name T10
Test name
Test status
Simulation time 550994194 ps
CPU time 18.4 seconds
Started Aug 25 04:10:22 AM UTC 24
Finished Aug 25 04:10:48 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225208506
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.2252085061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1596608295
Short name T11
Test name
Test status
Simulation time 5278482324 ps
CPU time 38.33 seconds
Started Aug 25 04:10:18 AM UTC 24
Finished Aug 25 04:10:58 AM UTC 24
Peak memory 243172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1596608295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1596608295
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1725570084
Short name T51
Test name
Test status
Simulation time 8703175318 ps
CPU time 294.76 seconds
Started Aug 25 04:10:22 AM UTC 24
Finished Aug 25 04:15:28 AM UTC 24
Peak memory 256132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725570084 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.1725570084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3812009838
Short name T9
Test name
Test status
Simulation time 346854435 ps
CPU time 17.46 seconds
Started Aug 25 04:10:27 AM UTC 24
Finished Aug 25 04:10:47 AM UTC 24
Peak memory 228244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812009838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3812009838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3529371916
Short name T17
Test name
Test status
Simulation time 5876186442 ps
CPU time 86.72 seconds
Started Aug 25 04:10:24 AM UTC 24
Finished Aug 25 04:12:33 AM UTC 24
Peak memory 234984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3529371916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3529371916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1740324336
Short name T56
Test name
Test status
Simulation time 333925376 ps
CPU time 18 seconds
Started Aug 25 04:10:56 AM UTC 24
Finished Aug 25 04:11:19 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740324336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1740324336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.4208640256
Short name T91
Test name
Test status
Simulation time 2218501554 ps
CPU time 37.94 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:11:53 AM UTC 24
Peak memory 228904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420864025
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.4208640256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3618547074
Short name T123
Test name
Test status
Simulation time 637371612 ps
CPU time 119.49 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:24:20 AM UTC 24
Peak memory 223864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618547074 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.3618547074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1254883384
Short name T53
Test name
Test status
Simulation time 52804769124 ps
CPU time 335.56 seconds
Started Aug 25 04:10:18 AM UTC 24
Finished Aug 25 04:15:59 AM UTC 24
Peak memory 249220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254883384 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.1254883384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1113554872
Short name T12
Test name
Test status
Simulation time 544574395 ps
CPU time 29.96 seconds
Started Aug 25 04:10:18 AM UTC 24
Finished Aug 25 04:11:01 AM UTC 24
Peak memory 226236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111355487
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.1113554872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.299916832
Short name T142
Test name
Test status
Simulation time 189569174 ps
CPU time 15.32 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:11:30 AM UTC 24
Peak memory 228100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299916832 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.299916832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3925127116
Short name T34
Test name
Test status
Simulation time 3292163972 ps
CPU time 45.42 seconds
Started Aug 25 04:10:26 AM UTC 24
Finished Aug 25 04:11:26 AM UTC 24
Peak memory 228704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392512711
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.3925127116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.924033991
Short name T30
Test name
Test status
Simulation time 1240827823 ps
CPU time 169.23 seconds
Started Aug 25 04:10:41 AM UTC 24
Finished Aug 25 04:13:51 AM UTC 24
Peak memory 257404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924033991 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.924033991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2021252610
Short name T99
Test name
Test status
Simulation time 2147753369 ps
CPU time 80 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:23:48 AM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021252610 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.2021252610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2388980194
Short name T149
Test name
Test status
Simulation time 2066228311 ps
CPU time 47.83 seconds
Started Aug 25 04:11:18 AM UTC 24
Finished Aug 25 04:12:07 AM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238898019
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.2388980194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3986260582
Short name T129
Test name
Test status
Simulation time 338555866 ps
CPU time 130.37 seconds
Started Aug 25 02:22:31 AM UTC 24
Finished Aug 25 02:24:45 AM UTC 24
Peak memory 223624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986260582 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.3986260582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1514303689
Short name T33
Test name
Test status
Simulation time 1643936084 ps
CPU time 9.7 seconds
Started Aug 25 04:10:31 AM UTC 24
Finished Aug 25 04:11:10 AM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514303689 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1514303689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1792796857
Short name T25
Test name
Test status
Simulation time 6512293968 ps
CPU time 114.15 seconds
Started Aug 25 04:12:22 AM UTC 24
Finished Aug 25 04:14:19 AM UTC 24
Peak memory 239068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1792796857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1792796857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2343542438
Short name T125
Test name
Test status
Simulation time 353155293 ps
CPU time 217.48 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:26:02 AM UTC 24
Peak memory 225968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343542438 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.2343542438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1866896037
Short name T22
Test name
Test status
Simulation time 1346425102 ps
CPU time 84.65 seconds
Started Aug 25 04:11:16 AM UTC 24
Finished Aug 25 04:12:43 AM UTC 24
Peak memory 232860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1866896037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1866896037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3616376498
Short name T84
Test name
Test status
Simulation time 249420709 ps
CPU time 11.84 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:31 AM UTC 24
Peak memory 221932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616376498 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3616376498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2562529545
Short name T127
Test name
Test status
Simulation time 691570186 ps
CPU time 234.83 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:26:08 AM UTC 24
Peak memory 229368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562529545 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.2562529545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.607926127
Short name T4
Test name
Test status
Simulation time 1502044644 ps
CPU time 17.26 seconds
Started Aug 25 04:10:18 AM UTC 24
Finished Aug 25 04:10:37 AM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607926127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.607926127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2412170953
Short name T74
Test name
Test status
Simulation time 1025447394 ps
CPU time 9.29 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:18 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412170953 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2412170953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3636262383
Short name T322
Test name
Test status
Simulation time 3501374901 ps
CPU time 324.42 seconds
Started Aug 25 04:11:09 AM UTC 24
Finished Aug 25 04:16:42 AM UTC 24
Peak memory 261536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636262383 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.3636262383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1728394181
Short name T132
Test name
Test status
Simulation time 705577244 ps
CPU time 240.85 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:26:18 AM UTC 24
Peak memory 227392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728394181 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.1728394181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1519132072
Short name T157
Test name
Test status
Simulation time 512713366 ps
CPU time 33.32 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:34 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151913207
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.1519132072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2211336916
Short name T3
Test name
Test status
Simulation time 1022203646 ps
CPU time 10.62 seconds
Started Aug 25 04:10:18 AM UTC 24
Finished Aug 25 04:10:31 AM UTC 24
Peak memory 228052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211336916 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2211336916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.923489750
Short name T24
Test name
Test status
Simulation time 14908345054 ps
CPU time 247.19 seconds
Started Aug 25 04:13:50 AM UTC 24
Finished Aug 25 04:18:01 AM UTC 24
Peak memory 246536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=923489750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.rom_ctrl_stress_all_with_rand_reset.923489750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3751153809
Short name T184
Test name
Test status
Simulation time 507024357 ps
CPU time 32.12 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:11:47 AM UTC 24
Peak memory 228592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751153809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3751153809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.4063047855
Short name T183
Test name
Test status
Simulation time 1326278561 ps
CPU time 30.07 seconds
Started Aug 25 04:11:09 AM UTC 24
Finished Aug 25 04:11:44 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063047855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4063047855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1414441225
Short name T386
Test name
Test status
Simulation time 167587950 ps
CPU time 7.82 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:27 AM UTC 24
Peak memory 221752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414441225 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.1414441225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3471915144
Short name T389
Test name
Test status
Simulation time 3527538114 ps
CPU time 12.07 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:31 AM UTC 24
Peak memory 221880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471915144 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.3471915144
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3857348229
Short name T385
Test name
Test status
Simulation time 4119558100 ps
CPU time 17.82 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:27 AM UTC 24
Peak memory 223864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857348229 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.3857348229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1608077601
Short name T390
Test name
Test status
Simulation time 1071765295 ps
CPU time 12.22 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:31 AM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1608077601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
om_ctrl_csr_mem_rw_with_rand_reset.1608077601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2403235108
Short name T374
Test name
Test status
Simulation time 251795493 ps
CPU time 9.91 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:19 AM UTC 24
Peak memory 221244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403235108 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.2403235108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2567204518
Short name T370
Test name
Test status
Simulation time 577501983 ps
CPU time 8.88 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:18 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567204518 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.2567204518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2070994684
Short name T446
Test name
Test status
Simulation time 5851593716 ps
CPU time 81.1 seconds
Started Aug 25 02:22:01 AM UTC 24
Finished Aug 25 02:23:27 AM UTC 24
Peak memory 225932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070994684 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.2070994684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2492905563
Short name T108
Test name
Test status
Simulation time 260659146 ps
CPU time 12.89 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:32 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492905563 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.2492905563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4142363459
Short name T376
Test name
Test status
Simulation time 987988904 ps
CPU time 14.41 seconds
Started Aug 25 02:22:01 AM UTC 24
Finished Aug 25 02:22:19 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142363459 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4142363459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4145346852
Short name T69
Test name
Test status
Simulation time 2332480205 ps
CPU time 105.27 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:23:55 AM UTC 24
Peak memory 223920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145346852 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.4145346852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4025846424
Short name T421
Test name
Test status
Simulation time 1006558832 ps
CPU time 22.49 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:46 AM UTC 24
Peak memory 223996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025846424 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.4025846424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1003312649
Short name T394
Test name
Test status
Simulation time 288814017 ps
CPU time 12.82 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:36 AM UTC 24
Peak memory 221948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003312649 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.1003312649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2418620254
Short name T402
Test name
Test status
Simulation time 2498078622 ps
CPU time 19.08 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:39 AM UTC 24
Peak memory 223928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418620254 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.2418620254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3401200282
Short name T396
Test name
Test status
Simulation time 356785958 ps
CPU time 12.21 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:37 AM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3401200282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
om_ctrl_csr_mem_rw_with_rand_reset.3401200282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2135987835
Short name T388
Test name
Test status
Simulation time 181011592 ps
CPU time 10.65 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:30 AM UTC 24
Peak memory 221756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135987835 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.2135987835
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.827337790
Short name T395
Test name
Test status
Simulation time 250531403 ps
CPU time 13.09 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:36 AM UTC 24
Peak memory 221672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827337790 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.827337790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.906450312
Short name T97
Test name
Test status
Simulation time 1384573069 ps
CPU time 50.29 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:23:10 AM UTC 24
Peak memory 223892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906450312 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.906450312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2271098656
Short name T393
Test name
Test status
Simulation time 518047954 ps
CPU time 11.48 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:36 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271098656 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.2271098656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.992376450
Short name T392
Test name
Test status
Simulation time 209826863 ps
CPU time 12.71 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:32 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992376450 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.992376450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1909681764
Short name T420
Test name
Test status
Simulation time 8950612142 ps
CPU time 18.74 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:46 AM UTC 24
Peak memory 228080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1909681764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rom_ctrl_csr_mem_rw_with_rand_reset.1909681764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1714274065
Short name T92
Test name
Test status
Simulation time 690838590 ps
CPU time 11.17 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:38 AM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714274065 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1714274065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4142586708
Short name T417
Test name
Test status
Simulation time 269906555 ps
CPU time 18.36 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:45 AM UTC 24
Peak memory 223984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142586708 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.4142586708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.140200904
Short name T415
Test name
Test status
Simulation time 719677680 ps
CPU time 17.96 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:45 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140200904 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.140200904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3589150318
Short name T134
Test name
Test status
Simulation time 1539168547 ps
CPU time 236.38 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:26:26 AM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589150318 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.3589150318
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3063896668
Short name T404
Test name
Test status
Simulation time 503633636 ps
CPU time 13.16 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:41 AM UTC 24
Peak memory 227932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3063896668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rom_ctrl_csr_mem_rw_with_rand_reset.3063896668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1320570261
Short name T93
Test name
Test status
Simulation time 995717400 ps
CPU time 12.82 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:40 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320570261 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1320570261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4096560828
Short name T101
Test name
Test status
Simulation time 1568220428 ps
CPU time 89.72 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:23:58 AM UTC 24
Peak memory 225936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096560828 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.4096560828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1506324615
Short name T405
Test name
Test status
Simulation time 852369181 ps
CPU time 13.39 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:41 AM UTC 24
Peak memory 221808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506324615 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.1506324615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3873527773
Short name T422
Test name
Test status
Simulation time 1898142475 ps
CPU time 19.1 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:46 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873527773 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3873527773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2855140982
Short name T137
Test name
Test status
Simulation time 1128708880 ps
CPU time 237.54 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:26:27 AM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855140982 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.2855140982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3295049096
Short name T409
Test name
Test status
Simulation time 346766621 ps
CPU time 12.51 seconds
Started Aug 25 02:22:28 AM UTC 24
Finished Aug 25 02:22:42 AM UTC 24
Peak memory 228080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3295049096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rom_ctrl_csr_mem_rw_with_rand_reset.3295049096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1010450944
Short name T95
Test name
Test status
Simulation time 496806243 ps
CPU time 13.38 seconds
Started Aug 25 02:22:28 AM UTC 24
Finished Aug 25 02:22:43 AM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010450944 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1010450944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1437414894
Short name T104
Test name
Test status
Simulation time 721128448 ps
CPU time 54.6 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:23:22 AM UTC 24
Peak memory 225772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437414894 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.1437414894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1295979681
Short name T424
Test name
Test status
Simulation time 179023023 ps
CPU time 17.58 seconds
Started Aug 25 02:22:28 AM UTC 24
Finished Aug 25 02:22:47 AM UTC 24
Peak memory 221808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295979681 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.1295979681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4243248788
Short name T416
Test name
Test status
Simulation time 250136098 ps
CPU time 17.55 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:45 AM UTC 24
Peak memory 228104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243248788 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4243248788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.151201185
Short name T455
Test name
Test status
Simulation time 401183220 ps
CPU time 241.48 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:26:32 AM UTC 24
Peak memory 225912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151201185 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.151201185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.315679257
Short name T414
Test name
Test status
Simulation time 707492412 ps
CPU time 12.75 seconds
Started Aug 25 02:22:30 AM UTC 24
Finished Aug 25 02:22:45 AM UTC 24
Peak memory 228088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=315679257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.r
om_ctrl_csr_mem_rw_with_rand_reset.315679257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4025222228
Short name T96
Test name
Test status
Simulation time 248454278 ps
CPU time 13.43 seconds
Started Aug 25 02:22:28 AM UTC 24
Finished Aug 25 02:22:43 AM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025222228 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4025222228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.80784794
Short name T447
Test name
Test status
Simulation time 1040455617 ps
CPU time 63.16 seconds
Started Aug 25 02:22:28 AM UTC 24
Finished Aug 25 02:23:33 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80784794 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.80784794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4248020349
Short name T412
Test name
Test status
Simulation time 2757208471 ps
CPU time 13.43 seconds
Started Aug 25 02:22:28 AM UTC 24
Finished Aug 25 02:22:43 AM UTC 24
Peak memory 221872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248020349 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.4248020349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.289727079
Short name T442
Test name
Test status
Simulation time 986437873 ps
CPU time 28.75 seconds
Started Aug 25 02:22:28 AM UTC 24
Finished Aug 25 02:22:58 AM UTC 24
Peak memory 228836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289727079 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.289727079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1385255043
Short name T128
Test name
Test status
Simulation time 325878789 ps
CPU time 121.57 seconds
Started Aug 25 02:22:28 AM UTC 24
Finished Aug 25 02:24:32 AM UTC 24
Peak memory 225912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385255043 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.1385255043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3054842539
Short name T423
Test name
Test status
Simulation time 180848745 ps
CPU time 13.09 seconds
Started Aug 25 02:22:32 AM UTC 24
Finished Aug 25 02:22:47 AM UTC 24
Peak memory 228144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3054842539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rom_ctrl_csr_mem_rw_with_rand_reset.3054842539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2134390832
Short name T411
Test name
Test status
Simulation time 169778888 ps
CPU time 10.5 seconds
Started Aug 25 02:22:31 AM UTC 24
Finished Aug 25 02:22:43 AM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134390832 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2134390832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3612824231
Short name T102
Test name
Test status
Simulation time 6090903783 ps
CPU time 88.18 seconds
Started Aug 25 02:22:30 AM UTC 24
Finished Aug 25 02:24:01 AM UTC 24
Peak memory 228176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612824231 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.3612824231
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3966378228
Short name T418
Test name
Test status
Simulation time 720903561 ps
CPU time 11.7 seconds
Started Aug 25 02:22:32 AM UTC 24
Finished Aug 25 02:22:45 AM UTC 24
Peak memory 221936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966378228 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.3966378228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.107595631
Short name T429
Test name
Test status
Simulation time 338794147 ps
CPU time 18.64 seconds
Started Aug 25 02:22:31 AM UTC 24
Finished Aug 25 02:22:51 AM UTC 24
Peak memory 227628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107595631 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.107595631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3434826586
Short name T426
Test name
Test status
Simulation time 904576432 ps
CPU time 14.61 seconds
Started Aug 25 02:22:34 AM UTC 24
Finished Aug 25 02:22:50 AM UTC 24
Peak memory 225912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3434826586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rom_ctrl_csr_mem_rw_with_rand_reset.3434826586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1685840196
Short name T419
Test name
Test status
Simulation time 332971660 ps
CPU time 12.03 seconds
Started Aug 25 02:22:33 AM UTC 24
Finished Aug 25 02:22:46 AM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685840196 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1685840196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.956977330
Short name T453
Test name
Test status
Simulation time 6090503257 ps
CPU time 96.57 seconds
Started Aug 25 02:22:32 AM UTC 24
Finished Aug 25 02:24:12 AM UTC 24
Peak memory 228048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956977330 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.956977330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1820174023
Short name T427
Test name
Test status
Simulation time 334861503 ps
CPU time 16.49 seconds
Started Aug 25 02:22:33 AM UTC 24
Finished Aug 25 02:22:50 AM UTC 24
Peak memory 223856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820174023 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.1820174023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2925122850
Short name T432
Test name
Test status
Simulation time 174678428 ps
CPU time 18.43 seconds
Started Aug 25 02:22:32 AM UTC 24
Finished Aug 25 02:22:52 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925122850 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2925122850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.967609447
Short name T131
Test name
Test status
Simulation time 1246650599 ps
CPU time 122.86 seconds
Started Aug 25 02:22:32 AM UTC 24
Finished Aug 25 02:24:38 AM UTC 24
Peak memory 223992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967609447 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.967609447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3817627157
Short name T431
Test name
Test status
Simulation time 834812314 ps
CPU time 13.53 seconds
Started Aug 25 02:22:37 AM UTC 24
Finished Aug 25 02:22:52 AM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3817627157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rom_ctrl_csr_mem_rw_with_rand_reset.3817627157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.279655612
Short name T425
Test name
Test status
Simulation time 720334608 ps
CPU time 11.47 seconds
Started Aug 25 02:22:36 AM UTC 24
Finished Aug 25 02:22:49 AM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279655612 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.279655612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1228146828
Short name T454
Test name
Test status
Simulation time 6663707909 ps
CPU time 128.82 seconds
Started Aug 25 02:22:34 AM UTC 24
Finished Aug 25 02:24:45 AM UTC 24
Peak memory 226000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228146828 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.1228146828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2280762676
Short name T441
Test name
Test status
Simulation time 274497189 ps
CPU time 18.87 seconds
Started Aug 25 02:22:37 AM UTC 24
Finished Aug 25 02:22:57 AM UTC 24
Peak memory 223856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280762676 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.2280762676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3762644024
Short name T437
Test name
Test status
Simulation time 990091820 ps
CPU time 18.18 seconds
Started Aug 25 02:22:35 AM UTC 24
Finished Aug 25 02:22:55 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762644024 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3762644024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.624406255
Short name T124
Test name
Test status
Simulation time 324383104 ps
CPU time 131.48 seconds
Started Aug 25 02:22:35 AM UTC 24
Finished Aug 25 02:24:50 AM UTC 24
Peak memory 223864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624406255 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.624406255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2501939317
Short name T430
Test name
Test status
Simulation time 185392555 ps
CPU time 11.61 seconds
Started Aug 25 02:22:38 AM UTC 24
Finished Aug 25 02:22:51 AM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2501939317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rom_ctrl_csr_mem_rw_with_rand_reset.2501939317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2682394996
Short name T433
Test name
Test status
Simulation time 1764578271 ps
CPU time 13.23 seconds
Started Aug 25 02:22:38 AM UTC 24
Finished Aug 25 02:22:53 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682394996 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2682394996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2729758058
Short name T452
Test name
Test status
Simulation time 1313570548 ps
CPU time 79.06 seconds
Started Aug 25 02:22:37 AM UTC 24
Finished Aug 25 02:23:59 AM UTC 24
Peak memory 225936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729758058 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.2729758058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.546090714
Short name T435
Test name
Test status
Simulation time 507203667 ps
CPU time 14.45 seconds
Started Aug 25 02:22:38 AM UTC 24
Finished Aug 25 02:22:54 AM UTC 24
Peak memory 221820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546090714 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.546090714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2299284366
Short name T443
Test name
Test status
Simulation time 249657007 ps
CPU time 20.17 seconds
Started Aug 25 02:22:38 AM UTC 24
Finished Aug 25 02:23:00 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299284366 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2299284366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1824328805
Short name T135
Test name
Test status
Simulation time 267055306 ps
CPU time 136.01 seconds
Started Aug 25 02:22:38 AM UTC 24
Finished Aug 25 02:24:57 AM UTC 24
Peak memory 225912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824328805 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.1824328805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4288431288
Short name T439
Test name
Test status
Simulation time 263973393 ps
CPU time 14.21 seconds
Started Aug 25 02:22:40 AM UTC 24
Finished Aug 25 02:22:56 AM UTC 24
Peak memory 225912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4288431288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rom_ctrl_csr_mem_rw_with_rand_reset.4288431288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1806005990
Short name T428
Test name
Test status
Simulation time 3294286227 ps
CPU time 10.51 seconds
Started Aug 25 02:22:39 AM UTC 24
Finished Aug 25 02:22:51 AM UTC 24
Peak memory 221876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806005990 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1806005990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1439505694
Short name T448
Test name
Test status
Simulation time 1351415193 ps
CPU time 57.61 seconds
Started Aug 25 02:22:38 AM UTC 24
Finished Aug 25 02:23:38 AM UTC 24
Peak memory 226064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439505694 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.1439505694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1544329053
Short name T438
Test name
Test status
Simulation time 1121309883 ps
CPU time 13.24 seconds
Started Aug 25 02:22:40 AM UTC 24
Finished Aug 25 02:22:55 AM UTC 24
Peak memory 221872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544329053 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.1544329053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.105011911
Short name T440
Test name
Test status
Simulation time 663282821 ps
CPU time 15.32 seconds
Started Aug 25 02:22:39 AM UTC 24
Finished Aug 25 02:22:56 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105011911 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.105011911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4246391852
Short name T456
Test name
Test status
Simulation time 1907796074 ps
CPU time 239.92 seconds
Started Aug 25 02:22:39 AM UTC 24
Finished Aug 25 02:26:43 AM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246391852 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.4246391852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1584157613
Short name T434
Test name
Test status
Simulation time 183202739 ps
CPU time 9.87 seconds
Started Aug 25 02:22:43 AM UTC 24
Finished Aug 25 02:22:54 AM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1584157613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rom_ctrl_csr_mem_rw_with_rand_reset.1584157613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.340104175
Short name T436
Test name
Test status
Simulation time 687587049 ps
CPU time 11.72 seconds
Started Aug 25 02:22:42 AM UTC 24
Finished Aug 25 02:22:55 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340104175 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.340104175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3411225365
Short name T451
Test name
Test status
Simulation time 14488135319 ps
CPU time 62.72 seconds
Started Aug 25 02:22:42 AM UTC 24
Finished Aug 25 02:23:46 AM UTC 24
Peak memory 226000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411225365 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.3411225365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.407849048
Short name T445
Test name
Test status
Simulation time 5176506008 ps
CPU time 18.42 seconds
Started Aug 25 02:22:42 AM UTC 24
Finished Aug 25 02:23:01 AM UTC 24
Peak memory 223924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407849048 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.407849048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.572927297
Short name T444
Test name
Test status
Simulation time 1501060107 ps
CPU time 17.73 seconds
Started Aug 25 02:22:42 AM UTC 24
Finished Aug 25 02:23:01 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572927297 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.572927297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.349163208
Short name T130
Test name
Test status
Simulation time 2166847729 ps
CPU time 199.24 seconds
Started Aug 25 02:22:42 AM UTC 24
Finished Aug 25 02:26:04 AM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349163208 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.349163208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4011719475
Short name T72
Test name
Test status
Simulation time 338804607 ps
CPU time 7.92 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:18 AM UTC 24
Peak memory 221944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011719475 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.4011719475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1464221644
Short name T375
Test name
Test status
Simulation time 950722794 ps
CPU time 8.91 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:19 AM UTC 24
Peak memory 221848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464221644 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.1464221644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1845596205
Short name T114
Test name
Test status
Simulation time 254691895 ps
CPU time 12.38 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:22 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845596205 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.1845596205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3776686385
Short name T378
Test name
Test status
Simulation time 1003474479 ps
CPU time 9.43 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:20 AM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3776686385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
om_ctrl_csr_mem_rw_with_rand_reset.3776686385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3206097452
Short name T112
Test name
Test status
Simulation time 323655715 ps
CPU time 8.56 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:19 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206097452 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3206097452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.24751385
Short name T372
Test name
Test status
Simulation time 1078767894 ps
CPU time 8.57 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:18 AM UTC 24
Peak memory 221612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24751385 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.24751385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1982734932
Short name T373
Test name
Test status
Simulation time 485079691 ps
CPU time 8.84 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:19 AM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982734932 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.1982734932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4269716961
Short name T103
Test name
Test status
Simulation time 6089278540 ps
CPU time 71.24 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:23:21 AM UTC 24
Peak memory 226004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269716961 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.4269716961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1985126970
Short name T106
Test name
Test status
Simulation time 4952344768 ps
CPU time 9.48 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:19 AM UTC 24
Peak memory 221932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985126970 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.1985126970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3627382181
Short name T379
Test name
Test status
Simulation time 551117176 ps
CPU time 10.37 seconds
Started Aug 25 02:22:05 AM UTC 24
Finished Aug 25 02:22:20 AM UTC 24
Peak memory 228184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627382181 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3627382181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.124331864
Short name T68
Test name
Test status
Simulation time 635322785 ps
CPU time 101.87 seconds
Started Aug 25 02:22:08 AM UTC 24
Finished Aug 25 02:23:53 AM UTC 24
Peak memory 223860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124331864 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.124331864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3307484815
Short name T78
Test name
Test status
Simulation time 170701507 ps
CPU time 9.34 seconds
Started Aug 25 02:22:11 AM UTC 24
Finished Aug 25 02:22:24 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307484815 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.3307484815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.258541114
Short name T73
Test name
Test status
Simulation time 922402594 ps
CPU time 7.78 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:18 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258541114 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.258541114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1219614297
Short name T80
Test name
Test status
Simulation time 704561496 ps
CPU time 15.41 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:26 AM UTC 24
Peak memory 223864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219614297 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.1219614297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.173070373
Short name T384
Test name
Test status
Simulation time 356612536 ps
CPU time 11.73 seconds
Started Aug 25 02:22:11 AM UTC 24
Finished Aug 25 02:22:27 AM UTC 24
Peak memory 229360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=173070373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ro
m_ctrl_csr_mem_rw_with_rand_reset.173070373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.203766523
Short name T113
Test name
Test status
Simulation time 252570073 ps
CPU time 8.99 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:19 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203766523 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.203766523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1773190943
Short name T377
Test name
Test status
Simulation time 1185426493 ps
CPU time 9.15 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:19 AM UTC 24
Peak memory 221752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773190943 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.1773190943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2607742067
Short name T371
Test name
Test status
Simulation time 174619789 ps
CPU time 7.94 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:18 AM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607742067 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.2607742067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.907990750
Short name T140
Test name
Test status
Simulation time 2746989897 ps
CPU time 42.02 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:52 AM UTC 24
Peak memory 226008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907990750 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.907990750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3804012971
Short name T79
Test name
Test status
Simulation time 174402480 ps
CPU time 9.77 seconds
Started Aug 25 02:22:11 AM UTC 24
Finished Aug 25 02:22:25 AM UTC 24
Peak memory 221800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804012971 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.3804012971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3988096063
Short name T381
Test name
Test status
Simulation time 313129801 ps
CPU time 13.52 seconds
Started Aug 25 02:22:09 AM UTC 24
Finished Aug 25 02:22:24 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988096063 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3988096063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.832597918
Short name T82
Test name
Test status
Simulation time 3926835589 ps
CPU time 16 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:22:31 AM UTC 24
Peak memory 223860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832597918 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.832597918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1344762642
Short name T116
Test name
Test status
Simulation time 260315630 ps
CPU time 9.82 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:22:24 AM UTC 24
Peak memory 221892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344762642 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.1344762642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2264210918
Short name T86
Test name
Test status
Simulation time 171948766 ps
CPU time 19.11 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:22:34 AM UTC 24
Peak memory 223928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264210918 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.2264210918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4043458361
Short name T383
Test name
Test status
Simulation time 266420554 ps
CPU time 11.77 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:22:26 AM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4043458361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
om_ctrl_csr_mem_rw_with_rand_reset.4043458361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1633268555
Short name T115
Test name
Test status
Simulation time 993044412 ps
CPU time 9.29 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:22:24 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633268555 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1633268555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.591873795
Short name T380
Test name
Test status
Simulation time 687615651 ps
CPU time 7.57 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:22:22 AM UTC 24
Peak memory 221680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591873795 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.591873795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1884917805
Short name T382
Test name
Test status
Simulation time 260318260 ps
CPU time 9.79 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:22:24 AM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884917805 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.1884917805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1626254659
Short name T98
Test name
Test status
Simulation time 1594760046 ps
CPU time 91.16 seconds
Started Aug 25 02:22:11 AM UTC 24
Finished Aug 25 02:23:47 AM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626254659 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.1626254659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2757086489
Short name T81
Test name
Test status
Simulation time 338566691 ps
CPU time 12.46 seconds
Started Aug 25 02:22:13 AM UTC 24
Finished Aug 25 02:22:27 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757086489 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.2757086489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.745198993
Short name T387
Test name
Test status
Simulation time 346229300 ps
CPU time 13.64 seconds
Started Aug 25 02:22:11 AM UTC 24
Finished Aug 25 02:22:29 AM UTC 24
Peak memory 228112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745198993 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.745198993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.192599955
Short name T391
Test name
Test status
Simulation time 186540193 ps
CPU time 9.73 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:32 AM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=192599955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ro
m_ctrl_csr_mem_rw_with_rand_reset.192599955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3220402755
Short name T85
Test name
Test status
Simulation time 780379317 ps
CPU time 13.4 seconds
Started Aug 25 02:22:18 AM UTC 24
Finished Aug 25 02:22:33 AM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220402755 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3220402755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.187984625
Short name T141
Test name
Test status
Simulation time 687883328 ps
CPU time 48.03 seconds
Started Aug 25 02:22:14 AM UTC 24
Finished Aug 25 02:23:04 AM UTC 24
Peak memory 225928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187984625 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.187984625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1448107815
Short name T110
Test name
Test status
Simulation time 508021007 ps
CPU time 13.38 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:35 AM UTC 24
Peak memory 223636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448107815 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.1448107815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1849932204
Short name T398
Test name
Test status
Simulation time 691079113 ps
CPU time 16.62 seconds
Started Aug 25 02:22:18 AM UTC 24
Finished Aug 25 02:22:37 AM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849932204 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1849932204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.505596531
Short name T70
Test name
Test status
Simulation time 3922413059 ps
CPU time 116.71 seconds
Started Aug 25 02:22:18 AM UTC 24
Finished Aug 25 02:24:17 AM UTC 24
Peak memory 225972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505596531 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.505596531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.177331989
Short name T401
Test name
Test status
Simulation time 1153793843 ps
CPU time 16.1 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:38 AM UTC 24
Peak memory 228256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=177331989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ro
m_ctrl_csr_mem_rw_with_rand_reset.177331989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.60311192
Short name T87
Test name
Test status
Simulation time 1496994726 ps
CPU time 11.82 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:34 AM UTC 24
Peak memory 222000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60311192 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.60311192
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3576683777
Short name T100
Test name
Test status
Simulation time 3175211573 ps
CPU time 93.21 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:23:56 AM UTC 24
Peak memory 226004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576683777 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.3576683777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4000306297
Short name T403
Test name
Test status
Simulation time 721091825 ps
CPU time 17.03 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:39 AM UTC 24
Peak memory 223848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000306297 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.4000306297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3806130338
Short name T410
Test name
Test status
Simulation time 172619172 ps
CPU time 20.03 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:42 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806130338 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3806130338
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3392392773
Short name T126
Test name
Test status
Simulation time 965699121 ps
CPU time 114.8 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:24:18 AM UTC 24
Peak memory 225904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392392773 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.3392392773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.250547459
Short name T397
Test name
Test status
Simulation time 1807888655 ps
CPU time 14.35 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:37 AM UTC 24
Peak memory 227912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=250547459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ro
m_ctrl_csr_mem_rw_with_rand_reset.250547459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1033884165
Short name T83
Test name
Test status
Simulation time 635765938 ps
CPU time 8.41 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:31 AM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033884165 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1033884165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3092352315
Short name T450
Test name
Test status
Simulation time 1055242928 ps
CPU time 80.57 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:23:44 AM UTC 24
Peak memory 225944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092352315 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.3092352315
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2164462399
Short name T109
Test name
Test status
Simulation time 339020408 ps
CPU time 10.44 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:33 AM UTC 24
Peak memory 221804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164462399 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.2164462399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4086691436
Short name T400
Test name
Test status
Simulation time 171037508 ps
CPU time 14.86 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:37 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086691436 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4086691436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.862080537
Short name T399
Test name
Test status
Simulation time 259275275 ps
CPU time 14.16 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:37 AM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=862080537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ro
m_ctrl_csr_mem_rw_with_rand_reset.862080537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4129739023
Short name T107
Test name
Test status
Simulation time 171312165 ps
CPU time 8.48 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:31 AM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129739023 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4129739023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4062764852
Short name T105
Test name
Test status
Simulation time 1554642132 ps
CPU time 91.94 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:23:56 AM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062764852 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.4062764852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2682676549
Short name T111
Test name
Test status
Simulation time 690950630 ps
CPU time 12.93 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:36 AM UTC 24
Peak memory 221800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682676549 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.2682676549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2376822304
Short name T408
Test name
Test status
Simulation time 252883993 ps
CPU time 19.07 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:22:42 AM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376822304 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2376822304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.528112672
Short name T136
Test name
Test status
Simulation time 491763727 ps
CPU time 217.07 seconds
Started Aug 25 02:22:21 AM UTC 24
Finished Aug 25 02:26:02 AM UTC 24
Peak memory 225908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528112672 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.528112672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1305725620
Short name T407
Test name
Test status
Simulation time 542128321 ps
CPU time 14.18 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:41 AM UTC 24
Peak memory 227656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1305725620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
om_ctrl_csr_mem_rw_with_rand_reset.1305725620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2164862732
Short name T94
Test name
Test status
Simulation time 250175609 ps
CPU time 13.51 seconds
Started Aug 25 02:22:25 AM UTC 24
Finished Aug 25 02:22:40 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164862732 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2164862732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1355199293
Short name T449
Test name
Test status
Simulation time 1039910188 ps
CPU time 79.21 seconds
Started Aug 25 02:22:22 AM UTC 24
Finished Aug 25 02:23:43 AM UTC 24
Peak memory 225940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355199293 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.1355199293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.816342032
Short name T413
Test name
Test status
Simulation time 1022247983 ps
CPU time 17.59 seconds
Started Aug 25 02:22:26 AM UTC 24
Finished Aug 25 02:22:44 AM UTC 24
Peak memory 223868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816342032 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.816342032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3876061712
Short name T406
Test name
Test status
Simulation time 663625352 ps
CPU time 17.8 seconds
Started Aug 25 02:22:22 AM UTC 24
Finished Aug 25 02:22:41 AM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876061712 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3876061712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1147685267
Short name T133
Test name
Test status
Simulation time 1421408660 ps
CPU time 240.91 seconds
Started Aug 25 02:22:22 AM UTC 24
Finished Aug 25 02:26:27 AM UTC 24
Peak memory 226104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147685267 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.1147685267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4206235139
Short name T1
Test name
Test status
Simulation time 1646345715 ps
CPU time 7.27 seconds
Started Aug 25 04:10:18 AM UTC 24
Finished Aug 25 04:10:27 AM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206235139 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4206235139
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1036285170
Short name T29
Test name
Test status
Simulation time 354293788 ps
CPU time 149.33 seconds
Started Aug 25 04:10:18 AM UTC 24
Finished Aug 25 04:12:50 AM UTC 24
Peak memory 258444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036285170 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1036285170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.922824126
Short name T2
Test name
Test status
Simulation time 698411678 ps
CPU time 9.64 seconds
Started Aug 25 04:10:18 AM UTC 24
Finished Aug 25 04:10:30 AM UTC 24
Peak memory 223216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922824126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64k
B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.922824126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3438078128
Short name T5
Test name
Test status
Simulation time 688056165 ps
CPU time 7.23 seconds
Started Aug 25 04:10:26 AM UTC 24
Finished Aug 25 04:10:38 AM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438078128 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3438078128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3378714744
Short name T7
Test name
Test status
Simulation time 310937639 ps
CPU time 9.32 seconds
Started Aug 25 04:10:22 AM UTC 24
Finished Aug 25 04:10:39 AM UTC 24
Peak memory 228392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378714744 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3378714744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.4207456957
Short name T40
Test name
Test status
Simulation time 1083425268 ps
CPU time 317.02 seconds
Started Aug 25 04:10:25 AM UTC 24
Finished Aug 25 04:16:01 AM UTC 24
Peak memory 259668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207456957 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4207456957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.67218398
Short name T152
Test name
Test status
Simulation time 250607845 ps
CPU time 13.86 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:11:28 AM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67218398 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.67218398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2414848241
Short name T334
Test name
Test status
Simulation time 3590655493 ps
CPU time 380.9 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:17:39 AM UTC 24
Peak memory 246176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414848241 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.2414848241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3462943311
Short name T144
Test name
Test status
Simulation time 187426788 ps
CPU time 15.44 seconds
Started Aug 25 04:11:05 AM UTC 24
Finished Aug 25 04:11:31 AM UTC 24
Peak memory 228328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462943311 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3462943311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2674699832
Short name T197
Test name
Test status
Simulation time 3942910948 ps
CPU time 52.54 seconds
Started Aug 25 04:11:01 AM UTC 24
Finished Aug 25 04:12:03 AM UTC 24
Peak memory 228628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267469983
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.2674699832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1825702712
Short name T317
Test name
Test status
Simulation time 24954090905 ps
CPU time 301.04 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:16:19 AM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1825702712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1825702712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1539597942
Short name T153
Test name
Test status
Simulation time 993608904 ps
CPU time 14.35 seconds
Started Aug 25 04:11:09 AM UTC 24
Finished Aug 25 04:11:25 AM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539597942 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1539597942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2215561360
Short name T55
Test name
Test status
Simulation time 12158421304 ps
CPU time 314.8 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:16:34 AM UTC 24
Peak memory 259480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215561360 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.2215561360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1270599156
Short name T32
Test name
Test status
Simulation time 5500643840 ps
CPU time 30.4 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:11:46 AM UTC 24
Peak memory 228496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270599156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1270599156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2739502217
Short name T313
Test name
Test status
Simulation time 20583690445 ps
CPU time 298.69 seconds
Started Aug 25 04:11:07 AM UTC 24
Finished Aug 25 04:16:12 AM UTC 24
Peak memory 241180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2739502217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2739502217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.4052279779
Short name T175
Test name
Test status
Simulation time 4109102993 ps
CPU time 13.58 seconds
Started Aug 25 04:11:10 AM UTC 24
Finished Aug 25 04:11:28 AM UTC 24
Peak memory 227840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052279779 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4052279779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2440243756
Short name T119
Test name
Test status
Simulation time 1071774427 ps
CPU time 17.9 seconds
Started Aug 25 04:11:09 AM UTC 24
Finished Aug 25 04:11:29 AM UTC 24
Peak memory 228244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440243756 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2440243756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2195693576
Short name T90
Test name
Test status
Simulation time 2100492349 ps
CPU time 38.34 seconds
Started Aug 25 04:11:09 AM UTC 24
Finished Aug 25 04:11:49 AM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219569357
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.2195693576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2990488984
Short name T297
Test name
Test status
Simulation time 6452912754 ps
CPU time 255.63 seconds
Started Aug 25 04:11:10 AM UTC 24
Finished Aug 25 04:15:29 AM UTC 24
Peak memory 246548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2990488984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2990488984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.277707770
Short name T156
Test name
Test status
Simulation time 992846714 ps
CPU time 14.53 seconds
Started Aug 25 04:11:12 AM UTC 24
Finished Aug 25 04:11:31 AM UTC 24
Peak memory 228136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277707770 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.277707770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3404414267
Short name T339
Test name
Test status
Simulation time 12357386721 ps
CPU time 412.25 seconds
Started Aug 25 04:11:11 AM UTC 24
Finished Aug 25 04:18:12 AM UTC 24
Peak memory 257432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404414267 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.3404414267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3593008044
Short name T187
Test name
Test status
Simulation time 1973135027 ps
CPU time 34.09 seconds
Started Aug 25 04:11:11 AM UTC 24
Finished Aug 25 04:11:50 AM UTC 24
Peak memory 228080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593008044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3593008044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.3072661533
Short name T121
Test name
Test status
Simulation time 528581714 ps
CPU time 16.5 seconds
Started Aug 25 04:11:10 AM UTC 24
Finished Aug 25 04:11:30 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072661533 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3072661533
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2243543877
Short name T158
Test name
Test status
Simulation time 1452198613 ps
CPU time 37.24 seconds
Started Aug 25 04:11:10 AM UTC 24
Finished Aug 25 04:11:52 AM UTC 24
Peak memory 227632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224354387
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.2243543877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.88254309
Short name T302
Test name
Test status
Simulation time 16636266130 ps
CPU time 261.19 seconds
Started Aug 25 04:11:12 AM UTC 24
Finished Aug 25 04:15:41 AM UTC 24
Peak memory 246356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=88254309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 13.rom_ctrl_stress_all_with_rand_reset.88254309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1317550437
Short name T155
Test name
Test status
Simulation time 510056377 ps
CPU time 14.06 seconds
Started Aug 25 04:11:16 AM UTC 24
Finished Aug 25 04:11:32 AM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317550437 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1317550437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.644769450
Short name T336
Test name
Test status
Simulation time 9116461647 ps
CPU time 384.02 seconds
Started Aug 25 04:11:13 AM UTC 24
Finished Aug 25 04:17:43 AM UTC 24
Peak memory 257288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644769450 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.644769450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.927855589
Short name T170
Test name
Test status
Simulation time 4515151011 ps
CPU time 34.95 seconds
Started Aug 25 04:11:16 AM UTC 24
Finished Aug 25 04:11:53 AM UTC 24
Peak memory 228764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927855589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.927855589
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.510141037
Short name T120
Test name
Test status
Simulation time 348083265 ps
CPU time 15.21 seconds
Started Aug 25 04:11:13 AM UTC 24
Finished Aug 25 04:11:30 AM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510141037 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.510141037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2792365950
Short name T167
Test name
Test status
Simulation time 1115238572 ps
CPU time 26.82 seconds
Started Aug 25 04:11:13 AM UTC 24
Finished Aug 25 04:11:41 AM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279236595
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.2792365950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.306989644
Short name T164
Test name
Test status
Simulation time 989222172 ps
CPU time 13.94 seconds
Started Aug 25 04:11:23 AM UTC 24
Finished Aug 25 04:11:38 AM UTC 24
Peak memory 227968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306989644 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.306989644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1316859163
Short name T28
Test name
Test status
Simulation time 12046979985 ps
CPU time 227.33 seconds
Started Aug 25 04:11:20 AM UTC 24
Finished Aug 25 04:15:11 AM UTC 24
Peak memory 257440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316859163 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.1316859163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1330053180
Short name T185
Test name
Test status
Simulation time 332568420 ps
CPU time 26.22 seconds
Started Aug 25 04:11:20 AM UTC 24
Finished Aug 25 04:11:47 AM UTC 24
Peak memory 228112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330053180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1330053180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.862067756
Short name T177
Test name
Test status
Simulation time 183049908 ps
CPU time 15.15 seconds
Started Aug 25 04:11:19 AM UTC 24
Finished Aug 25 04:11:35 AM UTC 24
Peak memory 228220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862067756 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.862067756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.4254479302
Short name T245
Test name
Test status
Simulation time 12041581485 ps
CPU time 137.23 seconds
Started Aug 25 04:11:23 AM UTC 24
Finished Aug 25 04:13:43 AM UTC 24
Peak memory 239076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4254479302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.4254479302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.530975082
Short name T179
Test name
Test status
Simulation time 260869256 ps
CPU time 12.47 seconds
Started Aug 25 04:11:26 AM UTC 24
Finished Aug 25 04:11:40 AM UTC 24
Peak memory 227476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530975082 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.530975082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.195788326
Short name T355
Test name
Test status
Simulation time 18496706575 ps
CPU time 523.59 seconds
Started Aug 25 04:11:24 AM UTC 24
Finished Aug 25 04:20:15 AM UTC 24
Peak memory 257332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195788326 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.195788326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.4240667048
Short name T191
Test name
Test status
Simulation time 346508327 ps
CPU time 29.68 seconds
Started Aug 25 04:11:24 AM UTC 24
Finished Aug 25 04:11:55 AM UTC 24
Peak memory 228216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240667048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4240667048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3375506104
Short name T182
Test name
Test status
Simulation time 268147762 ps
CPU time 17.2 seconds
Started Aug 25 04:11:24 AM UTC 24
Finished Aug 25 04:11:42 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375506104 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3375506104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3547940448
Short name T150
Test name
Test status
Simulation time 1397283969 ps
CPU time 18.17 seconds
Started Aug 25 04:11:24 AM UTC 24
Finished Aug 25 04:11:43 AM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354794044
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.3547940448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2748314332
Short name T281
Test name
Test status
Simulation time 2861570089 ps
CPU time 196.63 seconds
Started Aug 25 04:11:26 AM UTC 24
Finished Aug 25 04:14:46 AM UTC 24
Peak memory 234972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2748314332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2748314332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2145698572
Short name T146
Test name
Test status
Simulation time 249184370 ps
CPU time 13.58 seconds
Started Aug 25 04:11:30 AM UTC 24
Finished Aug 25 04:11:45 AM UTC 24
Peak memory 227784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145698572 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2145698572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.842444281
Short name T330
Test name
Test status
Simulation time 4356618181 ps
CPU time 333.28 seconds
Started Aug 25 04:11:28 AM UTC 24
Finished Aug 25 04:17:07 AM UTC 24
Peak memory 258672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842444281 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.842444281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.593054772
Short name T195
Test name
Test status
Simulation time 3295604316 ps
CPU time 31.65 seconds
Started Aug 25 04:11:28 AM UTC 24
Finished Aug 25 04:12:01 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593054772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.593054772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2293810939
Short name T180
Test name
Test status
Simulation time 516713483 ps
CPU time 12.83 seconds
Started Aug 25 04:11:26 AM UTC 24
Finished Aug 25 04:11:40 AM UTC 24
Peak memory 228096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293810939 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2293810939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3062646432
Short name T162
Test name
Test status
Simulation time 1065029014 ps
CPU time 31.15 seconds
Started Aug 25 04:11:26 AM UTC 24
Finished Aug 25 04:11:59 AM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306264643
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.3062646432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2625011930
Short name T306
Test name
Test status
Simulation time 3329895970 ps
CPU time 261.92 seconds
Started Aug 25 04:11:28 AM UTC 24
Finished Aug 25 04:15:55 AM UTC 24
Peak memory 235164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2625011930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2625011930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1965517864
Short name T18
Test name
Test status
Simulation time 347264974 ps
CPU time 11.86 seconds
Started Aug 25 04:11:33 AM UTC 24
Finished Aug 25 04:11:46 AM UTC 24
Peak memory 227756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965517864 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1965517864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1754763303
Short name T362
Test name
Test status
Simulation time 22230974590 ps
CPU time 592.9 seconds
Started Aug 25 04:11:30 AM UTC 24
Finished Aug 25 04:21:32 AM UTC 24
Peak memory 261556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754763303 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.1754763303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2353384635
Short name T200
Test name
Test status
Simulation time 516487132 ps
CPU time 33.27 seconds
Started Aug 25 04:11:30 AM UTC 24
Finished Aug 25 04:12:05 AM UTC 24
Peak memory 228096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353384635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2353384635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1964366524
Short name T192
Test name
Test status
Simulation time 5497760547 ps
CPU time 24.14 seconds
Started Aug 25 04:11:30 AM UTC 24
Finished Aug 25 04:11:56 AM UTC 24
Peak memory 228632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964366524 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1964366524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3622751853
Short name T194
Test name
Test status
Simulation time 520215440 ps
CPU time 29.35 seconds
Started Aug 25 04:11:30 AM UTC 24
Finished Aug 25 04:12:01 AM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362275185
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.3622751853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2049876988
Short name T58
Test name
Test status
Simulation time 22704027458 ps
CPU time 248.39 seconds
Started Aug 25 04:11:31 AM UTC 24
Finished Aug 25 04:15:43 AM UTC 24
Peak memory 236016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2049876988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2049876988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3476842033
Short name T168
Test name
Test status
Simulation time 261101409 ps
CPU time 14.15 seconds
Started Aug 25 04:11:36 AM UTC 24
Finished Aug 25 04:11:51 AM UTC 24
Peak memory 227968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476842033 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3476842033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3028892804
Short name T354
Test name
Test status
Simulation time 6803271545 ps
CPU time 511.49 seconds
Started Aug 25 04:11:33 AM UTC 24
Finished Aug 25 04:20:13 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028892804 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.3028892804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.340414308
Short name T196
Test name
Test status
Simulation time 332433017 ps
CPU time 27.26 seconds
Started Aug 25 04:11:33 AM UTC 24
Finished Aug 25 04:12:01 AM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340414308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.340414308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.441001212
Short name T189
Test name
Test status
Simulation time 1022224098 ps
CPU time 18.95 seconds
Started Aug 25 04:11:33 AM UTC 24
Finished Aug 25 04:11:53 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441001212 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.441001212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2483028540
Short name T161
Test name
Test status
Simulation time 510480445 ps
CPU time 47.54 seconds
Started Aug 25 04:11:33 AM UTC 24
Finished Aug 25 04:12:22 AM UTC 24
Peak memory 228660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248302854
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.2483028540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.288862629
Short name T21
Test name
Test status
Simulation time 970054775 ps
CPU time 61.03 seconds
Started Aug 25 04:11:33 AM UTC 24
Finished Aug 25 04:12:36 AM UTC 24
Peak memory 233052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=288862629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.rom_ctrl_stress_all_with_rand_reset.288862629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3428510675
Short name T342
Test name
Test status
Simulation time 9746719769 ps
CPU time 464.79 seconds
Started Aug 25 04:10:27 AM UTC 24
Finished Aug 25 04:18:20 AM UTC 24
Peak memory 259464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428510675 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.3428510675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2434872460
Short name T6
Test name
Test status
Simulation time 376736950 ps
CPU time 9.42 seconds
Started Aug 25 04:10:27 AM UTC 24
Finished Aug 25 04:10:39 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434872460 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2434872460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2104136512
Short name T31
Test name
Test status
Simulation time 465895991 ps
CPU time 186.05 seconds
Started Aug 25 04:10:30 AM UTC 24
Finished Aug 25 04:14:14 AM UTC 24
Peak memory 257556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104136512 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2104136512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1671154868
Short name T8
Test name
Test status
Simulation time 179055498 ps
CPU time 9.45 seconds
Started Aug 25 04:10:26 AM UTC 24
Finished Aug 25 04:10:40 AM UTC 24
Peak memory 225112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671154868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1671154868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1604195732
Short name T42
Test name
Test status
Simulation time 4890019105 ps
CPU time 139.47 seconds
Started Aug 25 04:10:27 AM UTC 24
Finished Aug 25 04:12:51 AM UTC 24
Peak memory 234980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1604195732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1604195732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3085003606
Short name T181
Test name
Test status
Simulation time 4129275028 ps
CPU time 14.15 seconds
Started Aug 25 04:11:38 AM UTC 24
Finished Aug 25 04:11:54 AM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085003606 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3085003606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3530149359
Short name T52
Test name
Test status
Simulation time 5210829888 ps
CPU time 245.77 seconds
Started Aug 25 04:11:36 AM UTC 24
Finished Aug 25 04:15:46 AM UTC 24
Peak memory 257060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530149359 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.3530149359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2684565048
Short name T204
Test name
Test status
Simulation time 517396593 ps
CPU time 33.62 seconds
Started Aug 25 04:11:36 AM UTC 24
Finished Aug 25 04:12:11 AM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684565048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2684565048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2488934802
Short name T190
Test name
Test status
Simulation time 260733227 ps
CPU time 16.67 seconds
Started Aug 25 04:11:36 AM UTC 24
Finished Aug 25 04:11:54 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488934802 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2488934802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2935891354
Short name T201
Test name
Test status
Simulation time 536170680 ps
CPU time 30.92 seconds
Started Aug 25 04:11:36 AM UTC 24
Finished Aug 25 04:12:08 AM UTC 24
Peak memory 228496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293589135
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.2935891354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3806555691
Short name T257
Test name
Test status
Simulation time 27292971233 ps
CPU time 141.32 seconds
Started Aug 25 04:11:38 AM UTC 24
Finished Aug 25 04:14:02 AM UTC 24
Peak memory 246540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3806555691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3806555691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.414557628
Short name T171
Test name
Test status
Simulation time 852909313 ps
CPU time 14.17 seconds
Started Aug 25 04:11:43 AM UTC 24
Finished Aug 25 04:11:58 AM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414557628 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.414557628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3918503841
Short name T26
Test name
Test status
Simulation time 1996525006 ps
CPU time 238.38 seconds
Started Aug 25 04:11:40 AM UTC 24
Finished Aug 25 04:15:43 AM UTC 24
Peak memory 244668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918503841 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.3918503841
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2891593676
Short name T202
Test name
Test status
Simulation time 335777489 ps
CPU time 27.49 seconds
Started Aug 25 04:11:40 AM UTC 24
Finished Aug 25 04:12:09 AM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891593676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2891593676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1437294363
Short name T193
Test name
Test status
Simulation time 187015561 ps
CPU time 15.27 seconds
Started Aug 25 04:11:39 AM UTC 24
Finished Aug 25 04:11:56 AM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437294363 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1437294363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.3331914554
Short name T151
Test name
Test status
Simulation time 212830616 ps
CPU time 26.92 seconds
Started Aug 25 04:11:38 AM UTC 24
Finished Aug 25 04:12:07 AM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333191455
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.3331914554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2019351347
Short name T259
Test name
Test status
Simulation time 6318829849 ps
CPU time 142.18 seconds
Started Aug 25 04:11:43 AM UTC 24
Finished Aug 25 04:14:08 AM UTC 24
Peak memory 235228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2019351347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2019351347
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.65673797
Short name T71
Test name
Test status
Simulation time 688899891 ps
CPU time 12.15 seconds
Started Aug 25 04:11:47 AM UTC 24
Finished Aug 25 04:12:00 AM UTC 24
Peak memory 228064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65673797 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.65673797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3730269141
Short name T343
Test name
Test status
Simulation time 4117872767 ps
CPU time 396.37 seconds
Started Aug 25 04:11:45 AM UTC 24
Finished Aug 25 04:18:27 AM UTC 24
Peak memory 259488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730269141 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.3730269141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.2620096892
Short name T206
Test name
Test status
Simulation time 4938660730 ps
CPU time 31.63 seconds
Started Aug 25 04:11:46 AM UTC 24
Finished Aug 25 04:12:19 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620096892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2620096892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2331788308
Short name T199
Test name
Test status
Simulation time 267353389 ps
CPU time 18.73 seconds
Started Aug 25 04:11:45 AM UTC 24
Finished Aug 25 04:12:05 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331788308 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2331788308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.40867460
Short name T159
Test name
Test status
Simulation time 542227341 ps
CPU time 41.93 seconds
Started Aug 25 04:11:44 AM UTC 24
Finished Aug 25 04:12:27 AM UTC 24
Peak memory 228748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40867460
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.40867460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3653124904
Short name T239
Test name
Test status
Simulation time 1844580390 ps
CPU time 100.11 seconds
Started Aug 25 04:11:47 AM UTC 24
Finished Aug 25 04:13:29 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3653124904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3653124904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2139003952
Short name T163
Test name
Test status
Simulation time 2736321738 ps
CPU time 14.6 seconds
Started Aug 25 04:11:50 AM UTC 24
Finished Aug 25 04:12:06 AM UTC 24
Peak memory 227872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139003952 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2139003952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.580506170
Short name T335
Test name
Test status
Simulation time 3517224397 ps
CPU time 347.13 seconds
Started Aug 25 04:11:49 AM UTC 24
Finished Aug 25 04:17:42 AM UTC 24
Peak memory 257392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580506170 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.580506170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.643264951
Short name T210
Test name
Test status
Simulation time 2600219285 ps
CPU time 34.76 seconds
Started Aug 25 04:11:50 AM UTC 24
Finished Aug 25 04:12:26 AM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643264951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.643264951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3703642155
Short name T198
Test name
Test status
Simulation time 271614301 ps
CPU time 14.32 seconds
Started Aug 25 04:11:48 AM UTC 24
Finished Aug 25 04:12:04 AM UTC 24
Peak memory 228100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703642155 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3703642155
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3267551770
Short name T166
Test name
Test status
Simulation time 394150915 ps
CPU time 21.74 seconds
Started Aug 25 04:11:47 AM UTC 24
Finished Aug 25 04:12:10 AM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326755177
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.3267551770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3452991473
Short name T321
Test name
Test status
Simulation time 18132078983 ps
CPU time 284.34 seconds
Started Aug 25 04:11:50 AM UTC 24
Finished Aug 25 04:16:39 AM UTC 24
Peak memory 239068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3452991473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3452991473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4097211990
Short name T174
Test name
Test status
Simulation time 259611548 ps
CPU time 14.42 seconds
Started Aug 25 04:11:54 AM UTC 24
Finished Aug 25 04:12:09 AM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097211990 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4097211990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2404227097
Short name T331
Test name
Test status
Simulation time 11177245257 ps
CPU time 309.32 seconds
Started Aug 25 04:11:53 AM UTC 24
Finished Aug 25 04:17:07 AM UTC 24
Peak memory 259488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404227097 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.2404227097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1400678853
Short name T212
Test name
Test status
Simulation time 1985832002 ps
CPU time 33.15 seconds
Started Aug 25 04:11:54 AM UTC 24
Finished Aug 25 04:12:28 AM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400678853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1400678853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3833199448
Short name T203
Test name
Test status
Simulation time 1100153506 ps
CPU time 17.11 seconds
Started Aug 25 04:11:52 AM UTC 24
Finished Aug 25 04:12:11 AM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833199448 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3833199448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2248826656
Short name T154
Test name
Test status
Simulation time 364909236 ps
CPU time 35.15 seconds
Started Aug 25 04:11:52 AM UTC 24
Finished Aug 25 04:12:29 AM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224882665
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.2248826656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3387856566
Short name T266
Test name
Test status
Simulation time 6115669335 ps
CPU time 142.88 seconds
Started Aug 25 04:11:54 AM UTC 24
Finished Aug 25 04:14:19 AM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3387856566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3387856566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1931651328
Short name T169
Test name
Test status
Simulation time 258071846 ps
CPU time 14.52 seconds
Started Aug 25 04:11:59 AM UTC 24
Finished Aug 25 04:12:15 AM UTC 24
Peak memory 227896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931651328 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1931651328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2318528161
Short name T357
Test name
Test status
Simulation time 23016620109 ps
CPU time 532.16 seconds
Started Aug 25 04:11:56 AM UTC 24
Finished Aug 25 04:20:56 AM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318528161 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.2318528161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1659332349
Short name T209
Test name
Test status
Simulation time 1379419689 ps
CPU time 26.65 seconds
Started Aug 25 04:11:57 AM UTC 24
Finished Aug 25 04:12:25 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659332349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1659332349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3705036761
Short name T205
Test name
Test status
Simulation time 1217815409 ps
CPU time 18.62 seconds
Started Aug 25 04:11:55 AM UTC 24
Finished Aug 25 04:12:15 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705036761 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3705036761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2866616172
Short name T160
Test name
Test status
Simulation time 302107026 ps
CPU time 30.14 seconds
Started Aug 25 04:11:55 AM UTC 24
Finished Aug 25 04:12:26 AM UTC 24
Peak memory 228836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286661617
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.2866616172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1413962596
Short name T273
Test name
Test status
Simulation time 11754623027 ps
CPU time 150.53 seconds
Started Aug 25 04:11:57 AM UTC 24
Finished Aug 25 04:14:30 AM UTC 24
Peak memory 235164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1413962596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1413962596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3432565282
Short name T165
Test name
Test status
Simulation time 1016180134 ps
CPU time 21.67 seconds
Started Aug 25 04:12:03 AM UTC 24
Finished Aug 25 04:12:26 AM UTC 24
Peak memory 227928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432565282 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3432565282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2710756473
Short name T327
Test name
Test status
Simulation time 17386707304 ps
CPU time 294.38 seconds
Started Aug 25 04:12:02 AM UTC 24
Finished Aug 25 04:17:02 AM UTC 24
Peak memory 257568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710756473 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.2710756473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1966375160
Short name T215
Test name
Test status
Simulation time 512949322 ps
CPU time 32.1 seconds
Started Aug 25 04:12:02 AM UTC 24
Finished Aug 25 04:12:36 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966375160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1966375160
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.4206147369
Short name T207
Test name
Test status
Simulation time 1342524396 ps
CPU time 18.08 seconds
Started Aug 25 04:12:01 AM UTC 24
Finished Aug 25 04:12:21 AM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206147369 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4206147369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.465274307
Short name T216
Test name
Test status
Simulation time 524470281 ps
CPU time 36.95 seconds
Started Aug 25 04:11:59 AM UTC 24
Finished Aug 25 04:12:37 AM UTC 24
Peak memory 228756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465274307
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.465274307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4193065613
Short name T323
Test name
Test status
Simulation time 5058449978 ps
CPU time 279.42 seconds
Started Aug 25 04:12:02 AM UTC 24
Finished Aug 25 04:16:47 AM UTC 24
Peak memory 246344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4193065613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.rom_ctrl_stress_all_with_rand_reset.4193065613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.639650837
Short name T208
Test name
Test status
Simulation time 296150740 ps
CPU time 14.15 seconds
Started Aug 25 04:12:08 AM UTC 24
Finished Aug 25 04:12:24 AM UTC 24
Peak memory 227968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639650837 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.639650837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2602271954
Short name T316
Test name
Test status
Simulation time 1924048732 ps
CPU time 247.05 seconds
Started Aug 25 04:12:07 AM UTC 24
Finished Aug 25 04:16:18 AM UTC 24
Peak memory 259416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602271954 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.2602271954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2142565618
Short name T217
Test name
Test status
Simulation time 350845124 ps
CPU time 31.27 seconds
Started Aug 25 04:12:07 AM UTC 24
Finished Aug 25 04:12:40 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142565618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2142565618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.3485326098
Short name T211
Test name
Test status
Simulation time 4522867502 ps
CPU time 20.06 seconds
Started Aug 25 04:12:06 AM UTC 24
Finished Aug 25 04:12:27 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485326098 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3485326098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.675411086
Short name T221
Test name
Test status
Simulation time 2143185702 ps
CPU time 37.87 seconds
Started Aug 25 04:12:04 AM UTC 24
Finished Aug 25 04:12:44 AM UTC 24
Peak memory 228668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675411086
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.675411086
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4200084502
Short name T65
Test name
Test status
Simulation time 13732228787 ps
CPU time 73.32 seconds
Started Aug 25 04:12:08 AM UTC 24
Finished Aug 25 04:13:24 AM UTC 24
Peak memory 239324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4200084502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.rom_ctrl_stress_all_with_rand_reset.4200084502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.1258462691
Short name T173
Test name
Test status
Simulation time 331784074 ps
CPU time 13.04 seconds
Started Aug 25 04:12:12 AM UTC 24
Finished Aug 25 04:12:26 AM UTC 24
Peak memory 227968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258462691 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1258462691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2160100549
Short name T352
Test name
Test status
Simulation time 46462203301 ps
CPU time 473.79 seconds
Started Aug 25 04:12:10 AM UTC 24
Finished Aug 25 04:20:11 AM UTC 24
Peak memory 228836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160100549 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.2160100549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.2019688354
Short name T220
Test name
Test status
Simulation time 2538822462 ps
CPU time 30.56 seconds
Started Aug 25 04:12:11 AM UTC 24
Finished Aug 25 04:12:43 AM UTC 24
Peak memory 228496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019688354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2019688354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1483947633
Short name T213
Test name
Test status
Simulation time 513755847 ps
CPU time 18.36 seconds
Started Aug 25 04:12:10 AM UTC 24
Finished Aug 25 04:12:30 AM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483947633 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1483947633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3558673381
Short name T226
Test name
Test status
Simulation time 1746299705 ps
CPU time 55.57 seconds
Started Aug 25 04:12:10 AM UTC 24
Finished Aug 25 04:13:07 AM UTC 24
Peak memory 230696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355867338
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.3558673381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3394949891
Short name T307
Test name
Test status
Simulation time 13015552756 ps
CPU time 219.98 seconds
Started Aug 25 04:12:12 AM UTC 24
Finished Aug 25 04:15:56 AM UTC 24
Peak memory 235540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3394949891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3394949891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.496924106
Short name T218
Test name
Test status
Simulation time 255183361 ps
CPU time 15.07 seconds
Started Aug 25 04:12:24 AM UTC 24
Finished Aug 25 04:12:41 AM UTC 24
Peak memory 228144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496924106 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.496924106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2229158831
Short name T61
Test name
Test status
Simulation time 29654938726 ps
CPU time 227.97 seconds
Started Aug 25 04:12:19 AM UTC 24
Finished Aug 25 04:16:11 AM UTC 24
Peak memory 259488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229158831 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.2229158831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3290377889
Short name T43
Test name
Test status
Simulation time 345988306 ps
CPU time 28.35 seconds
Started Aug 25 04:12:21 AM UTC 24
Finished Aug 25 04:12:51 AM UTC 24
Peak memory 228136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290377889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3290377889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3329155046
Short name T214
Test name
Test status
Simulation time 1961121424 ps
CPU time 14.37 seconds
Started Aug 25 04:12:15 AM UTC 24
Finished Aug 25 04:12:31 AM UTC 24
Peak memory 228276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329155046 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3329155046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2267216123
Short name T44
Test name
Test status
Simulation time 2069894013 ps
CPU time 34.77 seconds
Started Aug 25 04:12:15 AM UTC 24
Finished Aug 25 04:12:52 AM UTC 24
Peak memory 228500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226721612
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.2267216123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.545289892
Short name T75
Test name
Test status
Simulation time 346005748 ps
CPU time 10.16 seconds
Started Aug 25 04:10:37 AM UTC 24
Finished Aug 25 04:11:15 AM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545289892 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.545289892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2962917510
Short name T54
Test name
Test status
Simulation time 10884435650 ps
CPU time 298.69 seconds
Started Aug 25 04:10:34 AM UTC 24
Finished Aug 25 04:16:08 AM UTC 24
Peak memory 257192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962917510 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.2962917510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2914127679
Short name T36
Test name
Test status
Simulation time 6600350051 ps
CPU time 28.24 seconds
Started Aug 25 04:10:34 AM UTC 24
Finished Aug 25 04:11:34 AM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914127679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2914127679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.840396349
Short name T118
Test name
Test status
Simulation time 183109085 ps
CPU time 10.09 seconds
Started Aug 25 04:10:34 AM UTC 24
Finished Aug 25 04:11:15 AM UTC 24
Peak memory 228160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840396349 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.840396349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3754982279
Short name T41
Test name
Test status
Simulation time 382375914 ps
CPU time 350.09 seconds
Started Aug 25 04:10:37 AM UTC 24
Finished Aug 25 04:16:59 AM UTC 24
Peak memory 258444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754982279 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3754982279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1815975070
Short name T62
Test name
Test status
Simulation time 176730168 ps
CPU time 12 seconds
Started Aug 25 04:10:31 AM UTC 24
Finished Aug 25 04:11:12 AM UTC 24
Peak memory 228640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815975070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1815975070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2702303330
Short name T176
Test name
Test status
Simulation time 1035562418 ps
CPU time 26.43 seconds
Started Aug 25 04:10:32 AM UTC 24
Finished Aug 25 04:11:32 AM UTC 24
Peak memory 228400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270230333
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.2702303330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.213162010
Short name T64
Test name
Test status
Simulation time 2699753526 ps
CPU time 135.3 seconds
Started Aug 25 04:10:36 AM UTC 24
Finished Aug 25 04:13:18 AM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=213162010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.rom_ctrl_stress_all_with_rand_reset.213162010
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1744680057
Short name T219
Test name
Test status
Simulation time 173542900 ps
CPU time 12.64 seconds
Started Aug 25 04:12:28 AM UTC 24
Finished Aug 25 04:12:42 AM UTC 24
Peak memory 227832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744680057 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1744680057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3816937673
Short name T337
Test name
Test status
Simulation time 5120685429 ps
CPU time 312.03 seconds
Started Aug 25 04:12:27 AM UTC 24
Finished Aug 25 04:17:44 AM UTC 24
Peak memory 257488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816937673 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.3816937673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2077594481
Short name T47
Test name
Test status
Simulation time 332285685 ps
CPU time 27.77 seconds
Started Aug 25 04:12:28 AM UTC 24
Finished Aug 25 04:12:57 AM UTC 24
Peak memory 228764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077594481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2077594481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3533182242
Short name T223
Test name
Test status
Simulation time 917702728 ps
CPU time 17.9 seconds
Started Aug 25 04:12:27 AM UTC 24
Finished Aug 25 04:12:46 AM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533182242 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3533182242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.745397833
Short name T45
Test name
Test status
Simulation time 582642356 ps
CPU time 28.48 seconds
Started Aug 25 04:12:26 AM UTC 24
Finished Aug 25 04:12:56 AM UTC 24
Peak memory 227628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745397833
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.745397833
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3227325686
Short name T353
Test name
Test status
Simulation time 10625998518 ps
CPU time 458.11 seconds
Started Aug 25 04:12:28 AM UTC 24
Finished Aug 25 04:20:12 AM UTC 24
Peak memory 246548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3227325686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3227325686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3894163149
Short name T224
Test name
Test status
Simulation time 212487416 ps
CPU time 11.6 seconds
Started Aug 25 04:12:33 AM UTC 24
Finished Aug 25 04:12:46 AM UTC 24
Peak memory 228048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894163149 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3894163149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1361347867
Short name T368
Test name
Test status
Simulation time 19617011648 ps
CPU time 749.42 seconds
Started Aug 25 04:12:30 AM UTC 24
Finished Aug 25 04:25:11 AM UTC 24
Peak memory 249172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361347867 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.1361347867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.4057844654
Short name T225
Test name
Test status
Simulation time 335487070 ps
CPU time 31.16 seconds
Started Aug 25 04:12:31 AM UTC 24
Finished Aug 25 04:13:04 AM UTC 24
Peak memory 227936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057844654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4057844654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2183186438
Short name T222
Test name
Test status
Simulation time 1430470971 ps
CPU time 15.16 seconds
Started Aug 25 04:12:29 AM UTC 24
Finished Aug 25 04:12:45 AM UTC 24
Peak memory 228052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183186438 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2183186438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2534698415
Short name T229
Test name
Test status
Simulation time 1032361492 ps
CPU time 42.77 seconds
Started Aug 25 04:12:28 AM UTC 24
Finished Aug 25 04:13:12 AM UTC 24
Peak memory 228776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253469841
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.2534698415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2481013759
Short name T262
Test name
Test status
Simulation time 21195320337 ps
CPU time 98.8 seconds
Started Aug 25 04:12:32 AM UTC 24
Finished Aug 25 04:14:13 AM UTC 24
Peak memory 243164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2481013759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2481013759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1525790326
Short name T48
Test name
Test status
Simulation time 254848654 ps
CPU time 13.82 seconds
Started Aug 25 04:12:43 AM UTC 24
Finished Aug 25 04:12:59 AM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525790326 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1525790326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3248523911
Short name T325
Test name
Test status
Simulation time 2382372514 ps
CPU time 254.89 seconds
Started Aug 25 04:12:38 AM UTC 24
Finished Aug 25 04:16:58 AM UTC 24
Peak memory 257288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248523911 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.3248523911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2684569542
Short name T46
Test name
Test status
Simulation time 3173280506 ps
CPU time 17.48 seconds
Started Aug 25 04:12:37 AM UTC 24
Finished Aug 25 04:12:56 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684569542 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2684569542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2106367895
Short name T233
Test name
Test status
Simulation time 1559012909 ps
CPU time 42.38 seconds
Started Aug 25 04:12:36 AM UTC 24
Finished Aug 25 04:13:20 AM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210636789
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.2106367895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.895737314
Short name T250
Test name
Test status
Simulation time 3597799693 ps
CPU time 65.66 seconds
Started Aug 25 04:12:42 AM UTC 24
Finished Aug 25 04:13:49 AM UTC 24
Peak memory 239132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=895737314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.rom_ctrl_stress_all_with_rand_reset.895737314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.531057436
Short name T49
Test name
Test status
Simulation time 729850942 ps
CPU time 13.15 seconds
Started Aug 25 04:12:47 AM UTC 24
Finished Aug 25 04:13:01 AM UTC 24
Peak memory 227816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531057436 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.531057436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3394635853
Short name T346
Test name
Test status
Simulation time 3950367052 ps
CPU time 351.06 seconds
Started Aug 25 04:12:45 AM UTC 24
Finished Aug 25 04:18:42 AM UTC 24
Peak memory 228000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394635853 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.3394635853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.341632378
Short name T232
Test name
Test status
Simulation time 718821559 ps
CPU time 29.46 seconds
Started Aug 25 04:12:46 AM UTC 24
Finished Aug 25 04:13:17 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341632378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.341632378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.4195391038
Short name T50
Test name
Test status
Simulation time 515465349 ps
CPU time 18.49 seconds
Started Aug 25 04:12:44 AM UTC 24
Finished Aug 25 04:13:04 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195391038 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4195391038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1460432178
Short name T234
Test name
Test status
Simulation time 516533350 ps
CPU time 36.17 seconds
Started Aug 25 04:12:44 AM UTC 24
Finished Aug 25 04:13:21 AM UTC 24
Peak memory 228644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146043217
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.1460432178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2839564613
Short name T312
Test name
Test status
Simulation time 15094276762 ps
CPU time 196.84 seconds
Started Aug 25 04:12:46 AM UTC 24
Finished Aug 25 04:16:06 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2839564613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2839564613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1195276523
Short name T228
Test name
Test status
Simulation time 4926273502 ps
CPU time 13.37 seconds
Started Aug 25 04:12:56 AM UTC 24
Finished Aug 25 04:13:11 AM UTC 24
Peak memory 228064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195276523 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1195276523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3731479814
Short name T340
Test name
Test status
Simulation time 4434771424 ps
CPU time 318.86 seconds
Started Aug 25 04:12:51 AM UTC 24
Finished Aug 25 04:18:15 AM UTC 24
Peak memory 257392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731479814 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.3731479814
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2820088635
Short name T236
Test name
Test status
Simulation time 512380505 ps
CPU time 31.35 seconds
Started Aug 25 04:12:52 AM UTC 24
Finished Aug 25 04:13:25 AM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820088635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2820088635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.4145680359
Short name T227
Test name
Test status
Simulation time 989473479 ps
CPU time 18.23 seconds
Started Aug 25 04:12:51 AM UTC 24
Finished Aug 25 04:13:11 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145680359 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4145680359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.13700444
Short name T244
Test name
Test status
Simulation time 1076666867 ps
CPU time 48.69 seconds
Started Aug 25 04:12:47 AM UTC 24
Finished Aug 25 04:13:37 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13700444
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.13700444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2905548780
Short name T59
Test name
Test status
Simulation time 2870168712 ps
CPU time 213.16 seconds
Started Aug 25 04:12:52 AM UTC 24
Finished Aug 25 04:16:29 AM UTC 24
Peak memory 246412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2905548780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2905548780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3235923867
Short name T231
Test name
Test status
Simulation time 170456944 ps
CPU time 10.97 seconds
Started Aug 25 04:13:05 AM UTC 24
Finished Aug 25 04:13:17 AM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235923867 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3235923867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.46710055
Short name T351
Test name
Test status
Simulation time 13034881176 ps
CPU time 416.03 seconds
Started Aug 25 04:13:00 AM UTC 24
Finished Aug 25 04:20:02 AM UTC 24
Peak memory 256436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46710055 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.46710055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3758864480
Short name T240
Test name
Test status
Simulation time 944496563 ps
CPU time 26.95 seconds
Started Aug 25 04:13:03 AM UTC 24
Finished Aug 25 04:13:31 AM UTC 24
Peak memory 228832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758864480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3758864480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2558013705
Short name T230
Test name
Test status
Simulation time 1021245851 ps
CPU time 17.3 seconds
Started Aug 25 04:12:57 AM UTC 24
Finished Aug 25 04:13:16 AM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558013705 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2558013705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.187743384
Short name T235
Test name
Test status
Simulation time 300540437 ps
CPU time 22.57 seconds
Started Aug 25 04:12:57 AM UTC 24
Finished Aug 25 04:13:21 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187743384
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.187743384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2245612694
Short name T295
Test name
Test status
Simulation time 1920518160 ps
CPU time 140.5 seconds
Started Aug 25 04:13:05 AM UTC 24
Finished Aug 25 04:15:28 AM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2245612694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2245612694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3388597042
Short name T237
Test name
Test status
Simulation time 1269181600 ps
CPU time 12.24 seconds
Started Aug 25 04:13:13 AM UTC 24
Finished Aug 25 04:13:26 AM UTC 24
Peak memory 228040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388597042 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3388597042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3216718780
Short name T328
Test name
Test status
Simulation time 2445270580 ps
CPU time 227.41 seconds
Started Aug 25 04:13:11 AM UTC 24
Finished Aug 25 04:17:02 AM UTC 24
Peak memory 259480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216718780 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.3216718780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1795396877
Short name T248
Test name
Test status
Simulation time 1030444926 ps
CPU time 33.5 seconds
Started Aug 25 04:13:12 AM UTC 24
Finished Aug 25 04:13:47 AM UTC 24
Peak memory 228248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795396877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1795396877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1599299399
Short name T238
Test name
Test status
Simulation time 716051752 ps
CPU time 15.91 seconds
Started Aug 25 04:13:10 AM UTC 24
Finished Aug 25 04:13:27 AM UTC 24
Peak memory 228100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599299399 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1599299399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1644165443
Short name T241
Test name
Test status
Simulation time 199729846 ps
CPU time 22.06 seconds
Started Aug 25 04:13:08 AM UTC 24
Finished Aug 25 04:13:31 AM UTC 24
Peak memory 228644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164416544
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.1644165443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2200017981
Short name T305
Test name
Test status
Simulation time 11928189796 ps
CPU time 158.04 seconds
Started Aug 25 04:13:13 AM UTC 24
Finished Aug 25 04:15:54 AM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2200017981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2200017981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1908814702
Short name T243
Test name
Test status
Simulation time 972322954 ps
CPU time 11.36 seconds
Started Aug 25 04:13:22 AM UTC 24
Finished Aug 25 04:13:35 AM UTC 24
Peak memory 227936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908814702 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1908814702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2722601545
Short name T326
Test name
Test status
Simulation time 28219964975 ps
CPU time 218.74 seconds
Started Aug 25 04:13:18 AM UTC 24
Finished Aug 25 04:17:01 AM UTC 24
Peak memory 259488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722601545 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.2722601545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2181167710
Short name T249
Test name
Test status
Simulation time 342713082 ps
CPU time 29.36 seconds
Started Aug 25 04:13:18 AM UTC 24
Finished Aug 25 04:13:49 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181167710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2181167710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.887648313
Short name T242
Test name
Test status
Simulation time 729484715 ps
CPU time 15.39 seconds
Started Aug 25 04:13:17 AM UTC 24
Finished Aug 25 04:13:34 AM UTC 24
Peak memory 228044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887648313 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.887648313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2207719634
Short name T251
Test name
Test status
Simulation time 354034708 ps
CPU time 31.33 seconds
Started Aug 25 04:13:17 AM UTC 24
Finished Aug 25 04:13:50 AM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220771963
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.2207719634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3510221456
Short name T270
Test name
Test status
Simulation time 5231685015 ps
CPU time 64.5 seconds
Started Aug 25 04:13:21 AM UTC 24
Finished Aug 25 04:14:28 AM UTC 24
Peak memory 243356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3510221456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3510221456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.4021492320
Short name T246
Test name
Test status
Simulation time 688437117 ps
CPU time 11.85 seconds
Started Aug 25 04:13:30 AM UTC 24
Finished Aug 25 04:13:43 AM UTC 24
Peak memory 228376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021492320 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4021492320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.894525494
Short name T369
Test name
Test status
Simulation time 132597004553 ps
CPU time 842.38 seconds
Started Aug 25 04:13:26 AM UTC 24
Finished Aug 25 04:27:40 AM UTC 24
Peak memory 261660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894525494 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.894525494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.4048482939
Short name T255
Test name
Test status
Simulation time 1012284426 ps
CPU time 30.71 seconds
Started Aug 25 04:13:28 AM UTC 24
Finished Aug 25 04:14:00 AM UTC 24
Peak memory 228248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048482939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4048482939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.74836944
Short name T247
Test name
Test status
Simulation time 270098538 ps
CPU time 17.3 seconds
Started Aug 25 04:13:25 AM UTC 24
Finished Aug 25 04:13:43 AM UTC 24
Peak memory 228596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74836944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.74836944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.775195835
Short name T265
Test name
Test status
Simulation time 1143369098 ps
CPU time 54.77 seconds
Started Aug 25 04:13:22 AM UTC 24
Finished Aug 25 04:14:19 AM UTC 24
Peak memory 228644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775195835
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.775195835
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1550582160
Short name T363
Test name
Test status
Simulation time 24721258294 ps
CPU time 479.21 seconds
Started Aug 25 04:13:28 AM UTC 24
Finished Aug 25 04:21:34 AM UTC 24
Peak memory 241188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1550582160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1550582160
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3504593536
Short name T253
Test name
Test status
Simulation time 1376767220 ps
CPU time 12.09 seconds
Started Aug 25 04:13:43 AM UTC 24
Finished Aug 25 04:13:56 AM UTC 24
Peak memory 228032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504593536 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3504593536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1660160113
Short name T350
Test name
Test status
Simulation time 4233321871 ps
CPU time 364.62 seconds
Started Aug 25 04:13:35 AM UTC 24
Finished Aug 25 04:19:46 AM UTC 24
Peak memory 245948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660160113 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.1660160113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.707044419
Short name T261
Test name
Test status
Simulation time 1011374910 ps
CPU time 31.66 seconds
Started Aug 25 04:13:36 AM UTC 24
Finished Aug 25 04:14:09 AM UTC 24
Peak memory 228104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707044419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.707044419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1611947364
Short name T252
Test name
Test status
Simulation time 4239043265 ps
CPU time 16.93 seconds
Started Aug 25 04:13:32 AM UTC 24
Finished Aug 25 04:13:51 AM UTC 24
Peak memory 228696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611947364 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1611947364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3921647516
Short name T254
Test name
Test status
Simulation time 3416265023 ps
CPU time 22.83 seconds
Started Aug 25 04:13:32 AM UTC 24
Finished Aug 25 04:13:57 AM UTC 24
Peak memory 228632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392164751
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.3921647516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3309173571
Short name T303
Test name
Test status
Simulation time 19150151714 ps
CPU time 127.23 seconds
Started Aug 25 04:13:38 AM UTC 24
Finished Aug 25 04:15:48 AM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3309173571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3309173571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.3203276406
Short name T76
Test name
Test status
Simulation time 1271560930 ps
CPU time 10.7 seconds
Started Aug 25 04:10:43 AM UTC 24
Finished Aug 25 04:11:15 AM UTC 24
Peak memory 227908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203276406 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3203276406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.365701249
Short name T358
Test name
Test status
Simulation time 77388082005 ps
CPU time 605.25 seconds
Started Aug 25 04:10:40 AM UTC 24
Finished Aug 25 04:20:57 AM UTC 24
Peak memory 249292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365701249 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.365701249
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3307785617
Short name T39
Test name
Test status
Simulation time 6601836049 ps
CPU time 25.89 seconds
Started Aug 25 04:10:40 AM UTC 24
Finished Aug 25 04:11:31 AM UTC 24
Peak memory 228768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307785617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3307785617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.88181060
Short name T138
Test name
Test status
Simulation time 3664726820 ps
CPU time 23.16 seconds
Started Aug 25 04:10:38 AM UTC 24
Finished Aug 25 04:11:34 AM UTC 24
Peak memory 228824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88181060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.88181060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1492499052
Short name T19
Test name
Test status
Simulation time 179480625 ps
CPU time 12.77 seconds
Started Aug 25 04:10:37 AM UTC 24
Finished Aug 25 04:11:18 AM UTC 24
Peak memory 228644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492499052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1492499052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2936554355
Short name T172
Test name
Test status
Simulation time 373377455 ps
CPU time 33.14 seconds
Started Aug 25 04:10:38 AM UTC 24
Finished Aug 25 04:11:44 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293655435
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.2936554355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1581300529
Short name T63
Test name
Test status
Simulation time 8634626234 ps
CPU time 104.57 seconds
Started Aug 25 04:10:41 AM UTC 24
Finished Aug 25 04:12:46 AM UTC 24
Peak memory 235172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1581300529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1581300529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.2682676025
Short name T258
Test name
Test status
Simulation time 394850875 ps
CPU time 11.64 seconds
Started Aug 25 04:13:51 AM UTC 24
Finished Aug 25 04:14:04 AM UTC 24
Peak memory 227668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682676025 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2682676025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3876897325
Short name T361
Test name
Test status
Simulation time 9006093310 ps
CPU time 453.47 seconds
Started Aug 25 04:13:48 AM UTC 24
Finished Aug 25 04:21:29 AM UTC 24
Peak memory 257224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876897325 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.3876897325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2035683194
Short name T268
Test name
Test status
Simulation time 496537655 ps
CPU time 32.45 seconds
Started Aug 25 04:13:49 AM UTC 24
Finished Aug 25 04:14:23 AM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035683194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2035683194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.339410695
Short name T256
Test name
Test status
Simulation time 699677727 ps
CPU time 15.87 seconds
Started Aug 25 04:13:44 AM UTC 24
Finished Aug 25 04:14:02 AM UTC 24
Peak memory 228572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339410695 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.339410695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2296250450
Short name T275
Test name
Test status
Simulation time 791173300 ps
CPU time 51.61 seconds
Started Aug 25 04:13:43 AM UTC 24
Finished Aug 25 04:14:36 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229625045
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.2296250450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.420869126
Short name T264
Test name
Test status
Simulation time 688821034 ps
CPU time 11.92 seconds
Started Aug 25 04:14:01 AM UTC 24
Finished Aug 25 04:14:14 AM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420869126 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.420869126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3714109741
Short name T332
Test name
Test status
Simulation time 3872879055 ps
CPU time 202.59 seconds
Started Aug 25 04:13:57 AM UTC 24
Finished Aug 25 04:17:23 AM UTC 24
Peak memory 259592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714109741 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.3714109741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3721063408
Short name T272
Test name
Test status
Simulation time 2074856309 ps
CPU time 31.77 seconds
Started Aug 25 04:13:57 AM UTC 24
Finished Aug 25 04:14:30 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721063408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3721063408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.788458751
Short name T260
Test name
Test status
Simulation time 182388679 ps
CPU time 15.47 seconds
Started Aug 25 04:13:52 AM UTC 24
Finished Aug 25 04:14:08 AM UTC 24
Peak memory 227936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788458751 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.788458751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2420995358
Short name T263
Test name
Test status
Simulation time 222105017 ps
CPU time 20.45 seconds
Started Aug 25 04:13:52 AM UTC 24
Finished Aug 25 04:14:13 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242099535
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.2420995358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1835608766
Short name T315
Test name
Test status
Simulation time 3893131390 ps
CPU time 135.25 seconds
Started Aug 25 04:13:58 AM UTC 24
Finished Aug 25 04:16:16 AM UTC 24
Peak memory 235036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1835608766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1835608766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2073084928
Short name T269
Test name
Test status
Simulation time 508537303 ps
CPU time 14.43 seconds
Started Aug 25 04:14:10 AM UTC 24
Finished Aug 25 04:14:26 AM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073084928 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2073084928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3483516732
Short name T356
Test name
Test status
Simulation time 5022600521 ps
CPU time 389.98 seconds
Started Aug 25 04:14:04 AM UTC 24
Finished Aug 25 04:20:40 AM UTC 24
Peak memory 258824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483516732 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.3483516732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3983922701
Short name T276
Test name
Test status
Simulation time 333943604 ps
CPU time 27.75 seconds
Started Aug 25 04:14:08 AM UTC 24
Finished Aug 25 04:14:37 AM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983922701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3983922701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.994784744
Short name T267
Test name
Test status
Simulation time 175093828 ps
CPU time 16.26 seconds
Started Aug 25 04:14:03 AM UTC 24
Finished Aug 25 04:14:21 AM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994784744 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.994784744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1141279377
Short name T271
Test name
Test status
Simulation time 291052358 ps
CPU time 24.49 seconds
Started Aug 25 04:14:02 AM UTC 24
Finished Aug 25 04:14:28 AM UTC 24
Peak memory 228756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114127937
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.1141279377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3698299525
Short name T308
Test name
Test status
Simulation time 16848919548 ps
CPU time 105.69 seconds
Started Aug 25 04:14:09 AM UTC 24
Finished Aug 25 04:15:57 AM UTC 24
Peak memory 245404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3698299525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3698299525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3072279977
Short name T279
Test name
Test status
Simulation time 19722079747 ps
CPU time 22.8 seconds
Started Aug 25 04:14:20 AM UTC 24
Finished Aug 25 04:14:44 AM UTC 24
Peak memory 228472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072279977 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3072279977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2126492736
Short name T366
Test name
Test status
Simulation time 40209253175 ps
CPU time 480.98 seconds
Started Aug 25 04:14:15 AM UTC 24
Finished Aug 25 04:22:23 AM UTC 24
Peak memory 257404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126492736 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.2126492736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3583570045
Short name T282
Test name
Test status
Simulation time 5520704777 ps
CPU time 30.51 seconds
Started Aug 25 04:14:15 AM UTC 24
Finished Aug 25 04:14:47 AM UTC 24
Peak memory 228700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583570045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3583570045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.4152530679
Short name T274
Test name
Test status
Simulation time 175640440 ps
CPU time 15.63 seconds
Started Aug 25 04:14:14 AM UTC 24
Finished Aug 25 04:14:31 AM UTC 24
Peak memory 228328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152530679 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4152530679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2992506473
Short name T290
Test name
Test status
Simulation time 1551600033 ps
CPU time 51.84 seconds
Started Aug 25 04:14:14 AM UTC 24
Finished Aug 25 04:15:08 AM UTC 24
Peak memory 228648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299250647
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.2992506473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3616981950
Short name T360
Test name
Test status
Simulation time 22295326209 ps
CPU time 403.22 seconds
Started Aug 25 04:14:20 AM UTC 24
Finished Aug 25 04:21:09 AM UTC 24
Peak memory 241116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3616981950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3616981950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2051286873
Short name T280
Test name
Test status
Simulation time 1118917205 ps
CPU time 14.4 seconds
Started Aug 25 04:14:29 AM UTC 24
Finished Aug 25 04:14:45 AM UTC 24
Peak memory 227808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051286873 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2051286873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.308840856
Short name T329
Test name
Test status
Simulation time 10098980167 ps
CPU time 155.31 seconds
Started Aug 25 04:14:24 AM UTC 24
Finished Aug 25 04:17:02 AM UTC 24
Peak memory 246544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308840856 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.308840856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3677561710
Short name T285
Test name
Test status
Simulation time 1009610297 ps
CPU time 32.4 seconds
Started Aug 25 04:14:27 AM UTC 24
Finished Aug 25 04:15:01 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677561710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3677561710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3011814372
Short name T277
Test name
Test status
Simulation time 181593688 ps
CPU time 15.04 seconds
Started Aug 25 04:14:22 AM UTC 24
Finished Aug 25 04:14:38 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011814372 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3011814372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3334131555
Short name T278
Test name
Test status
Simulation time 861864265 ps
CPU time 21.7 seconds
Started Aug 25 04:14:21 AM UTC 24
Finished Aug 25 04:14:44 AM UTC 24
Peak memory 228280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333413155
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.3334131555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1069105971
Short name T345
Test name
Test status
Simulation time 3300987692 ps
CPU time 238 seconds
Started Aug 25 04:14:28 AM UTC 24
Finished Aug 25 04:18:30 AM UTC 24
Peak memory 239068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1069105971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1069105971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.4087489366
Short name T284
Test name
Test status
Simulation time 1033149365 ps
CPU time 13.69 seconds
Started Aug 25 04:14:38 AM UTC 24
Finished Aug 25 04:14:53 AM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087489366 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4087489366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1418386800
Short name T365
Test name
Test status
Simulation time 16799506209 ps
CPU time 432.01 seconds
Started Aug 25 04:14:31 AM UTC 24
Finished Aug 25 04:21:50 AM UTC 24
Peak memory 257448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418386800 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.1418386800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1234709975
Short name T289
Test name
Test status
Simulation time 1053767219 ps
CPU time 32.59 seconds
Started Aug 25 04:14:32 AM UTC 24
Finished Aug 25 04:15:06 AM UTC 24
Peak memory 225652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234709975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1234709975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.340583777
Short name T283
Test name
Test status
Simulation time 426142747 ps
CPU time 15.5 seconds
Started Aug 25 04:14:31 AM UTC 24
Finished Aug 25 04:14:48 AM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340583777 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.340583777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.4057941170
Short name T288
Test name
Test status
Simulation time 2216213389 ps
CPU time 34.13 seconds
Started Aug 25 04:14:29 AM UTC 24
Finished Aug 25 04:15:05 AM UTC 24
Peak memory 228628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405794117
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.4057941170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.140437043
Short name T344
Test name
Test status
Simulation time 14899271314 ps
CPU time 226.31 seconds
Started Aug 25 04:14:37 AM UTC 24
Finished Aug 25 04:18:28 AM UTC 24
Peak memory 245276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=140437043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_stress_all_with_rand_reset.140437043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4173956603
Short name T287
Test name
Test status
Simulation time 2479426350 ps
CPU time 13.85 seconds
Started Aug 25 04:14:48 AM UTC 24
Finished Aug 25 04:15:03 AM UTC 24
Peak memory 228000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173956603 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4173956603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1987129601
Short name T367
Test name
Test status
Simulation time 11823615503 ps
CPU time 461.64 seconds
Started Aug 25 04:14:45 AM UTC 24
Finished Aug 25 04:22:33 AM UTC 24
Peak memory 259616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987129601 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.1987129601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1977882112
Short name T294
Test name
Test status
Simulation time 2056547818 ps
CPU time 34.16 seconds
Started Aug 25 04:14:46 AM UTC 24
Finished Aug 25 04:15:21 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977882112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1977882112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1174392381
Short name T286
Test name
Test status
Simulation time 176886949 ps
CPU time 15.81 seconds
Started Aug 25 04:14:45 AM UTC 24
Finished Aug 25 04:15:02 AM UTC 24
Peak memory 228584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174392381 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1174392381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3944137625
Short name T299
Test name
Test status
Simulation time 833358936 ps
CPU time 57.01 seconds
Started Aug 25 04:14:39 AM UTC 24
Finished Aug 25 04:15:37 AM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394413762
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.3944137625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.911289406
Short name T341
Test name
Test status
Simulation time 3902988586 ps
CPU time 206.91 seconds
Started Aug 25 04:14:47 AM UTC 24
Finished Aug 25 04:18:17 AM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=911289406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.rom_ctrl_stress_all_with_rand_reset.911289406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3946044886
Short name T292
Test name
Test status
Simulation time 340863820 ps
CPU time 12.04 seconds
Started Aug 25 04:15:05 AM UTC 24
Finished Aug 25 04:15:19 AM UTC 24
Peak memory 227436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946044886 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3946044886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4209677654
Short name T349
Test name
Test status
Simulation time 15792252270 ps
CPU time 273.66 seconds
Started Aug 25 04:15:02 AM UTC 24
Finished Aug 25 04:19:40 AM UTC 24
Peak memory 245120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209677654 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.4209677654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.2965909693
Short name T301
Test name
Test status
Simulation time 4940760197 ps
CPU time 34.8 seconds
Started Aug 25 04:15:02 AM UTC 24
Finished Aug 25 04:15:38 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965909693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2965909693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1218359976
Short name T291
Test name
Test status
Simulation time 183144642 ps
CPU time 16.42 seconds
Started Aug 25 04:14:54 AM UTC 24
Finished Aug 25 04:15:12 AM UTC 24
Peak memory 228044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218359976 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1218359976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.4106145770
Short name T298
Test name
Test status
Simulation time 1239372509 ps
CPU time 41.87 seconds
Started Aug 25 04:14:49 AM UTC 24
Finished Aug 25 04:15:32 AM UTC 24
Peak memory 228840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410614577
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.4106145770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1684958716
Short name T320
Test name
Test status
Simulation time 1395003003 ps
CPU time 83.74 seconds
Started Aug 25 04:15:04 AM UTC 24
Finished Aug 25 04:16:30 AM UTC 24
Peak memory 233116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1684958716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1684958716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.4291299123
Short name T296
Test name
Test status
Simulation time 1297593408 ps
CPU time 14.62 seconds
Started Aug 25 04:15:13 AM UTC 24
Finished Aug 25 04:15:29 AM UTC 24
Peak memory 228160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291299123 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4291299123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3457773445
Short name T347
Test name
Test status
Simulation time 3973297592 ps
CPU time 213.47 seconds
Started Aug 25 04:15:08 AM UTC 24
Finished Aug 25 04:18:46 AM UTC 24
Peak memory 257440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457773445 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.3457773445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.978167022
Short name T311
Test name
Test status
Simulation time 39445192389 ps
CPU time 49.67 seconds
Started Aug 25 04:15:11 AM UTC 24
Finished Aug 25 04:16:02 AM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978167022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.978167022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3969359711
Short name T293
Test name
Test status
Simulation time 186357266 ps
CPU time 11.95 seconds
Started Aug 25 04:15:07 AM UTC 24
Finished Aug 25 04:15:21 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969359711 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3969359711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3821478418
Short name T309
Test name
Test status
Simulation time 7849759351 ps
CPU time 52.14 seconds
Started Aug 25 04:15:05 AM UTC 24
Finished Aug 25 04:16:00 AM UTC 24
Peak memory 228248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382147841
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.3821478418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2498559154
Short name T318
Test name
Test status
Simulation time 1152528899 ps
CPU time 65.89 seconds
Started Aug 25 04:15:13 AM UTC 24
Finished Aug 25 04:16:21 AM UTC 24
Peak memory 230812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2498559154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2498559154
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3205101846
Short name T304
Test name
Test status
Simulation time 3760505498 ps
CPU time 20.85 seconds
Started Aug 25 04:15:29 AM UTC 24
Finished Aug 25 04:15:51 AM UTC 24
Peak memory 228040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205101846 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3205101846
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1733561731
Short name T359
Test name
Test status
Simulation time 5807537124 ps
CPU time 333.01 seconds
Started Aug 25 04:15:22 AM UTC 24
Finished Aug 25 04:21:00 AM UTC 24
Peak memory 261536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733561731 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.1733561731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.809209131
Short name T310
Test name
Test status
Simulation time 1980393844 ps
CPU time 34.74 seconds
Started Aug 25 04:15:25 AM UTC 24
Finished Aug 25 04:16:01 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809209131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.809209131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.764227395
Short name T300
Test name
Test status
Simulation time 354139347 ps
CPU time 14.98 seconds
Started Aug 25 04:15:22 AM UTC 24
Finished Aug 25 04:15:38 AM UTC 24
Peak memory 228252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764227395 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.764227395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.391202245
Short name T314
Test name
Test status
Simulation time 809395552 ps
CPU time 53.72 seconds
Started Aug 25 04:15:20 AM UTC 24
Finished Aug 25 04:16:15 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391202245
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.391202245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2090011598
Short name T139
Test name
Test status
Simulation time 12780868410 ps
CPU time 73.06 seconds
Started Aug 25 04:15:29 AM UTC 24
Finished Aug 25 04:16:44 AM UTC 24
Peak memory 239260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2090011598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2090011598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2336625662
Short name T67
Test name
Test status
Simulation time 260613481 ps
CPU time 8.62 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:09 AM UTC 24
Peak memory 227768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336625662 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2336625662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3969426629
Short name T324
Test name
Test status
Simulation time 3748003335 ps
CPU time 343.14 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:16:48 AM UTC 24
Peak memory 259228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969426629 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.3969426629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.2182252903
Short name T38
Test name
Test status
Simulation time 2473494860 ps
CPU time 25.12 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:25 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182252903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2182252903
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1976163452
Short name T14
Test name
Test status
Simulation time 705668764 ps
CPU time 9.44 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:10 AM UTC 24
Peak memory 227940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976163452 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1976163452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2495932393
Short name T13
Test name
Test status
Simulation time 1334116057 ps
CPU time 15.46 seconds
Started Aug 25 04:10:47 AM UTC 24
Finished Aug 25 04:11:05 AM UTC 24
Peak memory 225476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495932393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2495932393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3492282643
Short name T186
Test name
Test status
Simulation time 1547713378 ps
CPU time 36.99 seconds
Started Aug 25 04:10:49 AM UTC 24
Finished Aug 25 04:11:48 AM UTC 24
Peak memory 228488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349228264
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.3492282643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3805516653
Short name T319
Test name
Test status
Simulation time 8424781427 ps
CPU time 324.64 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:16:29 AM UTC 24
Peak memory 246356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3805516653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3805516653
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1916539441
Short name T66
Test name
Test status
Simulation time 169476619 ps
CPU time 7.34 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:08 AM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916539441 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1916539441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3229891388
Short name T333
Test name
Test status
Simulation time 3589233098 ps
CPU time 392.81 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:17:38 AM UTC 24
Peak memory 259412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229891388 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.3229891388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.670078753
Short name T57
Test name
Test status
Simulation time 1576825128 ps
CPU time 20.57 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:21 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670078753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.670078753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3741063699
Short name T122
Test name
Test status
Simulation time 1064043259 ps
CPU time 11.01 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:12 AM UTC 24
Peak memory 228456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741063699 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3741063699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.87489026
Short name T60
Test name
Test status
Simulation time 271901594 ps
CPU time 12.19 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:13 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87489026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_
TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.87489026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1571745998
Short name T23
Test name
Test status
Simulation time 9471845714 ps
CPU time 127.08 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:13:09 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1571745998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1571745998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1009510586
Short name T147
Test name
Test status
Simulation time 989328392 ps
CPU time 13.77 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:24 AM UTC 24
Peak memory 228072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009510586 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1009510586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1990112774
Short name T364
Test name
Test status
Simulation time 45809709876 ps
CPU time 639.32 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:21:49 AM UTC 24
Peak memory 259144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990112774 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.1990112774
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.2885255286
Short name T37
Test name
Test status
Simulation time 1654538215 ps
CPU time 19.08 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:20 AM UTC 24
Peak memory 228400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885255286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2885255286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3785686393
Short name T117
Test name
Test status
Simulation time 691080117 ps
CPU time 11.36 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:12 AM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785686393 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3785686393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3420826885
Short name T15
Test name
Test status
Simulation time 184517158 ps
CPU time 10.55 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:11 AM UTC 24
Peak memory 225396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420826885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3420826885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2952146308
Short name T188
Test name
Test status
Simulation time 2110034940 ps
CPU time 48.72 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:50 AM UTC 24
Peak memory 228472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295214630
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.2952146308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1629949439
Short name T338
Test name
Test status
Simulation time 5770095694 ps
CPU time 408.96 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:18:05 AM UTC 24
Peak memory 238836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1629949439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1629949439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4035449421
Short name T148
Test name
Test status
Simulation time 1648962716 ps
CPU time 11.47 seconds
Started Aug 25 04:10:56 AM UTC 24
Finished Aug 25 04:11:22 AM UTC 24
Peak memory 227660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035449421 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4035449421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2078063944
Short name T27
Test name
Test status
Simulation time 2482183070 ps
CPU time 201.04 seconds
Started Aug 25 04:10:53 AM UTC 24
Finished Aug 25 04:14:28 AM UTC 24
Peak memory 257068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078063944 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.2078063944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1790048705
Short name T143
Test name
Test status
Simulation time 495162297 ps
CPU time 13.21 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:24 AM UTC 24
Peak memory 228392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790048705 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1790048705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3989873124
Short name T145
Test name
Test status
Simulation time 186110894 ps
CPU time 15.09 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:26 AM UTC 24
Peak memory 225668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989873124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3989873124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2321866604
Short name T89
Test name
Test status
Simulation time 1059312690 ps
CPU time 25.09 seconds
Started Aug 25 04:10:52 AM UTC 24
Finished Aug 25 04:11:36 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232186660
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.2321866604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1185974717
Short name T77
Test name
Test status
Simulation time 172925546 ps
CPU time 11.03 seconds
Started Aug 25 04:11:01 AM UTC 24
Finished Aug 25 04:11:21 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185974717 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1185974717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2103821816
Short name T348
Test name
Test status
Simulation time 6854952444 ps
CPU time 488.5 seconds
Started Aug 25 04:10:56 AM UTC 24
Finished Aug 25 04:19:15 AM UTC 24
Peak memory 259472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103821816 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.2103821816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3053882112
Short name T35
Test name
Test status
Simulation time 1982124234 ps
CPU time 23.09 seconds
Started Aug 25 04:10:58 AM UTC 24
Finished Aug 25 04:11:23 AM UTC 24
Peak memory 227964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053882112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3053882112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3013673199
Short name T20
Test name
Test status
Simulation time 266253048 ps
CPU time 17.08 seconds
Started Aug 25 04:10:56 AM UTC 24
Finished Aug 25 04:11:28 AM UTC 24
Peak memory 228288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013673199 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3013673199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2826619805
Short name T88
Test name
Test status
Simulation time 347906884 ps
CPU time 19 seconds
Started Aug 25 04:10:56 AM UTC 24
Finished Aug 25 04:11:30 AM UTC 24
Peak memory 228796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826619805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2826619805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4247845848
Short name T178
Test name
Test status
Simulation time 558010935 ps
CPU time 25.84 seconds
Started Aug 25 04:10:56 AM UTC 24
Finished Aug 25 04:11:37 AM UTC 24
Peak memory 228492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424784584
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.4247845848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.386488185
Short name T16
Test name
Test status
Simulation time 4122237935 ps
CPU time 41.86 seconds
Started Aug 25 04:10:59 AM UTC 24
Finished Aug 25 04:11:53 AM UTC 24
Peak memory 230904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=386488185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.rom_ctrl_stress_all_with_rand_reset.386488185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest
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