Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

450797

1

T1

22

T2

110

T7

43

full_word

286060

1

T1

2

T2

10

T7

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	736567	1			T1	24		T2	120		T7	47
auto[TlIntgErrCmd]	92	1			T76	5		T77	1		T78	4
auto[TlIntgErrData]	91	1			T76	3		T77	3		T78	1
auto[TlIntgErrBoth]	107	1			T76	2		T77	6		T78	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135703

1

T1

24

T2

120

T7

47

auto[1]

601154

1

T19

12571

T20

10139

T21

2664

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	66029	1			T1	22		T2	110		T7	43
auto[TlIntgErrNone]	partial	auto[1]	384509	1			T19	7406		T20	6486		T21	1752
auto[TlIntgErrNone]	full_word	auto[0]	69545	1			T1	2		T2	10		T7	4
auto[TlIntgErrNone]	full_word	auto[1]	216484	1			T19	5165		T20	3653		T21	912
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T76	3		T115	2		T118	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T76	2		T77	1		T78	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T115	1		T124	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T124	2		T125	3		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T115	2		T118	2		T119	2
auto[TlIntgErrData]	partial	auto[1]	33	1			T76	3		T77	3		T119	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T116	1		T120	1		T126	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T78	1		T115	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T76	1		T77	1		T78	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T76	1		T77	5		T78	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T78	1		T124	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T116	1		T127	1		T128	1