Line Coverage for Module :
rom_ctrl_mux
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 17 | 17 | 100.00 |
| CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
67 );
68 1/1 assign sel_bus_q = mubi4_t'(sel_bus_q_raw);
Tests: T1 T2 T3
69
70 prim_flop #(.Width (4), .ResetValue ({MuBi4False}))
71 u_sel_bus_qq_flop (
72 .clk_i,
73 .rst_ni,
74 .d_i (sel_bus_q),
75 .q_o (sel_bus_qq_raw)
76 );
77 1/1 assign sel_bus_qq = mubi4_t'(sel_bus_qq_raw);
Tests: T1 T2 T3
78
79 // Spot if the sel_bus_i signal or its register version has a corrupt value.
80 //
81 // SEC_CM: MUX.MUBI
82 logic sel_invalid;
83 1/1 assign sel_invalid = mubi4_test_invalid(sel_bus_i) || mubi4_test_invalid(sel_bus_q);
Tests: T1 T2 T3
84
85 // Spot if the select signal switches back to the checker once we've switched to the bus. Doing so
86 // will have no lasting effect because of how we calculate sel_bus_q) but isn't supposed to
87 // happen, so we want to trigger an alert.
88 //
89 // SEC_CM: MUX.CONSISTENCY
90 logic sel_reverted;
91 1/1 assign sel_reverted = mubi4_test_true_loose(sel_bus_q) & mubi4_test_false_loose(sel_bus_i);
Tests: T1 T2 T3
92
93 // Spot if the sel_bus_q signal has reverted somehow.
94 //
95 // SEC_CM: MUX.CONSISTENCY
96 logic sel_q_reverted;
97 1/1 assign sel_q_reverted = mubi4_test_true_loose(sel_bus_qq) & mubi4_test_false_loose(sel_bus_q);
Tests: T1 T2 T3
98
99 logic alert_q, alert_d;
100
101 1/1 assign alert_d = sel_invalid | sel_reverted | sel_q_reverted;
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin
104 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
105 1/1 alert_q <= 0;
Tests: T1 T2 T3
106 end else begin
107 1/1 alert_q <= alert_q | alert_d;
Tests: T1 T2 T3
108 end
109 end
110
111 1/1 assign alert_o = alert_q;
Tests: T1 T2 T3
112
113 // The bus can have access every cycle, from when the select signal switches to the bus.
114 1/1 assign bus_gnt_o = mubi4_test_true_strict(sel_bus_i);
Tests: T1 T2 T3
115 1/1 assign bus_rdata_o = rom_clr_rdata_i;
Tests: T1 T2 T3
116 // A high rom_rvalid_i is a response to a bus request if the select signal pointed at the bus on
117 // the previous cycle.
118 1/1 assign bus_rvalid_o = mubi4_test_true_strict(sel_bus_q) & rom_rvalid_i;
Tests: T1 T2 T3
119
120 1/1 assign chk_rdata_o = rom_scr_rdata_i;
Tests: T1 T2 T3
121
122 1/1 assign rom_req_o = mubi4_test_true_strict(sel_bus_i) ? bus_req_i : chk_req_i;
Tests: T1 T2 T3
123 1/1 assign rom_rom_addr_o = mubi4_test_true_strict(sel_bus_i) ? bus_rom_addr_i : chk_addr_i;
Tests: T1 T2 T3
124 1/1 assign rom_prince_addr_o = mubi4_test_true_strict(sel_bus_i) ? bus_prince_addr_i : chk_addr_i;
Tests: T1 T2 T3
Cond Coverage for Module :
rom_ctrl_mux
| Total | Covered | Percent |
|---|
| Conditions | 7 | 6 | 85.71 |
| Logical | 7 | 6 | 85.71 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 101
EXPRESSION (sel_invalid | sel_reverted | sel_q_reverted)
-----1----- ------2----- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Not Covered | |
| 0 | 1 | 0 | Covered | T24,T25,T26 |
| 1 | 0 | 0 | Covered | T27,T28,T29 |
LINE 107
EXPRESSION (alert_q | alert_d)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T24,T28 |
| 1 | 0 | Covered | T25,T26,T30 |
Branch Coverage for Module :
rom_ctrl_mux
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
104 if (!rst_ni) begin
-1-
105 alert_q <= 0;
==>
106 end else begin
107 alert_q <= alert_q | alert_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |