| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.42 | 96.89 | 92.13 | 97.68 | 100.00 | 98.28 | 97.90 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 71.41 | 71.41 | 93.06 | 93.06 | 83.29 | 83.29 | 59.40 | 59.40 | 40.00 | 40.00 | 92.07 | 92.07 | 94.60 | 94.60 | 37.47 | 37.47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1504987056 |
| 85.12 | 13.71 | 96.29 | 3.23 | 85.96 | 2.67 | 84.66 | 25.26 | 53.33 | 13.33 | 94.14 | 2.07 | 94.60 | 0.00 | 86.89 | 49.41 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1049408979 |
| 92.05 | 6.92 | 96.41 | 0.12 | 88.34 | 2.39 | 89.38 | 4.72 | 93.33 | 40.00 | 94.83 | 0.69 | 94.90 | 0.30 | 87.12 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.83873883 |
| 93.35 | 1.31 | 96.65 | 0.24 | 89.33 | 0.98 | 93.35 | 3.97 | 93.33 | 0.00 | 96.55 | 1.72 | 95.50 | 0.60 | 88.76 | 1.64 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3803362360 |
| 94.51 | 1.15 | 96.89 | 0.24 | 90.03 | 0.70 | 93.35 | 0.00 | 93.33 | 0.00 | 97.59 | 1.03 | 95.50 | 0.00 | 94.85 | 6.09 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.464201543 |
| 95.59 | 1.08 | 96.89 | 0.00 | 90.45 | 0.42 | 93.35 | 0.00 | 100.00 | 6.67 | 97.59 | 0.00 | 95.50 | 0.00 | 95.32 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1236286146 |
| 96.19 | 0.61 | 96.89 | 0.00 | 90.59 | 0.14 | 96.70 | 3.35 | 100.00 | 0.00 | 97.59 | 0.00 | 96.25 | 0.75 | 95.32 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.3553987002 |
| 96.51 | 0.32 | 96.89 | 0.00 | 91.15 | 0.56 | 96.80 | 0.10 | 100.00 | 0.00 | 97.93 | 0.34 | 96.55 | 0.30 | 96.25 | 0.94 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.687517651 |
| 96.70 | 0.19 | 96.89 | 0.00 | 91.29 | 0.14 | 96.80 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 97.75 | 1.20 | 96.25 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3869484574 |
| 96.81 | 0.11 | 96.89 | 0.00 | 91.43 | 0.14 | 97.08 | 0.27 | 100.00 | 0.00 | 98.28 | 0.34 | 97.75 | 0.00 | 96.25 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.955098142 |
| 96.91 | 0.10 | 96.89 | 0.00 | 91.43 | 0.00 | 97.08 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 96.96 | 0.70 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1210935562 |
| 97.01 | 0.10 | 96.89 | 0.00 | 91.99 | 0.56 | 97.20 | 0.12 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 96.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3908184676 |
| 97.08 | 0.07 | 96.89 | 0.00 | 91.99 | 0.00 | 97.20 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 97.42 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3203067777 |
| 97.14 | 0.07 | 96.89 | 0.00 | 91.99 | 0.00 | 97.20 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 97.89 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.2378216306 |
| 97.20 | 0.06 | 96.89 | 0.00 | 92.13 | 0.14 | 97.48 | 0.27 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 97.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1453043483 |
| 97.24 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.48 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 98.13 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3075951055 |
| 97.27 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.48 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 98.36 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.750595547 |
| 97.30 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.48 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 98.59 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3913000992 |
| 97.34 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.48 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3476973336 |
| 97.37 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.48 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3232522073 |
| 97.39 | 0.02 | 96.89 | 0.00 | 92.13 | 0.00 | 97.48 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1132636966 |
| 97.41 | 0.02 | 96.89 | 0.00 | 92.13 | 0.00 | 97.63 | 0.15 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1937513896 |
| 97.42 | 0.01 | 96.89 | 0.00 | 92.13 | 0.00 | 97.68 | 0.05 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3688333059 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.149784399 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2389331945 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1884497135 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2891682299 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3558014164 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2888275645 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3210277804 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3442029492 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4186546442 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2163938794 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3696823525 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2290825692 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4006410598 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2545733256 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2671384394 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2036365197 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4018637404 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3688982896 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2376503575 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1192236895 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.461094312 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3907563112 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3513422078 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2343866614 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4053859451 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1345071383 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4192053285 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3972284829 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.887029997 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2816512062 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.872432866 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3444167227 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3368174553 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1996560113 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1218561674 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4695266 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.359575035 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3691936714 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2152019686 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.156446060 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4172341867 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3788412564 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2478171743 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3272788071 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1185341529 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.853762750 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.279988957 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3426652857 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.51946752 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4066748057 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2219359731 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.754567552 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3963330575 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3367711794 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1960639423 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.398516885 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4058537480 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1238872832 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3049028784 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2726329320 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.744365770 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3939289324 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.546049912 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.997259898 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1993851961 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.846323326 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1682328835 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3900002808 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.100783854 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.277133369 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2574483625 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1415442403 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3257957381 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4226360185 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2390617738 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.357012395 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3133938473 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3522509454 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.547576740 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1711266156 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3212003530 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2371404585 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.812127676 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1169419605 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3640841771 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3754029889 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3950638864 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3565753553 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1927537533 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1058630060 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2524804027 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.565825618 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4138284385 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2235670190 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.339159888 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.444084542 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3912855049 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4173173512 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2214418551 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2858555839 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2891232636 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1987599317 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.493064350 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2241225759 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3463719717 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.308671527 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3577323993 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.421116037 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1406034409 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.328615754 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2637757948 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.767861891 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3339612187 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1702773657 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2189679910 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4006847471 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2199743584 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.542153905 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3690648607 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3204210304 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2181152183 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4046771068 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1055926408 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1831994723 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.649213175 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1846562159 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3024217414 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2550839649 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.581670536 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3960855114 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4144118551 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1420572323 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3289511189 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3295843376 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3786776235 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3241714450 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1316416497 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1824739207 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4170270572 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1157675657 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.1039359685 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3497439993 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3401644556 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2347414089 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.702522647 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.604694103 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4260493269 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.863137516 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1795091348 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1272587460 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.502504528 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1606095202 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.265226569 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2353201910 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.549695239 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3971973006 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3725196650 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1083834648 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3838660356 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3217412829 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.75430349 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.870559346 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1035515870 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1717543036 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3367802229 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2131984307 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1872121546 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.215417006 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2349942968 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1261710733 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1855539981 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2641700207 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3375407084 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3221272451 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3365451389 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3373988801 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2122489553 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3385213515 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3478860834 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1817901763 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.4275886826 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.375002140 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.255723317 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1310020246 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2529882293 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1578075345 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3512498248 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3147441133 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2108083380 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.3357150148 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3121262469 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.4070214705 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2065241133 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3314185941 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.533631968 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.414778669 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1987927088 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.3684953136 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3857506230 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1746766670 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1478316415 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1620396109 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3388895296 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.961169432 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2371036557 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1914926120 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.55669996 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1556171585 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3456701463 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.4284806910 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2409699861 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.514667926 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.2688082360 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1907910599 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1176253503 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2617388771 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2207216498 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1662847185 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.59127690 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1792713667 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.1280338808 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2286902491 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.997485939 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1673190687 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.1353029068 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3254654927 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.2132139711 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2690022371 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.22774928 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.1660979448 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2380275247 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2608859490 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2990953873 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2202617431 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2506044317 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2145298706 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1752772659 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1272361737 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3402080506 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2417629975 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3697224389 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2957911273 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3278521207 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1169938858 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1027934776 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1076818730 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3341142555 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1856848663 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1416611245 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.251884180 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.4023362709 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1284622449 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3346898259 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.51626006 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1514453169 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2667883214 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.2761296056 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3494721488 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2349083973 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2625938726 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.947728227 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.283512254 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.14578857 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3917698309 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.509456464 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.644461769 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1450590511 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.668348397 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.2757035168 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1303605827 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1485057379 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.4139729755 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2222164769 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.789107401 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3132979060 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3521139226 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.916999324 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3919097810 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1030157291 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2893937312 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2340789171 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1387067979 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1672411270 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.991136281 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4073868818 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3088713553 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.3602576725 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.4220901224 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2024235206 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.670481258 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1410857157 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2882216448 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.3807148354 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2764134773 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2276094011 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.3995590417 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.516630964 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2618747069 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.3956035984 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3910819300 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.4171385693 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.518569509 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.4041593628 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3126121006 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2845383670 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4061376581 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.840375070 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2450615873 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.2878928180 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1058231063 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3401164272 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4202548075 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3726017187 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1549224351 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3719639892 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3792664853 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.249140137 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1532227860 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3713005786 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1624026735 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1923471169 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2501877344 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2707000758 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3674248127 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3264506468 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4244106251 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2592828987 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2051484534 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.1020558727 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1588373554 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.3661565587 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3845509608 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3059876784 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1707387667 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3897244763 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.4285372868 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2845605959 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3727097376 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1732193410 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2881074533 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3964946346 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.1010640148 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2980364408 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1643239636 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3112180071 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3979725837 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2159717048 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3616980360 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.488968776 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3524559426 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.314288676 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.2706117742 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.225873325 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.3416697136 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2102241772 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3721018578 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4262447373 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.4197925444 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.718057599 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.4128659845 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.441889 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.7980183 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.225613390 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.513705733 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1236775955 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.2654338430 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2616778698 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.4066690640 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2581163364 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3092267396 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.353063214 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1369273514 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1397099083 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.177818006 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.494577255 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2126719557 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.3784947163 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3672781239 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2666494152 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3355887048 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2993550383 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.370259578 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2680734978 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3288278756 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.548373605 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1078616113 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3530605947 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1042826147 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.2889890076 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3605948316 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2726132190 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3781979290 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3088054867 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1554395586 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2498546869 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.4251575764 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.88086841 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2656383731 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3546028996 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.324407230 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2453829041 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.589337130 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.999421471 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3886374691 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2277009849 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3084873369 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1665002101 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2900689370 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2973115487 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4108592189 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.488778806 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3723250467 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3428170584 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.369844928 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3621648731 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1898149107 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1121976709 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1554509787 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1025243894 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2068564290 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.634702334 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2180446901 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.541645606 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4219710304 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3265824072 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1642472123 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2755821997 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3520529570 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3826313791 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1288841291 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1696042302 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.1039359685 | Aug 28 09:58:59 PM UTC 24 | Aug 28 09:59:17 PM UTC 24 | 1119376996 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4170270572 | Aug 28 09:59:17 PM UTC 24 | Aug 28 09:59:35 PM UTC 24 | 270912329 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3688333059 | Aug 28 09:59:03 PM UTC 24 | Aug 28 09:59:44 PM UTC 24 | 1095066059 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1316416497 | Aug 28 09:59:39 PM UTC 24 | Aug 28 09:59:51 PM UTC 24 | 331708126 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3803362360 | Aug 28 09:59:28 PM UTC 24 | Aug 28 10:00:00 PM UTC 24 | 503301361 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.702522647 | Aug 28 09:59:45 PM UTC 24 | Aug 28 10:00:04 PM UTC 24 | 1156689187 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.2378216306 | Aug 28 09:59:53 PM UTC 24 | Aug 28 10:00:13 PM UTC 24 | 2634567941 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1504987056 | Aug 28 09:59:33 PM UTC 24 | Aug 28 10:00:26 PM UTC 24 | 2567914100 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3497439993 | Aug 28 10:00:14 PM UTC 24 | Aug 28 10:00:26 PM UTC 24 | 174417142 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3401644556 | Aug 28 10:00:08 PM UTC 24 | Aug 28 10:00:35 PM UTC 24 | 508050266 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.961169432 | Aug 28 10:00:27 PM UTC 24 | Aug 28 10:00:40 PM UTC 24 | 5153264841 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.3553987002 | Aug 28 09:59:46 PM UTC 24 | Aug 28 10:00:42 PM UTC 24 | 1579977042 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1620396109 | Aug 28 10:00:30 PM UTC 24 | Aug 28 10:00:46 PM UTC 24 | 688643049 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3908184676 | Aug 28 10:00:43 PM UTC 24 | Aug 28 10:00:57 PM UTC 24 | 2351195696 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.2757035168 | Aug 28 10:00:46 PM UTC 24 | Aug 28 10:01:02 PM UTC 24 | 362738605 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1478316415 | Aug 28 10:00:42 PM UTC 24 | Aug 28 10:01:11 PM UTC 24 | 1964957288 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2371036557 | Aug 28 10:00:27 PM UTC 24 | Aug 28 10:01:15 PM UTC 24 | 10381528412 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.668348397 | Aug 28 10:01:02 PM UTC 24 | Aug 28 10:01:21 PM UTC 24 | 991888311 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1303605827 | Aug 28 10:00:57 PM UTC 24 | Aug 28 10:01:31 PM UTC 24 | 6463065140 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.509456464 | Aug 28 10:01:32 PM UTC 24 | Aug 28 10:01:42 PM UTC 24 | 498689340 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1450590511 | Aug 28 10:01:16 PM UTC 24 | Aug 28 10:01:48 PM UTC 24 | 498493000 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3897244763 | Aug 28 10:01:43 PM UTC 24 | Aug 28 10:02:00 PM UTC 24 | 1028424367 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.4285372868 | Aug 28 10:01:48 PM UTC 24 | Aug 28 10:02:13 PM UTC 24 | 696861144 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1157675657 | Aug 28 09:59:35 PM UTC 24 | Aug 28 10:02:14 PM UTC 24 | 598040190 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3059876784 | Aug 28 10:02:00 PM UTC 24 | Aug 28 10:02:15 PM UTC 24 | 179183583 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.955098142 | Aug 28 10:02:13 PM UTC 24 | Aug 28 10:02:41 PM UTC 24 | 349657982 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.3661565587 | Aug 28 10:02:36 PM UTC 24 | Aug 28 10:02:47 PM UTC 24 | 253086223 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1049408979 | Aug 28 10:00:08 PM UTC 24 | Aug 28 10:02:50 PM UTC 24 | 10695497786 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2453829041 | Aug 28 10:02:42 PM UTC 24 | Aug 28 10:02:58 PM UTC 24 | 643831651 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.324407230 | Aug 28 10:02:51 PM UTC 24 | Aug 28 10:03:03 PM UTC 24 | 3471312798 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1914926120 | Aug 28 10:00:42 PM UTC 24 | Aug 28 10:03:09 PM UTC 24 | 6163065479 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.589337130 | Aug 28 10:02:48 PM UTC 24 | Aug 28 10:03:20 PM UTC 24 | 551367436 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3546028996 | Aug 28 10:02:59 PM UTC 24 | Aug 28 10:03:25 PM UTC 24 | 1014938316 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2656383731 | Aug 28 10:03:11 PM UTC 24 | Aug 28 10:03:25 PM UTC 24 | 615057345 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.687517651 | Aug 28 10:01:22 PM UTC 24 | Aug 28 10:03:26 PM UTC 24 | 236763972 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2900689370 | Aug 28 10:03:11 PM UTC 24 | Aug 28 10:03:29 PM UTC 24 | 257557411 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3886374691 | Aug 28 10:03:27 PM UTC 24 | Aug 28 10:03:37 PM UTC 24 | 169605438 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1665002101 | Aug 28 10:03:22 PM UTC 24 | Aug 28 10:03:40 PM UTC 24 | 265959036 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3621648731 | Aug 28 10:03:29 PM UTC 24 | Aug 28 10:03:45 PM UTC 24 | 2870614162 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.369844928 | Aug 28 10:03:41 PM UTC 24 | Aug 28 10:03:59 PM UTC 24 | 361057120 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3084873369 | Aug 28 10:03:27 PM UTC 24 | Aug 28 10:04:03 PM UTC 24 | 504800334 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2973115487 | Aug 28 10:03:22 PM UTC 24 | Aug 28 10:04:23 PM UTC 24 | 733193115 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1898149107 | Aug 28 10:03:38 PM UTC 24 | Aug 28 10:04:24 PM UTC 24 | 798767891 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.488778806 | Aug 28 10:04:17 PM UTC 24 | Aug 28 10:04:29 PM UTC 24 | 591733671 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3428170584 | Aug 28 10:04:00 PM UTC 24 | Aug 28 10:04:31 PM UTC 24 | 1907514199 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.541645606 | Aug 28 10:04:17 PM UTC 24 | Aug 28 10:04:33 PM UTC 24 | 422725923 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2180446901 | Aug 28 10:04:17 PM UTC 24 | Aug 28 10:04:35 PM UTC 24 | 4232444378 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.634702334 | Aug 28 10:04:24 PM UTC 24 | Aug 28 10:04:41 PM UTC 24 | 1284350680 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1554509787 | Aug 28 10:04:33 PM UTC 24 | Aug 28 10:04:46 PM UTC 24 | 689418143 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1453043483 | Aug 28 10:02:56 PM UTC 24 | Aug 28 10:04:48 PM UTC 24 | 4051236284 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3826313791 | Aug 28 10:04:35 PM UTC 24 | Aug 28 10:04:49 PM UTC 24 | 2322030424 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3388895296 | Aug 28 10:00:42 PM UTC 24 | Aug 28 10:04:56 PM UTC 24 | 1420656035 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1121976709 | Aug 28 10:04:04 PM UTC 24 | Aug 28 10:04:59 PM UTC 24 | 14039750946 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2068564290 | Aug 28 10:04:29 PM UTC 24 | Aug 28 10:04:59 PM UTC 24 | 661218547 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1485057379 | Aug 28 10:01:19 PM UTC 24 | Aug 28 10:05:00 PM UTC 24 | 17940779918 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3520529570 | Aug 28 10:04:47 PM UTC 24 | Aug 28 10:05:01 PM UTC 24 | 210564669 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2347414089 | Aug 28 10:00:14 PM UTC 24 | Aug 28 10:05:03 PM UTC 24 | 503615718 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.83873883 | Aug 28 10:00:01 PM UTC 24 | Aug 28 10:05:03 PM UTC 24 | 3403755930 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1824739207 | Aug 28 09:59:23 PM UTC 24 | Aug 28 10:05:07 PM UTC 24 | 5737486382 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1288841291 | Aug 28 10:04:42 PM UTC 24 | Aug 28 10:05:12 PM UTC 24 | 1032840425 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1795091348 | Aug 28 10:05:01 PM UTC 24 | Aug 28 10:05:12 PM UTC 24 | 730392268 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3265824072 | Aug 28 10:05:00 PM UTC 24 | Aug 28 10:05:14 PM UTC 24 | 248428642 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1272587460 | Aug 28 10:05:00 PM UTC 24 | Aug 28 10:05:17 PM UTC 24 | 795603371 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2755821997 | Aug 28 10:04:50 PM UTC 24 | Aug 28 10:05:19 PM UTC 24 | 1326938902 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.604694103 | Aug 28 10:05:08 PM UTC 24 | Aug 28 10:05:20 PM UTC 24 | 688613250 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.863137516 | Aug 28 10:05:04 PM UTC 24 | Aug 28 10:05:26 PM UTC 24 | 650254256 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2353201910 | Aug 28 10:05:13 PM UTC 24 | Aug 28 10:05:29 PM UTC 24 | 1081708262 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4108592189 | Aug 28 10:03:27 PM UTC 24 | Aug 28 10:05:31 PM UTC 24 | 1424316732 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.549695239 | Aug 28 10:05:12 PM UTC 24 | Aug 28 10:05:31 PM UTC 24 | 200738543 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1707387667 | Aug 28 10:02:16 PM UTC 24 | Aug 28 10:05:32 PM UTC 24 | 632705763 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.502504528 | Aug 28 10:05:22 PM UTC 24 | Aug 28 10:05:35 PM UTC 24 | 2743585250 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3838660356 | Aug 28 10:05:29 PM UTC 24 | Aug 28 10:05:47 PM UTC 24 | 517984717 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.265226569 | Aug 28 10:05:18 PM UTC 24 | Aug 28 10:05:50 PM UTC 24 | 344090986 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1717543036 | Aug 28 10:05:36 PM UTC 24 | Aug 28 10:05:51 PM UTC 24 | 701375834 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1083834648 | Aug 28 10:05:30 PM UTC 24 | Aug 28 10:05:53 PM UTC 24 | 1306887448 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3971973006 | Aug 28 10:05:33 PM UTC 24 | Aug 28 10:05:57 PM UTC 24 | 1026043516 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3476973336 | Aug 28 10:05:20 PM UTC 24 | Aug 28 10:06:06 PM UTC 24 | 880751509 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.870559346 | Aug 28 10:05:54 PM UTC 24 | Aug 28 10:06:08 PM UTC 24 | 1658256059 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1937513896 | Aug 28 10:05:04 PM UTC 24 | Aug 28 10:06:09 PM UTC 24 | 983107010 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.999421471 | Aug 28 10:03:04 PM UTC 24 | Aug 28 10:06:11 PM UTC 24 | 3561416322 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3217412829 | Aug 28 10:05:22 PM UTC 24 | Aug 28 10:06:15 PM UTC 24 | 846198633 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3367802229 | Aug 28 10:05:33 PM UTC 24 | Aug 28 10:06:18 PM UTC 24 | 797218320 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1035515870 | Aug 28 10:05:51 PM UTC 24 | Aug 28 10:06:20 PM UTC 24 | 346050022 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2845605959 | Aug 28 10:02:15 PM UTC 24 | Aug 28 10:06:24 PM UTC 24 | 6447152449 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1261710733 | Aug 28 10:06:07 PM UTC 24 | Aug 28 10:06:24 PM UTC 24 | 715559719 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1872121546 | Aug 28 10:06:16 PM UTC 24 | Aug 28 10:06:30 PM UTC 24 | 170963000 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3373988801 | Aug 28 10:06:21 PM UTC 24 | Aug 28 10:06:36 PM UTC 24 | 178979049 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1855539981 | Aug 28 10:05:58 PM UTC 24 | Aug 28 10:06:37 PM UTC 24 | 559350496 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2349942968 | Aug 28 10:06:09 PM UTC 24 | Aug 28 10:06:41 PM UTC 24 | 1377116935 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3375407084 | Aug 28 10:06:37 PM UTC 24 | Aug 28 10:06:51 PM UTC 24 | 170744457 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3365451389 | Aug 28 10:06:26 PM UTC 24 | Aug 28 10:06:54 PM UTC 24 | 347175252 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.375002140 | Aug 28 10:06:41 PM UTC 24 | Aug 28 10:07:00 PM UTC 24 | 179005198 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.255723317 | Aug 28 10:06:38 PM UTC 24 | Aug 28 10:07:01 PM UTC 24 | 1095144778 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3478860834 | Aug 28 10:07:01 PM UTC 24 | Aug 28 10:07:17 PM UTC 24 | 1023567950 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3512498248 | Aug 28 10:07:10 PM UTC 24 | Aug 28 10:07:27 PM UTC 24 | 187970888 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.4275886826 | Aug 28 10:06:56 PM UTC 24 | Aug 28 10:07:28 PM UTC 24 | 2071090608 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1310020246 | Aug 28 10:06:56 PM UTC 24 | Aug 28 10:07:30 PM UTC 24 | 936576004 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2122489553 | Aug 28 10:06:19 PM UTC 24 | Aug 28 10:07:32 PM UTC 24 | 13960497591 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.75430349 | Aug 28 10:05:32 PM UTC 24 | Aug 28 10:07:45 PM UTC 24 | 4454463648 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2529882293 | Aug 28 10:07:31 PM UTC 24 | Aug 28 10:07:46 PM UTC 24 | 507809799 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.644461769 | Aug 28 10:01:11 PM UTC 24 | Aug 28 10:07:49 PM UTC 24 | 10917580408 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1578075345 | Aug 28 10:07:27 PM UTC 24 | Aug 28 10:07:59 PM UTC 24 | 2150144962 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2065241133 | Aug 28 10:07:46 PM UTC 24 | Aug 28 10:08:05 PM UTC 24 | 274409931 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3147441133 | Aug 28 10:07:02 PM UTC 24 | Aug 28 10:08:07 PM UTC 24 | 855117509 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1696042302 | Aug 28 10:04:57 PM UTC 24 | Aug 28 10:08:17 PM UTC 24 | 13100835486 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1236286146 | Aug 28 10:05:48 PM UTC 24 | Aug 28 10:08:18 PM UTC 24 | 7016911300 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1025243894 | Aug 28 10:04:25 PM UTC 24 | Aug 28 10:08:19 PM UTC 24 | 6807809721 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3314185941 | Aug 28 10:07:33 PM UTC 24 | Aug 28 10:08:19 PM UTC 24 | 3990667706 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3723250467 | Aug 28 10:03:46 PM UTC 24 | Aug 28 10:08:19 PM UTC 24 | 24587157833 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4219710304 | Aug 28 10:04:32 PM UTC 24 | Aug 28 10:08:19 PM UTC 24 | 3671429739 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.4070214705 | Aug 28 10:07:50 PM UTC 24 | Aug 28 10:08:21 PM UTC 24 | 1986338047 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.3357150148 | Aug 28 10:08:06 PM UTC 24 | Aug 28 10:08:29 PM UTC 24 | 3953650270 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1987927088 | Aug 28 10:08:15 PM UTC 24 | Aug 28 10:08:31 PM UTC 24 | 789136939 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.533631968 | Aug 28 10:08:20 PM UTC 24 | Aug 28 10:08:35 PM UTC 24 | 1547088401 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2131984307 | Aug 28 10:05:52 PM UTC 24 | Aug 28 10:08:35 PM UTC 24 | 11750430889 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.4284806910 | Aug 28 10:08:20 PM UTC 24 | Aug 28 10:08:40 PM UTC 24 | 627486132 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3385213515 | Aug 28 10:06:31 PM UTC 24 | Aug 28 10:08:41 PM UTC 24 | 2177773771 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.3684953136 | Aug 28 10:08:15 PM UTC 24 | Aug 28 10:08:43 PM UTC 24 | 206555002 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1642472123 | Aug 28 10:04:49 PM UTC 24 | Aug 28 10:08:43 PM UTC 24 | 11813771302 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2108083380 | Aug 28 10:07:28 PM UTC 24 | Aug 28 10:08:47 PM UTC 24 | 1684006266 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.55669996 | Aug 28 10:08:35 PM UTC 24 | Aug 28 10:08:49 PM UTC 24 | 622697399 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.414778669 | Aug 28 10:08:19 PM UTC 24 | Aug 28 10:08:51 PM UTC 24 | 1181345976 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3456701463 | Aug 28 10:08:30 PM UTC 24 | Aug 28 10:08:52 PM UTC 24 | 1833345258 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1606095202 | Aug 28 10:05:15 PM UTC 24 | Aug 28 10:09:00 PM UTC 24 | 4655737773 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.2688082360 | Aug 28 10:08:48 PM UTC 24 | Aug 28 10:09:01 PM UTC 24 | 662023836 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3845509608 | Aug 28 10:02:01 PM UTC 24 | Aug 28 10:09:08 PM UTC 24 | 19386963764 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2617388771 | Aug 28 10:08:40 PM UTC 24 | Aug 28 10:09:09 PM UTC 24 | 4150203308 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1176253503 | Aug 28 10:08:44 PM UTC 24 | Aug 28 10:09:11 PM UTC 24 | 1375887701 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2286902491 | Aug 28 10:08:54 PM UTC 24 | Aug 28 10:09:12 PM UTC 24 | 2582374223 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2207216498 | Aug 28 10:08:36 PM UTC 24 | Aug 28 10:09:14 PM UTC 24 | 2286210520 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.215417006 | Aug 28 10:06:09 PM UTC 24 | Aug 28 10:09:18 PM UTC 24 | 3836464701 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.59127690 | Aug 28 10:09:04 PM UTC 24 | Aug 28 10:09:19 PM UTC 24 | 250432691 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.997485939 | Aug 28 10:08:53 PM UTC 24 | Aug 28 10:09:25 PM UTC 24 | 3084459369 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2277009849 | Aug 28 10:03:25 PM UTC 24 | Aug 28 10:09:26 PM UTC 24 | 23715301398 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.1280338808 | Aug 28 10:08:54 PM UTC 24 | Aug 28 10:09:27 PM UTC 24 | 336056574 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2690022371 | Aug 28 10:09:09 PM UTC 24 | Aug 28 10:09:28 PM UTC 24 | 730533532 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.1353029068 | Aug 28 10:09:15 PM UTC 24 | Aug 28 10:09:28 PM UTC 24 | 459994300 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1746766670 | Aug 28 10:00:36 PM UTC 24 | Aug 28 10:09:30 PM UTC 24 | 7628735694 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2990953873 | Aug 28 10:09:20 PM UTC 24 | Aug 28 10:09:35 PM UTC 24 | 191035104 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.2132139711 | Aug 28 10:09:11 PM UTC 24 | Aug 28 10:09:35 PM UTC 24 | 347092578 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1169938858 | Aug 28 10:09:41 PM UTC 24 | Aug 28 10:10:04 PM UTC 24 | 6183573283 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2409699861 | Aug 28 10:08:20 PM UTC 24 | Aug 28 10:09:37 PM UTC 24 | 6244688608 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3221272451 | Aug 28 10:06:25 PM UTC 24 | Aug 28 10:09:37 PM UTC 24 | 2504033365 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.1660979448 | Aug 28 10:09:28 PM UTC 24 | Aug 28 10:09:40 PM UTC 24 | 660244981 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.22774928 | Aug 28 10:09:04 PM UTC 24 | Aug 28 10:09:41 PM UTC 24 | 1167228333 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2641700207 | Aug 28 10:06:11 PM UTC 24 | Aug 28 10:09:43 PM UTC 24 | 16502268299 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3402080506 | Aug 28 10:09:28 PM UTC 24 | Aug 28 10:09:45 PM UTC 24 | 696163086 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2145298706 | Aug 28 10:09:36 PM UTC 24 | Aug 28 10:09:46 PM UTC 24 | 772373458 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2608859490 | Aug 28 10:09:26 PM UTC 24 | Aug 28 10:09:47 PM UTC 24 | 332197509 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1272361737 | Aug 28 10:09:31 PM UTC 24 | Aug 28 10:09:52 PM UTC 24 | 675674094 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1673190687 | Aug 28 10:09:04 PM UTC 24 | Aug 28 10:09:52 PM UTC 24 | 22595801005 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1027934776 | Aug 28 10:09:38 PM UTC 24 | Aug 28 10:09:55 PM UTC 24 | 696687238 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2957911273 | Aug 28 10:09:44 PM UTC 24 | Aug 28 10:09:59 PM UTC 24 | 251832086 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4260493269 | Aug 28 10:05:02 PM UTC 24 | Aug 28 10:10:01 PM UTC 24 | 16182481096 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.251884180 | Aug 28 10:09:47 PM UTC 24 | Aug 28 10:10:04 PM UTC 24 | 255443991 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3341142555 | Aug 28 10:09:56 PM UTC 24 | Aug 28 10:10:08 PM UTC 24 | 340767086 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2417629975 | Aug 28 10:09:28 PM UTC 24 | Aug 28 10:10:09 PM UTC 24 | 377859367 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2202617431 | Aug 28 10:09:19 PM UTC 24 | Aug 28 10:10:10 PM UTC 24 | 567558983 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2667883214 | Aug 28 10:10:01 PM UTC 24 | Aug 28 10:10:14 PM UTC 24 | 699859210 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1416611245 | Aug 28 10:09:52 PM UTC 24 | Aug 28 10:10:16 PM UTC 24 | 1376517033 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.514667926 | Aug 28 10:08:31 PM UTC 24 | Aug 28 10:10:21 PM UTC 24 | 6110317723 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.2761296056 | Aug 28 10:09:59 PM UTC 24 | Aug 28 10:10:23 PM UTC 24 | 218010294 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3346898259 | Aug 28 10:10:09 PM UTC 24 | Aug 28 10:10:23 PM UTC 24 | 231808995 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.283512254 | Aug 28 10:10:11 PM UTC 24 | Aug 28 10:10:23 PM UTC 24 | 821381656 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1514453169 | Aug 28 10:10:05 PM UTC 24 | Aug 28 10:10:34 PM UTC 24 | 344283070 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2349083973 | Aug 28 10:10:22 PM UTC 24 | Aug 28 10:10:36 PM UTC 24 | 325656987 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3725196650 | Aug 28 10:05:29 PM UTC 24 | Aug 28 10:10:36 PM UTC 24 | 21663870869 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.14578857 | Aug 28 10:10:10 PM UTC 24 | Aug 28 10:10:37 PM UTC 24 | 1109199005 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.4023362709 | Aug 28 10:09:45 PM UTC 24 | Aug 28 10:10:38 PM UTC 24 | 2874156466 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3132979060 | Aug 28 10:10:24 PM UTC 24 | Aug 28 10:10:43 PM UTC 24 | 269023973 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1076818730 | Aug 28 10:09:37 PM UTC 24 | Aug 28 10:10:46 PM UTC 24 | 1053532009 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3521139226 | Aug 28 10:10:24 PM UTC 24 | Aug 28 10:10:48 PM UTC 24 | 751329463 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.947728227 | Aug 28 10:10:22 PM UTC 24 | Aug 28 10:10:48 PM UTC 24 | 1985345342 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.4139729755 | Aug 28 10:10:37 PM UTC 24 | Aug 28 10:10:49 PM UTC 24 | 236296689 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2340789171 | Aug 28 10:10:38 PM UTC 24 | Aug 28 10:10:52 PM UTC 24 | 679152062 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2506044317 | Aug 28 10:09:27 PM UTC 24 | Aug 28 10:11:01 PM UTC 24 | 7603378971 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3919097810 | Aug 28 10:10:49 PM UTC 24 | Aug 28 10:11:03 PM UTC 24 | 661128073 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.4220901224 | Aug 28 10:10:50 PM UTC 24 | Aug 28 10:11:07 PM UTC 24 | 553310168 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.3602576725 | Aug 28 10:10:53 PM UTC 24 | Aug 28 10:11:13 PM UTC 24 | 881018148 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1907910599 | Aug 28 10:08:42 PM UTC 24 | Aug 28 10:11:13 PM UTC 24 | 2779809789 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2893937312 | Aug 28 10:10:47 PM UTC 24 | Aug 28 10:11:18 PM UTC 24 | 333225357 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.991136281 | Aug 28 10:11:08 PM UTC 24 | Aug 28 10:11:19 PM UTC 24 | 1026283345 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.789107401 | Aug 28 10:10:35 PM UTC 24 | Aug 28 10:11:20 PM UTC 24 | 15083691936 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.3807148354 | Aug 28 10:11:14 PM UTC 24 | Aug 28 10:11:26 PM UTC 24 | 182468186 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3088713553 | Aug 28 10:11:04 PM UTC 24 | Aug 28 10:11:32 PM UTC 24 | 3086602780 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1387067979 | Aug 28 10:10:38 PM UTC 24 | Aug 28 10:11:33 PM UTC 24 | 6656760958 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.670481258 | Aug 28 10:11:27 PM UTC 24 | Aug 28 10:11:39 PM UTC 24 | 225128309 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3121262469 | Aug 28 10:07:47 PM UTC 24 | Aug 28 10:11:40 PM UTC 24 | 3866465158 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2276094011 | Aug 28 10:11:21 PM UTC 24 | Aug 28 10:11:43 PM UTC 24 | 2727816018 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2618747069 | Aug 28 10:11:34 PM UTC 24 | Aug 28 10:11:48 PM UTC 24 | 659697392 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2882216448 | Aug 28 10:11:20 PM UTC 24 | Aug 28 10:11:48 PM UTC 24 | 333570093 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2764134773 | Aug 28 10:11:13 PM UTC 24 | Aug 28 10:11:53 PM UTC 24 | 2380077453 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.3995590417 | Aug 28 10:11:49 PM UTC 24 | Aug 28 10:12:06 PM UTC 24 | 253006846 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3126121006 | Aug 28 10:11:54 PM UTC 24 | Aug 28 10:12:06 PM UTC 24 | 366975426 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1284622449 | Aug 28 10:09:53 PM UTC 24 | Aug 28 10:12:07 PM UTC 24 | 1561920095 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.916999324 | Aug 28 10:10:37 PM UTC 24 | Aug 28 10:12:07 PM UTC 24 | 32981715529 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.516630964 | Aug 28 10:11:40 PM UTC 24 | Aug 28 10:12:13 PM UTC 24 | 688862080 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3857506230 | Aug 28 10:08:20 PM UTC 24 | Aug 28 10:12:19 PM UTC 24 | 10347117193 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.4171385693 | Aug 28 10:12:09 PM UTC 24 | Aug 28 10:12:23 PM UTC 24 | 516870423 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2845383670 | Aug 28 10:11:49 PM UTC 24 | Aug 28 10:12:25 PM UTC 24 | 317338550 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.3956035984 | Aug 28 10:11:33 PM UTC 24 | Aug 28 10:12:25 PM UTC 24 | 3207726998 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1792713667 | Aug 28 10:08:54 PM UTC 24 | Aug 28 10:12:28 PM UTC 24 | 8387034090 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1058231063 | Aug 28 10:12:20 PM UTC 24 | Aug 28 10:12:35 PM UTC 24 | 2123470856 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.4041593628 | Aug 28 10:12:07 PM UTC 24 | Aug 28 10:12:37 PM UTC 24 | 662353305 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3401164272 | Aug 28 10:12:14 PM UTC 24 | Aug 28 10:12:42 PM UTC 24 | 1063308570 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1672411270 | Aug 28 10:10:49 PM UTC 24 | Aug 28 10:12:50 PM UTC 24 | 8134460055 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3917698309 | Aug 28 10:10:22 PM UTC 24 | Aug 28 10:12:51 PM UTC 24 | 19927712753 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.2878928180 | Aug 28 10:12:25 PM UTC 24 | Aug 28 10:12:57 PM UTC 24 | 1572399545 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.840375070 | Aug 28 10:12:42 PM UTC 24 | Aug 28 10:12:57 PM UTC 24 | 988742130 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3792664853 | Aug 28 10:12:42 PM UTC 24 | Aug 28 10:13:02 PM UTC 24 | 1031312929 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3726017187 | Aug 28 10:12:51 PM UTC 24 | Aug 28 10:13:03 PM UTC 24 | 660861661 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2501877344 | Aug 28 10:12:57 PM UTC 24 | Aug 28 10:13:13 PM UTC 24 | 729391242 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3719639892 | Aug 28 10:12:44 PM UTC 24 | Aug 28 10:13:15 PM UTC 24 | 1380032097 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2380275247 | Aug 28 10:09:24 PM UTC 24 | Aug 28 10:13:15 PM UTC 24 | 2907155602 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3713005786 | Aug 28 10:13:03 PM UTC 24 | Aug 28 10:13:17 PM UTC 24 | 174612721 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1662847185 | Aug 28 10:08:44 PM UTC 24 | Aug 28 10:13:19 PM UTC 24 | 4482063043 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.51626006 | Aug 28 10:10:05 PM UTC 24 | Aug 28 10:13:25 PM UTC 24 | 3683543244 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.249140137 | Aug 28 10:12:42 PM UTC 24 | Aug 28 10:13:27 PM UTC 24 | 742685143 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2707000758 | Aug 28 10:12:52 PM UTC 24 | Aug 28 10:13:27 PM UTC 24 | 667196413 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2051484534 | Aug 28 10:13:15 PM UTC 24 | Aug 28 10:13:27 PM UTC 24 | 667156579 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3910819300 | Aug 28 10:11:44 PM UTC 24 | Aug 28 10:13:29 PM UTC 24 | 2026745541 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3697224389 | Aug 28 10:09:36 PM UTC 24 | Aug 28 10:13:37 PM UTC 24 | 8638234425 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1923471169 | Aug 28 10:13:01 PM UTC 24 | Aug 28 10:13:37 PM UTC 24 | 2047169040 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3264506468 | Aug 28 10:13:28 PM UTC 24 | Aug 28 10:13:40 PM UTC 24 | 688198038 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3278521207 | Aug 28 10:09:38 PM UTC 24 | Aug 28 10:13:43 PM UTC 24 | 3145116763 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3964946346 | Aug 28 10:13:28 PM UTC 24 | Aug 28 10:13:44 PM UTC 24 | 182005331 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2592828987 | Aug 28 10:13:17 PM UTC 24 | Aug 28 10:13:45 PM UTC 24 | 2154703156 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3727097376 | Aug 28 10:13:38 PM UTC 24 | Aug 28 10:13:51 PM UTC 24 | 1032325360 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2625938726 | Aug 28 10:10:22 PM UTC 24 | Aug 28 10:13:53 PM UTC 24 | 11745975269 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1556171585 | Aug 28 10:08:22 PM UTC 24 | Aug 28 10:13:55 PM UTC 24 | 68675933501 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2881074533 | Aug 28 10:13:28 PM UTC 24 | Aug 28 10:13:57 PM UTC 24 | 506522760 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2159717048 | Aug 28 10:13:41 PM UTC 24 | Aug 28 10:13:59 PM UTC 24 | 183198479 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3616980360 | Aug 28 10:13:38 PM UTC 24 | Aug 28 10:14:03 PM UTC 24 | 968719851 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3254654927 | Aug 28 10:09:09 PM UTC 24 | Aug 28 10:14:04 PM UTC 24 | 5809104010 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.1020558727 | Aug 28 10:13:14 PM UTC 24 | Aug 28 10:14:06 PM UTC 24 | 2429230722 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.1010640148 | Aug 28 10:13:28 PM UTC 24 | Aug 28 10:14:06 PM UTC 24 | 2136144382 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1643239636 | Aug 28 10:13:52 PM UTC 24 | Aug 28 10:14:08 PM UTC 24 | 1074994812 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1030157291 | Aug 28 10:10:43 PM UTC 24 | Aug 28 10:14:09 PM UTC 24 | 6460163220 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.225873325 | Aug 28 10:13:55 PM UTC 24 | Aug 28 10:14:12 PM UTC 24 | 266005495 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1817901763 | Aug 28 10:06:51 PM UTC 24 | Aug 28 10:14:16 PM UTC 24 | 19370731162 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3524559426 | Aug 28 10:14:04 PM UTC 24 | Aug 28 10:14:17 PM UTC 24 | 474967581 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3979725837 | Aug 28 10:13:45 PM UTC 24 | Aug 28 10:14:17 PM UTC 24 | 2062290010 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3494721488 | Aug 28 10:10:08 PM UTC 24 | Aug 28 10:14:19 PM UTC 24 | 17991329388 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3232522073 | Aug 28 10:08:18 PM UTC 24 | Aug 28 10:14:20 PM UTC 24 | 8389370635 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.718057599 | Aug 28 10:14:07 PM UTC 24 | Aug 28 10:14:22 PM UTC 24 | 731385783 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4202548075 | Aug 28 10:12:26 PM UTC 24 | Aug 28 10:14:23 PM UTC 24 | 2307127795 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3674248127 | Aug 28 10:13:03 PM UTC 24 | Aug 28 10:14:25 PM UTC 24 | 2555132081 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.3416697136 | Aug 28 10:13:53 PM UTC 24 | Aug 28 10:14:28 PM UTC 24 | 1343049115 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3721018578 | Aug 28 10:14:17 PM UTC 24 | Aug 28 10:14:30 PM UTC 24 | 263358624 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1236775955 | Aug 28 10:14:18 PM UTC 24 | Aug 28 10:14:32 PM UTC 24 | 299755376 ps |
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