| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.47 | 96.89 | 92.13 | 97.68 | 100.00 | 98.62 | 97.90 | 99.06 |
| T304 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.491475192 | Sep 09 07:56:05 AM UTC 24 | Sep 09 07:56:20 AM UTC 24 | 2878726726 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3922529442 | Sep 09 07:56:21 AM UTC 24 | Sep 09 07:56:50 AM UTC 24 | 668955333 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2994280201 | Sep 09 07:56:16 AM UTC 24 | Sep 09 07:56:52 AM UTC 24 | 2117457326 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.261991707 | Sep 09 07:53:52 AM UTC 24 | Sep 09 07:56:55 AM UTC 24 | 13341475597 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1727829017 | Sep 09 07:56:51 AM UTC 24 | Sep 09 07:57:01 AM UTC 24 | 688110276 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4013595394 | Sep 09 07:55:15 AM UTC 24 | Sep 09 07:57:05 AM UTC 24 | 7123980907 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.842457803 | Sep 09 07:56:56 AM UTC 24 | Sep 09 07:57:09 AM UTC 24 | 183101176 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1851209627 | Sep 09 07:54:19 AM UTC 24 | Sep 09 07:57:12 AM UTC 24 | 19487087960 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1922308843 | Sep 09 07:56:53 AM UTC 24 | Sep 09 07:57:20 AM UTC 24 | 1050418358 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4014187835 | Sep 09 07:50:59 AM UTC 24 | Sep 09 07:57:20 AM UTC 24 | 6553105741 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1389557640 | Sep 09 07:57:14 AM UTC 24 | Sep 09 07:57:24 AM UTC 24 | 1179064161 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4168708233 | Sep 09 07:54:42 AM UTC 24 | Sep 09 07:57:27 AM UTC 24 | 9133233611 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.2290002326 | Sep 09 07:57:07 AM UTC 24 | Sep 09 07:57:29 AM UTC 24 | 706655996 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.412758526 | Sep 09 07:57:21 AM UTC 24 | Sep 09 07:57:34 AM UTC 24 | 1556596769 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1060750346 | Sep 09 07:57:35 AM UTC 24 | Sep 09 07:57:47 AM UTC 24 | 250099966 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.4219421574 | Sep 09 07:57:28 AM UTC 24 | Sep 09 07:57:51 AM UTC 24 | 347791114 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3302383582 | Sep 09 07:57:21 AM UTC 24 | Sep 09 07:57:57 AM UTC 24 | 540325503 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3105709067 | Sep 09 07:51:28 AM UTC 24 | Sep 09 07:58:02 AM UTC 24 | 38778401239 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.342991938 | Sep 09 07:57:52 AM UTC 24 | Sep 09 07:58:04 AM UTC 24 | 648866891 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1850908551 | Sep 09 07:55:06 AM UTC 24 | Sep 09 07:58:11 AM UTC 24 | 6382481803 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2091426735 | Sep 09 07:57:10 AM UTC 24 | Sep 09 07:58:12 AM UTC 24 | 8340483487 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.630981296 | Sep 09 07:57:48 AM UTC 24 | Sep 09 07:58:16 AM UTC 24 | 3882525643 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.4197923717 | Sep 09 07:58:12 AM UTC 24 | Sep 09 07:58:22 AM UTC 24 | 231547830 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1701830189 | Sep 09 07:58:03 AM UTC 24 | Sep 09 07:58:29 AM UTC 24 | 1976374938 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.958016826 | Sep 09 07:58:17 AM UTC 24 | Sep 09 07:58:30 AM UTC 24 | 359743398 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1404229969 | Sep 09 07:58:14 AM UTC 24 | Sep 09 07:58:53 AM UTC 24 | 2205123489 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2762115161 | Sep 09 07:58:29 AM UTC 24 | Sep 09 07:58:56 AM UTC 24 | 5496934224 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.4045457833 | Sep 09 07:58:54 AM UTC 24 | Sep 09 07:59:06 AM UTC 24 | 884755772 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1100243914 | Sep 09 07:59:07 AM UTC 24 | Sep 09 07:59:21 AM UTC 24 | 258080292 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3293531780 | Sep 09 07:53:24 AM UTC 24 | Sep 09 07:59:21 AM UTC 24 | 25400111991 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1703693089 | Sep 09 07:58:57 AM UTC 24 | Sep 09 07:59:23 AM UTC 24 | 211425928 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3422070414 | Sep 09 07:59:22 AM UTC 24 | Sep 09 07:59:45 AM UTC 24 | 343692362 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4207318292 | Sep 09 07:59:45 AM UTC 24 | Sep 09 07:59:58 AM UTC 24 | 497788394 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.329320755 | Sep 09 07:58:05 AM UTC 24 | Sep 09 08:00:13 AM UTC 24 | 2571129916 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.474976247 | Sep 09 07:57:30 AM UTC 24 | Sep 09 08:00:18 AM UTC 24 | 39275202753 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3862935219 | Sep 09 07:59:59 AM UTC 24 | Sep 09 08:00:27 AM UTC 24 | 470620140 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2240599469 | Sep 09 08:00:14 AM UTC 24 | Sep 09 08:00:29 AM UTC 24 | 1180771140 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.906108589 | Sep 09 07:54:18 AM UTC 24 | Sep 09 08:00:34 AM UTC 24 | 25017838408 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3287231756 | Sep 09 08:00:34 AM UTC 24 | Sep 09 08:00:47 AM UTC 24 | 260292826 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3030234081 | Sep 09 08:00:28 AM UTC 24 | Sep 09 08:00:54 AM UTC 24 | 1030396204 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.162141451 | Sep 09 07:56:08 AM UTC 24 | Sep 09 08:01:04 AM UTC 24 | 13721988211 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2626654495 | Sep 09 07:55:35 AM UTC 24 | Sep 09 08:01:07 AM UTC 24 | 25303340000 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.674810281 | Sep 09 08:00:55 AM UTC 24 | Sep 09 08:01:09 AM UTC 24 | 1077822466 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.2524424847 | Sep 09 08:00:48 AM UTC 24 | Sep 09 08:01:23 AM UTC 24 | 1573360819 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.685544423 | Sep 09 08:01:07 AM UTC 24 | Sep 09 08:01:34 AM UTC 24 | 2601156561 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1122522964 | Sep 09 08:01:24 AM UTC 24 | Sep 09 08:01:35 AM UTC 24 | 338710198 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3294259776 | Sep 09 08:01:36 AM UTC 24 | Sep 09 08:01:50 AM UTC 24 | 2127395087 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1026983618 | Sep 09 08:01:35 AM UTC 24 | Sep 09 08:02:14 AM UTC 24 | 529229919 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1319729242 | Sep 09 07:59:22 AM UTC 24 | Sep 09 08:02:25 AM UTC 24 | 12579678132 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1510545603 | Sep 09 07:59:24 AM UTC 24 | Sep 09 08:02:32 AM UTC 24 | 18227301198 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1639180556 | Sep 09 08:02:15 AM UTC 24 | Sep 09 08:02:41 AM UTC 24 | 516604817 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.314257667 | Sep 09 07:58:31 AM UTC 24 | Sep 09 08:02:42 AM UTC 24 | 9307951425 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1478588078 | Sep 09 08:02:33 AM UTC 24 | Sep 09 08:02:44 AM UTC 24 | 1124165329 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2827732783 | Sep 09 08:02:25 AM UTC 24 | Sep 09 08:02:57 AM UTC 24 | 2649126363 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2233674823 | Sep 09 07:57:57 AM UTC 24 | Sep 09 08:02:59 AM UTC 24 | 37151009567 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4002889795 | Sep 09 08:00:29 AM UTC 24 | Sep 09 08:03:01 AM UTC 24 | 5977049846 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4291628163 | Sep 09 07:57:02 AM UTC 24 | Sep 09 08:03:14 AM UTC 24 | 23477668046 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4228838585 | Sep 09 08:01:10 AM UTC 24 | Sep 09 08:03:31 AM UTC 24 | 2485716601 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.326414975 | Sep 09 07:58:23 AM UTC 24 | Sep 09 08:04:03 AM UTC 24 | 22446844520 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4087673904 | Sep 09 08:00:19 AM UTC 24 | Sep 09 08:04:40 AM UTC 24 | 3362178805 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2391603848 | Sep 09 07:57:25 AM UTC 24 | Sep 09 08:04:48 AM UTC 24 | 30738619731 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3716063793 | Sep 09 08:01:05 AM UTC 24 | Sep 09 08:05:05 AM UTC 24 | 10365597095 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1081006442 | Sep 09 08:01:51 AM UTC 24 | Sep 09 08:05:26 AM UTC 24 | 14156536922 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2548653127 | Sep 09 05:09:31 AM UTC 24 | Sep 09 05:09:44 AM UTC 24 | 3297004734 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1803227587 | Sep 09 05:09:30 AM UTC 24 | Sep 09 05:09:44 AM UTC 24 | 174656685 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1011846601 | Sep 09 05:09:31 AM UTC 24 | Sep 09 05:09:45 AM UTC 24 | 167600867 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.907998844 | Sep 09 05:09:30 AM UTC 24 | Sep 09 05:09:45 AM UTC 24 | 258115680 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.526799025 | Sep 09 05:09:32 AM UTC 24 | Sep 09 05:09:46 AM UTC 24 | 171484870 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3954521992 | Sep 09 05:09:30 AM UTC 24 | Sep 09 05:09:46 AM UTC 24 | 993288661 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2706974223 | Sep 09 05:09:30 AM UTC 24 | Sep 09 05:09:47 AM UTC 24 | 713714021 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2232826860 | Sep 09 05:09:31 AM UTC 24 | Sep 09 05:09:48 AM UTC 24 | 258232334 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1309101536 | Sep 09 05:09:33 AM UTC 24 | Sep 09 05:09:49 AM UTC 24 | 272665100 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3725468360 | Sep 09 05:09:35 AM UTC 24 | Sep 09 05:09:51 AM UTC 24 | 4925766303 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3594198150 | Sep 09 05:09:35 AM UTC 24 | Sep 09 05:09:51 AM UTC 24 | 2254124444 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1227333996 | Sep 09 05:09:46 AM UTC 24 | Sep 09 05:09:59 AM UTC 24 | 394835314 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3237061950 | Sep 09 05:09:45 AM UTC 24 | Sep 09 05:09:59 AM UTC 24 | 319537185 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2075546202 | Sep 09 05:09:45 AM UTC 24 | Sep 09 05:09:59 AM UTC 24 | 661556304 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3217659881 | Sep 09 05:09:46 AM UTC 24 | Sep 09 05:10:00 AM UTC 24 | 539645871 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1211947932 | Sep 09 05:09:42 AM UTC 24 | Sep 09 05:10:02 AM UTC 24 | 516143374 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1437226222 | Sep 09 05:09:46 AM UTC 24 | Sep 09 05:10:02 AM UTC 24 | 852800302 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2405532049 | Sep 09 05:09:33 AM UTC 24 | Sep 09 05:10:03 AM UTC 24 | 3820650000 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1092852129 | Sep 09 05:09:54 AM UTC 24 | Sep 09 05:10:06 AM UTC 24 | 268789007 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2949583610 | Sep 09 05:09:52 AM UTC 24 | Sep 09 05:10:07 AM UTC 24 | 262464404 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3378639820 | Sep 09 05:09:49 AM UTC 24 | Sep 09 05:10:07 AM UTC 24 | 3786586078 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3435276967 | Sep 09 05:09:55 AM UTC 24 | Sep 09 05:10:09 AM UTC 24 | 167537798 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3027057522 | Sep 09 05:09:48 AM UTC 24 | Sep 09 05:10:10 AM UTC 24 | 1131766782 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1680441361 | Sep 09 05:09:52 AM UTC 24 | Sep 09 05:10:11 AM UTC 24 | 2781296270 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3890329066 | Sep 09 05:10:00 AM UTC 24 | Sep 09 05:10:11 AM UTC 24 | 168218646 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2073811942 | Sep 09 05:10:00 AM UTC 24 | Sep 09 05:10:11 AM UTC 24 | 178409245 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.692053772 | Sep 09 05:10:00 AM UTC 24 | Sep 09 05:10:14 AM UTC 24 | 660256640 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1925446775 | Sep 09 05:10:03 AM UTC 24 | Sep 09 05:10:17 AM UTC 24 | 169058662 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.880316061 | Sep 09 05:09:29 AM UTC 24 | Sep 09 05:10:18 AM UTC 24 | 1073349368 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4116379530 | Sep 09 05:10:02 AM UTC 24 | Sep 09 05:10:18 AM UTC 24 | 250106299 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3384033639 | Sep 09 05:10:07 AM UTC 24 | Sep 09 05:10:21 AM UTC 24 | 660842823 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2034775099 | Sep 09 05:10:09 AM UTC 24 | Sep 09 05:10:22 AM UTC 24 | 250706624 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1725241959 | Sep 09 05:10:07 AM UTC 24 | Sep 09 05:10:23 AM UTC 24 | 1000316254 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2328989105 | Sep 09 05:10:10 AM UTC 24 | Sep 09 05:10:25 AM UTC 24 | 1102518714 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1782939811 | Sep 09 05:10:08 AM UTC 24 | Sep 09 05:10:25 AM UTC 24 | 4952281790 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2414955867 | Sep 09 05:10:12 AM UTC 24 | Sep 09 05:10:28 AM UTC 24 | 270587618 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2121609514 | Sep 09 05:10:12 AM UTC 24 | Sep 09 05:10:28 AM UTC 24 | 905843076 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2372130825 | Sep 09 05:10:19 AM UTC 24 | Sep 09 05:10:34 AM UTC 24 | 505871369 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.731554879 | Sep 09 05:10:15 AM UTC 24 | Sep 09 05:10:34 AM UTC 24 | 168457709 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2517215246 | Sep 09 05:10:19 AM UTC 24 | Sep 09 05:10:35 AM UTC 24 | 1768656376 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4282687831 | Sep 09 05:10:24 AM UTC 24 | Sep 09 05:10:38 AM UTC 24 | 1383021486 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2102591087 | Sep 09 05:10:23 AM UTC 24 | Sep 09 05:10:39 AM UTC 24 | 257068709 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.552059330 | Sep 09 05:10:26 AM UTC 24 | Sep 09 05:10:40 AM UTC 24 | 661131034 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1151268311 | Sep 09 05:10:25 AM UTC 24 | Sep 09 05:10:42 AM UTC 24 | 1128157794 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3917186295 | Sep 09 05:10:28 AM UTC 24 | Sep 09 05:10:42 AM UTC 24 | 637756045 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1520045688 | Sep 09 05:10:22 AM UTC 24 | Sep 09 05:10:48 AM UTC 24 | 2827304179 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3486702793 | Sep 09 05:10:36 AM UTC 24 | Sep 09 05:10:50 AM UTC 24 | 169372315 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3884985744 | Sep 09 05:10:41 AM UTC 24 | Sep 09 05:10:50 AM UTC 24 | 661857847 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3679240826 | Sep 09 05:09:47 AM UTC 24 | Sep 09 05:10:55 AM UTC 24 | 10803727081 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4233425951 | Sep 09 05:10:43 AM UTC 24 | Sep 09 05:10:57 AM UTC 24 | 689100153 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2208068389 | Sep 09 05:10:39 AM UTC 24 | Sep 09 05:10:58 AM UTC 24 | 270935620 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3356913325 | Sep 09 05:10:45 AM UTC 24 | Sep 09 05:10:58 AM UTC 24 | 169447106 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2538902114 | Sep 09 05:10:48 AM UTC 24 | Sep 09 05:11:03 AM UTC 24 | 167696933 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1094122398 | Sep 09 05:10:34 AM UTC 24 | Sep 09 05:11:04 AM UTC 24 | 4110063622 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.811297319 | Sep 09 05:10:50 AM UTC 24 | Sep 09 05:11:05 AM UTC 24 | 365205247 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3266868480 | Sep 09 05:10:58 AM UTC 24 | Sep 09 05:11:07 AM UTC 24 | 2878329411 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4134764414 | Sep 09 05:10:58 AM UTC 24 | Sep 09 05:11:10 AM UTC 24 | 718088038 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2806558355 | Sep 09 05:10:57 AM UTC 24 | Sep 09 05:11:11 AM UTC 24 | 4111337533 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2860648343 | Sep 09 05:10:01 AM UTC 24 | Sep 09 05:11:12 AM UTC 24 | 3142780552 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.43657901 | Sep 09 05:10:56 AM UTC 24 | Sep 09 05:11:16 AM UTC 24 | 167702836 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1587279636 | Sep 09 05:11:04 AM UTC 24 | Sep 09 05:11:19 AM UTC 24 | 252454714 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2286083504 | Sep 09 05:11:06 AM UTC 24 | Sep 09 05:11:19 AM UTC 24 | 167595761 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1303249036 | Sep 09 05:10:29 AM UTC 24 | Sep 09 05:11:21 AM UTC 24 | 3424787998 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.98089635 | Sep 09 05:09:30 AM UTC 24 | Sep 09 05:11:21 AM UTC 24 | 490058336 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1059858388 | Sep 09 05:10:03 AM UTC 24 | Sep 09 05:11:22 AM UTC 24 | 649383974 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2560709538 | Sep 09 05:11:08 AM UTC 24 | Sep 09 05:11:28 AM UTC 24 | 893695259 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4147687171 | Sep 09 05:11:11 AM UTC 24 | Sep 09 05:11:28 AM UTC 24 | 1346638204 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2456666390 | Sep 09 05:11:13 AM UTC 24 | Sep 09 05:11:31 AM UTC 24 | 497575172 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3574374461 | Sep 09 05:11:20 AM UTC 24 | Sep 09 05:11:34 AM UTC 24 | 333498621 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1111520945 | Sep 09 05:11:20 AM UTC 24 | Sep 09 05:11:35 AM UTC 24 | 508148481 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3622956191 | Sep 09 05:11:21 AM UTC 24 | Sep 09 05:11:36 AM UTC 24 | 996724379 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.611393569 | Sep 09 05:09:33 AM UTC 24 | Sep 09 05:11:37 AM UTC 24 | 12171465367 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3766397849 | Sep 09 05:11:23 AM UTC 24 | Sep 09 05:11:40 AM UTC 24 | 689006520 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1407501062 | Sep 09 05:11:29 AM UTC 24 | Sep 09 05:11:42 AM UTC 24 | 177037790 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1815021705 | Sep 09 05:10:59 AM UTC 24 | Sep 09 05:11:44 AM UTC 24 | 2862279511 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2202861691 | Sep 09 05:10:12 AM UTC 24 | Sep 09 05:11:46 AM UTC 24 | 4298863403 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.965111741 | Sep 09 05:12:31 AM UTC 24 | Sep 09 05:12:44 AM UTC 24 | 2744784358 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2702219054 | Sep 09 05:11:32 AM UTC 24 | Sep 09 05:11:46 AM UTC 24 | 1072604567 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1928090491 | Sep 09 05:11:30 AM UTC 24 | Sep 09 05:11:47 AM UTC 24 | 1423202084 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3574912874 | Sep 09 05:11:38 AM UTC 24 | Sep 09 05:11:49 AM UTC 24 | 987845121 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1852020515 | Sep 09 05:10:41 AM UTC 24 | Sep 09 05:11:52 AM UTC 24 | 9497635036 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1627601140 | Sep 09 05:11:37 AM UTC 24 | Sep 09 05:11:53 AM UTC 24 | 495695238 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.930620988 | Sep 09 05:10:51 AM UTC 24 | Sep 09 05:11:56 AM UTC 24 | 1047852476 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3950138576 | Sep 09 05:11:40 AM UTC 24 | Sep 09 05:11:56 AM UTC 24 | 275887206 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.653486587 | Sep 09 05:11:36 AM UTC 24 | Sep 09 05:11:57 AM UTC 24 | 345423287 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3174351073 | Sep 09 05:11:44 AM UTC 24 | Sep 09 05:11:57 AM UTC 24 | 261540844 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3896382918 | Sep 09 05:11:41 AM UTC 24 | Sep 09 05:11:58 AM UTC 24 | 172461888 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.719595342 | Sep 09 05:11:47 AM UTC 24 | Sep 09 05:11:58 AM UTC 24 | 517976947 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1889122502 | Sep 09 05:11:46 AM UTC 24 | Sep 09 05:12:03 AM UTC 24 | 693523703 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1615455603 | Sep 09 05:11:50 AM UTC 24 | Sep 09 05:12:05 AM UTC 24 | 234502280 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3933885925 | Sep 09 05:11:54 AM UTC 24 | Sep 09 05:12:06 AM UTC 24 | 1836460587 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3125532506 | Sep 09 05:10:36 AM UTC 24 | Sep 09 05:12:10 AM UTC 24 | 2907655687 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1526114211 | Sep 09 05:11:59 AM UTC 24 | Sep 09 05:12:12 AM UTC 24 | 590965401 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3676738262 | Sep 09 05:11:58 AM UTC 24 | Sep 09 05:12:13 AM UTC 24 | 500147180 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3627577873 | Sep 09 05:11:12 AM UTC 24 | Sep 09 05:12:13 AM UTC 24 | 687752205 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.220079393 | Sep 09 05:12:05 AM UTC 24 | Sep 09 05:12:17 AM UTC 24 | 517692188 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3834631992 | Sep 09 05:11:57 AM UTC 24 | Sep 09 05:12:17 AM UTC 24 | 700860135 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3996550077 | Sep 09 05:11:58 AM UTC 24 | Sep 09 05:12:19 AM UTC 24 | 386583343 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2994868421 | Sep 09 05:12:03 AM UTC 24 | Sep 09 05:12:19 AM UTC 24 | 516671648 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3308797437 | Sep 09 05:09:48 AM UTC 24 | Sep 09 05:12:24 AM UTC 24 | 394194929 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2829964284 | Sep 09 05:11:22 AM UTC 24 | Sep 09 05:12:24 AM UTC 24 | 9385893689 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3137841431 | Sep 09 05:12:13 AM UTC 24 | Sep 09 05:12:27 AM UTC 24 | 242917781 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2580734161 | Sep 09 05:12:15 AM UTC 24 | Sep 09 05:12:28 AM UTC 24 | 1100225971 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1916178349 | Sep 09 05:12:10 AM UTC 24 | Sep 09 05:12:29 AM UTC 24 | 174676888 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.353051066 | Sep 09 05:11:47 AM UTC 24 | Sep 09 05:12:30 AM UTC 24 | 13706793300 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4095885542 | Sep 09 05:12:18 AM UTC 24 | Sep 09 05:12:35 AM UTC 24 | 549139190 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1241610861 | Sep 09 05:12:25 AM UTC 24 | Sep 09 05:12:36 AM UTC 24 | 253703086 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1183448126 | Sep 09 05:12:20 AM UTC 24 | Sep 09 05:12:39 AM UTC 24 | 167676369 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1381300346 | Sep 09 05:12:25 AM UTC 24 | Sep 09 05:12:39 AM UTC 24 | 178336073 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1671705665 | Sep 09 05:10:18 AM UTC 24 | Sep 09 05:12:40 AM UTC 24 | 1261393700 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.303075771 | Sep 09 05:12:28 AM UTC 24 | Sep 09 05:12:42 AM UTC 24 | 388424590 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.818784077 | Sep 09 05:11:35 AM UTC 24 | Sep 09 05:12:43 AM UTC 24 | 3040300774 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3466252263 | Sep 09 05:10:57 AM UTC 24 | Sep 09 05:12:43 AM UTC 24 | 477651386 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1777768989 | Sep 09 05:09:34 AM UTC 24 | Sep 09 05:12:45 AM UTC 24 | 5470873034 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1184650574 | Sep 09 05:12:41 AM UTC 24 | Sep 09 05:12:49 AM UTC 24 | 636653362 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4193241681 | Sep 09 05:12:35 AM UTC 24 | Sep 09 05:12:50 AM UTC 24 | 1569872359 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.268518930 | Sep 09 05:11:41 AM UTC 24 | Sep 09 05:12:51 AM UTC 24 | 2026542491 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.376618513 | Sep 09 05:12:30 AM UTC 24 | Sep 09 05:12:52 AM UTC 24 | 594293164 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3215222922 | Sep 09 05:11:58 AM UTC 24 | Sep 09 05:12:52 AM UTC 24 | 2471921435 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.430239601 | Sep 09 05:12:31 AM UTC 24 | Sep 09 05:12:53 AM UTC 24 | 362705285 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1386763220 | Sep 09 05:12:43 AM UTC 24 | Sep 09 05:12:56 AM UTC 24 | 554312003 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3146539452 | Sep 09 05:12:44 AM UTC 24 | Sep 09 05:12:58 AM UTC 24 | 270294202 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2289131950 | Sep 09 05:12:52 AM UTC 24 | Sep 09 05:13:02 AM UTC 24 | 707757729 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3875090141 | Sep 09 05:12:50 AM UTC 24 | Sep 09 05:13:04 AM UTC 24 | 338437554 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2374692763 | Sep 09 05:12:41 AM UTC 24 | Sep 09 05:13:04 AM UTC 24 | 914879011 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4251851005 | Sep 09 05:12:50 AM UTC 24 | Sep 09 05:13:04 AM UTC 24 | 171551274 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1583042240 | Sep 09 05:12:45 AM UTC 24 | Sep 09 05:13:07 AM UTC 24 | 311524757 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2209422667 | Sep 09 05:10:43 AM UTC 24 | Sep 09 05:13:21 AM UTC 24 | 1473738515 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.108173885 | Sep 09 05:12:07 AM UTC 24 | Sep 09 05:13:23 AM UTC 24 | 1075188420 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2858213818 | Sep 09 05:11:59 AM UTC 24 | Sep 09 05:13:26 AM UTC 24 | 476276352 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2711210123 | Sep 09 05:12:28 AM UTC 24 | Sep 09 05:13:38 AM UTC 24 | 4043808525 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.958621837 | Sep 09 05:12:20 AM UTC 24 | Sep 09 05:13:40 AM UTC 24 | 624500267 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2325908691 | Sep 09 05:11:53 AM UTC 24 | Sep 09 05:13:44 AM UTC 24 | 1491423630 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.74109093 | Sep 09 05:12:18 AM UTC 24 | Sep 09 05:13:46 AM UTC 24 | 30530295545 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.740492765 | Sep 09 05:11:24 AM UTC 24 | Sep 09 05:13:58 AM UTC 24 | 1435467513 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.546408895 | Sep 09 05:11:05 AM UTC 24 | Sep 09 05:14:00 AM UTC 24 | 1176041636 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2753333675 | Sep 09 05:12:44 AM UTC 24 | Sep 09 05:14:03 AM UTC 24 | 3049455374 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3669659617 | Sep 09 05:12:37 AM UTC 24 | Sep 09 05:14:09 AM UTC 24 | 16894689337 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2706282590 | Sep 09 05:12:41 AM UTC 24 | Sep 09 05:14:19 AM UTC 24 | 353988238 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2626818161 | Sep 09 05:12:46 AM UTC 24 | Sep 09 05:14:22 AM UTC 24 | 338627899 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1932841443 | Sep 09 05:11:42 AM UTC 24 | Sep 09 05:14:24 AM UTC 24 | 1515322382 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1467321511 | Sep 09 05:11:36 AM UTC 24 | Sep 09 05:14:26 AM UTC 24 | 4883729402 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.208212304 | Sep 09 05:11:16 AM UTC 24 | Sep 09 05:14:34 AM UTC 24 | 1663384828 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1193634424 | Sep 09 05:12:12 AM UTC 24 | Sep 09 05:15:20 AM UTC 24 | 522793423 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1048755122 | Sep 09 05:12:30 AM UTC 24 | Sep 09 05:15:30 AM UTC 24 | 1547452538 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3614672917 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 569077307 ps |
| CPU time | 28.23 seconds |
| Started | Sep 09 07:29:51 AM UTC 24 |
| Finished | Sep 09 07:30:20 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361467291 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.3614672917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3419801843 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9269049250 ps |
| CPU time | 121.96 seconds |
| Started | Sep 09 07:30:10 AM UTC 24 |
| Finished | Sep 09 07:32:14 AM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3419801843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3419801843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2067780581 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 22123586960 ps |
| CPU time | 233.48 seconds |
| Started | Sep 09 07:30:07 AM UTC 24 |
| Finished | Sep 09 07:34:04 AM UTC 24 |
| Peak memory | 257452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067780581 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.2067780581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2532523981 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 82653443414 ps |
| CPU time | 460.34 seconds |
| Started | Sep 09 07:31:45 AM UTC 24 |
| Finished | Sep 09 07:39:33 AM UTC 24 |
| Peak memory | 257192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532523981 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.2532523981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3308797437 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 394194929 ps |
| CPU time | 152.7 seconds |
| Started | Sep 09 05:09:48 AM UTC 24 |
| Finished | Sep 09 05:12:24 AM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308797437 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.3308797437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1929100508 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1042309386 ps |
| CPU time | 55.6 seconds |
| Started | Sep 09 07:30:06 AM UTC 24 |
| Finished | Sep 09 07:31:03 AM UTC 24 |
| Peak memory | 230952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192910050 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.1929100508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2094205992 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 322449551 ps |
| CPU time | 137.25 seconds |
| Started | Sep 09 07:30:20 AM UTC 24 |
| Finished | Sep 09 07:32:40 AM UTC 24 |
| Peak memory | 254364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094205992 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2094205992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2706974223 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 713714021 ps |
| CPU time | 15.87 seconds |
| Started | Sep 09 05:09:30 AM UTC 24 |
| Finished | Sep 09 05:09:47 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706974223 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.2706974223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1777768989 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 5470873034 ps |
| CPU time | 188.37 seconds |
| Started | Sep 09 05:09:34 AM UTC 24 |
| Finished | Sep 09 05:12:45 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777768989 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.1777768989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2660861069 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2555155092 ps |
| CPU time | 108.75 seconds |
| Started | Sep 09 07:32:55 AM UTC 24 |
| Finished | Sep 09 07:34:46 AM UTC 24 |
| Peak memory | 239268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2660861069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2660861069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2298871767 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 262046304 ps |
| CPU time | 11.51 seconds |
| Started | Sep 09 07:29:53 AM UTC 24 |
| Finished | Sep 09 07:30:06 AM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298871767 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2298871767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3127527395 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1457442072 ps |
| CPU time | 25.62 seconds |
| Started | Sep 09 07:30:07 AM UTC 24 |
| Finished | Sep 09 07:30:34 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127527395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3127527395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.4025749522 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 332454955 ps |
| CPU time | 21.78 seconds |
| Started | Sep 09 07:44:26 AM UTC 24 |
| Finished | Sep 09 07:44:49 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025749522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4025749522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2698331880 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 347344595 ps |
| CPU time | 21.51 seconds |
| Started | Sep 09 07:55:11 AM UTC 24 |
| Finished | Sep 09 07:55:34 AM UTC 24 |
| Peak memory | 228608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698331880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2698331880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1932841443 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1515322382 ps |
| CPU time | 159.62 seconds |
| Started | Sep 09 05:11:42 AM UTC 24 |
| Finished | Sep 09 05:14:24 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932841443 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.1932841443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1193634424 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 522793423 ps |
| CPU time | 184.74 seconds |
| Started | Sep 09 05:12:12 AM UTC 24 |
| Finished | Sep 09 05:15:20 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193634424 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.1193634424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3679240826 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 10803727081 ps |
| CPU time | 66.21 seconds |
| Started | Sep 09 05:09:47 AM UTC 24 |
| Finished | Sep 09 05:10:55 AM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679240826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.3679240826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2509366666 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2843829038 ps |
| CPU time | 118.13 seconds |
| Started | Sep 09 07:29:51 AM UTC 24 |
| Finished | Sep 09 07:31:51 AM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509366666 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.2509366666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2858213818 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 476276352 ps |
| CPU time | 85.31 seconds |
| Started | Sep 09 05:11:59 AM UTC 24 |
| Finished | Sep 09 05:13:26 AM UTC 24 |
| Peak memory | 226040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858213818 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.2858213818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2548653127 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3297004734 ps |
| CPU time | 11.11 seconds |
| Started | Sep 09 05:09:31 AM UTC 24 |
| Finished | Sep 09 05:09:44 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548653127 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.2548653127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1011846601 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 167600867 ps |
| CPU time | 12.73 seconds |
| Started | Sep 09 05:09:31 AM UTC 24 |
| Finished | Sep 09 05:09:45 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011846601 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.1011846601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1309101536 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 272665100 ps |
| CPU time | 15.27 seconds |
| Started | Sep 09 05:09:33 AM UTC 24 |
| Finished | Sep 09 05:09:49 AM UTC 24 |
| Peak memory | 228148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1309101536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r om_ctrl_csr_mem_rw_with_rand_reset.1309101536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2232826860 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 258232334 ps |
| CPU time | 15.1 seconds |
| Started | Sep 09 05:09:31 AM UTC 24 |
| Finished | Sep 09 05:09:48 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232826860 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2232826860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3954521992 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 993288661 ps |
| CPU time | 14.76 seconds |
| Started | Sep 09 05:09:30 AM UTC 24 |
| Finished | Sep 09 05:09:46 AM UTC 24 |
| Peak memory | 221632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954521992 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.3954521992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1803227587 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 174656685 ps |
| CPU time | 12.89 seconds |
| Started | Sep 09 05:09:30 AM UTC 24 |
| Finished | Sep 09 05:09:44 AM UTC 24 |
| Peak memory | 221684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803227587 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.1803227587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.880316061 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1073349368 ps |
| CPU time | 47.22 seconds |
| Started | Sep 09 05:09:29 AM UTC 24 |
| Finished | Sep 09 05:10:18 AM UTC 24 |
| Peak memory | 225948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880316061 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.880316061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.526799025 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 171484870 ps |
| CPU time | 11.94 seconds |
| Started | Sep 09 05:09:32 AM UTC 24 |
| Finished | Sep 09 05:09:46 AM UTC 24 |
| Peak memory | 221820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526799025 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.526799025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.907998844 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 258115680 ps |
| CPU time | 14.26 seconds |
| Started | Sep 09 05:09:30 AM UTC 24 |
| Finished | Sep 09 05:09:45 AM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907998844 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.907998844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.98089635 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 490058336 ps |
| CPU time | 109.16 seconds |
| Started | Sep 09 05:09:30 AM UTC 24 |
| Finished | Sep 09 05:11:21 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98089635 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.98089635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1437226222 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 852800302 ps |
| CPU time | 14.78 seconds |
| Started | Sep 09 05:09:46 AM UTC 24 |
| Finished | Sep 09 05:10:02 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437226222 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.1437226222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2075546202 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 661556304 ps |
| CPU time | 13.41 seconds |
| Started | Sep 09 05:09:45 AM UTC 24 |
| Finished | Sep 09 05:09:59 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075546202 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.2075546202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1211947932 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 516143374 ps |
| CPU time | 18.5 seconds |
| Started | Sep 09 05:09:42 AM UTC 24 |
| Finished | Sep 09 05:10:02 AM UTC 24 |
| Peak memory | 221744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211947932 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.1211947932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3217659881 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 539645871 ps |
| CPU time | 13.07 seconds |
| Started | Sep 09 05:09:46 AM UTC 24 |
| Finished | Sep 09 05:10:00 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3217659881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r om_ctrl_csr_mem_rw_with_rand_reset.3217659881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3237061950 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 319537185 ps |
| CPU time | 12.85 seconds |
| Started | Sep 09 05:09:45 AM UTC 24 |
| Finished | Sep 09 05:09:59 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237061950 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3237061950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3594198150 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2254124444 ps |
| CPU time | 14.9 seconds |
| Started | Sep 09 05:09:35 AM UTC 24 |
| Finished | Sep 09 05:09:51 AM UTC 24 |
| Peak memory | 221632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594198150 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.3594198150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3725468360 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4925766303 ps |
| CPU time | 14.7 seconds |
| Started | Sep 09 05:09:35 AM UTC 24 |
| Finished | Sep 09 05:09:51 AM UTC 24 |
| Peak memory | 221580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725468360 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.3725468360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.611393569 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 12171465367 ps |
| CPU time | 122.34 seconds |
| Started | Sep 09 05:09:33 AM UTC 24 |
| Finished | Sep 09 05:11:37 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611393569 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.611393569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1227333996 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 394835314 ps |
| CPU time | 11.4 seconds |
| Started | Sep 09 05:09:46 AM UTC 24 |
| Finished | Sep 09 05:09:59 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227333996 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.1227333996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2405532049 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3820650000 ps |
| CPU time | 28.51 seconds |
| Started | Sep 09 05:09:33 AM UTC 24 |
| Finished | Sep 09 05:10:03 AM UTC 24 |
| Peak memory | 229028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405532049 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2405532049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2702219054 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1072604567 ps |
| CPU time | 13.56 seconds |
| Started | Sep 09 05:11:32 AM UTC 24 |
| Finished | Sep 09 05:11:46 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2702219054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. rom_ctrl_csr_mem_rw_with_rand_reset.2702219054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1407501062 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 177037790 ps |
| CPU time | 12.04 seconds |
| Started | Sep 09 05:11:29 AM UTC 24 |
| Finished | Sep 09 05:11:42 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407501062 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1407501062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2829964284 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 9385893689 ps |
| CPU time | 60.29 seconds |
| Started | Sep 09 05:11:22 AM UTC 24 |
| Finished | Sep 09 05:12:24 AM UTC 24 |
| Peak memory | 225948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829964284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.2829964284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1928090491 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1423202084 ps |
| CPU time | 16.15 seconds |
| Started | Sep 09 05:11:30 AM UTC 24 |
| Finished | Sep 09 05:11:47 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928090491 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.1928090491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3766397849 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 689006520 ps |
| CPU time | 15.85 seconds |
| Started | Sep 09 05:11:23 AM UTC 24 |
| Finished | Sep 09 05:11:40 AM UTC 24 |
| Peak memory | 228120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766397849 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3766397849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.740492765 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1435467513 ps |
| CPU time | 150.82 seconds |
| Started | Sep 09 05:11:24 AM UTC 24 |
| Finished | Sep 09 05:13:58 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740492765 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.740492765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3950138576 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 275887206 ps |
| CPU time | 15.32 seconds |
| Started | Sep 09 05:11:40 AM UTC 24 |
| Finished | Sep 09 05:11:56 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3950138576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rom_ctrl_csr_mem_rw_with_rand_reset.3950138576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1627601140 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 495695238 ps |
| CPU time | 14.7 seconds |
| Started | Sep 09 05:11:37 AM UTC 24 |
| Finished | Sep 09 05:11:53 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627601140 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1627601140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.818784077 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3040300774 ps |
| CPU time | 66.25 seconds |
| Started | Sep 09 05:11:35 AM UTC 24 |
| Finished | Sep 09 05:12:43 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818784077 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.818784077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3574912874 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 987845121 ps |
| CPU time | 9.86 seconds |
| Started | Sep 09 05:11:38 AM UTC 24 |
| Finished | Sep 09 05:11:49 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574912874 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.3574912874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.653486587 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 345423287 ps |
| CPU time | 19.63 seconds |
| Started | Sep 09 05:11:36 AM UTC 24 |
| Finished | Sep 09 05:11:57 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653486587 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.653486587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1467321511 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4883729402 ps |
| CPU time | 167.18 seconds |
| Started | Sep 09 05:11:36 AM UTC 24 |
| Finished | Sep 09 05:14:26 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467321511 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.1467321511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.719595342 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 517976947 ps |
| CPU time | 9.82 seconds |
| Started | Sep 09 05:11:47 AM UTC 24 |
| Finished | Sep 09 05:11:58 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=719595342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.r om_ctrl_csr_mem_rw_with_rand_reset.719595342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3174351073 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 261540844 ps |
| CPU time | 11.6 seconds |
| Started | Sep 09 05:11:44 AM UTC 24 |
| Finished | Sep 09 05:11:57 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174351073 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3174351073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.268518930 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2026542491 ps |
| CPU time | 68.56 seconds |
| Started | Sep 09 05:11:41 AM UTC 24 |
| Finished | Sep 09 05:12:51 AM UTC 24 |
| Peak memory | 225940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268518930 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.268518930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1889122502 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 693523703 ps |
| CPU time | 15.09 seconds |
| Started | Sep 09 05:11:46 AM UTC 24 |
| Finished | Sep 09 05:12:03 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889122502 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.1889122502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3896382918 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 172461888 ps |
| CPU time | 15.71 seconds |
| Started | Sep 09 05:11:41 AM UTC 24 |
| Finished | Sep 09 05:11:58 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896382918 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3896382918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3676738262 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 500147180 ps |
| CPU time | 13.62 seconds |
| Started | Sep 09 05:11:58 AM UTC 24 |
| Finished | Sep 09 05:12:13 AM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3676738262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. rom_ctrl_csr_mem_rw_with_rand_reset.3676738262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3933885925 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1836460587 ps |
| CPU time | 11.54 seconds |
| Started | Sep 09 05:11:54 AM UTC 24 |
| Finished | Sep 09 05:12:06 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933885925 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3933885925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.353051066 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 13706793300 ps |
| CPU time | 40.8 seconds |
| Started | Sep 09 05:11:47 AM UTC 24 |
| Finished | Sep 09 05:12:30 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353051066 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.353051066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3834631992 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 700860135 ps |
| CPU time | 19.11 seconds |
| Started | Sep 09 05:11:57 AM UTC 24 |
| Finished | Sep 09 05:12:17 AM UTC 24 |
| Peak memory | 224052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834631992 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.3834631992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1615455603 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 234502280 ps |
| CPU time | 14.18 seconds |
| Started | Sep 09 05:11:50 AM UTC 24 |
| Finished | Sep 09 05:12:05 AM UTC 24 |
| Peak memory | 228184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615455603 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1615455603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2325908691 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1491423630 ps |
| CPU time | 109.2 seconds |
| Started | Sep 09 05:11:53 AM UTC 24 |
| Finished | Sep 09 05:13:44 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325908691 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.2325908691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.220079393 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 517692188 ps |
| CPU time | 10.57 seconds |
| Started | Sep 09 05:12:05 AM UTC 24 |
| Finished | Sep 09 05:12:17 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=220079393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.r om_ctrl_csr_mem_rw_with_rand_reset.220079393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1526114211 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 590965401 ps |
| CPU time | 11.55 seconds |
| Started | Sep 09 05:11:59 AM UTC 24 |
| Finished | Sep 09 05:12:12 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526114211 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1526114211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3215222922 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2471921435 ps |
| CPU time | 52.87 seconds |
| Started | Sep 09 05:11:58 AM UTC 24 |
| Finished | Sep 09 05:12:52 AM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215222922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.3215222922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2994868421 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 516671648 ps |
| CPU time | 14.98 seconds |
| Started | Sep 09 05:12:03 AM UTC 24 |
| Finished | Sep 09 05:12:19 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994868421 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.2994868421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3996550077 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 386583343 ps |
| CPU time | 19.64 seconds |
| Started | Sep 09 05:11:58 AM UTC 24 |
| Finished | Sep 09 05:12:19 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996550077 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3996550077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4095885542 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 549139190 ps |
| CPU time | 15.83 seconds |
| Started | Sep 09 05:12:18 AM UTC 24 |
| Finished | Sep 09 05:12:35 AM UTC 24 |
| Peak memory | 228088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4095885542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rom_ctrl_csr_mem_rw_with_rand_reset.4095885542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3137841431 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 242917781 ps |
| CPU time | 11.51 seconds |
| Started | Sep 09 05:12:13 AM UTC 24 |
| Finished | Sep 09 05:12:27 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137841431 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3137841431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.108173885 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1075188420 ps |
| CPU time | 73.96 seconds |
| Started | Sep 09 05:12:07 AM UTC 24 |
| Finished | Sep 09 05:13:23 AM UTC 24 |
| Peak memory | 225940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108173885 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.108173885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2580734161 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1100225971 ps |
| CPU time | 11.62 seconds |
| Started | Sep 09 05:12:15 AM UTC 24 |
| Finished | Sep 09 05:12:28 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580734161 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.2580734161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1916178349 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 174676888 ps |
| CPU time | 17.23 seconds |
| Started | Sep 09 05:12:10 AM UTC 24 |
| Finished | Sep 09 05:12:29 AM UTC 24 |
| Peak memory | 228120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916178349 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1916178349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.303075771 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 388424590 ps |
| CPU time | 13.06 seconds |
| Started | Sep 09 05:12:28 AM UTC 24 |
| Finished | Sep 09 05:12:42 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=303075771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.r om_ctrl_csr_mem_rw_with_rand_reset.303075771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1381300346 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 178336073 ps |
| CPU time | 13.23 seconds |
| Started | Sep 09 05:12:25 AM UTC 24 |
| Finished | Sep 09 05:12:39 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381300346 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1381300346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.74109093 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 30530295545 ps |
| CPU time | 86.34 seconds |
| Started | Sep 09 05:12:18 AM UTC 24 |
| Finished | Sep 09 05:13:46 AM UTC 24 |
| Peak memory | 226008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74109093 -assert nopostproc +U VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.74109093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1241610861 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 253703086 ps |
| CPU time | 10.03 seconds |
| Started | Sep 09 05:12:25 AM UTC 24 |
| Finished | Sep 09 05:12:36 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241610861 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.1241610861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1183448126 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 167676369 ps |
| CPU time | 18.36 seconds |
| Started | Sep 09 05:12:20 AM UTC 24 |
| Finished | Sep 09 05:12:39 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183448126 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1183448126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.958621837 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 624500267 ps |
| CPU time | 78.2 seconds |
| Started | Sep 09 05:12:20 AM UTC 24 |
| Finished | Sep 09 05:13:40 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958621837 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.958621837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4193241681 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1569872359 ps |
| CPU time | 12.94 seconds |
| Started | Sep 09 05:12:35 AM UTC 24 |
| Finished | Sep 09 05:12:50 AM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4193241681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. rom_ctrl_csr_mem_rw_with_rand_reset.4193241681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.965111741 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2744784358 ps |
| CPU time | 11.57 seconds |
| Started | Sep 09 05:12:31 AM UTC 24 |
| Finished | Sep 09 05:12:44 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965111741 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.965111741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2711210123 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 4043808525 ps |
| CPU time | 68.57 seconds |
| Started | Sep 09 05:12:28 AM UTC 24 |
| Finished | Sep 09 05:13:38 AM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711210123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.2711210123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.430239601 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 362705285 ps |
| CPU time | 20.19 seconds |
| Started | Sep 09 05:12:31 AM UTC 24 |
| Finished | Sep 09 05:12:53 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430239601 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.430239601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.376618513 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 594293164 ps |
| CPU time | 20.27 seconds |
| Started | Sep 09 05:12:30 AM UTC 24 |
| Finished | Sep 09 05:12:52 AM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376618513 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.376618513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1048755122 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1547452538 ps |
| CPU time | 177.12 seconds |
| Started | Sep 09 05:12:30 AM UTC 24 |
| Finished | Sep 09 05:15:30 AM UTC 24 |
| Peak memory | 223748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048755122 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.1048755122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3146539452 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 270294202 ps |
| CPU time | 13.16 seconds |
| Started | Sep 09 05:12:44 AM UTC 24 |
| Finished | Sep 09 05:12:58 AM UTC 24 |
| Peak memory | 228152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3146539452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. rom_ctrl_csr_mem_rw_with_rand_reset.3146539452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1184650574 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 636653362 ps |
| CPU time | 7.56 seconds |
| Started | Sep 09 05:12:41 AM UTC 24 |
| Finished | Sep 09 05:12:49 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184650574 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1184650574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3669659617 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 16894689337 ps |
| CPU time | 90.93 seconds |
| Started | Sep 09 05:12:37 AM UTC 24 |
| Finished | Sep 09 05:14:09 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669659617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.3669659617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1386763220 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 554312003 ps |
| CPU time | 12.4 seconds |
| Started | Sep 09 05:12:43 AM UTC 24 |
| Finished | Sep 09 05:12:56 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386763220 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.1386763220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2374692763 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 914879011 ps |
| CPU time | 22.05 seconds |
| Started | Sep 09 05:12:41 AM UTC 24 |
| Finished | Sep 09 05:13:04 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374692763 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2374692763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2706282590 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 353988238 ps |
| CPU time | 96.08 seconds |
| Started | Sep 09 05:12:41 AM UTC 24 |
| Finished | Sep 09 05:14:19 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706282590 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.2706282590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2289131950 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 707757729 ps |
| CPU time | 9.07 seconds |
| Started | Sep 09 05:12:52 AM UTC 24 |
| Finished | Sep 09 05:13:02 AM UTC 24 |
| Peak memory | 229424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2289131950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rom_ctrl_csr_mem_rw_with_rand_reset.2289131950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4251851005 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 171551274 ps |
| CPU time | 13 seconds |
| Started | Sep 09 05:12:50 AM UTC 24 |
| Finished | Sep 09 05:13:04 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251851005 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4251851005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2753333675 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3049455374 ps |
| CPU time | 77.23 seconds |
| Started | Sep 09 05:12:44 AM UTC 24 |
| Finished | Sep 09 05:14:03 AM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753333675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.2753333675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3875090141 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 338437554 ps |
| CPU time | 12.47 seconds |
| Started | Sep 09 05:12:50 AM UTC 24 |
| Finished | Sep 09 05:13:04 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875090141 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.3875090141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1583042240 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 311524757 ps |
| CPU time | 21.06 seconds |
| Started | Sep 09 05:12:45 AM UTC 24 |
| Finished | Sep 09 05:13:07 AM UTC 24 |
| Peak memory | 228120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583042240 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1583042240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2626818161 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 338627899 ps |
| CPU time | 93.9 seconds |
| Started | Sep 09 05:12:46 AM UTC 24 |
| Finished | Sep 09 05:14:22 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626818161 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.2626818161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3890329066 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 168218646 ps |
| CPU time | 10.1 seconds |
| Started | Sep 09 05:10:00 AM UTC 24 |
| Finished | Sep 09 05:10:11 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890329066 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.3890329066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3435276967 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 167537798 ps |
| CPU time | 13.13 seconds |
| Started | Sep 09 05:09:55 AM UTC 24 |
| Finished | Sep 09 05:10:09 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435276967 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.3435276967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1680441361 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2781296270 ps |
| CPU time | 18 seconds |
| Started | Sep 09 05:09:52 AM UTC 24 |
| Finished | Sep 09 05:10:11 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680441361 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.1680441361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2073811942 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 178409245 ps |
| CPU time | 10.06 seconds |
| Started | Sep 09 05:10:00 AM UTC 24 |
| Finished | Sep 09 05:10:11 AM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2073811942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r om_ctrl_csr_mem_rw_with_rand_reset.2073811942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1092852129 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 268789007 ps |
| CPU time | 11.59 seconds |
| Started | Sep 09 05:09:54 AM UTC 24 |
| Finished | Sep 09 05:10:06 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092852129 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1092852129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2949583610 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 262464404 ps |
| CPU time | 14 seconds |
| Started | Sep 09 05:09:52 AM UTC 24 |
| Finished | Sep 09 05:10:07 AM UTC 24 |
| Peak memory | 221684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949583610 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.2949583610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3378639820 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3786586078 ps |
| CPU time | 16.41 seconds |
| Started | Sep 09 05:09:49 AM UTC 24 |
| Finished | Sep 09 05:10:07 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378639820 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.3378639820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.692053772 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 660256640 ps |
| CPU time | 13.08 seconds |
| Started | Sep 09 05:10:00 AM UTC 24 |
| Finished | Sep 09 05:10:14 AM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692053772 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.692053772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3027057522 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1131766782 ps |
| CPU time | 20.12 seconds |
| Started | Sep 09 05:09:48 AM UTC 24 |
| Finished | Sep 09 05:10:10 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027057522 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3027057522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2328989105 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1102518714 ps |
| CPU time | 12.93 seconds |
| Started | Sep 09 05:10:10 AM UTC 24 |
| Finished | Sep 09 05:10:25 AM UTC 24 |
| Peak memory | 221744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328989105 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.2328989105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2034775099 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 250706624 ps |
| CPU time | 11.9 seconds |
| Started | Sep 09 05:10:09 AM UTC 24 |
| Finished | Sep 09 05:10:22 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034775099 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.2034775099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1725241959 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1000316254 ps |
| CPU time | 14.59 seconds |
| Started | Sep 09 05:10:07 AM UTC 24 |
| Finished | Sep 09 05:10:23 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725241959 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.1725241959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2121609514 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 905843076 ps |
| CPU time | 15.36 seconds |
| Started | Sep 09 05:10:12 AM UTC 24 |
| Finished | Sep 09 05:10:28 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2121609514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r om_ctrl_csr_mem_rw_with_rand_reset.2121609514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1782939811 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 4952281790 ps |
| CPU time | 15.35 seconds |
| Started | Sep 09 05:10:08 AM UTC 24 |
| Finished | Sep 09 05:10:25 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782939811 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1782939811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3384033639 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 660842823 ps |
| CPU time | 12.77 seconds |
| Started | Sep 09 05:10:07 AM UTC 24 |
| Finished | Sep 09 05:10:21 AM UTC 24 |
| Peak memory | 221760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384033639 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.3384033639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1925446775 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 169058662 ps |
| CPU time | 12.86 seconds |
| Started | Sep 09 05:10:03 AM UTC 24 |
| Finished | Sep 09 05:10:17 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925446775 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.1925446775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2860648343 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3142780552 ps |
| CPU time | 69.06 seconds |
| Started | Sep 09 05:10:01 AM UTC 24 |
| Finished | Sep 09 05:11:12 AM UTC 24 |
| Peak memory | 226132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860648343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.2860648343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2414955867 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 270587618 ps |
| CPU time | 15.1 seconds |
| Started | Sep 09 05:10:12 AM UTC 24 |
| Finished | Sep 09 05:10:28 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414955867 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.2414955867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4116379530 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 250106299 ps |
| CPU time | 15.29 seconds |
| Started | Sep 09 05:10:02 AM UTC 24 |
| Finished | Sep 09 05:10:18 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116379530 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4116379530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1059858388 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 649383974 ps |
| CPU time | 77.35 seconds |
| Started | Sep 09 05:10:03 AM UTC 24 |
| Finished | Sep 09 05:11:22 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059858388 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.1059858388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1151268311 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1128157794 ps |
| CPU time | 15.14 seconds |
| Started | Sep 09 05:10:25 AM UTC 24 |
| Finished | Sep 09 05:10:42 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151268311 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.1151268311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4282687831 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1383021486 ps |
| CPU time | 12.67 seconds |
| Started | Sep 09 05:10:24 AM UTC 24 |
| Finished | Sep 09 05:10:38 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282687831 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.4282687831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1520045688 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2827304179 ps |
| CPU time | 23.45 seconds |
| Started | Sep 09 05:10:22 AM UTC 24 |
| Finished | Sep 09 05:10:48 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520045688 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.1520045688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3917186295 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 637756045 ps |
| CPU time | 12.47 seconds |
| Started | Sep 09 05:10:28 AM UTC 24 |
| Finished | Sep 09 05:10:42 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3917186295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r om_ctrl_csr_mem_rw_with_rand_reset.3917186295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2102591087 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 257068709 ps |
| CPU time | 15.08 seconds |
| Started | Sep 09 05:10:23 AM UTC 24 |
| Finished | Sep 09 05:10:39 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102591087 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2102591087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2517215246 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1768656376 ps |
| CPU time | 14.71 seconds |
| Started | Sep 09 05:10:19 AM UTC 24 |
| Finished | Sep 09 05:10:35 AM UTC 24 |
| Peak memory | 221632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517215246 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.2517215246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2372130825 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 505871369 ps |
| CPU time | 13.68 seconds |
| Started | Sep 09 05:10:19 AM UTC 24 |
| Finished | Sep 09 05:10:34 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372130825 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.2372130825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2202861691 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4298863403 ps |
| CPU time | 92.22 seconds |
| Started | Sep 09 05:10:12 AM UTC 24 |
| Finished | Sep 09 05:11:46 AM UTC 24 |
| Peak memory | 226132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202861691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.2202861691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.552059330 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 661131034 ps |
| CPU time | 12.32 seconds |
| Started | Sep 09 05:10:26 AM UTC 24 |
| Finished | Sep 09 05:10:40 AM UTC 24 |
| Peak memory | 221756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552059330 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.552059330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.731554879 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 168457709 ps |
| CPU time | 18.57 seconds |
| Started | Sep 09 05:10:15 AM UTC 24 |
| Finished | Sep 09 05:10:34 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731554879 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.731554879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1671705665 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1261393700 ps |
| CPU time | 139.46 seconds |
| Started | Sep 09 05:10:18 AM UTC 24 |
| Finished | Sep 09 05:12:40 AM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671705665 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.1671705665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3884985744 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 661857847 ps |
| CPU time | 8.17 seconds |
| Started | Sep 09 05:10:41 AM UTC 24 |
| Finished | Sep 09 05:10:50 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3884985744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r om_ctrl_csr_mem_rw_with_rand_reset.3884985744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3486702793 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 169372315 ps |
| CPU time | 12.94 seconds |
| Started | Sep 09 05:10:36 AM UTC 24 |
| Finished | Sep 09 05:10:50 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486702793 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3486702793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1303249036 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3424787998 ps |
| CPU time | 49.17 seconds |
| Started | Sep 09 05:10:29 AM UTC 24 |
| Finished | Sep 09 05:11:21 AM UTC 24 |
| Peak memory | 226132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303249036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.1303249036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2208068389 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 270935620 ps |
| CPU time | 17.91 seconds |
| Started | Sep 09 05:10:39 AM UTC 24 |
| Finished | Sep 09 05:10:58 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208068389 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.2208068389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1094122398 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 4110063622 ps |
| CPU time | 27.83 seconds |
| Started | Sep 09 05:10:34 AM UTC 24 |
| Finished | Sep 09 05:11:04 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094122398 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1094122398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3125532506 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2907655687 ps |
| CPU time | 91.69 seconds |
| Started | Sep 09 05:10:36 AM UTC 24 |
| Finished | Sep 09 05:12:10 AM UTC 24 |
| Peak memory | 224052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125532506 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.3125532506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.811297319 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 365205247 ps |
| CPU time | 13.42 seconds |
| Started | Sep 09 05:10:50 AM UTC 24 |
| Finished | Sep 09 05:11:05 AM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=811297319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ro m_ctrl_csr_mem_rw_with_rand_reset.811297319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3356913325 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 169447106 ps |
| CPU time | 12.26 seconds |
| Started | Sep 09 05:10:45 AM UTC 24 |
| Finished | Sep 09 05:10:58 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356913325 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3356913325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1852020515 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 9497635036 ps |
| CPU time | 69.53 seconds |
| Started | Sep 09 05:10:41 AM UTC 24 |
| Finished | Sep 09 05:11:52 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852020515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.1852020515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2538902114 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 167696933 ps |
| CPU time | 13.26 seconds |
| Started | Sep 09 05:10:48 AM UTC 24 |
| Finished | Sep 09 05:11:03 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538902114 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.2538902114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4233425951 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 689100153 ps |
| CPU time | 13.17 seconds |
| Started | Sep 09 05:10:43 AM UTC 24 |
| Finished | Sep 09 05:10:57 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233425951 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4233425951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2209422667 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1473738515 ps |
| CPU time | 155.28 seconds |
| Started | Sep 09 05:10:43 AM UTC 24 |
| Finished | Sep 09 05:13:21 AM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209422667 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.2209422667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3266868480 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2878329411 ps |
| CPU time | 7.71 seconds |
| Started | Sep 09 05:10:58 AM UTC 24 |
| Finished | Sep 09 05:11:07 AM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3266868480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r om_ctrl_csr_mem_rw_with_rand_reset.3266868480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2806558355 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4111337533 ps |
| CPU time | 12.41 seconds |
| Started | Sep 09 05:10:57 AM UTC 24 |
| Finished | Sep 09 05:11:11 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806558355 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2806558355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.930620988 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1047852476 ps |
| CPU time | 63.44 seconds |
| Started | Sep 09 05:10:51 AM UTC 24 |
| Finished | Sep 09 05:11:56 AM UTC 24 |
| Peak memory | 223832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930620988 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.930620988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4134764414 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 718088038 ps |
| CPU time | 10.52 seconds |
| Started | Sep 09 05:10:58 AM UTC 24 |
| Finished | Sep 09 05:11:10 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134764414 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.4134764414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.43657901 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 167702836 ps |
| CPU time | 18.23 seconds |
| Started | Sep 09 05:10:56 AM UTC 24 |
| Finished | Sep 09 05:11:16 AM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43657901 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.43657901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3466252263 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 477651386 ps |
| CPU time | 103.28 seconds |
| Started | Sep 09 05:10:57 AM UTC 24 |
| Finished | Sep 09 05:12:43 AM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466252263 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.3466252263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4147687171 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1346638204 ps |
| CPU time | 16.3 seconds |
| Started | Sep 09 05:11:11 AM UTC 24 |
| Finished | Sep 09 05:11:28 AM UTC 24 |
| Peak memory | 228148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4147687171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r om_ctrl_csr_mem_rw_with_rand_reset.4147687171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2286083504 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 167595761 ps |
| CPU time | 12.61 seconds |
| Started | Sep 09 05:11:06 AM UTC 24 |
| Finished | Sep 09 05:11:19 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286083504 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2286083504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1815021705 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2862279511 ps |
| CPU time | 42.71 seconds |
| Started | Sep 09 05:10:59 AM UTC 24 |
| Finished | Sep 09 05:11:44 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815021705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.1815021705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2560709538 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 893695259 ps |
| CPU time | 18.93 seconds |
| Started | Sep 09 05:11:08 AM UTC 24 |
| Finished | Sep 09 05:11:28 AM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560709538 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.2560709538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1587279636 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 252454714 ps |
| CPU time | 14.45 seconds |
| Started | Sep 09 05:11:04 AM UTC 24 |
| Finished | Sep 09 05:11:19 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587279636 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1587279636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.546408895 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1176041636 ps |
| CPU time | 172.48 seconds |
| Started | Sep 09 05:11:05 AM UTC 24 |
| Finished | Sep 09 05:14:00 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546408895 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.546408895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3622956191 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 996724379 ps |
| CPU time | 13.99 seconds |
| Started | Sep 09 05:11:21 AM UTC 24 |
| Finished | Sep 09 05:11:36 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3622956191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r om_ctrl_csr_mem_rw_with_rand_reset.3622956191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1111520945 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 508148481 ps |
| CPU time | 13.97 seconds |
| Started | Sep 09 05:11:20 AM UTC 24 |
| Finished | Sep 09 05:11:35 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111520945 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1111520945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3627577873 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 687752205 ps |
| CPU time | 59.55 seconds |
| Started | Sep 09 05:11:12 AM UTC 24 |
| Finished | Sep 09 05:12:13 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627577873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.3627577873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3574374461 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 333498621 ps |
| CPU time | 13.04 seconds |
| Started | Sep 09 05:11:20 AM UTC 24 |
| Finished | Sep 09 05:11:34 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574374461 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.3574374461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2456666390 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 497575172 ps |
| CPU time | 17.18 seconds |
| Started | Sep 09 05:11:13 AM UTC 24 |
| Finished | Sep 09 05:11:31 AM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456666390 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2456666390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.208212304 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1663384828 ps |
| CPU time | 194.69 seconds |
| Started | Sep 09 05:11:16 AM UTC 24 |
| Finished | Sep 09 05:14:34 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208212304 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.208212304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.4183002057 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1709078444 ps |
| CPU time | 27.09 seconds |
| Started | Sep 09 07:29:51 AM UTC 24 |
| Finished | Sep 09 07:30:19 AM UTC 24 |
| Peak memory | 228896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183002057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4183002057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1035254793 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1060909273 ps |
| CPU time | 14 seconds |
| Started | Sep 09 07:29:51 AM UTC 24 |
| Finished | Sep 09 07:30:06 AM UTC 24 |
| Peak memory | 228148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035254793 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1035254793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1378015929 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1020109277 ps |
| CPU time | 269.43 seconds |
| Started | Sep 09 07:29:51 AM UTC 24 |
| Finished | Sep 09 07:34:25 AM UTC 24 |
| Peak memory | 258524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378015929 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1378015929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.459326949 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2838963350 ps |
| CPU time | 14.46 seconds |
| Started | Sep 09 07:29:51 AM UTC 24 |
| Finished | Sep 09 07:30:06 AM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459326949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.459326949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.535358440 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13914067170 ps |
| CPU time | 59.86 seconds |
| Started | Sep 09 07:29:51 AM UTC 24 |
| Finished | Sep 09 07:30:53 AM UTC 24 |
| Peak memory | 239336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=535358440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.rom_ctrl_stress_all_with_rand_reset.535358440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2586940814 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 661527890 ps |
| CPU time | 9.14 seconds |
| Started | Sep 09 07:30:21 AM UTC 24 |
| Finished | Sep 09 07:30:32 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586940814 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2586940814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.4099611893 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 695660785 ps |
| CPU time | 12.8 seconds |
| Started | Sep 09 07:30:07 AM UTC 24 |
| Finished | Sep 09 07:30:21 AM UTC 24 |
| Peak memory | 228644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099611893 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4099611893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3556112919 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3634695002 ps |
| CPU time | 14.53 seconds |
| Started | Sep 09 07:29:53 AM UTC 24 |
| Finished | Sep 09 07:30:09 AM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556112919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3556112919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.60773275 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 689670423 ps |
| CPU time | 8.75 seconds |
| Started | Sep 09 07:37:44 AM UTC 24 |
| Finished | Sep 09 07:37:54 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60773275 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.60773275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.358753722 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5011211833 ps |
| CPU time | 310.22 seconds |
| Started | Sep 09 07:37:19 AM UTC 24 |
| Finished | Sep 09 07:42:35 AM UTC 24 |
| Peak memory | 260524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358753722 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.358753722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3363651683 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 517884908 ps |
| CPU time | 24.57 seconds |
| Started | Sep 09 07:37:27 AM UTC 24 |
| Finished | Sep 09 07:37:53 AM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363651683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3363651683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1016854330 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 525672848 ps |
| CPU time | 12.9 seconds |
| Started | Sep 09 07:37:12 AM UTC 24 |
| Finished | Sep 09 07:37:26 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016854330 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1016854330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2619585756 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 8041961189 ps |
| CPU time | 37.37 seconds |
| Started | Sep 09 07:37:04 AM UTC 24 |
| Finished | Sep 09 07:37:43 AM UTC 24 |
| Peak memory | 228976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261958575 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.2619585756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2180489325 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2501280992 ps |
| CPU time | 139.55 seconds |
| Started | Sep 09 07:37:42 AM UTC 24 |
| Finished | Sep 09 07:40:05 AM UTC 24 |
| Peak memory | 239336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2180489325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2180489325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.760374415 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 175059119 ps |
| CPU time | 9.41 seconds |
| Started | Sep 09 07:39:09 AM UTC 24 |
| Finished | Sep 09 07:39:19 AM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760374415 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.760374415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3870934485 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5943845396 ps |
| CPU time | 199.69 seconds |
| Started | Sep 09 07:38:10 AM UTC 24 |
| Finished | Sep 09 07:41:34 AM UTC 24 |
| Peak memory | 228216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870934485 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.3870934485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1067624957 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1982290501 ps |
| CPU time | 25.61 seconds |
| Started | Sep 09 07:38:41 AM UTC 24 |
| Finished | Sep 09 07:39:08 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067624957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1067624957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.432491530 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1288371053 ps |
| CPU time | 13.32 seconds |
| Started | Sep 09 07:37:55 AM UTC 24 |
| Finished | Sep 09 07:38:10 AM UTC 24 |
| Peak memory | 228716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432491530 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.432491530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3382354434 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8617908061 ps |
| CPU time | 43.98 seconds |
| Started | Sep 09 07:37:54 AM UTC 24 |
| Finished | Sep 09 07:38:40 AM UTC 24 |
| Peak memory | 230832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338235443 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.3382354434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1544702418 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 15902352096 ps |
| CPU time | 58.2 seconds |
| Started | Sep 09 07:39:00 AM UTC 24 |
| Finished | Sep 09 07:40:00 AM UTC 24 |
| Peak memory | 239064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1544702418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1544702418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.116211281 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 169318651 ps |
| CPU time | 9.54 seconds |
| Started | Sep 09 07:39:47 AM UTC 24 |
| Finished | Sep 09 07:39:58 AM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116211281 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.116211281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1589369386 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 21493573266 ps |
| CPU time | 178.72 seconds |
| Started | Sep 09 07:39:34 AM UTC 24 |
| Finished | Sep 09 07:42:36 AM UTC 24 |
| Peak memory | 259564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589369386 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.1589369386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3618148872 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 496997171 ps |
| CPU time | 24.62 seconds |
| Started | Sep 09 07:39:34 AM UTC 24 |
| Finished | Sep 09 07:40:00 AM UTC 24 |
| Peak memory | 228136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618148872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3618148872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1484240964 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 694450977 ps |
| CPU time | 11.74 seconds |
| Started | Sep 09 07:39:20 AM UTC 24 |
| Finished | Sep 09 07:39:33 AM UTC 24 |
| Peak memory | 228508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484240964 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1484240964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3603920521 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 569566507 ps |
| CPU time | 43.14 seconds |
| Started | Sep 09 07:39:20 AM UTC 24 |
| Finished | Sep 09 07:40:04 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360392052 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.3603920521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.144451531 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1295463729 ps |
| CPU time | 53.77 seconds |
| Started | Sep 09 07:39:43 AM UTC 24 |
| Finished | Sep 09 07:40:39 AM UTC 24 |
| Peak memory | 233064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=144451531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.rom_ctrl_stress_all_with_rand_reset.144451531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3129530154 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 339338548 ps |
| CPU time | 8.92 seconds |
| Started | Sep 09 07:40:06 AM UTC 24 |
| Finished | Sep 09 07:40:16 AM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129530154 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3129530154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4281774680 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 25270156389 ps |
| CPU time | 267.74 seconds |
| Started | Sep 09 07:40:01 AM UTC 24 |
| Finished | Sep 09 07:44:33 AM UTC 24 |
| Peak memory | 259500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281774680 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.4281774680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.771763746 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3799501223 ps |
| CPU time | 25.07 seconds |
| Started | Sep 09 07:40:01 AM UTC 24 |
| Finished | Sep 09 07:40:27 AM UTC 24 |
| Peak memory | 228316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771763746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.771763746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1549553696 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 272646608 ps |
| CPU time | 13.25 seconds |
| Started | Sep 09 07:39:58 AM UTC 24 |
| Finished | Sep 09 07:40:13 AM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549553696 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1549553696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1566107361 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2100919461 ps |
| CPU time | 30.02 seconds |
| Started | Sep 09 07:39:56 AM UTC 24 |
| Finished | Sep 09 07:40:28 AM UTC 24 |
| Peak memory | 227512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156610736 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.1566107361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3073716198 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2323494756 ps |
| CPU time | 55.33 seconds |
| Started | Sep 09 07:40:06 AM UTC 24 |
| Finished | Sep 09 07:41:03 AM UTC 24 |
| Peak memory | 233000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3073716198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3073716198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.4228842235 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 259936253 ps |
| CPU time | 10.78 seconds |
| Started | Sep 09 07:40:39 AM UTC 24 |
| Finished | Sep 09 07:40:51 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228842235 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4228842235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1476394653 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1644484055 ps |
| CPU time | 150.62 seconds |
| Started | Sep 09 07:40:28 AM UTC 24 |
| Finished | Sep 09 07:43:02 AM UTC 24 |
| Peak memory | 259492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476394653 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.1476394653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2898314391 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 333549058 ps |
| CPU time | 21.47 seconds |
| Started | Sep 09 07:40:29 AM UTC 24 |
| Finished | Sep 09 07:40:52 AM UTC 24 |
| Peak memory | 228012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898314391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2898314391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.636103136 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 699007356 ps |
| CPU time | 11.72 seconds |
| Started | Sep 09 07:40:17 AM UTC 24 |
| Finished | Sep 09 07:40:30 AM UTC 24 |
| Peak memory | 228096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636103136 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.636103136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3388466591 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2213629454 ps |
| CPU time | 34.03 seconds |
| Started | Sep 09 07:40:14 AM UTC 24 |
| Finished | Sep 09 07:40:50 AM UTC 24 |
| Peak memory | 228896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338846659 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.3388466591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2235036617 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2564624621 ps |
| CPU time | 101.32 seconds |
| Started | Sep 09 07:40:31 AM UTC 24 |
| Finished | Sep 09 07:42:15 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2235036617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2235036617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.1989013775 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 660233607 ps |
| CPU time | 9.22 seconds |
| Started | Sep 09 07:41:27 AM UTC 24 |
| Finished | Sep 09 07:41:37 AM UTC 24 |
| Peak memory | 228064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989013775 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1989013775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2177293460 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 18763155494 ps |
| CPU time | 271.37 seconds |
| Started | Sep 09 07:40:53 AM UTC 24 |
| Finished | Sep 09 07:45:29 AM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177293460 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.2177293460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3189987878 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 827908581 ps |
| CPU time | 21.28 seconds |
| Started | Sep 09 07:41:04 AM UTC 24 |
| Finished | Sep 09 07:41:26 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189987878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3189987878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1993391152 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 355588752 ps |
| CPU time | 11.55 seconds |
| Started | Sep 09 07:40:51 AM UTC 24 |
| Finished | Sep 09 07:41:04 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993391152 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1993391152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3607682718 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3241455168 ps |
| CPU time | 46.14 seconds |
| Started | Sep 09 07:40:50 AM UTC 24 |
| Finished | Sep 09 07:41:38 AM UTC 24 |
| Peak memory | 228680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360768271 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.3607682718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3035068187 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 8525271533 ps |
| CPU time | 109.61 seconds |
| Started | Sep 09 07:41:05 AM UTC 24 |
| Finished | Sep 09 07:42:57 AM UTC 24 |
| Peak memory | 246552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3035068187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3035068187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3479836175 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 691883010 ps |
| CPU time | 9.1 seconds |
| Started | Sep 09 07:42:00 AM UTC 24 |
| Finished | Sep 09 07:42:10 AM UTC 24 |
| Peak memory | 227792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479836175 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3479836175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2461965011 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2528753849 ps |
| CPU time | 195.32 seconds |
| Started | Sep 09 07:41:39 AM UTC 24 |
| Finished | Sep 09 07:44:58 AM UTC 24 |
| Peak memory | 259496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461965011 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.2461965011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3902680109 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3781879003 ps |
| CPU time | 24.61 seconds |
| Started | Sep 09 07:41:55 AM UTC 24 |
| Finished | Sep 09 07:42:21 AM UTC 24 |
| Peak memory | 228572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902680109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3902680109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1376847036 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 262232974 ps |
| CPU time | 12.81 seconds |
| Started | Sep 09 07:41:38 AM UTC 24 |
| Finished | Sep 09 07:41:52 AM UTC 24 |
| Peak memory | 228076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376847036 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1376847036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3829989473 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1621413962 ps |
| CPU time | 23.88 seconds |
| Started | Sep 09 07:41:34 AM UTC 24 |
| Finished | Sep 09 07:41:59 AM UTC 24 |
| Peak memory | 227784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382998947 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.3829989473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2147760250 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1693701953 ps |
| CPU time | 90.42 seconds |
| Started | Sep 09 07:41:55 AM UTC 24 |
| Finished | Sep 09 07:43:27 AM UTC 24 |
| Peak memory | 232864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2147760250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2147760250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.146681378 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 174286796 ps |
| CPU time | 9.15 seconds |
| Started | Sep 09 07:42:35 AM UTC 24 |
| Finished | Sep 09 07:42:45 AM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146681378 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.146681378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4286502492 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5947436706 ps |
| CPU time | 367.83 seconds |
| Started | Sep 09 07:42:20 AM UTC 24 |
| Finished | Sep 09 07:48:34 AM UTC 24 |
| Peak memory | 259684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286502492 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.4286502492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3964005039 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1382835264 ps |
| CPU time | 21.97 seconds |
| Started | Sep 09 07:42:21 AM UTC 24 |
| Finished | Sep 09 07:42:44 AM UTC 24 |
| Peak memory | 228828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964005039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3964005039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3214539798 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 274228270 ps |
| CPU time | 14.22 seconds |
| Started | Sep 09 07:42:17 AM UTC 24 |
| Finished | Sep 09 07:42:32 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214539798 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3214539798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1911205051 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2172068037 ps |
| CPU time | 24.78 seconds |
| Started | Sep 09 07:42:12 AM UTC 24 |
| Finished | Sep 09 07:42:38 AM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191120505 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.1911205051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4087764865 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2014648662 ps |
| CPU time | 57.6 seconds |
| Started | Sep 09 07:42:33 AM UTC 24 |
| Finished | Sep 09 07:43:33 AM UTC 24 |
| Peak memory | 232768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4087764865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.4087764865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1590815315 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 340626697 ps |
| CPU time | 10.59 seconds |
| Started | Sep 09 07:42:58 AM UTC 24 |
| Finished | Sep 09 07:43:10 AM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590815315 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1590815315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1472322008 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 9779488063 ps |
| CPU time | 306.43 seconds |
| Started | Sep 09 07:42:46 AM UTC 24 |
| Finished | Sep 09 07:47:57 AM UTC 24 |
| Peak memory | 258460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472322008 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.1472322008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2987312287 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 333191029 ps |
| CPU time | 21.66 seconds |
| Started | Sep 09 07:42:47 AM UTC 24 |
| Finished | Sep 09 07:43:10 AM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987312287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2987312287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1165394896 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 272592601 ps |
| CPU time | 12.98 seconds |
| Started | Sep 09 07:42:38 AM UTC 24 |
| Finished | Sep 09 07:42:53 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165394896 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1165394896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2788281731 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2091397742 ps |
| CPU time | 51.12 seconds |
| Started | Sep 09 07:42:37 AM UTC 24 |
| Finished | Sep 09 07:43:30 AM UTC 24 |
| Peak memory | 228848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278828173 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.2788281731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.553751753 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5016994509 ps |
| CPU time | 172.37 seconds |
| Started | Sep 09 07:42:54 AM UTC 24 |
| Finished | Sep 09 07:45:49 AM UTC 24 |
| Peak memory | 239080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=553751753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 18.rom_ctrl_stress_all_with_rand_reset.553751753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3329704543 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 636146381 ps |
| CPU time | 9.46 seconds |
| Started | Sep 09 07:43:31 AM UTC 24 |
| Finished | Sep 09 07:43:42 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329704543 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3329704543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2032705783 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 6541689912 ps |
| CPU time | 361.68 seconds |
| Started | Sep 09 07:43:10 AM UTC 24 |
| Finished | Sep 09 07:49:17 AM UTC 24 |
| Peak memory | 257288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032705783 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.2032705783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2182040439 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 340168438 ps |
| CPU time | 21.69 seconds |
| Started | Sep 09 07:43:25 AM UTC 24 |
| Finished | Sep 09 07:43:48 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182040439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2182040439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.4147677794 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1068486110 ps |
| CPU time | 12.76 seconds |
| Started | Sep 09 07:43:10 AM UTC 24 |
| Finished | Sep 09 07:43:24 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147677794 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4147677794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1203706897 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 538431922 ps |
| CPU time | 37.76 seconds |
| Started | Sep 09 07:43:03 AM UTC 24 |
| Finished | Sep 09 07:43:42 AM UTC 24 |
| Peak memory | 228888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120370689 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.1203706897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.4064706028 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2117929777 ps |
| CPU time | 106.43 seconds |
| Started | Sep 09 07:43:28 AM UTC 24 |
| Finished | Sep 09 07:45:17 AM UTC 24 |
| Peak memory | 233060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4064706028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.rom_ctrl_stress_all_with_rand_reset.4064706028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1445888643 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 325973239 ps |
| CPU time | 9.86 seconds |
| Started | Sep 09 07:31:03 AM UTC 24 |
| Finished | Sep 09 07:31:14 AM UTC 24 |
| Peak memory | 228000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445888643 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1445888643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.835566261 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5983183498 ps |
| CPU time | 343.33 seconds |
| Started | Sep 09 07:30:35 AM UTC 24 |
| Finished | Sep 09 07:36:24 AM UTC 24 |
| Peak memory | 246192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835566261 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.835566261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3642281547 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1965810665 ps |
| CPU time | 35.02 seconds |
| Started | Sep 09 07:30:48 AM UTC 24 |
| Finished | Sep 09 07:31:25 AM UTC 24 |
| Peak memory | 228040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642281547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3642281547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1220005951 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 740012290 ps |
| CPU time | 12.37 seconds |
| Started | Sep 09 07:30:34 AM UTC 24 |
| Finished | Sep 09 07:30:48 AM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220005951 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1220005951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1434391426 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 367345192 ps |
| CPU time | 141.45 seconds |
| Started | Sep 09 07:30:53 AM UTC 24 |
| Finished | Sep 09 07:33:17 AM UTC 24 |
| Peak memory | 256512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434391426 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1434391426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3540785009 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 721742768 ps |
| CPU time | 11.83 seconds |
| Started | Sep 09 07:30:21 AM UTC 24 |
| Finished | Sep 09 07:30:34 AM UTC 24 |
| Peak memory | 228632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540785009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3540785009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.983938989 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 358085875 ps |
| CPU time | 15.61 seconds |
| Started | Sep 09 07:30:32 AM UTC 24 |
| Finished | Sep 09 07:30:49 AM UTC 24 |
| Peak memory | 228348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983938989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.983938989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2442094993 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7604086175 ps |
| CPU time | 54.68 seconds |
| Started | Sep 09 07:30:49 AM UTC 24 |
| Finished | Sep 09 07:31:46 AM UTC 24 |
| Peak memory | 230884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2442094993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2442094993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.4049895555 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 168236041 ps |
| CPU time | 9.13 seconds |
| Started | Sep 09 07:43:58 AM UTC 24 |
| Finished | Sep 09 07:44:08 AM UTC 24 |
| Peak memory | 228372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049895555 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4049895555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3494496844 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2566597752 ps |
| CPU time | 169.51 seconds |
| Started | Sep 09 07:43:44 AM UTC 24 |
| Finished | Sep 09 07:46:37 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494496844 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.3494496844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3218225315 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 498328528 ps |
| CPU time | 24.58 seconds |
| Started | Sep 09 07:43:49 AM UTC 24 |
| Finished | Sep 09 07:44:15 AM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218225315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3218225315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1427163289 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 270902865 ps |
| CPU time | 12.74 seconds |
| Started | Sep 09 07:43:43 AM UTC 24 |
| Finished | Sep 09 07:43:57 AM UTC 24 |
| Peak memory | 228652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427163289 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1427163289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.649147633 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1117289693 ps |
| CPU time | 35.2 seconds |
| Started | Sep 09 07:43:33 AM UTC 24 |
| Finished | Sep 09 07:44:10 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649147633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.649147633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1512818225 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 8538049444 ps |
| CPU time | 67.49 seconds |
| Started | Sep 09 07:43:58 AM UTC 24 |
| Finished | Sep 09 07:45:07 AM UTC 24 |
| Peak memory | 242048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1512818225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1512818225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1170484284 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 257540674 ps |
| CPU time | 10.7 seconds |
| Started | Sep 09 07:44:51 AM UTC 24 |
| Finished | Sep 09 07:45:02 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170484284 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1170484284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1749947012 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 5083786322 ps |
| CPU time | 290.64 seconds |
| Started | Sep 09 07:44:15 AM UTC 24 |
| Finished | Sep 09 07:49:11 AM UTC 24 |
| Peak memory | 227968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749947012 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.1749947012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3150107778 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1486053878 ps |
| CPU time | 12.81 seconds |
| Started | Sep 09 07:44:11 AM UTC 24 |
| Finished | Sep 09 07:44:25 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150107778 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3150107778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.319675595 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2786227333 ps |
| CPU time | 42.48 seconds |
| Started | Sep 09 07:44:09 AM UTC 24 |
| Finished | Sep 09 07:44:53 AM UTC 24 |
| Peak memory | 228776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319675595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.319675595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1979447694 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 498325369 ps |
| CPU time | 10.26 seconds |
| Started | Sep 09 07:45:17 AM UTC 24 |
| Finished | Sep 09 07:45:29 AM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979447694 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1979447694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1018739944 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4074921154 ps |
| CPU time | 165.54 seconds |
| Started | Sep 09 07:45:03 AM UTC 24 |
| Finished | Sep 09 07:47:51 AM UTC 24 |
| Peak memory | 244364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018739944 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.1018739944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.954223919 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 661792401 ps |
| CPU time | 21.56 seconds |
| Started | Sep 09 07:45:08 AM UTC 24 |
| Finished | Sep 09 07:45:31 AM UTC 24 |
| Peak memory | 228252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954223919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.954223919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1729308849 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1066919051 ps |
| CPU time | 13.48 seconds |
| Started | Sep 09 07:44:59 AM UTC 24 |
| Finished | Sep 09 07:45:13 AM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729308849 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1729308849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3876450996 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 716616741 ps |
| CPU time | 21.66 seconds |
| Started | Sep 09 07:44:54 AM UTC 24 |
| Finished | Sep 09 07:45:17 AM UTC 24 |
| Peak memory | 228828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387645099 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.3876450996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3508617140 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 5263467292 ps |
| CPU time | 82.3 seconds |
| Started | Sep 09 07:45:14 AM UTC 24 |
| Finished | Sep 09 07:46:38 AM UTC 24 |
| Peak memory | 243360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3508617140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3508617140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.1216929511 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 260609440 ps |
| CPU time | 10.77 seconds |
| Started | Sep 09 07:45:37 AM UTC 24 |
| Finished | Sep 09 07:45:49 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216929511 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1216929511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2823631503 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 10231845893 ps |
| CPU time | 247.9 seconds |
| Started | Sep 09 07:45:30 AM UTC 24 |
| Finished | Sep 09 07:49:42 AM UTC 24 |
| Peak memory | 259624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823631503 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.2823631503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3026714985 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1323829110 ps |
| CPU time | 21.96 seconds |
| Started | Sep 09 07:45:30 AM UTC 24 |
| Finished | Sep 09 07:45:53 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026714985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3026714985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2928203757 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 262370602 ps |
| CPU time | 13.06 seconds |
| Started | Sep 09 07:45:28 AM UTC 24 |
| Finished | Sep 09 07:45:42 AM UTC 24 |
| Peak memory | 228144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928203757 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2928203757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2272242183 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 365067569 ps |
| CPU time | 16.17 seconds |
| Started | Sep 09 07:45:18 AM UTC 24 |
| Finished | Sep 09 07:45:36 AM UTC 24 |
| Peak memory | 228912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227224218 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.2272242183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.401458309 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 11876868919 ps |
| CPU time | 118.05 seconds |
| Started | Sep 09 07:45:32 AM UTC 24 |
| Finished | Sep 09 07:47:33 AM UTC 24 |
| Peak memory | 246548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=401458309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 23.rom_ctrl_stress_all_with_rand_reset.401458309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3215438383 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1031249960 ps |
| CPU time | 10.63 seconds |
| Started | Sep 09 07:46:16 AM UTC 24 |
| Finished | Sep 09 07:46:28 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215438383 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3215438383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3513372959 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 6920563307 ps |
| CPU time | 264.62 seconds |
| Started | Sep 09 07:45:50 AM UTC 24 |
| Finished | Sep 09 07:50:19 AM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513372959 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.3513372959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2353674291 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1376786510 ps |
| CPU time | 21.4 seconds |
| Started | Sep 09 07:45:54 AM UTC 24 |
| Finished | Sep 09 07:46:16 AM UTC 24 |
| Peak memory | 228832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353674291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2353674291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.575478383 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1075028015 ps |
| CPU time | 13.72 seconds |
| Started | Sep 09 07:45:50 AM UTC 24 |
| Finished | Sep 09 07:46:05 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575478383 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.575478383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.948426162 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 548853636 ps |
| CPU time | 31.74 seconds |
| Started | Sep 09 07:45:42 AM UTC 24 |
| Finished | Sep 09 07:46:15 AM UTC 24 |
| Peak memory | 228712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948426162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.948426162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2759396769 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 9022951969 ps |
| CPU time | 177.85 seconds |
| Started | Sep 09 07:46:06 AM UTC 24 |
| Finished | Sep 09 07:49:07 AM UTC 24 |
| Peak memory | 246556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2759396769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2759396769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3271017737 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1046986478 ps |
| CPU time | 16.19 seconds |
| Started | Sep 09 07:46:50 AM UTC 24 |
| Finished | Sep 09 07:47:07 AM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271017737 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3271017737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1926362531 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 14467629104 ps |
| CPU time | 230.09 seconds |
| Started | Sep 09 07:46:37 AM UTC 24 |
| Finished | Sep 09 07:50:31 AM UTC 24 |
| Peak memory | 228672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926362531 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.1926362531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.222596560 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 349995208 ps |
| CPU time | 22.56 seconds |
| Started | Sep 09 07:46:39 AM UTC 24 |
| Finished | Sep 09 07:47:03 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222596560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.222596560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2270785395 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1009233389 ps |
| CPU time | 11.41 seconds |
| Started | Sep 09 07:46:28 AM UTC 24 |
| Finished | Sep 09 07:46:41 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270785395 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2270785395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1675074339 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 367162947 ps |
| CPU time | 29.96 seconds |
| Started | Sep 09 07:46:17 AM UTC 24 |
| Finished | Sep 09 07:46:48 AM UTC 24 |
| Peak memory | 228720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167507433 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.1675074339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.707702309 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2826991686 ps |
| CPU time | 46.95 seconds |
| Started | Sep 09 07:46:41 AM UTC 24 |
| Finished | Sep 09 07:47:30 AM UTC 24 |
| Peak memory | 230888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=707702309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 25.rom_ctrl_stress_all_with_rand_reset.707702309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3728842907 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 517644549 ps |
| CPU time | 10.91 seconds |
| Started | Sep 09 07:47:33 AM UTC 24 |
| Finished | Sep 09 07:47:45 AM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728842907 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3728842907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3332716625 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 25096001442 ps |
| CPU time | 360.73 seconds |
| Started | Sep 09 07:47:23 AM UTC 24 |
| Finished | Sep 09 07:53:30 AM UTC 24 |
| Peak memory | 249252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332716625 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.3332716625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.999441390 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 505894782 ps |
| CPU time | 25.2 seconds |
| Started | Sep 09 07:47:31 AM UTC 24 |
| Finished | Sep 09 07:47:58 AM UTC 24 |
| Peak memory | 227964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999441390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.999441390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.3109211889 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 269939412 ps |
| CPU time | 13.48 seconds |
| Started | Sep 09 07:47:08 AM UTC 24 |
| Finished | Sep 09 07:47:23 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109211889 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3109211889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2393177954 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 818960175 ps |
| CPU time | 25.15 seconds |
| Started | Sep 09 07:47:04 AM UTC 24 |
| Finished | Sep 09 07:47:30 AM UTC 24 |
| Peak memory | 228832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239317795 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.2393177954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.329668519 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 5562170241 ps |
| CPU time | 205.33 seconds |
| Started | Sep 09 07:47:31 AM UTC 24 |
| Finished | Sep 09 07:51:00 AM UTC 24 |
| Peak memory | 239080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=329668519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 26.rom_ctrl_stress_all_with_rand_reset.329668519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.214101082 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 885387254 ps |
| CPU time | 10.49 seconds |
| Started | Sep 09 07:48:08 AM UTC 24 |
| Finished | Sep 09 07:48:20 AM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214101082 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.214101082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.778280661 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 27899478107 ps |
| CPU time | 155.61 seconds |
| Started | Sep 09 07:47:58 AM UTC 24 |
| Finished | Sep 09 07:50:36 AM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778280661 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.778280661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1742654786 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1375791630 ps |
| CPU time | 21.45 seconds |
| Started | Sep 09 07:47:59 AM UTC 24 |
| Finished | Sep 09 07:48:21 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742654786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1742654786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.934809492 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1014290872 ps |
| CPU time | 13.06 seconds |
| Started | Sep 09 07:47:53 AM UTC 24 |
| Finished | Sep 09 07:48:07 AM UTC 24 |
| Peak memory | 228156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934809492 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.934809492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2103704448 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 558024529 ps |
| CPU time | 14.26 seconds |
| Started | Sep 09 07:47:46 AM UTC 24 |
| Finished | Sep 09 07:48:02 AM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210370444 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.2103704448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2212876646 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 9762046015 ps |
| CPU time | 136.5 seconds |
| Started | Sep 09 07:48:03 AM UTC 24 |
| Finished | Sep 09 07:50:22 AM UTC 24 |
| Peak memory | 239076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2212876646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2212876646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.204097702 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3774225110 ps |
| CPU time | 14.88 seconds |
| Started | Sep 09 07:49:05 AM UTC 24 |
| Finished | Sep 09 07:49:21 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204097702 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.204097702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1692253372 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 19418001505 ps |
| CPU time | 247.98 seconds |
| Started | Sep 09 07:48:34 AM UTC 24 |
| Finished | Sep 09 07:52:47 AM UTC 24 |
| Peak memory | 232044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692253372 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.1692253372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.576255737 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 5515640863 ps |
| CPU time | 25.8 seconds |
| Started | Sep 09 07:48:37 AM UTC 24 |
| Finished | Sep 09 07:49:04 AM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576255737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.576255737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.928955598 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 695097266 ps |
| CPU time | 11.93 seconds |
| Started | Sep 09 07:48:22 AM UTC 24 |
| Finished | Sep 09 07:48:35 AM UTC 24 |
| Peak memory | 228716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928955598 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.928955598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3894357041 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1534232622 ps |
| CPU time | 16.78 seconds |
| Started | Sep 09 07:48:20 AM UTC 24 |
| Finished | Sep 09 07:48:38 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389435704 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.3894357041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2689274476 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 18583624528 ps |
| CPU time | 205.57 seconds |
| Started | Sep 09 07:48:39 AM UTC 24 |
| Finished | Sep 09 07:52:08 AM UTC 24 |
| Peak memory | 241128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2689274476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2689274476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2342287956 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 292836268 ps |
| CPU time | 9.35 seconds |
| Started | Sep 09 07:49:39 AM UTC 24 |
| Finished | Sep 09 07:49:49 AM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342287956 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2342287956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.113276879 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4505034534 ps |
| CPU time | 331.3 seconds |
| Started | Sep 09 07:49:18 AM UTC 24 |
| Finished | Sep 09 07:54:55 AM UTC 24 |
| Peak memory | 263620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113276879 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.113276879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3593683287 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 665292725 ps |
| CPU time | 20.98 seconds |
| Started | Sep 09 07:49:22 AM UTC 24 |
| Finished | Sep 09 07:49:45 AM UTC 24 |
| Peak memory | 228140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593683287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3593683287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2327424231 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 922015692 ps |
| CPU time | 11.62 seconds |
| Started | Sep 09 07:49:11 AM UTC 24 |
| Finished | Sep 09 07:49:24 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327424231 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2327424231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.820477166 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 561572185 ps |
| CPU time | 28.4 seconds |
| Started | Sep 09 07:49:08 AM UTC 24 |
| Finished | Sep 09 07:49:38 AM UTC 24 |
| Peak memory | 228840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820477166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.820477166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.285685618 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2979105997 ps |
| CPU time | 43.6 seconds |
| Started | Sep 09 07:49:25 AM UTC 24 |
| Finished | Sep 09 07:50:10 AM UTC 24 |
| Peak memory | 232936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=285685618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 29.rom_ctrl_stress_all_with_rand_reset.285685618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2997130746 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 339063617 ps |
| CPU time | 9.13 seconds |
| Started | Sep 09 07:32:14 AM UTC 24 |
| Finished | Sep 09 07:32:24 AM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997130746 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2997130746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.249817332 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1031963540 ps |
| CPU time | 24.87 seconds |
| Started | Sep 09 07:31:46 AM UTC 24 |
| Finished | Sep 09 07:32:13 AM UTC 24 |
| Peak memory | 228348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249817332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.249817332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.820299501 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 920056724 ps |
| CPU time | 13.28 seconds |
| Started | Sep 09 07:31:30 AM UTC 24 |
| Finished | Sep 09 07:31:45 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820299501 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.820299501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.4277441185 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2675829595 ps |
| CPU time | 132.44 seconds |
| Started | Sep 09 07:31:56 AM UTC 24 |
| Finished | Sep 09 07:34:11 AM UTC 24 |
| Peak memory | 257548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277441185 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4277441185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.4072315990 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 270943684 ps |
| CPU time | 13.53 seconds |
| Started | Sep 09 07:31:15 AM UTC 24 |
| Finished | Sep 09 07:31:30 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072315990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4072315990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3040539748 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 381656903 ps |
| CPU time | 28.24 seconds |
| Started | Sep 09 07:31:25 AM UTC 24 |
| Finished | Sep 09 07:31:55 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304053974 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.3040539748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3019667917 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9519618894 ps |
| CPU time | 133.2 seconds |
| Started | Sep 09 07:31:53 AM UTC 24 |
| Finished | Sep 09 07:34:08 AM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3019667917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3019667917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.3469766845 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 496870838 ps |
| CPU time | 10.55 seconds |
| Started | Sep 09 07:50:21 AM UTC 24 |
| Finished | Sep 09 07:50:32 AM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469766845 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3469766845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.806460204 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 20583471887 ps |
| CPU time | 253.43 seconds |
| Started | Sep 09 07:49:50 AM UTC 24 |
| Finished | Sep 09 07:54:08 AM UTC 24 |
| Peak memory | 229240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806460204 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.806460204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.1440027520 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 516165734 ps |
| CPU time | 25.14 seconds |
| Started | Sep 09 07:49:59 AM UTC 24 |
| Finished | Sep 09 07:50:26 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440027520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1440027520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1263427080 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 239191866 ps |
| CPU time | 11.53 seconds |
| Started | Sep 09 07:49:46 AM UTC 24 |
| Finished | Sep 09 07:49:59 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263427080 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1263427080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2067059983 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 15514281790 ps |
| CPU time | 47.4 seconds |
| Started | Sep 09 07:49:43 AM UTC 24 |
| Finished | Sep 09 07:50:32 AM UTC 24 |
| Peak memory | 229036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206705998 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.2067059983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.16997658 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 11065606754 ps |
| CPU time | 208 seconds |
| Started | Sep 09 07:50:10 AM UTC 24 |
| Finished | Sep 09 07:53:42 AM UTC 24 |
| Peak memory | 241440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=16997658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.16997658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3586884273 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 830585880 ps |
| CPU time | 9.32 seconds |
| Started | Sep 09 07:50:37 AM UTC 24 |
| Finished | Sep 09 07:50:48 AM UTC 24 |
| Peak memory | 228072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586884273 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3586884273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3554265591 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 10860293394 ps |
| CPU time | 204.26 seconds |
| Started | Sep 09 07:50:32 AM UTC 24 |
| Finished | Sep 09 07:54:00 AM UTC 24 |
| Peak memory | 259628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554265591 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.3554265591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2689834061 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 8203636915 ps |
| CPU time | 33.88 seconds |
| Started | Sep 09 07:50:33 AM UTC 24 |
| Finished | Sep 09 07:51:09 AM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689834061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2689834061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2396464861 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 724811649 ps |
| CPU time | 11.41 seconds |
| Started | Sep 09 07:50:27 AM UTC 24 |
| Finished | Sep 09 07:50:39 AM UTC 24 |
| Peak memory | 228572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396464861 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2396464861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1915898403 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2227186404 ps |
| CPU time | 33.97 seconds |
| Started | Sep 09 07:50:23 AM UTC 24 |
| Finished | Sep 09 07:50:58 AM UTC 24 |
| Peak memory | 228976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191589840 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.1915898403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3878463676 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 51347568362 ps |
| CPU time | 166.84 seconds |
| Started | Sep 09 07:50:33 AM UTC 24 |
| Finished | Sep 09 07:53:23 AM UTC 24 |
| Peak memory | 241312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3878463676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3878463676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.941267626 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 4474534881 ps |
| CPU time | 15.06 seconds |
| Started | Sep 09 07:51:06 AM UTC 24 |
| Finished | Sep 09 07:51:22 AM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941267626 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.941267626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4014187835 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 6553105741 ps |
| CPU time | 375.74 seconds |
| Started | Sep 09 07:50:59 AM UTC 24 |
| Finished | Sep 09 07:57:20 AM UTC 24 |
| Peak memory | 259588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014187835 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.4014187835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.712452953 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2118235986 ps |
| CPU time | 33.45 seconds |
| Started | Sep 09 07:51:01 AM UTC 24 |
| Finished | Sep 09 07:51:36 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712452953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.712452953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.67592601 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2314123184 ps |
| CPU time | 12.85 seconds |
| Started | Sep 09 07:50:49 AM UTC 24 |
| Finished | Sep 09 07:51:03 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67592601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.67592601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3539897622 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1580653890 ps |
| CPU time | 23.22 seconds |
| Started | Sep 09 07:50:40 AM UTC 24 |
| Finished | Sep 09 07:51:05 AM UTC 24 |
| Peak memory | 228912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353989762 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.3539897622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.250633293 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 10845805165 ps |
| CPU time | 153.26 seconds |
| Started | Sep 09 07:51:03 AM UTC 24 |
| Finished | Sep 09 07:53:39 AM UTC 24 |
| Peak memory | 246552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=250633293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 32.rom_ctrl_stress_all_with_rand_reset.250633293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1174736240 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 174955934 ps |
| CPU time | 9.06 seconds |
| Started | Sep 09 07:52:04 AM UTC 24 |
| Finished | Sep 09 07:52:14 AM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174736240 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1174736240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3105709067 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 38778401239 ps |
| CPU time | 387.13 seconds |
| Started | Sep 09 07:51:28 AM UTC 24 |
| Finished | Sep 09 07:58:02 AM UTC 24 |
| Peak memory | 261536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105709067 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.3105709067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.1406090712 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2065126178 ps |
| CPU time | 25.06 seconds |
| Started | Sep 09 07:51:37 AM UTC 24 |
| Finished | Sep 09 07:52:03 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406090712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1406090712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2607381681 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 725343371 ps |
| CPU time | 11.58 seconds |
| Started | Sep 09 07:51:23 AM UTC 24 |
| Finished | Sep 09 07:51:36 AM UTC 24 |
| Peak memory | 228092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607381681 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2607381681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.609070618 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 680732541 ps |
| CPU time | 17.7 seconds |
| Started | Sep 09 07:51:09 AM UTC 24 |
| Finished | Sep 09 07:51:28 AM UTC 24 |
| Peak memory | 228696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609070618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.609070618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2072031288 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1842603167 ps |
| CPU time | 78.32 seconds |
| Started | Sep 09 07:51:37 AM UTC 24 |
| Finished | Sep 09 07:52:57 AM UTC 24 |
| Peak memory | 245292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2072031288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2072031288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.671214076 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 252124936 ps |
| CPU time | 10.65 seconds |
| Started | Sep 09 07:52:58 AM UTC 24 |
| Finished | Sep 09 07:53:10 AM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671214076 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.671214076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.826213347 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2244410915 ps |
| CPU time | 137.68 seconds |
| Started | Sep 09 07:52:29 AM UTC 24 |
| Finished | Sep 09 07:54:49 AM UTC 24 |
| Peak memory | 244108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826213347 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.826213347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.392888409 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 620871227 ps |
| CPU time | 24.71 seconds |
| Started | Sep 09 07:52:48 AM UTC 24 |
| Finished | Sep 09 07:53:14 AM UTC 24 |
| Peak memory | 227964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392888409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.392888409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.627504498 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 182786057 ps |
| CPU time | 11.59 seconds |
| Started | Sep 09 07:52:15 AM UTC 24 |
| Finished | Sep 09 07:52:28 AM UTC 24 |
| Peak memory | 228104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627504498 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.627504498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1613839962 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 4743635970 ps |
| CPU time | 39.29 seconds |
| Started | Sep 09 07:52:09 AM UTC 24 |
| Finished | Sep 09 07:52:50 AM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161383996 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.1613839962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1965756064 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3645464101 ps |
| CPU time | 136.31 seconds |
| Started | Sep 09 07:52:51 AM UTC 24 |
| Finished | Sep 09 07:55:10 AM UTC 24 |
| Peak memory | 235240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1965756064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1965756064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.628686518 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4933957061 ps |
| CPU time | 10.99 seconds |
| Started | Sep 09 07:53:40 AM UTC 24 |
| Finished | Sep 09 07:53:52 AM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628686518 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.628686518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3293531780 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 25400111991 ps |
| CPU time | 351.13 seconds |
| Started | Sep 09 07:53:24 AM UTC 24 |
| Finished | Sep 09 07:59:21 AM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293531780 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.3293531780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.182383233 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1500573659 ps |
| CPU time | 21.32 seconds |
| Started | Sep 09 07:53:29 AM UTC 24 |
| Finished | Sep 09 07:53:51 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182383233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.182383233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.4036486747 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 180244607 ps |
| CPU time | 12.23 seconds |
| Started | Sep 09 07:53:14 AM UTC 24 |
| Finished | Sep 09 07:53:28 AM UTC 24 |
| Peak memory | 228164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036486747 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4036486747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1015951108 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 352437805 ps |
| CPU time | 30.28 seconds |
| Started | Sep 09 07:53:10 AM UTC 24 |
| Finished | Sep 09 07:53:42 AM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101595110 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.1015951108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1836996828 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3554109497 ps |
| CPU time | 45.37 seconds |
| Started | Sep 09 07:53:31 AM UTC 24 |
| Finished | Sep 09 07:54:18 AM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1836996828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1836996828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2296282931 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1960496520 ps |
| CPU time | 15.34 seconds |
| Started | Sep 09 07:54:01 AM UTC 24 |
| Finished | Sep 09 07:54:17 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296282931 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2296282931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.261991707 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 13341475597 ps |
| CPU time | 179.58 seconds |
| Started | Sep 09 07:53:52 AM UTC 24 |
| Finished | Sep 09 07:56:55 AM UTC 24 |
| Peak memory | 228892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261991707 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.261991707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.963662806 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 8242344240 ps |
| CPU time | 34.31 seconds |
| Started | Sep 09 07:53:52 AM UTC 24 |
| Finished | Sep 09 07:54:28 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963662806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.963662806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2733649870 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 738173645 ps |
| CPU time | 12.3 seconds |
| Started | Sep 09 07:53:43 AM UTC 24 |
| Finished | Sep 09 07:53:57 AM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733649870 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2733649870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2949759956 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 311789267 ps |
| CPU time | 26.63 seconds |
| Started | Sep 09 07:53:43 AM UTC 24 |
| Finished | Sep 09 07:54:11 AM UTC 24 |
| Peak memory | 228784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294975995 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.2949759956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3630823536 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 169053024 ps |
| CPU time | 9.03 seconds |
| Started | Sep 09 07:54:27 AM UTC 24 |
| Finished | Sep 09 07:54:37 AM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630823536 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3630823536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.906108589 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 25017838408 ps |
| CPU time | 370.02 seconds |
| Started | Sep 09 07:54:18 AM UTC 24 |
| Finished | Sep 09 08:00:34 AM UTC 24 |
| Peak memory | 259504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906108589 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.906108589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1833383317 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 346959937 ps |
| CPU time | 21.33 seconds |
| Started | Sep 09 07:54:18 AM UTC 24 |
| Finished | Sep 09 07:54:41 AM UTC 24 |
| Peak memory | 228096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833383317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1833383317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3312143970 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 686037240 ps |
| CPU time | 12.39 seconds |
| Started | Sep 09 07:54:12 AM UTC 24 |
| Finished | Sep 09 07:54:25 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312143970 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3312143970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.3130308505 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1075126629 ps |
| CPU time | 49.15 seconds |
| Started | Sep 09 07:54:09 AM UTC 24 |
| Finished | Sep 09 07:55:00 AM UTC 24 |
| Peak memory | 229040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313030850 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.3130308505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1851209627 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 19487087960 ps |
| CPU time | 169.89 seconds |
| Started | Sep 09 07:54:19 AM UTC 24 |
| Finished | Sep 09 07:57:12 AM UTC 24 |
| Peak memory | 246548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1851209627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1851209627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3493807490 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 422478145 ps |
| CPU time | 11.28 seconds |
| Started | Sep 09 07:54:52 AM UTC 24 |
| Finished | Sep 09 07:55:05 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493807490 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3493807490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4168708233 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 9133233611 ps |
| CPU time | 161.32 seconds |
| Started | Sep 09 07:54:42 AM UTC 24 |
| Finished | Sep 09 07:57:27 AM UTC 24 |
| Peak memory | 257428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168708233 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.4168708233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2200421410 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2259534296 ps |
| CPU time | 24.81 seconds |
| Started | Sep 09 07:54:50 AM UTC 24 |
| Finished | Sep 09 07:55:16 AM UTC 24 |
| Peak memory | 228700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200421410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2200421410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3044508627 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 275272922 ps |
| CPU time | 12.91 seconds |
| Started | Sep 09 07:54:38 AM UTC 24 |
| Finished | Sep 09 07:54:52 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044508627 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3044508627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.576473228 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1048877324 ps |
| CPU time | 21.73 seconds |
| Started | Sep 09 07:54:29 AM UTC 24 |
| Finished | Sep 09 07:54:52 AM UTC 24 |
| Peak memory | 228632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576473228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.576473228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2838065689 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1154324747 ps |
| CPU time | 49.93 seconds |
| Started | Sep 09 07:54:52 AM UTC 24 |
| Finished | Sep 09 07:55:44 AM UTC 24 |
| Peak memory | 233064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2838065689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2838065689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.4140594867 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1033665230 ps |
| CPU time | 10.78 seconds |
| Started | Sep 09 07:55:16 AM UTC 24 |
| Finished | Sep 09 07:55:28 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140594867 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4140594867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1850908551 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 6382481803 ps |
| CPU time | 181.27 seconds |
| Started | Sep 09 07:55:06 AM UTC 24 |
| Finished | Sep 09 07:58:11 AM UTC 24 |
| Peak memory | 257548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850908551 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.1850908551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3811757280 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1984808676 ps |
| CPU time | 13.32 seconds |
| Started | Sep 09 07:55:01 AM UTC 24 |
| Finished | Sep 09 07:55:15 AM UTC 24 |
| Peak memory | 228580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811757280 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3811757280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.145284814 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 544210692 ps |
| CPU time | 17.3 seconds |
| Started | Sep 09 07:54:56 AM UTC 24 |
| Finished | Sep 09 07:55:14 AM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145284814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.145284814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4013595394 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 7123980907 ps |
| CPU time | 107.89 seconds |
| Started | Sep 09 07:55:15 AM UTC 24 |
| Finished | Sep 09 07:57:05 AM UTC 24 |
| Peak memory | 235176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4013595394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.4013595394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1073317514 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 174422279 ps |
| CPU time | 9.01 seconds |
| Started | Sep 09 07:33:14 AM UTC 24 |
| Finished | Sep 09 07:33:24 AM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073317514 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1073317514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3048765616 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8603666786 ps |
| CPU time | 138.41 seconds |
| Started | Sep 09 07:32:41 AM UTC 24 |
| Finished | Sep 09 07:35:02 AM UTC 24 |
| Peak memory | 245996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048765616 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.3048765616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.4276909507 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1053632394 ps |
| CPU time | 25.1 seconds |
| Started | Sep 09 07:32:47 AM UTC 24 |
| Finished | Sep 09 07:33:13 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276909507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4276909507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1818765009 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1065896800 ps |
| CPU time | 13.41 seconds |
| Started | Sep 09 07:32:31 AM UTC 24 |
| Finished | Sep 09 07:32:46 AM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818765009 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1818765009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2219361197 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 590956378 ps |
| CPU time | 263.24 seconds |
| Started | Sep 09 07:33:13 AM UTC 24 |
| Finished | Sep 09 07:37:41 AM UTC 24 |
| Peak memory | 258528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219361197 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2219361197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1754490245 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 515673011 ps |
| CPU time | 13.72 seconds |
| Started | Sep 09 07:32:15 AM UTC 24 |
| Finished | Sep 09 07:32:30 AM UTC 24 |
| Peak memory | 225468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754490245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1754490245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.72572224 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2165124191 ps |
| CPU time | 27.63 seconds |
| Started | Sep 09 07:32:25 AM UTC 24 |
| Finished | Sep 09 07:32:54 AM UTC 24 |
| Peak memory | 228700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72572224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.72572224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.4214494646 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 717544143 ps |
| CPU time | 9.17 seconds |
| Started | Sep 09 07:55:45 AM UTC 24 |
| Finished | Sep 09 07:55:55 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214494646 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4214494646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2626654495 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 25303340000 ps |
| CPU time | 326.46 seconds |
| Started | Sep 09 07:55:35 AM UTC 24 |
| Finished | Sep 09 08:01:07 AM UTC 24 |
| Peak memory | 258732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626654495 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.2626654495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1405538605 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 347573403 ps |
| CPU time | 21.9 seconds |
| Started | Sep 09 07:55:42 AM UTC 24 |
| Finished | Sep 09 07:56:05 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405538605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1405538605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3548181470 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 354599153 ps |
| CPU time | 11.59 seconds |
| Started | Sep 09 07:55:30 AM UTC 24 |
| Finished | Sep 09 07:55:42 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548181470 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3548181470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.862598687 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 604466229 ps |
| CPU time | 22.4 seconds |
| Started | Sep 09 07:55:17 AM UTC 24 |
| Finished | Sep 09 07:55:41 AM UTC 24 |
| Peak memory | 228824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862598687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.862598687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3272667079 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 677300285 ps |
| CPU time | 22.07 seconds |
| Started | Sep 09 07:55:43 AM UTC 24 |
| Finished | Sep 09 07:56:06 AM UTC 24 |
| Peak memory | 231016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3272667079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3272667079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1727829017 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 688110276 ps |
| CPU time | 9.03 seconds |
| Started | Sep 09 07:56:51 AM UTC 24 |
| Finished | Sep 09 07:57:01 AM UTC 24 |
| Peak memory | 228316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727829017 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1727829017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.162141451 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 13721988211 ps |
| CPU time | 291.33 seconds |
| Started | Sep 09 07:56:08 AM UTC 24 |
| Finished | Sep 09 08:01:04 AM UTC 24 |
| Peak memory | 261588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162141451 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.162141451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2994280201 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2117457326 ps |
| CPU time | 34.79 seconds |
| Started | Sep 09 07:56:16 AM UTC 24 |
| Finished | Sep 09 07:56:52 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994280201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2994280201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.491475192 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2878726726 ps |
| CPU time | 13.37 seconds |
| Started | Sep 09 07:56:05 AM UTC 24 |
| Finished | Sep 09 07:56:20 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491475192 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.491475192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3212854655 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 245148094 ps |
| CPU time | 16.89 seconds |
| Started | Sep 09 07:55:56 AM UTC 24 |
| Finished | Sep 09 07:56:14 AM UTC 24 |
| Peak memory | 228720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321285465 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.3212854655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3922529442 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 668955333 ps |
| CPU time | 27.95 seconds |
| Started | Sep 09 07:56:21 AM UTC 24 |
| Finished | Sep 09 07:56:50 AM UTC 24 |
| Peak memory | 230800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3922529442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3922529442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1389557640 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1179064161 ps |
| CPU time | 9.16 seconds |
| Started | Sep 09 07:57:14 AM UTC 24 |
| Finished | Sep 09 07:57:24 AM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389557640 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1389557640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4291628163 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 23477668046 ps |
| CPU time | 365.49 seconds |
| Started | Sep 09 07:57:02 AM UTC 24 |
| Finished | Sep 09 08:03:14 AM UTC 24 |
| Peak memory | 249248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291628163 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.4291628163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.2290002326 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 706655996 ps |
| CPU time | 21.38 seconds |
| Started | Sep 09 07:57:07 AM UTC 24 |
| Finished | Sep 09 07:57:29 AM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290002326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2290002326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.842457803 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 183101176 ps |
| CPU time | 11.71 seconds |
| Started | Sep 09 07:56:56 AM UTC 24 |
| Finished | Sep 09 07:57:09 AM UTC 24 |
| Peak memory | 228112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842457803 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.842457803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1922308843 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1050418358 ps |
| CPU time | 25.01 seconds |
| Started | Sep 09 07:56:53 AM UTC 24 |
| Finished | Sep 09 07:57:20 AM UTC 24 |
| Peak memory | 228760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192230884 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.1922308843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2091426735 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 8340483487 ps |
| CPU time | 60.93 seconds |
| Started | Sep 09 07:57:10 AM UTC 24 |
| Finished | Sep 09 07:58:12 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2091426735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2091426735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1060750346 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 250099966 ps |
| CPU time | 10.75 seconds |
| Started | Sep 09 07:57:35 AM UTC 24 |
| Finished | Sep 09 07:57:47 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060750346 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1060750346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2391603848 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 30738619731 ps |
| CPU time | 435.9 seconds |
| Started | Sep 09 07:57:25 AM UTC 24 |
| Finished | Sep 09 08:04:48 AM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391603848 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.2391603848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.4219421574 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 347791114 ps |
| CPU time | 21.49 seconds |
| Started | Sep 09 07:57:28 AM UTC 24 |
| Finished | Sep 09 07:57:51 AM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219421574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4219421574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.412758526 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1556596769 ps |
| CPU time | 11.48 seconds |
| Started | Sep 09 07:57:21 AM UTC 24 |
| Finished | Sep 09 07:57:34 AM UTC 24 |
| Peak memory | 228376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412758526 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.412758526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3302383582 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 540325503 ps |
| CPU time | 34.22 seconds |
| Started | Sep 09 07:57:21 AM UTC 24 |
| Finished | Sep 09 07:57:57 AM UTC 24 |
| Peak memory | 228700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330238358 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.3302383582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.474976247 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 39275202753 ps |
| CPU time | 165.35 seconds |
| Started | Sep 09 07:57:30 AM UTC 24 |
| Finished | Sep 09 08:00:18 AM UTC 24 |
| Peak memory | 239080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=474976247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 43.rom_ctrl_stress_all_with_rand_reset.474976247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.4197923717 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 231547830 ps |
| CPU time | 8.92 seconds |
| Started | Sep 09 07:58:12 AM UTC 24 |
| Finished | Sep 09 07:58:22 AM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197923717 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4197923717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2233674823 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 37151009567 ps |
| CPU time | 297.33 seconds |
| Started | Sep 09 07:57:57 AM UTC 24 |
| Finished | Sep 09 08:02:59 AM UTC 24 |
| Peak memory | 259756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233674823 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.2233674823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1701830189 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1976374938 ps |
| CPU time | 24.08 seconds |
| Started | Sep 09 07:58:03 AM UTC 24 |
| Finished | Sep 09 07:58:29 AM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701830189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1701830189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.342991938 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 648866891 ps |
| CPU time | 11.31 seconds |
| Started | Sep 09 07:57:52 AM UTC 24 |
| Finished | Sep 09 07:58:04 AM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342991938 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.342991938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.630981296 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3882525643 ps |
| CPU time | 26.53 seconds |
| Started | Sep 09 07:57:48 AM UTC 24 |
| Finished | Sep 09 07:58:16 AM UTC 24 |
| Peak memory | 228696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630981296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.630981296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.329320755 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2571129916 ps |
| CPU time | 125.27 seconds |
| Started | Sep 09 07:58:05 AM UTC 24 |
| Finished | Sep 09 08:00:13 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=329320755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 44.rom_ctrl_stress_all_with_rand_reset.329320755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.4045457833 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 884755772 ps |
| CPU time | 11.3 seconds |
| Started | Sep 09 07:58:54 AM UTC 24 |
| Finished | Sep 09 07:59:06 AM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045457833 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4045457833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.326414975 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 22446844520 ps |
| CPU time | 334.61 seconds |
| Started | Sep 09 07:58:23 AM UTC 24 |
| Finished | Sep 09 08:04:03 AM UTC 24 |
| Peak memory | 259756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326414975 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.326414975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2762115161 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5496934224 ps |
| CPU time | 25.11 seconds |
| Started | Sep 09 07:58:29 AM UTC 24 |
| Finished | Sep 09 07:58:56 AM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762115161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2762115161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.958016826 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 359743398 ps |
| CPU time | 12.14 seconds |
| Started | Sep 09 07:58:17 AM UTC 24 |
| Finished | Sep 09 07:58:30 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958016826 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.958016826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1404229969 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2205123489 ps |
| CPU time | 37.59 seconds |
| Started | Sep 09 07:58:14 AM UTC 24 |
| Finished | Sep 09 07:58:53 AM UTC 24 |
| Peak memory | 228780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140422996 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.1404229969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.314257667 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 9307951425 ps |
| CPU time | 245.78 seconds |
| Started | Sep 09 07:58:31 AM UTC 24 |
| Finished | Sep 09 08:02:42 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=314257667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 45.rom_ctrl_stress_all_with_rand_reset.314257667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4207318292 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 497788394 ps |
| CPU time | 11.02 seconds |
| Started | Sep 09 07:59:45 AM UTC 24 |
| Finished | Sep 09 07:59:58 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207318292 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4207318292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1319729242 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 12579678132 ps |
| CPU time | 179.14 seconds |
| Started | Sep 09 07:59:22 AM UTC 24 |
| Finished | Sep 09 08:02:25 AM UTC 24 |
| Peak memory | 259628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319729242 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.1319729242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3422070414 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 343692362 ps |
| CPU time | 21.67 seconds |
| Started | Sep 09 07:59:22 AM UTC 24 |
| Finished | Sep 09 07:59:45 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422070414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3422070414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1100243914 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 258080292 ps |
| CPU time | 12.78 seconds |
| Started | Sep 09 07:59:07 AM UTC 24 |
| Finished | Sep 09 07:59:21 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100243914 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1100243914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1703693089 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 211425928 ps |
| CPU time | 25.07 seconds |
| Started | Sep 09 07:58:57 AM UTC 24 |
| Finished | Sep 09 07:59:23 AM UTC 24 |
| Peak memory | 228600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170369308 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.1703693089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1510545603 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 18227301198 ps |
| CPU time | 184.08 seconds |
| Started | Sep 09 07:59:24 AM UTC 24 |
| Finished | Sep 09 08:02:32 AM UTC 24 |
| Peak memory | 246344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1510545603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1510545603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3287231756 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 260292826 ps |
| CPU time | 10.83 seconds |
| Started | Sep 09 08:00:34 AM UTC 24 |
| Finished | Sep 09 08:00:47 AM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287231756 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3287231756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4087673904 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3362178805 ps |
| CPU time | 257 seconds |
| Started | Sep 09 08:00:19 AM UTC 24 |
| Finished | Sep 09 08:04:40 AM UTC 24 |
| Peak memory | 247464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087673904 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.4087673904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3030234081 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1030396204 ps |
| CPU time | 24.74 seconds |
| Started | Sep 09 08:00:28 AM UTC 24 |
| Finished | Sep 09 08:00:54 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030234081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3030234081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2240599469 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1180771140 ps |
| CPU time | 13.45 seconds |
| Started | Sep 09 08:00:14 AM UTC 24 |
| Finished | Sep 09 08:00:29 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240599469 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2240599469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3862935219 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 470620140 ps |
| CPU time | 27.1 seconds |
| Started | Sep 09 07:59:59 AM UTC 24 |
| Finished | Sep 09 08:00:27 AM UTC 24 |
| Peak memory | 228976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386293521 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.3862935219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4002889795 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5977049846 ps |
| CPU time | 148.41 seconds |
| Started | Sep 09 08:00:29 AM UTC 24 |
| Finished | Sep 09 08:03:01 AM UTC 24 |
| Peak memory | 246356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4002889795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4002889795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1122522964 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 338710198 ps |
| CPU time | 9.03 seconds |
| Started | Sep 09 08:01:24 AM UTC 24 |
| Finished | Sep 09 08:01:35 AM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122522964 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1122522964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3716063793 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 10365597095 ps |
| CPU time | 236.17 seconds |
| Started | Sep 09 08:01:05 AM UTC 24 |
| Finished | Sep 09 08:05:05 AM UTC 24 |
| Peak memory | 256320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716063793 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.3716063793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.685544423 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2601156561 ps |
| CPU time | 25.17 seconds |
| Started | Sep 09 08:01:07 AM UTC 24 |
| Finished | Sep 09 08:01:34 AM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685544423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.685544423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.674810281 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1077822466 ps |
| CPU time | 13.25 seconds |
| Started | Sep 09 08:00:55 AM UTC 24 |
| Finished | Sep 09 08:01:09 AM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674810281 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.674810281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.2524424847 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1573360819 ps |
| CPU time | 34.39 seconds |
| Started | Sep 09 08:00:48 AM UTC 24 |
| Finished | Sep 09 08:01:23 AM UTC 24 |
| Peak memory | 228832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252442484 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.2524424847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4228838585 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2485716601 ps |
| CPU time | 137.72 seconds |
| Started | Sep 09 08:01:10 AM UTC 24 |
| Finished | Sep 09 08:03:31 AM UTC 24 |
| Peak memory | 243432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4228838585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.4228838585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1478588078 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1124165329 ps |
| CPU time | 10.72 seconds |
| Started | Sep 09 08:02:33 AM UTC 24 |
| Finished | Sep 09 08:02:44 AM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478588078 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1478588078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1081006442 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 14156536922 ps |
| CPU time | 211.57 seconds |
| Started | Sep 09 08:01:51 AM UTC 24 |
| Finished | Sep 09 08:05:26 AM UTC 24 |
| Peak memory | 245016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081006442 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.1081006442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1639180556 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 516604817 ps |
| CPU time | 24.99 seconds |
| Started | Sep 09 08:02:15 AM UTC 24 |
| Finished | Sep 09 08:02:41 AM UTC 24 |
| Peak memory | 228128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639180556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1639180556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3294259776 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2127395087 ps |
| CPU time | 13.04 seconds |
| Started | Sep 09 08:01:36 AM UTC 24 |
| Finished | Sep 09 08:01:50 AM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294259776 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3294259776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1026983618 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 529229919 ps |
| CPU time | 37.98 seconds |
| Started | Sep 09 08:01:35 AM UTC 24 |
| Finished | Sep 09 08:02:14 AM UTC 24 |
| Peak memory | 228832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102698361 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.1026983618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2827732783 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2649126363 ps |
| CPU time | 29.8 seconds |
| Started | Sep 09 08:02:25 AM UTC 24 |
| Finished | Sep 09 08:02:57 AM UTC 24 |
| Peak memory | 230884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2827732783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2827732783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1824020986 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 507191483 ps |
| CPU time | 10.41 seconds |
| Started | Sep 09 07:34:12 AM UTC 24 |
| Finished | Sep 09 07:34:24 AM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824020986 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1824020986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3024924741 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12069634221 ps |
| CPU time | 307.23 seconds |
| Started | Sep 09 07:33:47 AM UTC 24 |
| Finished | Sep 09 07:38:59 AM UTC 24 |
| Peak memory | 261664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024924741 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.3024924741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3211940134 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 8216782232 ps |
| CPU time | 35.64 seconds |
| Started | Sep 09 07:34:05 AM UTC 24 |
| Finished | Sep 09 07:34:42 AM UTC 24 |
| Peak memory | 228700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211940134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3211940134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.251233052 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1050523464 ps |
| CPU time | 13.36 seconds |
| Started | Sep 09 07:33:31 AM UTC 24 |
| Finished | Sep 09 07:33:46 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251233052 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.251233052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3417225810 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 364144218 ps |
| CPU time | 11.44 seconds |
| Started | Sep 09 07:33:18 AM UTC 24 |
| Finished | Sep 09 07:33:31 AM UTC 24 |
| Peak memory | 225468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417225810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3417225810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1220214408 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 6022844382 ps |
| CPU time | 45.67 seconds |
| Started | Sep 09 07:33:25 AM UTC 24 |
| Finished | Sep 09 07:34:13 AM UTC 24 |
| Peak memory | 230744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122021440 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.1220214408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1552855985 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 6460661825 ps |
| CPU time | 129.06 seconds |
| Started | Sep 09 07:34:10 AM UTC 24 |
| Finished | Sep 09 07:36:22 AM UTC 24 |
| Peak memory | 235176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1552855985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1552855985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2850306022 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 174388669 ps |
| CPU time | 9.21 seconds |
| Started | Sep 09 07:34:42 AM UTC 24 |
| Finished | Sep 09 07:34:53 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850306022 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2850306022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3338485245 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 61998439021 ps |
| CPU time | 288.41 seconds |
| Started | Sep 09 07:34:26 AM UTC 24 |
| Finished | Sep 09 07:39:19 AM UTC 24 |
| Peak memory | 259476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338485245 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.3338485245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2565858109 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1838860247 ps |
| CPU time | 25.22 seconds |
| Started | Sep 09 07:34:28 AM UTC 24 |
| Finished | Sep 09 07:34:55 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565858109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2565858109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.44517974 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1512571655 ps |
| CPU time | 13.48 seconds |
| Started | Sep 09 07:34:24 AM UTC 24 |
| Finished | Sep 09 07:34:39 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44517974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.44517974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1230266982 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 530337729 ps |
| CPU time | 13.03 seconds |
| Started | Sep 09 07:34:13 AM UTC 24 |
| Finished | Sep 09 07:34:27 AM UTC 24 |
| Peak memory | 228708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230266982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1230266982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1426970217 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 543561339 ps |
| CPU time | 38.13 seconds |
| Started | Sep 09 07:34:14 AM UTC 24 |
| Finished | Sep 09 07:34:54 AM UTC 24 |
| Peak memory | 228904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142697021 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.1426970217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3068215925 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2066364632 ps |
| CPU time | 112.62 seconds |
| Started | Sep 09 07:34:39 AM UTC 24 |
| Finished | Sep 09 07:36:34 AM UTC 24 |
| Peak memory | 243112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3068215925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3068215925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3525515190 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1501684217 ps |
| CPU time | 9.22 seconds |
| Started | Sep 09 07:35:10 AM UTC 24 |
| Finished | Sep 09 07:35:20 AM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525515190 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3525515190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2204148151 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 152146501550 ps |
| CPU time | 410.06 seconds |
| Started | Sep 09 07:34:56 AM UTC 24 |
| Finished | Sep 09 07:41:52 AM UTC 24 |
| Peak memory | 256396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204148151 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.2204148151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.917402140 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1503219342 ps |
| CPU time | 21.59 seconds |
| Started | Sep 09 07:35:03 AM UTC 24 |
| Finished | Sep 09 07:35:26 AM UTC 24 |
| Peak memory | 228116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917402140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.917402140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2745000968 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 528289820 ps |
| CPU time | 13.73 seconds |
| Started | Sep 09 07:34:55 AM UTC 24 |
| Finished | Sep 09 07:35:09 AM UTC 24 |
| Peak memory | 228444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745000968 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2745000968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.261952966 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 997556086 ps |
| CPU time | 13.6 seconds |
| Started | Sep 09 07:34:47 AM UTC 24 |
| Finished | Sep 09 07:35:02 AM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261952966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.261952966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1831901107 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1442335118 ps |
| CPU time | 25.58 seconds |
| Started | Sep 09 07:34:53 AM UTC 24 |
| Finished | Sep 09 07:35:20 AM UTC 24 |
| Peak memory | 228824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183190110 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.1831901107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1690632283 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1896320622 ps |
| CPU time | 118.17 seconds |
| Started | Sep 09 07:35:03 AM UTC 24 |
| Finished | Sep 09 07:37:03 AM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1690632283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1690632283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3388463343 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 168604034 ps |
| CPU time | 9.24 seconds |
| Started | Sep 09 07:36:08 AM UTC 24 |
| Finished | Sep 09 07:36:19 AM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388463343 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3388463343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4281077164 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 22375492802 ps |
| CPU time | 245.88 seconds |
| Started | Sep 09 07:35:36 AM UTC 24 |
| Finished | Sep 09 07:39:47 AM UTC 24 |
| Peak memory | 259488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281077164 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.4281077164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3895266621 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1030317227 ps |
| CPU time | 25.02 seconds |
| Started | Sep 09 07:35:41 AM UTC 24 |
| Finished | Sep 09 07:36:08 AM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895266621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3895266621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1722160500 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 270716986 ps |
| CPU time | 13.68 seconds |
| Started | Sep 09 07:35:26 AM UTC 24 |
| Finished | Sep 09 07:35:41 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722160500 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1722160500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2418034136 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 260763304 ps |
| CPU time | 13.67 seconds |
| Started | Sep 09 07:35:21 AM UTC 24 |
| Finished | Sep 09 07:35:36 AM UTC 24 |
| Peak memory | 225468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418034136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2418034136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2766436486 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1214641945 ps |
| CPU time | 23.62 seconds |
| Started | Sep 09 07:35:21 AM UTC 24 |
| Finished | Sep 09 07:35:46 AM UTC 24 |
| Peak memory | 228900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276643648 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.2766436486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3499202833 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9319462959 ps |
| CPU time | 244.66 seconds |
| Started | Sep 09 07:35:46 AM UTC 24 |
| Finished | Sep 09 07:39:55 AM UTC 24 |
| Peak memory | 246612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3499202833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3499202833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.484936664 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 174273304 ps |
| CPU time | 9.49 seconds |
| Started | Sep 09 07:37:01 AM UTC 24 |
| Finished | Sep 09 07:37:11 AM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484936664 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.484936664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1113290587 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 125856273194 ps |
| CPU time | 437.04 seconds |
| Started | Sep 09 07:36:34 AM UTC 24 |
| Finished | Sep 09 07:43:57 AM UTC 24 |
| Peak memory | 259488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113290587 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.1113290587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3869864685 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 342692683 ps |
| CPU time | 22.93 seconds |
| Started | Sep 09 07:36:36 AM UTC 24 |
| Finished | Sep 09 07:37:00 AM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869864685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3869864685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3513755881 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 704407528 ps |
| CPU time | 11.26 seconds |
| Started | Sep 09 07:36:24 AM UTC 24 |
| Finished | Sep 09 07:36:37 AM UTC 24 |
| Peak memory | 228444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513755881 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3513755881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2904756939 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 903714520 ps |
| CPU time | 11.96 seconds |
| Started | Sep 09 07:36:19 AM UTC 24 |
| Finished | Sep 09 07:36:32 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904756939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2904756939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.742092596 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3120350116 ps |
| CPU time | 53.94 seconds |
| Started | Sep 09 07:36:22 AM UTC 24 |
| Finished | Sep 09 07:37:18 AM UTC 24 |
| Peak memory | 228700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742092596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.742092596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1316747291 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 12841754354 ps |
| CPU time | 180.72 seconds |
| Started | Sep 09 07:36:38 AM UTC 24 |
| Finished | Sep 09 07:39:42 AM UTC 24 |
| Peak memory | 246356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1316747291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1316747291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest |
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