| Name |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2548653127 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1011846601 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1309101536 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2232826860 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3954521992 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1803227587 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.880316061 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.526799025 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.907998844 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.98089635 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1437226222 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2075546202 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1211947932 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3217659881 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3237061950 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3594198150 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3725468360 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.611393569 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1227333996 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2405532049 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2702219054 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1407501062 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2829964284 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1928090491 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3766397849 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.740492765 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3950138576 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1627601140 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.818784077 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3574912874 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.653486587 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1467321511 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.719595342 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3174351073 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.268518930 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1889122502 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3896382918 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3676738262 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3933885925 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.353051066 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3834631992 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1615455603 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2325908691 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.220079393 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1526114211 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3215222922 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2994868421 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3996550077 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4095885542 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3137841431 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.108173885 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2580734161 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1916178349 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.303075771 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1381300346 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.74109093 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1241610861 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1183448126 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.958621837 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4193241681 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.965111741 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2711210123 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.430239601 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.376618513 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1048755122 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3146539452 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1184650574 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3669659617 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1386763220 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2374692763 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2706282590 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2289131950 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4251851005 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2753333675 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3875090141 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1583042240 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2626818161 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3890329066 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3435276967 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1680441361 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2073811942 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1092852129 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2949583610 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3378639820 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.692053772 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3027057522 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2328989105 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2034775099 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1725241959 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2121609514 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1782939811 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3384033639 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1925446775 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2860648343 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2414955867 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4116379530 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1059858388 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1151268311 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4282687831 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1520045688 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3917186295 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2102591087 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2517215246 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2372130825 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2202861691 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.552059330 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.731554879 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1671705665 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3884985744 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3486702793 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1303249036 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2208068389 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1094122398 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3125532506 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.811297319 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3356913325 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1852020515 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2538902114 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4233425951 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2209422667 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3266868480 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2806558355 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.930620988 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4134764414 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.43657901 |
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| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.2524424847 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4228838585 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1478588078 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1081006442 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1639180556 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3294259776 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1026983618 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2827732783 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1824020986 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3024924741 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3211940134 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.251233052 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3417225810 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1220214408 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1552855985 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2850306022 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3338485245 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2565858109 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.44517974 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1230266982 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1426970217 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3068215925 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3525515190 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2204148151 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.917402140 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2745000968 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.261952966 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1831901107 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1690632283 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3388463343 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4281077164 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3895266621 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1722160500 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2418034136 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2766436486 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3499202833 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.484936664 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1113290587 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3869864685 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3513755881 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2904756939 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.742092596 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1316747291 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1035254793 |
|
|
Sep 09 07:29:51 AM UTC 24 |
Sep 09 07:30:06 AM UTC 24 |
1060909273 ps |
| T2 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2298871767 |
|
|
Sep 09 07:29:53 AM UTC 24 |
Sep 09 07:30:06 AM UTC 24 |
262046304 ps |
| T3 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.459326949 |
|
|
Sep 09 07:29:51 AM UTC 24 |
Sep 09 07:30:06 AM UTC 24 |
2838963350 ps |
| T4 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3556112919 |
|
|
Sep 09 07:29:53 AM UTC 24 |
Sep 09 07:30:09 AM UTC 24 |
3634695002 ps |
| T5 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.4183002057 |
|
|
Sep 09 07:29:51 AM UTC 24 |
Sep 09 07:30:19 AM UTC 24 |
1709078444 ps |
| T6 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3614672917 |
|
|
Sep 09 07:29:51 AM UTC 24 |
Sep 09 07:30:20 AM UTC 24 |
569077307 ps |
| T7 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.4099611893 |
|
|
Sep 09 07:30:07 AM UTC 24 |
Sep 09 07:30:21 AM UTC 24 |
695660785 ps |
| T8 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2586940814 |
|
|
Sep 09 07:30:21 AM UTC 24 |
Sep 09 07:30:32 AM UTC 24 |
661527890 ps |
| T9 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3127527395 |
|
|
Sep 09 07:30:07 AM UTC 24 |
Sep 09 07:30:34 AM UTC 24 |
1457442072 ps |
| T10 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3540785009 |
|
|
Sep 09 07:30:21 AM UTC 24 |
Sep 09 07:30:34 AM UTC 24 |
721742768 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1220005951 |
|
|
Sep 09 07:30:34 AM UTC 24 |
Sep 09 07:30:48 AM UTC 24 |
740012290 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.983938989 |
|
|
Sep 09 07:30:32 AM UTC 24 |
Sep 09 07:30:49 AM UTC 24 |
358085875 ps |
| T11 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.535358440 |
|
|
Sep 09 07:29:51 AM UTC 24 |
Sep 09 07:30:53 AM UTC 24 |
13914067170 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1929100508 |
|
|
Sep 09 07:30:06 AM UTC 24 |
Sep 09 07:31:03 AM UTC 24 |
1042309386 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1445888643 |
|
|
Sep 09 07:31:03 AM UTC 24 |
Sep 09 07:31:14 AM UTC 24 |
325973239 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3642281547 |
|
|
Sep 09 07:30:48 AM UTC 24 |
Sep 09 07:31:25 AM UTC 24 |
1965810665 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.4072315990 |
|
|
Sep 09 07:31:15 AM UTC 24 |
Sep 09 07:31:30 AM UTC 24 |
270943684 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.820299501 |
|
|
Sep 09 07:31:30 AM UTC 24 |
Sep 09 07:31:45 AM UTC 24 |
920056724 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2442094993 |
|
|
Sep 09 07:30:49 AM UTC 24 |
Sep 09 07:31:46 AM UTC 24 |
7604086175 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2509366666 |
|
|
Sep 09 07:29:51 AM UTC 24 |
Sep 09 07:31:51 AM UTC 24 |
2843829038 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3040539748 |
|
|
Sep 09 07:31:25 AM UTC 24 |
Sep 09 07:31:55 AM UTC 24 |
381656903 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.249817332 |
|
|
Sep 09 07:31:46 AM UTC 24 |
Sep 09 07:32:13 AM UTC 24 |
1031963540 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3419801843 |
|
|
Sep 09 07:30:10 AM UTC 24 |
Sep 09 07:32:14 AM UTC 24 |
9269049250 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2997130746 |
|
|
Sep 09 07:32:14 AM UTC 24 |
Sep 09 07:32:24 AM UTC 24 |
339063617 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1754490245 |
|
|
Sep 09 07:32:15 AM UTC 24 |
Sep 09 07:32:30 AM UTC 24 |
515673011 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2094205992 |
|
|
Sep 09 07:30:20 AM UTC 24 |
Sep 09 07:32:40 AM UTC 24 |
322449551 ps |
| T31 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1818765009 |
|
|
Sep 09 07:32:31 AM UTC 24 |
Sep 09 07:32:46 AM UTC 24 |
1065896800 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.72572224 |
|
|
Sep 09 07:32:25 AM UTC 24 |
Sep 09 07:32:54 AM UTC 24 |
2165124191 ps |
| T33 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.4276909507 |
|
|
Sep 09 07:32:47 AM UTC 24 |
Sep 09 07:33:13 AM UTC 24 |
1053632394 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1434391426 |
|
|
Sep 09 07:30:53 AM UTC 24 |
Sep 09 07:33:17 AM UTC 24 |
367345192 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1073317514 |
|
|
Sep 09 07:33:14 AM UTC 24 |
Sep 09 07:33:24 AM UTC 24 |
174422279 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3417225810 |
|
|
Sep 09 07:33:18 AM UTC 24 |
Sep 09 07:33:31 AM UTC 24 |
364144218 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.251233052 |
|
|
Sep 09 07:33:31 AM UTC 24 |
Sep 09 07:33:46 AM UTC 24 |
1050523464 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2067780581 |
|
|
Sep 09 07:30:07 AM UTC 24 |
Sep 09 07:34:04 AM UTC 24 |
22123586960 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3019667917 |
|
|
Sep 09 07:31:53 AM UTC 24 |
Sep 09 07:34:08 AM UTC 24 |
9519618894 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.4277441185 |
|
|
Sep 09 07:31:56 AM UTC 24 |
Sep 09 07:34:11 AM UTC 24 |
2675829595 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1220214408 |
|
|
Sep 09 07:33:25 AM UTC 24 |
Sep 09 07:34:13 AM UTC 24 |
6022844382 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1824020986 |
|
|
Sep 09 07:34:12 AM UTC 24 |
Sep 09 07:34:24 AM UTC 24 |
507191483 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1378015929 |
|
|
Sep 09 07:29:51 AM UTC 24 |
Sep 09 07:34:25 AM UTC 24 |
1020109277 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1230266982 |
|
|
Sep 09 07:34:13 AM UTC 24 |
Sep 09 07:34:27 AM UTC 24 |
530337729 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.44517974 |
|
|
Sep 09 07:34:24 AM UTC 24 |
Sep 09 07:34:39 AM UTC 24 |
1512571655 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3211940134 |
|
|
Sep 09 07:34:05 AM UTC 24 |
Sep 09 07:34:42 AM UTC 24 |
8216782232 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2660861069 |
|
|
Sep 09 07:32:55 AM UTC 24 |
Sep 09 07:34:46 AM UTC 24 |
2555155092 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2850306022 |
|
|
Sep 09 07:34:42 AM UTC 24 |
Sep 09 07:34:53 AM UTC 24 |
174388669 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1426970217 |
|
|
Sep 09 07:34:14 AM UTC 24 |
Sep 09 07:34:54 AM UTC 24 |
543561339 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2565858109 |
|
|
Sep 09 07:34:28 AM UTC 24 |
Sep 09 07:34:55 AM UTC 24 |
1838860247 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.261952966 |
|
|
Sep 09 07:34:47 AM UTC 24 |
Sep 09 07:35:02 AM UTC 24 |
997556086 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3048765616 |
|
|
Sep 09 07:32:41 AM UTC 24 |
Sep 09 07:35:02 AM UTC 24 |
8603666786 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2745000968 |
|
|
Sep 09 07:34:55 AM UTC 24 |
Sep 09 07:35:09 AM UTC 24 |
528289820 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3525515190 |
|
|
Sep 09 07:35:10 AM UTC 24 |
Sep 09 07:35:20 AM UTC 24 |
1501684217 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1831901107 |
|
|
Sep 09 07:34:53 AM UTC 24 |
Sep 09 07:35:20 AM UTC 24 |
1442335118 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.917402140 |
|
|
Sep 09 07:35:03 AM UTC 24 |
Sep 09 07:35:26 AM UTC 24 |
1503219342 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2418034136 |
|
|
Sep 09 07:35:21 AM UTC 24 |
Sep 09 07:35:36 AM UTC 24 |
260763304 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1722160500 |
|
|
Sep 09 07:35:26 AM UTC 24 |
Sep 09 07:35:41 AM UTC 24 |
270716986 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2766436486 |
|
|
Sep 09 07:35:21 AM UTC 24 |
Sep 09 07:35:46 AM UTC 24 |
1214641945 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3895266621 |
|
|
Sep 09 07:35:41 AM UTC 24 |
Sep 09 07:36:08 AM UTC 24 |
1030317227 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3388463343 |
|
|
Sep 09 07:36:08 AM UTC 24 |
Sep 09 07:36:19 AM UTC 24 |
168604034 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1552855985 |
|
|
Sep 09 07:34:10 AM UTC 24 |
Sep 09 07:36:22 AM UTC 24 |
6460661825 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.835566261 |
|
|
Sep 09 07:30:35 AM UTC 24 |
Sep 09 07:36:24 AM UTC 24 |
5983183498 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2904756939 |
|
|
Sep 09 07:36:19 AM UTC 24 |
Sep 09 07:36:32 AM UTC 24 |
903714520 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3068215925 |
|
|
Sep 09 07:34:39 AM UTC 24 |
Sep 09 07:36:34 AM UTC 24 |
2066364632 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3513755881 |
|
|
Sep 09 07:36:24 AM UTC 24 |
Sep 09 07:36:37 AM UTC 24 |
704407528 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3869864685 |
|
|
Sep 09 07:36:36 AM UTC 24 |
Sep 09 07:37:00 AM UTC 24 |
342692683 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1690632283 |
|
|
Sep 09 07:35:03 AM UTC 24 |
Sep 09 07:37:03 AM UTC 24 |
1896320622 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.484936664 |
|
|
Sep 09 07:37:01 AM UTC 24 |
Sep 09 07:37:11 AM UTC 24 |
174273304 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.742092596 |
|
|
Sep 09 07:36:22 AM UTC 24 |
Sep 09 07:37:18 AM UTC 24 |
3120350116 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1016854330 |
|
|
Sep 09 07:37:12 AM UTC 24 |
Sep 09 07:37:26 AM UTC 24 |
525672848 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2219361197 |
|
|
Sep 09 07:33:13 AM UTC 24 |
Sep 09 07:37:41 AM UTC 24 |
590956378 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2619585756 |
|
|
Sep 09 07:37:04 AM UTC 24 |
Sep 09 07:37:43 AM UTC 24 |
8041961189 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3363651683 |
|
|
Sep 09 07:37:27 AM UTC 24 |
Sep 09 07:37:53 AM UTC 24 |
517884908 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.60773275 |
|
|
Sep 09 07:37:44 AM UTC 24 |
Sep 09 07:37:54 AM UTC 24 |
689670423 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.432491530 |
|
|
Sep 09 07:37:55 AM UTC 24 |
Sep 09 07:38:10 AM UTC 24 |
1288371053 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3382354434 |
|
|
Sep 09 07:37:54 AM UTC 24 |
Sep 09 07:38:40 AM UTC 24 |
8617908061 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3024924741 |
|
|
Sep 09 07:33:47 AM UTC 24 |
Sep 09 07:38:59 AM UTC 24 |
12069634221 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1067624957 |
|
|
Sep 09 07:38:41 AM UTC 24 |
Sep 09 07:39:08 AM UTC 24 |
1982290501 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.760374415 |
|
|
Sep 09 07:39:09 AM UTC 24 |
Sep 09 07:39:19 AM UTC 24 |
175059119 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3338485245 |
|
|
Sep 09 07:34:26 AM UTC 24 |
Sep 09 07:39:19 AM UTC 24 |
61998439021 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1484240964 |
|
|
Sep 09 07:39:20 AM UTC 24 |
Sep 09 07:39:33 AM UTC 24 |
694450977 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2532523981 |
|
|
Sep 09 07:31:45 AM UTC 24 |
Sep 09 07:39:33 AM UTC 24 |
82653443414 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1316747291 |
|
|
Sep 09 07:36:38 AM UTC 24 |
Sep 09 07:39:42 AM UTC 24 |
12841754354 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4281077164 |
|
|
Sep 09 07:35:36 AM UTC 24 |
Sep 09 07:39:47 AM UTC 24 |
22375492802 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3499202833 |
|
|
Sep 09 07:35:46 AM UTC 24 |
Sep 09 07:39:55 AM UTC 24 |
9319462959 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.116211281 |
|
|
Sep 09 07:39:47 AM UTC 24 |
Sep 09 07:39:58 AM UTC 24 |
169318651 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1544702418 |
|
|
Sep 09 07:39:00 AM UTC 24 |
Sep 09 07:40:00 AM UTC 24 |
15902352096 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3618148872 |
|
|
Sep 09 07:39:34 AM UTC 24 |
Sep 09 07:40:00 AM UTC 24 |
496997171 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3603920521 |
|
|
Sep 09 07:39:20 AM UTC 24 |
Sep 09 07:40:04 AM UTC 24 |
569566507 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2180489325 |
|
|
Sep 09 07:37:42 AM UTC 24 |
Sep 09 07:40:05 AM UTC 24 |
2501280992 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1549553696 |
|
|
Sep 09 07:39:58 AM UTC 24 |
Sep 09 07:40:13 AM UTC 24 |
272646608 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3129530154 |
|
|
Sep 09 07:40:06 AM UTC 24 |
Sep 09 07:40:16 AM UTC 24 |
339338548 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.771763746 |
|
|
Sep 09 07:40:01 AM UTC 24 |
Sep 09 07:40:27 AM UTC 24 |
3799501223 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1566107361 |
|
|
Sep 09 07:39:56 AM UTC 24 |
Sep 09 07:40:28 AM UTC 24 |
2100919461 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.636103136 |
|
|
Sep 09 07:40:17 AM UTC 24 |
Sep 09 07:40:30 AM UTC 24 |
699007356 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.144451531 |
|
|
Sep 09 07:39:43 AM UTC 24 |
Sep 09 07:40:39 AM UTC 24 |
1295463729 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3388466591 |
|
|
Sep 09 07:40:14 AM UTC 24 |
Sep 09 07:40:50 AM UTC 24 |
2213629454 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.4228842235 |
|
|
Sep 09 07:40:39 AM UTC 24 |
Sep 09 07:40:51 AM UTC 24 |
259936253 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2898314391 |
|
|
Sep 09 07:40:29 AM UTC 24 |
Sep 09 07:40:52 AM UTC 24 |
333549058 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3073716198 |
|
|
Sep 09 07:40:06 AM UTC 24 |
Sep 09 07:41:03 AM UTC 24 |
2323494756 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1993391152 |
|
|
Sep 09 07:40:51 AM UTC 24 |
Sep 09 07:41:04 AM UTC 24 |
355588752 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3189987878 |
|
|
Sep 09 07:41:04 AM UTC 24 |
Sep 09 07:41:26 AM UTC 24 |
827908581 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3870934485 |
|
|
Sep 09 07:38:10 AM UTC 24 |
Sep 09 07:41:34 AM UTC 24 |
5943845396 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.1989013775 |
|
|
Sep 09 07:41:27 AM UTC 24 |
Sep 09 07:41:37 AM UTC 24 |
660233607 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3607682718 |
|
|
Sep 09 07:40:50 AM UTC 24 |
Sep 09 07:41:38 AM UTC 24 |
3241455168 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1376847036 |
|
|
Sep 09 07:41:38 AM UTC 24 |
Sep 09 07:41:52 AM UTC 24 |
262232974 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2204148151 |
|
|
Sep 09 07:34:56 AM UTC 24 |
Sep 09 07:41:52 AM UTC 24 |
152146501550 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3829989473 |
|
|
Sep 09 07:41:34 AM UTC 24 |
Sep 09 07:41:59 AM UTC 24 |
1621413962 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3479836175 |
|
|
Sep 09 07:42:00 AM UTC 24 |
Sep 09 07:42:10 AM UTC 24 |
691883010 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2235036617 |
|
|
Sep 09 07:40:31 AM UTC 24 |
Sep 09 07:42:15 AM UTC 24 |
2564624621 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3902680109 |
|
|
Sep 09 07:41:55 AM UTC 24 |
Sep 09 07:42:21 AM UTC 24 |
3781879003 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3214539798 |
|
|
Sep 09 07:42:17 AM UTC 24 |
Sep 09 07:42:32 AM UTC 24 |
274228270 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.358753722 |
|
|
Sep 09 07:37:19 AM UTC 24 |
Sep 09 07:42:35 AM UTC 24 |
5011211833 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1589369386 |
|
|
Sep 09 07:39:34 AM UTC 24 |
Sep 09 07:42:36 AM UTC 24 |
21493573266 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1911205051 |
|
|
Sep 09 07:42:12 AM UTC 24 |
Sep 09 07:42:38 AM UTC 24 |
2172068037 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3964005039 |
|
|
Sep 09 07:42:21 AM UTC 24 |
Sep 09 07:42:44 AM UTC 24 |
1382835264 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.146681378 |
|
|
Sep 09 07:42:35 AM UTC 24 |
Sep 09 07:42:45 AM UTC 24 |
174286796 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1165394896 |
|
|
Sep 09 07:42:38 AM UTC 24 |
Sep 09 07:42:53 AM UTC 24 |
272592601 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3035068187 |
|
|
Sep 09 07:41:05 AM UTC 24 |
Sep 09 07:42:57 AM UTC 24 |
8525271533 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1476394653 |
|
|
Sep 09 07:40:28 AM UTC 24 |
Sep 09 07:43:02 AM UTC 24 |
1644484055 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1590815315 |
|
|
Sep 09 07:42:58 AM UTC 24 |
Sep 09 07:43:10 AM UTC 24 |
340626697 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2987312287 |
|
|
Sep 09 07:42:47 AM UTC 24 |
Sep 09 07:43:10 AM UTC 24 |
333191029 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.4147677794 |
|
|
Sep 09 07:43:10 AM UTC 24 |
Sep 09 07:43:24 AM UTC 24 |
1068486110 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2147760250 |
|
|
Sep 09 07:41:55 AM UTC 24 |
Sep 09 07:43:27 AM UTC 24 |
1693701953 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2788281731 |
|
|
Sep 09 07:42:37 AM UTC 24 |
Sep 09 07:43:30 AM UTC 24 |
2091397742 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4087764865 |
|
|
Sep 09 07:42:33 AM UTC 24 |
Sep 09 07:43:33 AM UTC 24 |
2014648662 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3329704543 |
|
|
Sep 09 07:43:31 AM UTC 24 |
Sep 09 07:43:42 AM UTC 24 |
636146381 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1203706897 |
|
|
Sep 09 07:43:03 AM UTC 24 |
Sep 09 07:43:42 AM UTC 24 |
538431922 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2182040439 |
|
|
Sep 09 07:43:25 AM UTC 24 |
Sep 09 07:43:48 AM UTC 24 |
340168438 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1427163289 |
|
|
Sep 09 07:43:43 AM UTC 24 |
Sep 09 07:43:57 AM UTC 24 |
270902865 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1113290587 |
|
|
Sep 09 07:36:34 AM UTC 24 |
Sep 09 07:43:57 AM UTC 24 |
125856273194 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.4049895555 |
|
|
Sep 09 07:43:58 AM UTC 24 |
Sep 09 07:44:08 AM UTC 24 |
168236041 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.649147633 |
|
|
Sep 09 07:43:33 AM UTC 24 |
Sep 09 07:44:10 AM UTC 24 |
1117289693 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3218225315 |
|
|
Sep 09 07:43:49 AM UTC 24 |
Sep 09 07:44:15 AM UTC 24 |
498328528 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3150107778 |
|
|
Sep 09 07:44:11 AM UTC 24 |
Sep 09 07:44:25 AM UTC 24 |
1486053878 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4281774680 |
|
|
Sep 09 07:40:01 AM UTC 24 |
Sep 09 07:44:33 AM UTC 24 |
25270156389 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.4025749522 |
|
|
Sep 09 07:44:26 AM UTC 24 |
Sep 09 07:44:49 AM UTC 24 |
332454955 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.319675595 |
|
|
Sep 09 07:44:09 AM UTC 24 |
Sep 09 07:44:53 AM UTC 24 |
2786227333 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2461965011 |
|
|
Sep 09 07:41:39 AM UTC 24 |
Sep 09 07:44:58 AM UTC 24 |
2528753849 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1170484284 |
|
|
Sep 09 07:44:51 AM UTC 24 |
Sep 09 07:45:02 AM UTC 24 |
257540674 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1512818225 |
|
|
Sep 09 07:43:58 AM UTC 24 |
Sep 09 07:45:07 AM UTC 24 |
8538049444 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1729308849 |
|
|
Sep 09 07:44:59 AM UTC 24 |
Sep 09 07:45:13 AM UTC 24 |
1066919051 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3876450996 |
|
|
Sep 09 07:44:54 AM UTC 24 |
Sep 09 07:45:17 AM UTC 24 |
716616741 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.4064706028 |
|
|
Sep 09 07:43:28 AM UTC 24 |
Sep 09 07:45:17 AM UTC 24 |
2117929777 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2177293460 |
|
|
Sep 09 07:40:53 AM UTC 24 |
Sep 09 07:45:29 AM UTC 24 |
18763155494 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3494496844 |
|
|
Sep 09 07:43:44 AM UTC 24 |
Sep 09 07:46:37 AM UTC 24 |
2566597752 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1979447694 |
|
|
Sep 09 07:45:17 AM UTC 24 |
Sep 09 07:45:29 AM UTC 24 |
498325369 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.954223919 |
|
|
Sep 09 07:45:08 AM UTC 24 |
Sep 09 07:45:31 AM UTC 24 |
661792401 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2272242183 |
|
|
Sep 09 07:45:18 AM UTC 24 |
Sep 09 07:45:36 AM UTC 24 |
365067569 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2928203757 |
|
|
Sep 09 07:45:28 AM UTC 24 |
Sep 09 07:45:42 AM UTC 24 |
262370602 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.1216929511 |
|
|
Sep 09 07:45:37 AM UTC 24 |
Sep 09 07:45:49 AM UTC 24 |
260609440 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.553751753 |
|
|
Sep 09 07:42:54 AM UTC 24 |
Sep 09 07:45:49 AM UTC 24 |
5016994509 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3026714985 |
|
|
Sep 09 07:45:30 AM UTC 24 |
Sep 09 07:45:53 AM UTC 24 |
1323829110 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.575478383 |
|
|
Sep 09 07:45:50 AM UTC 24 |
Sep 09 07:46:05 AM UTC 24 |
1075028015 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.948426162 |
|
|
Sep 09 07:45:42 AM UTC 24 |
Sep 09 07:46:15 AM UTC 24 |
548853636 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2353674291 |
|
|
Sep 09 07:45:54 AM UTC 24 |
Sep 09 07:46:16 AM UTC 24 |
1376786510 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3215438383 |
|
|
Sep 09 07:46:16 AM UTC 24 |
Sep 09 07:46:28 AM UTC 24 |
1031249960 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3508617140 |
|
|
Sep 09 07:45:14 AM UTC 24 |
Sep 09 07:46:38 AM UTC 24 |
5263467292 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2270785395 |
|
|
Sep 09 07:46:28 AM UTC 24 |
Sep 09 07:46:41 AM UTC 24 |
1009233389 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1675074339 |
|
|
Sep 09 07:46:17 AM UTC 24 |
Sep 09 07:46:48 AM UTC 24 |
367162947 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.222596560 |
|
|
Sep 09 07:46:39 AM UTC 24 |
Sep 09 07:47:03 AM UTC 24 |
349995208 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3271017737 |
|
|
Sep 09 07:46:50 AM UTC 24 |
Sep 09 07:47:07 AM UTC 24 |
1046986478 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.3109211889 |
|
|
Sep 09 07:47:08 AM UTC 24 |
Sep 09 07:47:23 AM UTC 24 |
269939412 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.707702309 |
|
|
Sep 09 07:46:41 AM UTC 24 |
Sep 09 07:47:30 AM UTC 24 |
2826991686 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2393177954 |
|
|
Sep 09 07:47:04 AM UTC 24 |
Sep 09 07:47:30 AM UTC 24 |
818960175 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.401458309 |
|
|
Sep 09 07:45:32 AM UTC 24 |
Sep 09 07:47:33 AM UTC 24 |
11876868919 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3728842907 |
|
|
Sep 09 07:47:33 AM UTC 24 |
Sep 09 07:47:45 AM UTC 24 |
517644549 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1018739944 |
|
|
Sep 09 07:45:03 AM UTC 24 |
Sep 09 07:47:51 AM UTC 24 |
4074921154 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1472322008 |
|
|
Sep 09 07:42:46 AM UTC 24 |
Sep 09 07:47:57 AM UTC 24 |
9779488063 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.999441390 |
|
|
Sep 09 07:47:31 AM UTC 24 |
Sep 09 07:47:58 AM UTC 24 |
505894782 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2103704448 |
|
|
Sep 09 07:47:46 AM UTC 24 |
Sep 09 07:48:02 AM UTC 24 |
558024529 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.934809492 |
|
|
Sep 09 07:47:53 AM UTC 24 |
Sep 09 07:48:07 AM UTC 24 |
1014290872 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.214101082 |
|
|
Sep 09 07:48:08 AM UTC 24 |
Sep 09 07:48:20 AM UTC 24 |
885387254 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1742654786 |
|
|
Sep 09 07:47:59 AM UTC 24 |
Sep 09 07:48:21 AM UTC 24 |
1375791630 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4286502492 |
|
|
Sep 09 07:42:20 AM UTC 24 |
Sep 09 07:48:34 AM UTC 24 |
5947436706 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.928955598 |
|
|
Sep 09 07:48:22 AM UTC 24 |
Sep 09 07:48:35 AM UTC 24 |
695097266 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3894357041 |
|
|
Sep 09 07:48:20 AM UTC 24 |
Sep 09 07:48:38 AM UTC 24 |
1534232622 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.576255737 |
|
|
Sep 09 07:48:37 AM UTC 24 |
Sep 09 07:49:04 AM UTC 24 |
5515640863 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2759396769 |
|
|
Sep 09 07:46:06 AM UTC 24 |
Sep 09 07:49:07 AM UTC 24 |
9022951969 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1749947012 |
|
|
Sep 09 07:44:15 AM UTC 24 |
Sep 09 07:49:11 AM UTC 24 |
5083786322 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2032705783 |
|
|
Sep 09 07:43:10 AM UTC 24 |
Sep 09 07:49:17 AM UTC 24 |
6541689912 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.204097702 |
|
|
Sep 09 07:49:05 AM UTC 24 |
Sep 09 07:49:21 AM UTC 24 |
3774225110 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.963662806 |
|
|
Sep 09 07:53:52 AM UTC 24 |
Sep 09 07:54:28 AM UTC 24 |
8242344240 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2327424231 |
|
|
Sep 09 07:49:11 AM UTC 24 |
Sep 09 07:49:24 AM UTC 24 |
922015692 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.820477166 |
|
|
Sep 09 07:49:08 AM UTC 24 |
Sep 09 07:49:38 AM UTC 24 |
561572185 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2823631503 |
|
|
Sep 09 07:45:30 AM UTC 24 |
Sep 09 07:49:42 AM UTC 24 |
10231845893 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3593683287 |
|
|
Sep 09 07:49:22 AM UTC 24 |
Sep 09 07:49:45 AM UTC 24 |
665292725 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2342287956 |
|
|
Sep 09 07:49:39 AM UTC 24 |
Sep 09 07:49:49 AM UTC 24 |
292836268 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1263427080 |
|
|
Sep 09 07:49:46 AM UTC 24 |
Sep 09 07:49:59 AM UTC 24 |
239191866 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.285685618 |
|
|
Sep 09 07:49:25 AM UTC 24 |
Sep 09 07:50:10 AM UTC 24 |
2979105997 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3513372959 |
|
|
Sep 09 07:45:50 AM UTC 24 |
Sep 09 07:50:19 AM UTC 24 |
6920563307 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2212876646 |
|
|
Sep 09 07:48:03 AM UTC 24 |
Sep 09 07:50:22 AM UTC 24 |
9762046015 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.1440027520 |
|
|
Sep 09 07:49:59 AM UTC 24 |
Sep 09 07:50:26 AM UTC 24 |
516165734 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1926362531 |
|
|
Sep 09 07:46:37 AM UTC 24 |
Sep 09 07:50:31 AM UTC 24 |
14467629104 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2067059983 |
|
|
Sep 09 07:49:43 AM UTC 24 |
Sep 09 07:50:32 AM UTC 24 |
15514281790 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.3469766845 |
|
|
Sep 09 07:50:21 AM UTC 24 |
Sep 09 07:50:32 AM UTC 24 |
496870838 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.778280661 |
|
|
Sep 09 07:47:58 AM UTC 24 |
Sep 09 07:50:36 AM UTC 24 |
27899478107 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2396464861 |
|
|
Sep 09 07:50:27 AM UTC 24 |
Sep 09 07:50:39 AM UTC 24 |
724811649 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3586884273 |
|
|
Sep 09 07:50:37 AM UTC 24 |
Sep 09 07:50:48 AM UTC 24 |
830585880 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1915898403 |
|
|
Sep 09 07:50:23 AM UTC 24 |
Sep 09 07:50:58 AM UTC 24 |
2227186404 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.329668519 |
|
|
Sep 09 07:47:31 AM UTC 24 |
Sep 09 07:51:00 AM UTC 24 |
5562170241 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.67592601 |
|
|
Sep 09 07:50:49 AM UTC 24 |
Sep 09 07:51:03 AM UTC 24 |
2314123184 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3539897622 |
|
|
Sep 09 07:50:40 AM UTC 24 |
Sep 09 07:51:05 AM UTC 24 |
1580653890 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2689834061 |
|
|
Sep 09 07:50:33 AM UTC 24 |
Sep 09 07:51:09 AM UTC 24 |
8203636915 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.941267626 |
|
|
Sep 09 07:51:06 AM UTC 24 |
Sep 09 07:51:22 AM UTC 24 |
4474534881 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.609070618 |
|
|
Sep 09 07:51:09 AM UTC 24 |
Sep 09 07:51:28 AM UTC 24 |
680732541 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.712452953 |
|
|
Sep 09 07:51:01 AM UTC 24 |
Sep 09 07:51:36 AM UTC 24 |
2118235986 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2607381681 |
|
|
Sep 09 07:51:23 AM UTC 24 |
Sep 09 07:51:36 AM UTC 24 |
725343371 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.1406090712 |
|
|
Sep 09 07:51:37 AM UTC 24 |
Sep 09 07:52:03 AM UTC 24 |
2065126178 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2689274476 |
|
|
Sep 09 07:48:39 AM UTC 24 |
Sep 09 07:52:08 AM UTC 24 |
18583624528 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1174736240 |
|
|
Sep 09 07:52:04 AM UTC 24 |
Sep 09 07:52:14 AM UTC 24 |
174955934 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.627504498 |
|
|
Sep 09 07:52:15 AM UTC 24 |
Sep 09 07:52:28 AM UTC 24 |
182786057 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1692253372 |
|
|
Sep 09 07:48:34 AM UTC 24 |
Sep 09 07:52:47 AM UTC 24 |
19418001505 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1613839962 |
|
|
Sep 09 07:52:09 AM UTC 24 |
Sep 09 07:52:50 AM UTC 24 |
4743635970 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2072031288 |
|
|
Sep 09 07:51:37 AM UTC 24 |
Sep 09 07:52:57 AM UTC 24 |
1842603167 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.671214076 |
|
|
Sep 09 07:52:58 AM UTC 24 |
Sep 09 07:53:10 AM UTC 24 |
252124936 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.392888409 |
|
|
Sep 09 07:52:48 AM UTC 24 |
Sep 09 07:53:14 AM UTC 24 |
620871227 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3878463676 |
|
|
Sep 09 07:50:33 AM UTC 24 |
Sep 09 07:53:23 AM UTC 24 |
51347568362 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.4036486747 |
|
|
Sep 09 07:53:14 AM UTC 24 |
Sep 09 07:53:28 AM UTC 24 |
180244607 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3332716625 |
|
|
Sep 09 07:47:23 AM UTC 24 |
Sep 09 07:53:30 AM UTC 24 |
25096001442 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.250633293 |
|
|
Sep 09 07:51:03 AM UTC 24 |
Sep 09 07:53:39 AM UTC 24 |
10845805165 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.16997658 |
|
|
Sep 09 07:50:10 AM UTC 24 |
Sep 09 07:53:42 AM UTC 24 |
11065606754 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1015951108 |
|
|
Sep 09 07:53:10 AM UTC 24 |
Sep 09 07:53:42 AM UTC 24 |
352437805 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.182383233 |
|
|
Sep 09 07:53:29 AM UTC 24 |
Sep 09 07:53:51 AM UTC 24 |
1500573659 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.628686518 |
|
|
Sep 09 07:53:40 AM UTC 24 |
Sep 09 07:53:52 AM UTC 24 |
4933957061 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2733649870 |
|
|
Sep 09 07:53:43 AM UTC 24 |
Sep 09 07:53:57 AM UTC 24 |
738173645 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3554265591 |
|
|
Sep 09 07:50:32 AM UTC 24 |
Sep 09 07:54:00 AM UTC 24 |
10860293394 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.806460204 |
|
|
Sep 09 07:49:50 AM UTC 24 |
Sep 09 07:54:08 AM UTC 24 |
20583471887 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2949759956 |
|
|
Sep 09 07:53:43 AM UTC 24 |
Sep 09 07:54:11 AM UTC 24 |
311789267 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2296282931 |
|
|
Sep 09 07:54:01 AM UTC 24 |
Sep 09 07:54:17 AM UTC 24 |
1960496520 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1836996828 |
|
|
Sep 09 07:53:31 AM UTC 24 |
Sep 09 07:54:18 AM UTC 24 |
3554109497 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3312143970 |
|
|
Sep 09 07:54:12 AM UTC 24 |
Sep 09 07:54:25 AM UTC 24 |
686037240 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3630823536 |
|
|
Sep 09 07:54:27 AM UTC 24 |
Sep 09 07:54:37 AM UTC 24 |
169053024 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1833383317 |
|
|
Sep 09 07:54:18 AM UTC 24 |
Sep 09 07:54:41 AM UTC 24 |
346959937 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.826213347 |
|
|
Sep 09 07:52:29 AM UTC 24 |
Sep 09 07:54:49 AM UTC 24 |
2244410915 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.576473228 |
|
|
Sep 09 07:54:29 AM UTC 24 |
Sep 09 07:54:52 AM UTC 24 |
1048877324 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3044508627 |
|
|
Sep 09 07:54:38 AM UTC 24 |
Sep 09 07:54:52 AM UTC 24 |
275272922 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.113276879 |
|
|
Sep 09 07:49:18 AM UTC 24 |
Sep 09 07:54:55 AM UTC 24 |
4505034534 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.3130308505 |
|
|
Sep 09 07:54:09 AM UTC 24 |
Sep 09 07:55:00 AM UTC 24 |
1075126629 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3493807490 |
|
|
Sep 09 07:54:52 AM UTC 24 |
Sep 09 07:55:05 AM UTC 24 |
422478145 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1965756064 |
|
|
Sep 09 07:52:51 AM UTC 24 |
Sep 09 07:55:10 AM UTC 24 |
3645464101 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.145284814 |
|
|
Sep 09 07:54:56 AM UTC 24 |
Sep 09 07:55:14 AM UTC 24 |
544210692 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3811757280 |
|
|
Sep 09 07:55:01 AM UTC 24 |
Sep 09 07:55:15 AM UTC 24 |
1984808676 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2200421410 |
|
|
Sep 09 07:54:50 AM UTC 24 |
Sep 09 07:55:16 AM UTC 24 |
2259534296 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.4140594867 |
|
|
Sep 09 07:55:16 AM UTC 24 |
Sep 09 07:55:28 AM UTC 24 |
1033665230 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2698331880 |
|
|
Sep 09 07:55:11 AM UTC 24 |
Sep 09 07:55:34 AM UTC 24 |
347344595 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.862598687 |
|
|
Sep 09 07:55:17 AM UTC 24 |
Sep 09 07:55:41 AM UTC 24 |
604466229 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3548181470 |
|
|
Sep 09 07:55:30 AM UTC 24 |
Sep 09 07:55:42 AM UTC 24 |
354599153 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2838065689 |
|
|
Sep 09 07:54:52 AM UTC 24 |
Sep 09 07:55:44 AM UTC 24 |
1154324747 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.4214494646 |
|
|
Sep 09 07:55:45 AM UTC 24 |
Sep 09 07:55:55 AM UTC 24 |
717544143 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1405538605 |
|
|
Sep 09 07:55:42 AM UTC 24 |
Sep 09 07:56:05 AM UTC 24 |
347573403 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3272667079 |
|
|
Sep 09 07:55:43 AM UTC 24 |
Sep 09 07:56:06 AM UTC 24 |
677300285 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3212854655 |
|
|
Sep 09 07:55:56 AM UTC 24 |
Sep 09 07:56:14 AM UTC 24 |
245148094 ps |