Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

267554

1

T1

28

T3

1

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	97153	1			T1	215		T3	20		T4	23
values[0x0]	99949	1			T14	1146		T15	478		T16	956
values[0x1]	103745	1			T14	1148		T15	592		T16	923

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

285243

1

T1

131

T3

14

T4

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1377	1			T1	1		T7	3		T19	2
valid_sources[0x01]	1012	1			T1	1		T9	4		T148	1
valid_sources[0x02]	1035	1			T1	1		T7	6		T17	8
valid_sources[0x03]	1675	1			T1	1		T6	3		T7	2
valid_sources[0x04]	1077	1			T58	5		T149	2		T14	8
valid_sources[0x05]	1144	1			T7	3		T17	21		T59	1
valid_sources[0x06]	983	1			T148	1		T150	1		T14	9
valid_sources[0x07]	1075	1			T3	1		T7	1		T14	7
valid_sources[0x08]	1768	1			T1	2		T19	4		T59	2
valid_sources[0x09]	1342	1			T7	4		T55	30		T58	3
valid_sources[0x0a]	1041	1			T1	1		T7	1		T59	1
valid_sources[0x0b]	1108	1			T1	3		T9	6		T59	1
valid_sources[0x0c]	1070	1			T17	12		T148	1		T14	8
valid_sources[0x0d]	1039	1			T7	3		T62	1		T148	1
valid_sources[0x0e]	1033	1			T1	1		T7	1		T59	1
valid_sources[0x0f]	1042	1			T1	1		T9	1		T62	1
valid_sources[0x10]	1355	1			T1	3		T7	9		T129	1
valid_sources[0x11]	967	1			T7	3		T148	1		T150	1
valid_sources[0x12]	1455	1			T1	1		T59	2		T148	1
valid_sources[0x13]	1080	1			T149	1		T150	2		T151	1
valid_sources[0x14]	1930	1			T59	1		T62	2		T148	1
valid_sources[0x15]	1134	1			T1	3		T59	1		T148	2
valid_sources[0x16]	977	1			T1	1		T17	6		T59	1
valid_sources[0x17]	1005	1			T7	1		T30	3		T149	1
valid_sources[0x18]	1096	1			T4	1		T19	1		T79	3
valid_sources[0x19]	1981	1			T129	5		T151	1		T14	16
valid_sources[0x1a]	1049	1			T59	2		T148	1		T150	2
valid_sources[0x1b]	1301	1			T59	1		T149	1		T129	1
valid_sources[0x1c]	1725	1			T1	1		T7	2		T59	2
valid_sources[0x1d]	1083	1			T150	1		T14	12		T69	4
valid_sources[0x1e]	1067	1			T1	2		T7	1		T59	1
valid_sources[0x1f]	1049	1			T4	3		T19	2		T149	1
valid_sources[0x20]	1235	1			T1	1		T9	2		T19	3
valid_sources[0x21]	1243	1			T1	5		T7	3		T14	10
valid_sources[0x22]	961	1			T1	5		T7	1		T19	3
valid_sources[0x23]	1061	1			T1	2		T19	2		T59	1
valid_sources[0x24]	1034	1			T59	1		T14	13		T15	1
valid_sources[0x25]	1109	1			T13	3		T129	1		T14	7
valid_sources[0x26]	1070	1			T129	4		T14	12		T15	4
valid_sources[0x27]	989	1			T1	2		T59	1		T62	1
valid_sources[0x28]	1026	1			T150	1		T129	3		T14	16
valid_sources[0x29]	974	1			T1	1		T7	4		T19	1
valid_sources[0x2a]	1035	1			T1	2		T4	1		T7	7
valid_sources[0x2b]	1087	1			T14	15		T69	1		T71	3
valid_sources[0x2c]	1586	1			T1	3		T17	18		T59	4
valid_sources[0x2d]	1062	1			T149	1		T129	4		T14	7
valid_sources[0x2e]	1094	1			T59	1		T62	1		T129	12
valid_sources[0x2f]	1410	1			T1	1		T9	1		T59	1
valid_sources[0x30]	1216	1			T6	2		T148	1		T129	2
valid_sources[0x31]	1387	1			T150	1		T129	3		T14	23
valid_sources[0x32]	1013	1			T59	1		T14	18		T15	1
valid_sources[0x33]	1242	1			T59	1		T30	1		T149	1
valid_sources[0x34]	1453	1			T1	2		T9	1		T59	1
valid_sources[0x35]	1225	1			T17	25		T59	1		T79	1
valid_sources[0x36]	1110	1			T17	35		T59	2		T148	1
valid_sources[0x37]	1006	1			T1	3		T14	11		T69	1
valid_sources[0x38]	1301	1			T148	2		T79	1		T151	2
valid_sources[0x39]	1056	1			T1	1		T9	2		T20	45
valid_sources[0x3a]	1477	1			T1	1		T7	2		T149	1
valid_sources[0x3b]	1238	1			T1	1		T3	4		T148	1
valid_sources[0x3c]	1053	1			T58	4		T59	1		T14	12
valid_sources[0x3d]	1046	1			T7	2		T17	3		T59	1
valid_sources[0x3e]	1049	1			T1	3		T19	1		T59	2
valid_sources[0x3f]	1325	1			T1	1		T9	3		T59	2
valid_sources[0x40]	1549	1			T4	1		T62	1		T148	1
valid_sources[0x41]	1083	1			T1	3		T7	2		T59	1
valid_sources[0x42]	1154	1			T59	2		T152	1		T150	1
valid_sources[0x43]	1016	1			T59	3		T150	1		T14	7
valid_sources[0x44]	1170	1			T1	1		T148	1		T151	1
valid_sources[0x45]	999	1			T1	3		T14	17		T69	3
valid_sources[0x46]	1214	1			T59	4		T61	1		T149	1
valid_sources[0x47]	1151	1			T1	1		T6	4		T19	2
valid_sources[0x48]	995	1			T148	1		T129	3		T151	2
valid_sources[0x49]	1140	1			T55	10		T59	1		T129	6
valid_sources[0x4a]	986	1			T1	2		T7	1		T152	3
valid_sources[0x4b]	1147	1			T59	1		T62	1		T148	1
valid_sources[0x4c]	1060	1			T1	1		T148	1		T149	1
valid_sources[0x4d]	1018	1			T1	2		T59	1		T150	1
valid_sources[0x4e]	1131	1			T17	19		T59	1		T62	1
valid_sources[0x4f]	1074	1			T1	1		T17	5		T61	1
valid_sources[0x50]	1089	1			T149	2		T129	1		T151	1
valid_sources[0x51]	955	1			T4	2		T7	2		T9	2
valid_sources[0x52]	1140	1			T1	4		T3	1		T149	1
valid_sources[0x53]	1216	1			T1	1		T149	1		T151	1
valid_sources[0x54]	1042	1			T1	2		T6	6		T148	1
valid_sources[0x55]	1391	1			T1	2		T7	1		T61	6
valid_sources[0x56]	1015	1			T59	1		T151	2		T14	11
valid_sources[0x57]	1335	1			T1	2		T9	4		T13	1
valid_sources[0x58]	1536	1			T1	1		T4	3		T6	3
valid_sources[0x59]	1059	1			T7	3		T19	2		T59	1
valid_sources[0x5a]	1017	1			T59	1		T61	6		T62	1
valid_sources[0x5b]	1492	1			T148	1		T150	1		T151	1
valid_sources[0x5c]	1019	1			T1	2		T148	1		T149	1
valid_sources[0x5d]	1178	1			T1	2		T9	1		T148	1
valid_sources[0x5e]	965	1			T4	2		T7	5		T149	2
valid_sources[0x5f]	1054	1			T1	3		T17	12		T150	1
valid_sources[0x60]	1298	1			T13	4		T14	8		T15	4
valid_sources[0x61]	1112	1			T14	14		T71	3		T15	3
valid_sources[0x62]	1123	1			T3	4		T7	1		T148	1
valid_sources[0x63]	1043	1			T59	1		T62	1		T148	2
valid_sources[0x64]	979	1			T1	1		T9	1		T14	16
valid_sources[0x65]	1134	1			T1	3		T7	1		T148	1
valid_sources[0x66]	1033	1			T1	2		T17	3		T61	3
valid_sources[0x67]	1006	1			T59	2		T149	1		T150	1
valid_sources[0x68]	1706	1			T1	1		T13	4		T148	1
valid_sources[0x69]	1042	1			T1	1		T3	1		T7	4
valid_sources[0x6a]	998	1			T1	2		T55	39		T30	7
valid_sources[0x6b]	1030	1			T59	3		T148	1		T149	2
valid_sources[0x6c]	1114	1			T58	14		T59	2		T148	1
valid_sources[0x6d]	1375	1			T59	4		T149	2		T151	1
valid_sources[0x6e]	1084	1			T1	2		T9	1		T17	6
valid_sources[0x6f]	1167	1			T7	1		T17	22		T20	40
valid_sources[0x70]	1333	1			T9	3		T148	1		T149	1
valid_sources[0x71]	1437	1			T7	3		T152	1		T149	3
valid_sources[0x72]	1074	1			T7	1		T62	1		T14	10
valid_sources[0x73]	1563	1			T7	1		T59	1		T150	1
valid_sources[0x74]	1616	1			T20	17		T59	1		T14	11
valid_sources[0x75]	1168	1			T58	2		T59	1		T62	1
valid_sources[0x76]	1221	1			T14	6		T69	2		T15	6
valid_sources[0x77]	1507	1			T59	3		T149	1		T14	16
valid_sources[0x78]	1406	1			T7	1		T17	18		T59	2
valid_sources[0x79]	1075	1			T4	1		T13	1		T30	2
valid_sources[0x7a]	1605	1			T7	2		T59	1		T148	1
valid_sources[0x7b]	1107	1			T59	3		T149	1		T150	1
valid_sources[0x7c]	1082	1			T59	1		T129	7		T14	9
valid_sources[0x7d]	1539	1			T1	1		T7	3		T20	13
valid_sources[0x7e]	919	1			T148	3		T150	1		T14	10
valid_sources[0x7f]	1127	1			T1	3		T3	1		T7	2
valid_sources[0x80]	1159	1			T1	1		T19	2		T59	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69502

1

T1

28

T3

1

T6

3

values[0x0]

all_enables

biggest_size

99017

1

T14

1140

T15

474

T16

949

values[0x1]

all_enables

biggest_size

99035

1

T14

1111

T15

544

T16

884

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243144

1

T3

9

T4

9

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	73687	1			T3	16		T4	16		T6	16
values[0x0]	92193	1			T5	1		T8	8		T10	3
values[0x1]	105766	1			T2	1		T5	2		T8	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15375	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

256271

1

T3

11

T4

9

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	901	1			T11	2		T15	5		T16	1
valid_sources[0x01]	809	1			T4	1		T63	1		T15	8
valid_sources[0x02]	1106	1			T84	1		T32	1		T73	1
valid_sources[0x03]	1189	1			T8	1		T15	1		T16	8
valid_sources[0x04]	1013	1			T5	3		T8	1		T14	1
valid_sources[0x05]	1820	1			T15	11		T16	2		T64	5
valid_sources[0x06]	1504	1			T32	5		T15	13		T153	2
valid_sources[0x07]	1113	1			T9	1		T11	1		T30	1
valid_sources[0x08]	874	1			T62	3		T15	24		T16	2
valid_sources[0x09]	1265	1			T15	14		T64	4		T24	1
valid_sources[0x0a]	917	1			T32	1		T71	1		T15	4
valid_sources[0x0b]	980	1			T30	1		T71	1		T15	12
valid_sources[0x0c]	1056	1			T31	2		T14	2		T71	1
valid_sources[0x0d]	1106	1			T61	1		T14	246		T71	1
valid_sources[0x0e]	897	1			T61	1		T15	16		T64	7
valid_sources[0x0f]	1225	1			T30	1		T63	1		T71	1
valid_sources[0x10]	882	1			T11	1		T15	13		T154	1
valid_sources[0x11]	1292	1			T15	44		T155	1		T156	1
valid_sources[0x12]	827	1			T19	1		T14	17		T15	6
valid_sources[0x13]	936	1			T6	1		T15	24		T16	6
valid_sources[0x14]	903	1			T63	1		T14	4		T70	7
valid_sources[0x15]	967	1			T13	1		T71	1		T15	5
valid_sources[0x16]	1060	1			T15	24		T154	1		T157	3
valid_sources[0x17]	910	1			T11	1		T149	1		T157	3
valid_sources[0x18]	902	1			T31	1		T157	1		T64	10
valid_sources[0x19]	904	1			T79	1		T15	27		T16	43
valid_sources[0x1a]	1112	1			T73	1		T16	3		T64	5
valid_sources[0x1b]	1076	1			T9	2		T14	2		T71	1
valid_sources[0x1c]	1116	1			T6	1		T27	1		T79	1
valid_sources[0x1d]	975	1			T53	1		T15	9		T73	1
valid_sources[0x1e]	1369	1			T31	1		T149	1		T71	4
valid_sources[0x1f]	870	1			T15	10		T16	1		T156	1
valid_sources[0x20]	772	1			T11	1		T13	1		T18	1
valid_sources[0x21]	842	1			T84	2		T79	2		T71	2
valid_sources[0x22]	884	1			T14	1		T15	11		T64	18
valid_sources[0x23]	1104	1			T18	1		T15	9		T16	114
valid_sources[0x24]	1209	1			T15	21		T154	1		T64	7
valid_sources[0x25]	1209	1			T14	1		T15	14		T16	87
valid_sources[0x26]	955	1			T61	1		T14	1		T15	3
valid_sources[0x27]	802	1			T18	1		T71	1		T15	20
valid_sources[0x28]	1265	1			T13	1		T18	1		T130	4
valid_sources[0x29]	1161	1			T63	1		T15	7		T154	1
valid_sources[0x2a]	1276	1			T14	1		T15	6		T64	13
valid_sources[0x2b]	957	1			T84	1		T31	1		T14	141
valid_sources[0x2c]	760	1			T14	1		T15	12		T154	1
valid_sources[0x2d]	797	1			T11	2		T31	1		T15	5
valid_sources[0x2e]	1206	1			T15	13		T156	1		T64	8
valid_sources[0x2f]	941	1			T6	1		T13	1		T15	1
valid_sources[0x30]	1268	1			T30	1		T14	2		T15	12
valid_sources[0x31]	1436	1			T57	1		T13	1		T63	2
valid_sources[0x32]	1013	1			T13	1		T14	1		T71	1
valid_sources[0x33]	1399	1			T18	1		T32	4		T14	1
valid_sources[0x34]	964	1			T78	7		T130	1		T14	33
valid_sources[0x35]	828	1			T4	1		T15	6		T158	2
valid_sources[0x36]	1149	1			T15	30		T64	16		T159	1
valid_sources[0x37]	1299	1			T32	10		T14	1		T15	13
valid_sources[0x38]	1133	1			T56	16		T57	1		T152	1
valid_sources[0x39]	1088	1			T6	1		T14	8		T16	2
valid_sources[0x3a]	947	1			T13	1		T15	11		T64	14
valid_sources[0x3b]	932	1			T8	1		T32	3		T15	8
valid_sources[0x3c]	850	1			T31	2		T32	5		T14	4
valid_sources[0x3d]	806	1			T10	1		T152	1		T79	1
valid_sources[0x3e]	977	1			T14	1		T15	7		T154	1
valid_sources[0x3f]	1475	1			T13	2		T15	1		T64	12
valid_sources[0x40]	1365	1			T13	1		T130	1		T14	2
valid_sources[0x41]	1177	1			T9	1		T130	3		T14	1
valid_sources[0x42]	1459	1			T78	1		T15	20		T73	2
valid_sources[0x43]	873	1			T79	1		T15	30		T64	6
valid_sources[0x44]	765	1			T63	1		T79	2		T14	2
valid_sources[0x45]	1142	1			T14	3		T15	18		T16	8
valid_sources[0x46]	766	1			T14	1		T15	31		T16	1
valid_sources[0x47]	734	1			T15	7		T64	8		T159	2
valid_sources[0x48]	1241	1			T13	1		T30	1		T79	1
valid_sources[0x49]	892	1			T78	1		T15	6		T16	1
valid_sources[0x4a]	814	1			T6	2		T19	1		T13	1
valid_sources[0x4b]	922	1			T152	2		T79	1		T15	3
valid_sources[0x4c]	1000	1			T15	10		T154	1		T64	2
valid_sources[0x4d]	1040	1			T13	1		T152	2		T14	52
valid_sources[0x4e]	879	1			T15	11		T64	6		T160	8
valid_sources[0x4f]	970	1			T161	1		T15	1		T16	2
valid_sources[0x50]	904	1			T14	6		T71	1		T15	3
valid_sources[0x51]	1227	1			T3	16		T57	1		T32	5
valid_sources[0x52]	807	1			T15	10		T16	5		T157	5
valid_sources[0x53]	1055	1			T15	12		T64	14		T40	50
valid_sources[0x54]	927	1			T130	3		T14	2		T15	3
valid_sources[0x55]	1213	1			T13	1		T62	1		T14	8
valid_sources[0x56]	838	1			T9	2		T11	5		T14	2
valid_sources[0x57]	1361	1			T15	8		T64	12		T40	11
valid_sources[0x58]	1111	1			T11	1		T61	1		T14	1
valid_sources[0x59]	959	1			T83	8		T62	9		T15	13
valid_sources[0x5a]	882	1			T13	1		T15	1		T154	1
valid_sources[0x5b]	907	1			T14	1		T15	5		T64	8
valid_sources[0x5c]	1604	1			T28	1		T15	8		T64	20
valid_sources[0x5d]	1141	1			T30	1		T15	7		T157	2
valid_sources[0x5e]	786	1			T13	1		T63	3		T14	1
valid_sources[0x5f]	1141	1			T13	1		T14	1		T15	11
valid_sources[0x60]	1222	1			T13	1		T30	2		T15	8
valid_sources[0x61]	996	1			T4	3		T31	1		T15	18
valid_sources[0x62]	830	1			T6	1		T14	11		T15	4
valid_sources[0x63]	870	1			T57	1		T149	11		T15	5
valid_sources[0x64]	1132	1			T8	1		T13	2		T149	4
valid_sources[0x65]	1184	1			T15	4		T16	2		T162	3
valid_sources[0x66]	954	1			T15	24		T157	3		T64	4
valid_sources[0x67]	1159	1			T71	1		T15	18		T157	4
valid_sources[0x68]	909	1			T57	1		T15	4		T64	4
valid_sources[0x69]	1167	1			T14	130		T15	4		T157	1
valid_sources[0x6a]	841	1			T152	1		T14	2		T15	5
valid_sources[0x6b]	911	1			T13	1		T63	1		T71	1
valid_sources[0x6c]	897	1			T15	5		T16	1		T64	7
valid_sources[0x6d]	1121	1			T10	1		T152	1		T161	1
valid_sources[0x6e]	1543	1			T130	2		T15	2		T64	14
valid_sources[0x6f]	1116	1			T61	1		T31	2		T14	2
valid_sources[0x70]	1159	1			T15	7		T16	2		T64	5
valid_sources[0x71]	904	1			T15	8		T154	1		T16	74
valid_sources[0x72]	1540	1			T11	1		T71	1		T15	13
valid_sources[0x73]	927	1			T30	1		T15	11		T154	1
valid_sources[0x74]	868	1			T15	9		T73	1		T64	9
valid_sources[0x75]	1050	1			T130	6		T14	1		T15	2
valid_sources[0x76]	997	1			T14	1		T71	1		T15	14
valid_sources[0x77]	1078	1			T57	1		T30	1		T14	1
valid_sources[0x78]	1065	1			T18	1		T149	4		T130	4
valid_sources[0x79]	1014	1			T11	1		T15	3		T154	1
valid_sources[0x7a]	1305	1			T30	1		T14	157		T15	13
valid_sources[0x7b]	1034	1			T11	4		T14	3		T15	2
valid_sources[0x7c]	1348	1			T15	5		T64	5		T163	1
valid_sources[0x7d]	1199	1			T79	2		T14	1		T15	14
valid_sources[0x7e]	1090	1			T18	1		T14	4		T71	2
valid_sources[0x7f]	1256	1			T79	1		T14	108		T15	8
valid_sources[0x80]	822	1			T63	1		T14	16		T71	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62898

1

T3

9

T4

9

T6

7

values[0x0]

all_enables

biggest_size

89760

1

T8

2

T10

1

T56

4

values[0x1]

all_enables

biggest_size

90486

1

T5

2

T8

3

T56

1