| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.39 | 96.89 | 91.99 | 97.68 | 100.00 | 98.28 | 98.05 | 98.83 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 62.53 | 62.53 | 92.11 | 92.11 | 68.82 | 68.82 | 42.45 | 42.45 | 40.00 | 40.00 | 87.93 | 87.93 | 93.55 | 93.55 | 12.88 | 12.88 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.736806721 |
| 78.15 | 15.62 | 92.46 | 0.36 | 75.70 | 6.88 | 71.51 | 29.06 | 40.00 | 0.00 | 89.66 | 1.72 | 95.05 | 1.50 | 82.67 | 69.79 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1521191699 |
| 83.07 | 4.92 | 93.06 | 0.60 | 77.25 | 1.54 | 78.84 | 7.32 | 60.00 | 20.00 | 92.76 | 3.10 | 95.50 | 0.45 | 84.07 | 1.41 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1791448296 |
| 87.34 | 4.27 | 93.06 | 0.00 | 79.78 | 2.53 | 78.84 | 0.00 | 86.67 | 26.67 | 93.10 | 0.34 | 95.65 | 0.15 | 84.31 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.638386924 |
| 89.94 | 2.60 | 93.18 | 0.12 | 80.06 | 0.28 | 82.36 | 3.52 | 100.00 | 13.33 | 93.79 | 0.69 | 95.65 | 0.00 | 84.54 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3981158036 |
| 91.94 | 2.00 | 96.41 | 3.23 | 84.97 | 4.92 | 85.03 | 2.67 | 100.00 | 0.00 | 95.52 | 1.72 | 95.95 | 0.30 | 85.71 | 1.17 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1403067082 |
| 93.34 | 1.40 | 96.41 | 0.00 | 89.33 | 4.35 | 88.63 | 3.60 | 100.00 | 0.00 | 96.90 | 1.38 | 95.95 | 0.00 | 86.18 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2654125393 |
| 94.33 | 0.98 | 96.65 | 0.24 | 90.03 | 0.70 | 88.63 | 0.00 | 100.00 | 0.00 | 97.93 | 1.03 | 95.95 | 0.00 | 91.10 | 4.92 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.690074412 |
| 95.30 | 0.97 | 96.65 | 0.00 | 90.03 | 0.00 | 93.30 | 4.67 | 100.00 | 0.00 | 97.93 | 0.00 | 95.95 | 0.00 | 93.21 | 2.11 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.518292454 |
| 95.69 | 0.39 | 96.65 | 0.00 | 90.87 | 0.84 | 94.83 | 1.52 | 100.00 | 0.00 | 97.93 | 0.00 | 96.10 | 0.15 | 93.44 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2562659378 |
| 95.95 | 0.26 | 96.65 | 0.00 | 91.43 | 0.56 | 94.88 | 0.05 | 100.00 | 0.00 | 97.93 | 0.00 | 96.40 | 0.30 | 94.38 | 0.94 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1992047198 |
| 96.22 | 0.26 | 96.65 | 0.00 | 91.43 | 0.00 | 95.78 | 0.90 | 100.00 | 0.00 | 97.93 | 0.00 | 96.40 | 0.00 | 95.32 | 0.94 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3143620883 |
| 96.47 | 0.25 | 96.89 | 0.24 | 91.57 | 0.14 | 96.45 | 0.67 | 100.00 | 0.00 | 98.28 | 0.34 | 96.55 | 0.15 | 95.55 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.4087065002 |
| 96.67 | 0.20 | 96.89 | 0.00 | 91.57 | 0.00 | 96.45 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 96.55 | 0.00 | 96.96 | 1.41 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1731393404 |
| 96.84 | 0.17 | 96.89 | 0.00 | 91.71 | 0.14 | 96.45 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 1.05 | 96.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.168246720 |
| 96.97 | 0.13 | 96.89 | 0.00 | 91.71 | 0.00 | 96.45 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 97.89 | 0.94 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4017137482 |
| 97.05 | 0.07 | 96.89 | 0.00 | 91.71 | 0.00 | 96.98 | 0.52 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 97.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3334799693 |
| 97.12 | 0.07 | 96.89 | 0.00 | 91.99 | 0.28 | 96.98 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 98.13 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2867711528 |
| 97.19 | 0.07 | 96.89 | 0.00 | 91.99 | 0.00 | 96.98 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 98.59 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2858836280 |
| 97.25 | 0.06 | 96.89 | 0.00 | 91.99 | 0.00 | 97.38 | 0.40 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 98.59 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2016725063 |
| 97.28 | 0.03 | 96.89 | 0.00 | 91.99 | 0.00 | 97.38 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4248727799 |
| 97.31 | 0.03 | 96.89 | 0.00 | 91.99 | 0.00 | 97.60 | 0.22 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1125536892 |
| 97.33 | 0.02 | 96.89 | 0.00 | 91.99 | 0.00 | 97.60 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.15 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3083838830 |
| 97.36 | 0.02 | 96.89 | 0.00 | 91.99 | 0.00 | 97.60 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.15 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.407748792 |
| 97.38 | 0.02 | 96.89 | 0.00 | 91.99 | 0.00 | 97.60 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 98.05 | 0.15 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2396374150 |
| 97.38 | 0.01 | 96.89 | 0.00 | 91.99 | 0.00 | 97.65 | 0.05 | 100.00 | 0.00 | 98.28 | 0.00 | 98.05 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2214960070 |
| 97.39 | 0.01 | 96.89 | 0.00 | 91.99 | 0.00 | 97.68 | 0.02 | 100.00 | 0.00 | 98.28 | 0.00 | 98.05 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2294266344 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4101476462 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1512284887 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2111446044 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2381743307 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3637875097 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1689926235 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3932715148 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1093381468 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1856169814 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3849697667 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1546500619 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4113418521 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3842272506 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.198273831 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.882804642 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2516407481 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.685889865 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2307591478 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3573904668 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2236697538 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2576732099 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1644029659 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.566040908 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1163830584 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4103613528 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3314503478 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2967299028 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3020639156 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3724007046 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1998319524 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1455262542 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3827729958 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3587477756 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3535290584 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1442417755 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3489932452 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3696470866 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.715369641 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1774540156 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2285887190 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2767524648 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3021161979 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4037971276 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.531052709 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.922462240 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.916562707 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.22077493 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2171085689 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.754249883 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.344778235 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2666635991 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1894649613 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2952512408 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4091928742 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3942064433 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.10089562 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3607251235 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1116538331 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2263168849 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1003097344 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2137434433 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2521571682 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3698378757 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.499078256 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1328430088 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2117410370 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4065319575 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.31749673 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1431291652 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2875389236 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3445519256 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.251177515 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3505057427 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3821791233 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1003411110 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3569332863 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.798562300 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4196725360 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3810291595 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3487718913 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3012645681 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.405038651 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2544407853 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2387896815 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2878433092 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.404095298 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1215371757 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1615373837 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.815352019 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3339509995 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.786836926 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3595538934 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.883867104 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2429690187 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2306101418 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4263604523 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2944216529 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3465686594 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2688628564 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.74352114 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1248334746 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.166980576 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4282066770 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3230894915 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2808006589 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.376310245 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3681411656 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1610218378 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1891912421 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.987866541 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2264851311 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3185119544 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.357902737 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3367593386 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2466105258 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3985007880 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1431844870 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4225750649 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1292830903 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3303316441 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3915048433 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1509160052 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3882273592 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1308260686 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1891958704 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3899015456 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3413010232 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3938822977 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3868989084 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2843050480 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3395642206 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4275860411 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2520924971 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3493929071 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.540529176 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1316186079 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.78165858 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.764828737 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.761252712 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3312159512 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.3033099560 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.2141596777 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2031117373 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2131445395 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3839763584 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3532025167 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.547533018 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.900219479 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.2952483584 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1383937776 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3847061220 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4179117759 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.2709354173 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4037613604 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2972123205 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1279563380 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3676335743 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.142398182 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.2351430018 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.89631919 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.537825729 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2803043224 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1079399503 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2123476249 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3507215470 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.974804773 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2200733352 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1751321741 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1382053228 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.2613967149 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.741591211 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.778975416 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1990852756 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2971019261 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.597004942 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.952739188 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.989147752 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.842432526 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.147077125 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.491881736 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2658241824 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.890587523 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2925702508 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3927777311 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.905830848 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1406431494 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.111996922 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1808993564 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1218316243 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2149270944 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1242813136 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3101608572 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.26686818 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2287923421 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1638374778 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.1645988693 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3037435166 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2458101966 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1940634973 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.907307757 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.85437557 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3716628467 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2405650002 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2569796380 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1591404217 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.532457574 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2187484114 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.3944647304 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2715910737 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.4153033416 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2934315120 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3273187059 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1828765306 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3397146687 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2165915149 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2524728280 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.61884784 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3183202659 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.722965272 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2125065533 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3993191402 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.393350478 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1846825742 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.767698717 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1948868129 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.468237358 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.4165733960 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2719969527 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.487208341 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3103584597 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2021715260 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1465279986 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.96508812 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2795222637 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1716504022 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.974823907 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.729815419 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3708041606 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3180883059 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3094390041 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.590649996 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2165126900 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2021187768 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3653567356 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1682458035 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1004402570 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2254428738 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3375297130 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.223963701 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2853900859 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2783957266 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.709939215 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3844270895 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3364773558 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3081550781 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.574849087 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.3455335116 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3540413028 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3979710626 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3613701679 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.3596001283 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.48345822 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2629186727 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.3223179359 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.815331361 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2401265969 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1427289534 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.3823462478 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2607569695 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1360186376 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.319228787 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3266785739 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2836957783 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1534351716 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2137315471 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.1726283658 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.4146702506 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3073539576 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1269585604 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2272519984 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.372040996 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3921180596 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2565325073 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2630364899 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.326269370 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.4031938413 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2505344681 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.190269682 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.811062881 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2957026857 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.4240222792 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.3265146401 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.435175187 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2822718104 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.192168307 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3935021395 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3944125369 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.728175448 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3784139510 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.320657211 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.1959340000 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1491441934 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.951299049 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3649418263 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3162135330 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.2342988206 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3667282027 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1057946186 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4109220024 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3172450432 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2335190629 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.3032558769 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.601003682 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3624585851 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.677755378 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.2789759004 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2131545709 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3712398838 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.729283104 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.570876582 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2740069137 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.706535198 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.223779873 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3336519655 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2785693964 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.784494341 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.240950823 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.304692809 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3527592655 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1460897120 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2194833230 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.4129617964 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4191518633 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2824548064 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.4179464421 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.4117908518 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2455368801 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.91116383 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3438513084 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1637462241 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.2833270894 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.865295828 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2065128130 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.577264152 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.163621690 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1925796737 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2999035734 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1176087932 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1270212941 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1325478768 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4026814980 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3623286566 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.844989404 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1813972189 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3948863214 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.862113424 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.4213869909 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1457672961 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.4076581595 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1159427578 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3548669275 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.700261732 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3432241436 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.279740861 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3894491043 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1480038764 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3645714935 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.900248698 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.693412939 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2027635643 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3119454194 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3809593440 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3610124998 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.347449699 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1703551452 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1806808303 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1207551181 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2537055548 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2843752949 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2781319528 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3172345266 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2870093807 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1535237133 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2233595435 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.1013882263 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1867490903 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1744753244 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1164970548 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.2564450786 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3700862640 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1538923776 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.183668663 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3577904139 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2599082720 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1215339901 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3483888012 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1762747197 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.952648391 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.4029588175 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3221784813 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2576914794 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2891686771 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1710002239 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3487187983 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.932784156 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1111362843 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1604246226 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.373532533 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3168781103 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3660152496 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1319190966 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.376536836 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2030992477 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.844491998 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.78958926 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.150388410 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1707719827 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1982196956 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1501609269 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3218779911 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1383148454 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4232189573 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.801169411 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2348736162 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1659948586 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3586638456 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1181295504 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2015990291 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3294220784 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3366436609 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1984312331 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3312159512 | Sep 11 03:28:37 AM UTC 24 | Sep 11 03:28:49 AM UTC 24 | 181926343 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.764828737 | Sep 11 03:28:38 AM UTC 24 | Sep 11 03:28:50 AM UTC 24 | 468775000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.2141596777 | Sep 11 03:28:37 AM UTC 24 | Sep 11 03:28:51 AM UTC 24 | 1073741437 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3532025167 | Sep 11 03:28:39 AM UTC 24 | Sep 11 03:28:52 AM UTC 24 | 261743314 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2031117373 | Sep 11 03:28:43 AM UTC 24 | Sep 11 03:28:53 AM UTC 24 | 2746818344 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.4153033416 | Sep 11 03:28:43 AM UTC 24 | Sep 11 03:28:55 AM UTC 24 | 762025314 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3839763584 | Sep 11 03:28:39 AM UTC 24 | Sep 11 03:28:55 AM UTC 24 | 3201381876 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1360186376 | Sep 11 03:28:46 AM UTC 24 | Sep 11 03:28:56 AM UTC 24 | 174585112 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.736806721 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:28:57 AM UTC 24 | 544920205 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1403067082 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:28:58 AM UTC 24 | 258740398 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.91116383 | Sep 11 03:28:46 AM UTC 24 | Sep 11 03:28:59 AM UTC 24 | 697981590 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.4087065002 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:29:00 AM UTC 24 | 538932522 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.3944647304 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:29:01 AM UTC 24 | 376922922 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1125536892 | Sep 11 03:28:37 AM UTC 24 | Sep 11 03:29:01 AM UTC 24 | 524601574 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3334799693 | Sep 11 03:28:37 AM UTC 24 | Sep 11 03:29:02 AM UTC 24 | 507856831 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.4117908518 | Sep 11 03:28:48 AM UTC 24 | Sep 11 03:29:03 AM UTC 24 | 512740988 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2824548064 | Sep 11 03:28:52 AM UTC 24 | Sep 11 03:29:04 AM UTC 24 | 1123374880 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2576914794 | Sep 11 03:28:56 AM UTC 24 | Sep 11 03:29:06 AM UTC 24 | 614348280 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3266785739 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:29:08 AM UTC 24 | 555259241 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2214960070 | Sep 11 03:28:43 AM UTC 24 | Sep 11 03:29:08 AM UTC 24 | 661770480 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2187484114 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:29:09 AM UTC 24 | 3296404971 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1791448296 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:29:10 AM UTC 24 | 1375528633 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3660152496 | Sep 11 03:28:59 AM UTC 24 | Sep 11 03:29:11 AM UTC 24 | 270907810 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3487187983 | Sep 11 03:28:55 AM UTC 24 | Sep 11 03:29:13 AM UTC 24 | 728622722 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2654125393 | Sep 11 03:28:53 AM UTC 24 | Sep 11 03:29:13 AM UTC 24 | 7650920716 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.4179464421 | Sep 11 03:28:49 AM UTC 24 | Sep 11 03:29:14 AM UTC 24 | 1034121684 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1604246226 | Sep 11 03:29:01 AM UTC 24 | Sep 11 03:29:14 AM UTC 24 | 985779577 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1319190966 | Sep 11 03:28:57 AM UTC 24 | Sep 11 03:29:14 AM UTC 24 | 714193356 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1982196956 | Sep 11 03:29:01 AM UTC 24 | Sep 11 03:29:16 AM UTC 24 | 186498584 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.844491998 | Sep 11 03:29:06 AM UTC 24 | Sep 11 03:29:17 AM UTC 24 | 1031357920 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2294266344 | Sep 11 03:28:39 AM UTC 24 | Sep 11 03:29:17 AM UTC 24 | 721369179 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3438513084 | Sep 11 03:28:46 AM UTC 24 | Sep 11 03:29:17 AM UTC 24 | 4196896216 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1710002239 | Sep 11 03:28:56 AM UTC 24 | Sep 11 03:29:18 AM UTC 24 | 350615760 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1707719827 | Sep 11 03:29:03 AM UTC 24 | Sep 11 03:29:20 AM UTC 24 | 262434625 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2562659378 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:29:22 AM UTC 24 | 2016164215 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3168781103 | Sep 11 03:29:00 AM UTC 24 | Sep 11 03:29:24 AM UTC 24 | 333839662 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2348736162 | Sep 11 03:29:07 AM UTC 24 | Sep 11 03:29:25 AM UTC 24 | 397682369 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1383148454 | Sep 11 03:29:11 AM UTC 24 | Sep 11 03:29:25 AM UTC 24 | 972068545 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1659948586 | Sep 11 03:29:17 AM UTC 24 | Sep 11 03:29:26 AM UTC 24 | 339020306 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.932784156 | Sep 11 03:28:53 AM UTC 24 | Sep 11 03:29:26 AM UTC 24 | 2108118872 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1501609269 | Sep 11 03:29:02 AM UTC 24 | Sep 11 03:29:26 AM UTC 24 | 2427745756 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.801169411 | Sep 11 03:29:09 AM UTC 24 | Sep 11 03:29:26 AM UTC 24 | 1111630259 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3294220784 | Sep 11 03:29:12 AM UTC 24 | Sep 11 03:29:27 AM UTC 24 | 1108535043 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.150388410 | Sep 11 03:29:05 AM UTC 24 | Sep 11 03:29:28 AM UTC 24 | 1984419932 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2015990291 | Sep 11 03:29:14 AM UTC 24 | Sep 11 03:29:30 AM UTC 24 | 839625796 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1383937776 | Sep 11 03:29:18 AM UTC 24 | Sep 11 03:29:35 AM UTC 24 | 185128986 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3981158036 | Sep 11 03:29:10 AM UTC 24 | Sep 11 03:29:36 AM UTC 24 | 2757108905 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3366436609 | Sep 11 03:29:13 AM UTC 24 | Sep 11 03:29:36 AM UTC 24 | 748662161 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.547533018 | Sep 11 03:29:23 AM UTC 24 | Sep 11 03:29:36 AM UTC 24 | 338829172 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.518292454 | Sep 11 03:28:37 AM UTC 24 | Sep 11 03:29:38 AM UTC 24 | 2923698752 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.2709354173 | Sep 11 03:29:26 AM UTC 24 | Sep 11 03:29:39 AM UTC 24 | 1034276349 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1279563380 | Sep 11 03:29:25 AM UTC 24 | Sep 11 03:29:40 AM UTC 24 | 190390117 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.2351430018 | Sep 11 03:29:31 AM UTC 24 | Sep 11 03:29:40 AM UTC 24 | 178236293 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1181295504 | Sep 11 03:29:15 AM UTC 24 | Sep 11 03:29:42 AM UTC 24 | 3308371532 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.376536836 | Sep 11 03:28:57 AM UTC 24 | Sep 11 03:29:42 AM UTC 24 | 1550369213 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1521191699 | Sep 11 03:28:43 AM UTC 24 | Sep 11 03:29:43 AM UTC 24 | 9770794828 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2803043224 | Sep 11 03:29:28 AM UTC 24 | Sep 11 03:29:47 AM UTC 24 | 1063105414 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2016725063 | Sep 11 03:29:09 AM UTC 24 | Sep 11 03:29:47 AM UTC 24 | 548586599 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1990852756 | Sep 11 03:29:37 AM UTC 24 | Sep 11 03:29:48 AM UTC 24 | 2180835176 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2972123205 | Sep 11 03:29:26 AM UTC 24 | Sep 11 03:29:49 AM UTC 24 | 662477680 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.2952483584 | Sep 11 03:29:19 AM UTC 24 | Sep 11 03:29:51 AM UTC 24 | 335776940 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3507215470 | Sep 11 03:29:37 AM UTC 24 | Sep 11 03:29:51 AM UTC 24 | 484717351 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1382053228 | Sep 11 03:29:33 AM UTC 24 | Sep 11 03:29:53 AM UTC 24 | 2059908092 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1751321741 | Sep 11 03:29:34 AM UTC 24 | Sep 11 03:29:53 AM UTC 24 | 528256306 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.2613967149 | Sep 11 03:29:41 AM UTC 24 | Sep 11 03:29:55 AM UTC 24 | 826855882 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3218779911 | Sep 11 03:29:06 AM UTC 24 | Sep 11 03:29:56 AM UTC 24 | 1110815100 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.147077125 | Sep 11 03:29:43 AM UTC 24 | Sep 11 03:29:58 AM UTC 24 | 1858200912 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.537825729 | Sep 11 03:29:29 AM UTC 24 | Sep 11 03:30:00 AM UTC 24 | 497382925 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3847061220 | Sep 11 03:29:18 AM UTC 24 | Sep 11 03:30:02 AM UTC 24 | 807815559 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.491881736 | Sep 11 03:29:42 AM UTC 24 | Sep 11 03:30:02 AM UTC 24 | 537914580 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.952739188 | Sep 11 03:29:49 AM UTC 24 | Sep 11 03:30:02 AM UTC 24 | 2358482357 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3676335743 | Sep 11 03:29:25 AM UTC 24 | Sep 11 03:30:03 AM UTC 24 | 810406912 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.905830848 | Sep 11 03:29:52 AM UTC 24 | Sep 11 03:30:04 AM UTC 24 | 1167939510 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2200733352 | Sep 11 03:29:36 AM UTC 24 | Sep 11 03:30:05 AM UTC 24 | 1008816709 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3143620883 | Sep 11 03:29:11 AM UTC 24 | Sep 11 03:30:06 AM UTC 24 | 2041839676 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.890587523 | Sep 11 03:29:53 AM UTC 24 | Sep 11 03:30:08 AM UTC 24 | 1180608032 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.778975416 | Sep 11 03:29:40 AM UTC 24 | Sep 11 03:30:08 AM UTC 24 | 2060899348 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.842432526 | Sep 11 03:29:47 AM UTC 24 | Sep 11 03:30:11 AM UTC 24 | 515562104 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1242813136 | Sep 11 03:29:55 AM UTC 24 | Sep 11 03:30:13 AM UTC 24 | 259760897 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3927777311 | Sep 11 03:29:53 AM UTC 24 | Sep 11 03:30:15 AM UTC 24 | 373431154 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1808993564 | Sep 11 03:30:03 AM UTC 24 | Sep 11 03:30:17 AM UTC 24 | 505423551 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2287923421 | Sep 11 03:30:06 AM UTC 24 | Sep 11 03:30:17 AM UTC 24 | 250815483 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1079399503 | Sep 11 03:29:28 AM UTC 24 | Sep 11 03:30:18 AM UTC 24 | 3587916389 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2971019261 | Sep 11 03:29:37 AM UTC 24 | Sep 11 03:30:19 AM UTC 24 | 840239064 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1406431494 | Sep 11 03:29:50 AM UTC 24 | Sep 11 03:30:19 AM UTC 24 | 1055695454 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3037435166 | Sep 11 03:30:03 AM UTC 24 | Sep 11 03:30:19 AM UTC 24 | 916085571 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2149270944 | Sep 11 03:29:59 AM UTC 24 | Sep 11 03:30:21 AM UTC 24 | 516611494 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2405650002 | Sep 11 03:30:08 AM UTC 24 | Sep 11 03:30:23 AM UTC 24 | 366023071 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.907307757 | Sep 11 03:30:12 AM UTC 24 | Sep 11 03:30:25 AM UTC 24 | 993137881 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.1645988693 | Sep 11 03:30:05 AM UTC 24 | Sep 11 03:30:33 AM UTC 24 | 495548428 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3101608572 | Sep 11 03:29:54 AM UTC 24 | Sep 11 03:30:33 AM UTC 24 | 534262502 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3716628467 | Sep 11 03:30:09 AM UTC 24 | Sep 11 03:30:33 AM UTC 24 | 345226301 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3273187059 | Sep 11 03:30:19 AM UTC 24 | Sep 11 03:30:34 AM UTC 24 | 247591506 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.3033099560 | Sep 11 03:28:38 AM UTC 24 | Sep 11 03:30:35 AM UTC 24 | 1769508583 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2165915149 | Sep 11 03:30:16 AM UTC 24 | Sep 11 03:30:37 AM UTC 24 | 276059834 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3993191402 | Sep 11 03:30:20 AM UTC 24 | Sep 11 03:30:38 AM UTC 24 | 756222168 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3397146687 | Sep 11 03:30:18 AM UTC 24 | Sep 11 03:30:40 AM UTC 24 | 2763778636 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1111362843 | Sep 11 03:28:56 AM UTC 24 | Sep 11 03:30:40 AM UTC 24 | 20910556218 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.1726283658 | Sep 11 03:31:46 AM UTC 24 | Sep 11 03:32:22 AM UTC 24 | 510897135 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2836957783 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:30:40 AM UTC 24 | 1807805771 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3183202659 | Sep 11 03:30:25 AM UTC 24 | Sep 11 03:30:41 AM UTC 24 | 4119676314 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2658241824 | Sep 11 03:29:48 AM UTC 24 | Sep 11 03:30:41 AM UTC 24 | 13470978518 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2458101966 | Sep 11 03:30:03 AM UTC 24 | Sep 11 03:30:41 AM UTC 24 | 7118122851 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.393350478 | Sep 11 03:30:20 AM UTC 24 | Sep 11 03:30:42 AM UTC 24 | 430603490 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2569796380 | Sep 11 03:30:06 AM UTC 24 | Sep 11 03:30:42 AM UTC 24 | 531576277 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4179117759 | Sep 11 03:29:21 AM UTC 24 | Sep 11 03:30:44 AM UTC 24 | 3406706888 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2524728280 | Sep 11 03:30:14 AM UTC 24 | Sep 11 03:30:46 AM UTC 24 | 2132243106 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.4165733960 | Sep 11 03:30:33 AM UTC 24 | Sep 11 03:30:47 AM UTC 24 | 178998887 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1984312331 | Sep 11 03:29:15 AM UTC 24 | Sep 11 03:30:47 AM UTC 24 | 1653625484 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.767698717 | Sep 11 03:30:38 AM UTC 24 | Sep 11 03:30:52 AM UTC 24 | 174333289 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2125065533 | Sep 11 03:30:22 AM UTC 24 | Sep 11 03:30:52 AM UTC 24 | 1032592123 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.96508812 | Sep 11 03:30:41 AM UTC 24 | Sep 11 03:30:55 AM UTC 24 | 260583448 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3103584597 | Sep 11 03:30:42 AM UTC 24 | Sep 11 03:30:58 AM UTC 24 | 577392073 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.974823907 | Sep 11 03:30:47 AM UTC 24 | Sep 11 03:31:00 AM UTC 24 | 249093445 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.468237358 | Sep 11 03:30:35 AM UTC 24 | Sep 11 03:31:02 AM UTC 24 | 1980611723 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3180883059 | Sep 11 03:30:42 AM UTC 24 | Sep 11 03:31:02 AM UTC 24 | 1831215084 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2719969527 | Sep 11 03:30:33 AM UTC 24 | Sep 11 03:31:04 AM UTC 24 | 281088075 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1465279986 | Sep 11 03:30:41 AM UTC 24 | Sep 11 03:31:06 AM UTC 24 | 507915158 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.319228787 | Sep 11 03:28:46 AM UTC 24 | Sep 11 03:31:06 AM UTC 24 | 1672223482 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1682458035 | Sep 11 03:30:50 AM UTC 24 | Sep 11 03:31:07 AM UTC 24 | 261296004 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2165126900 | Sep 11 03:31:00 AM UTC 24 | Sep 11 03:31:12 AM UTC 24 | 260255778 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1004402570 | Sep 11 03:30:48 AM UTC 24 | Sep 11 03:31:13 AM UTC 24 | 209197999 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2783957266 | Sep 11 03:31:01 AM UTC 24 | Sep 11 03:31:13 AM UTC 24 | 238601217 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2934315120 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:31:14 AM UTC 24 | 5513226499 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2795222637 | Sep 11 03:30:39 AM UTC 24 | Sep 11 03:31:15 AM UTC 24 | 890060701 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3375297130 | Sep 11 03:31:06 AM UTC 24 | Sep 11 03:31:18 AM UTC 24 | 360755050 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3708041606 | Sep 11 03:30:45 AM UTC 24 | Sep 11 03:31:18 AM UTC 24 | 989101265 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3653567356 | Sep 11 03:30:53 AM UTC 24 | Sep 11 03:31:21 AM UTC 24 | 2539602963 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1940634973 | Sep 11 03:30:05 AM UTC 24 | Sep 11 03:31:25 AM UTC 24 | 22193754696 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.3455335116 | Sep 11 03:31:06 AM UTC 24 | Sep 11 03:31:26 AM UTC 24 | 294186389 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.574849087 | Sep 11 03:31:08 AM UTC 24 | Sep 11 03:31:26 AM UTC 24 | 270575442 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.532457574 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:31:27 AM UTC 24 | 9788723929 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3844270895 | Sep 11 03:31:15 AM UTC 24 | Sep 11 03:31:28 AM UTC 24 | 360444758 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3094390041 | Sep 11 03:30:42 AM UTC 24 | Sep 11 03:31:31 AM UTC 24 | 11889244548 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.3596001283 | Sep 11 03:31:19 AM UTC 24 | Sep 11 03:31:35 AM UTC 24 | 270004417 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3540413028 | Sep 11 03:31:27 AM UTC 24 | Sep 11 03:31:37 AM UTC 24 | 174212616 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2853900859 | Sep 11 03:31:03 AM UTC 24 | Sep 11 03:31:39 AM UTC 24 | 2751957760 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.48345822 | Sep 11 03:31:16 AM UTC 24 | Sep 11 03:31:40 AM UTC 24 | 664153299 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3081550781 | Sep 11 03:31:13 AM UTC 24 | Sep 11 03:31:40 AM UTC 24 | 346315251 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1427289534 | Sep 11 03:31:28 AM UTC 24 | Sep 11 03:31:45 AM UTC 24 | 692653090 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2396374150 | Sep 11 03:31:00 AM UTC 24 | Sep 11 03:31:47 AM UTC 24 | 1073969047 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.3223179359 | Sep 11 03:31:37 AM UTC 24 | Sep 11 03:31:51 AM UTC 24 | 281885053 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3613701679 | Sep 11 03:31:22 AM UTC 24 | Sep 11 03:31:52 AM UTC 24 | 504879992 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2401265969 | Sep 11 03:31:32 AM UTC 24 | Sep 11 03:31:53 AM UTC 24 | 678184109 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2891686771 | Sep 11 03:28:55 AM UTC 24 | Sep 11 03:31:57 AM UTC 24 | 7759348166 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.4146702506 | Sep 11 03:31:41 AM UTC 24 | Sep 11 03:31:57 AM UTC 24 | 727833413 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.597004942 | Sep 11 03:29:41 AM UTC 24 | Sep 11 03:31:57 AM UTC 24 | 28466268359 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1534351716 | Sep 11 03:31:52 AM UTC 24 | Sep 11 03:32:02 AM UTC 24 | 1773846263 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.26686818 | Sep 11 03:30:01 AM UTC 24 | Sep 11 03:32:02 AM UTC 24 | 1870692848 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.487208341 | Sep 11 03:30:37 AM UTC 24 | Sep 11 03:32:05 AM UTC 24 | 7760400869 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.3823462478 | Sep 11 03:31:27 AM UTC 24 | Sep 11 03:32:09 AM UTC 24 | 2148395766 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.142398182 | Sep 11 03:29:26 AM UTC 24 | Sep 11 03:32:10 AM UTC 24 | 12063740451 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2565325073 | Sep 11 03:31:54 AM UTC 24 | Sep 11 03:32:11 AM UTC 24 | 354717558 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2272519984 | Sep 11 03:31:58 AM UTC 24 | Sep 11 03:32:13 AM UTC 24 | 1028822372 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3073539576 | Sep 11 03:31:39 AM UTC 24 | Sep 11 03:32:16 AM UTC 24 | 1440800546 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2254428738 | Sep 11 03:30:55 AM UTC 24 | Sep 11 03:32:17 AM UTC 24 | 22139857767 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.811062881 | Sep 11 03:32:03 AM UTC 24 | Sep 11 03:32:18 AM UTC 24 | 1841472648 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.4031938413 | Sep 11 03:32:12 AM UTC 24 | Sep 11 03:32:22 AM UTC 24 | 499364163 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.111996922 | Sep 11 03:29:53 AM UTC 24 | Sep 11 03:32:23 AM UTC 24 | 2629077411 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1591404217 | Sep 11 03:30:09 AM UTC 24 | Sep 11 03:32:26 AM UTC 24 | 13270287605 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3921180596 | Sep 11 03:31:58 AM UTC 24 | Sep 11 03:32:29 AM UTC 24 | 336098885 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.192168307 | Sep 11 03:32:17 AM UTC 24 | Sep 11 03:32:31 AM UTC 24 | 272005917 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2123476249 | Sep 11 03:29:31 AM UTC 24 | Sep 11 03:32:31 AM UTC 24 | 5465191001 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.638386924 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:32:32 AM UTC 24 | 11701439187 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.3265146401 | Sep 11 03:32:23 AM UTC 24 | Sep 11 03:32:33 AM UTC 24 | 254647559 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2630364899 | Sep 11 03:31:53 AM UTC 24 | Sep 11 03:32:35 AM UTC 24 | 1352866714 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.61884784 | Sep 11 03:30:18 AM UTC 24 | Sep 11 03:32:36 AM UTC 24 | 8424480421 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.190269682 | Sep 11 03:32:09 AM UTC 24 | Sep 11 03:32:37 AM UTC 24 | 662584081 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1637462241 | Sep 11 03:28:50 AM UTC 24 | Sep 11 03:32:40 AM UTC 24 | 6055319911 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.900219479 | Sep 11 03:29:19 AM UTC 24 | Sep 11 03:32:43 AM UTC 24 | 7965835796 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2822718104 | Sep 11 03:32:19 AM UTC 24 | Sep 11 03:32:44 AM UTC 24 | 2243297500 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.1959340000 | Sep 11 03:32:27 AM UTC 24 | Sep 11 03:32:47 AM UTC 24 | 538497201 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2867711528 | Sep 11 03:28:48 AM UTC 24 | Sep 11 03:32:47 AM UTC 24 | 16518762872 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.728175448 | Sep 11 03:32:32 AM UTC 24 | Sep 11 03:32:47 AM UTC 24 | 1030421163 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.722965272 | Sep 11 03:30:20 AM UTC 24 | Sep 11 03:32:47 AM UTC 24 | 7980613230 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2957026857 | Sep 11 03:32:02 AM UTC 24 | Sep 11 03:32:47 AM UTC 24 | 844755673 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.373532533 | Sep 11 03:29:00 AM UTC 24 | Sep 11 03:32:48 AM UTC 24 | 14439619275 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3586638456 | Sep 11 03:29:14 AM UTC 24 | Sep 11 03:32:50 AM UTC 24 | 7614411179 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3935021395 | Sep 11 03:32:14 AM UTC 24 | Sep 11 03:32:51 AM UTC 24 | 1056013741 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3667282027 | Sep 11 03:32:37 AM UTC 24 | Sep 11 03:32:53 AM UTC 24 | 259808938 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3649418263 | Sep 11 03:32:40 AM UTC 24 | Sep 11 03:32:55 AM UTC 24 | 333517413 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.320657211 | Sep 11 03:32:31 AM UTC 24 | Sep 11 03:32:56 AM UTC 24 | 692930916 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4037613604 | Sep 11 03:29:26 AM UTC 24 | Sep 11 03:32:57 AM UTC 24 | 5058906951 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2030992477 | Sep 11 03:29:01 AM UTC 24 | Sep 11 03:32:58 AM UTC 24 | 18245096441 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.601003682 | Sep 11 03:32:44 AM UTC 24 | Sep 11 03:33:00 AM UTC 24 | 182737189 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2455368801 | Sep 11 03:28:51 AM UTC 24 | Sep 11 03:33:00 AM UTC 24 | 1116060629 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.2342988206 | Sep 11 03:32:38 AM UTC 24 | Sep 11 03:33:00 AM UTC 24 | 1381661637 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.729283104 | Sep 11 03:32:49 AM UTC 24 | Sep 11 03:33:02 AM UTC 24 | 2136262761 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.741591211 | Sep 11 03:29:39 AM UTC 24 | Sep 11 03:33:03 AM UTC 24 | 2184078645 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3172450432 | Sep 11 03:32:49 AM UTC 24 | Sep 11 03:33:03 AM UTC 24 | 260467720 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1491441934 | Sep 11 03:32:24 AM UTC 24 | Sep 11 03:33:04 AM UTC 24 | 2332789857 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1992047198 | Sep 11 03:28:43 AM UTC 24 | Sep 11 03:33:05 AM UTC 24 | 1417348876 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.709939215 | Sep 11 03:31:05 AM UTC 24 | Sep 11 03:33:08 AM UTC 24 | 5152099553 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.2789759004 | Sep 11 03:32:55 AM UTC 24 | Sep 11 03:33:08 AM UTC 24 | 987522787 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.570876582 | Sep 11 03:32:49 AM UTC 24 | Sep 11 03:33:13 AM UTC 24 | 297087392 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2785693964 | Sep 11 03:32:57 AM UTC 24 | Sep 11 03:33:15 AM UTC 24 | 5178634172 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.974804773 | Sep 11 03:29:35 AM UTC 24 | Sep 11 03:33:16 AM UTC 24 | 11962917740 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.706535198 | Sep 11 03:33:01 AM UTC 24 | Sep 11 03:33:16 AM UTC 24 | 498062248 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.3032558769 | Sep 11 03:32:48 AM UTC 24 | Sep 11 03:33:17 AM UTC 24 | 1770008572 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.729815419 | Sep 11 03:30:43 AM UTC 24 | Sep 11 03:33:17 AM UTC 24 | 6196963783 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1057946186 | Sep 11 03:32:33 AM UTC 24 | Sep 11 03:33:17 AM UTC 24 | 563505584 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.761252712 | Sep 11 03:28:37 AM UTC 24 | Sep 11 03:33:18 AM UTC 24 | 3128783014 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4232189573 | Sep 11 03:29:09 AM UTC 24 | Sep 11 03:33:20 AM UTC 24 | 20493920703 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3712398838 | Sep 11 03:32:52 AM UTC 24 | Sep 11 03:33:20 AM UTC 24 | 333945726 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.304692809 | Sep 11 03:33:09 AM UTC 24 | Sep 11 03:33:20 AM UTC 24 | 570556652 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2194833230 | Sep 11 03:33:04 AM UTC 24 | Sep 11 03:33:21 AM UTC 24 | 263717737 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3336519655 | Sep 11 03:33:00 AM UTC 24 | Sep 11 03:33:22 AM UTC 24 | 1319265171 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3624585851 | Sep 11 03:32:44 AM UTC 24 | Sep 11 03:33:22 AM UTC 24 | 567482315 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.2833270894 | Sep 11 03:33:17 AM UTC 24 | Sep 11 03:33:29 AM UTC 24 | 660897437 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1460897120 | Sep 11 03:33:05 AM UTC 24 | Sep 11 03:33:29 AM UTC 24 | 945409964 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.78958926 | Sep 11 03:29:04 AM UTC 24 | Sep 11 03:33:31 AM UTC 24 | 52496020037 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.577264152 | Sep 11 03:33:14 AM UTC 24 | Sep 11 03:33:33 AM UTC 24 | 259490769 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1846825742 | Sep 11 03:30:24 AM UTC 24 | Sep 11 03:33:35 AM UTC 24 | 18375620486 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.862113424 | Sep 11 03:33:23 AM UTC 24 | Sep 11 03:33:35 AM UTC 24 | 729544427 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2999035734 | Sep 11 03:33:22 AM UTC 24 | Sep 11 03:33:36 AM UTC 24 | 293152303 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1325478768 | Sep 11 03:33:18 AM UTC 24 | Sep 11 03:33:36 AM UTC 24 | 261032835 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2715910737 | Sep 11 03:28:44 AM UTC 24 | Sep 11 03:33:40 AM UTC 24 | 423986731 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1948868129 | Sep 11 03:30:34 AM UTC 24 | Sep 11 03:33:41 AM UTC 24 | 9476674482 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.4129617964 | Sep 11 03:33:02 AM UTC 24 | Sep 11 03:33:41 AM UTC 24 | 537592873 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4026814980 | Sep 11 03:33:17 AM UTC 24 | Sep 11 03:33:43 AM UTC 24 | 1609542647 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2740069137 | Sep 11 03:32:54 AM UTC 24 | Sep 11 03:33:44 AM UTC 24 | 964036531 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.590649996 | Sep 11 03:30:46 AM UTC 24 | Sep 11 03:33:44 AM UTC 24 | 2572217128 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.163621690 | Sep 11 03:33:09 AM UTC 24 | Sep 11 03:33:45 AM UTC 24 | 657350120 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2065128130 | Sep 11 03:33:16 AM UTC 24 | Sep 11 03:33:46 AM UTC 24 | 345727524 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2021715260 | Sep 11 03:30:41 AM UTC 24 | Sep 11 03:33:46 AM UTC 24 | 3885592481 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.844989404 | Sep 11 03:33:32 AM UTC 24 | Sep 11 03:33:47 AM UTC 24 | 257991437 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.85437557 | Sep 11 03:30:08 AM UTC 24 | Sep 11 03:33:48 AM UTC 24 | 9874688567 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1270212941 | Sep 11 03:33:20 AM UTC 24 | Sep 11 03:33:48 AM UTC 24 | 340237601 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.700261732 | Sep 11 03:33:36 AM UTC 24 | Sep 11 03:33:49 AM UTC 24 | 358923217 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3364773558 | Sep 11 03:31:13 AM UTC 24 | Sep 11 03:33:50 AM UTC 24 | 5560176385 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2925702508 | Sep 11 03:29:52 AM UTC 24 | Sep 11 03:33:50 AM UTC 24 | 3497969700 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3948863214 | Sep 11 03:33:30 AM UTC 24 | Sep 11 03:33:53 AM UTC 24 | 336036865 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.4076581595 | Sep 11 03:33:41 AM UTC 24 | Sep 11 03:33:54 AM UTC 24 | 340904429 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.784494341 | Sep 11 03:32:57 AM UTC 24 | Sep 11 03:33:57 AM UTC 24 | 2800914184 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.900248698 | Sep 11 03:33:43 AM UTC 24 | Sep 11 03:33:57 AM UTC 24 | 380329174 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3944125369 | Sep 11 03:32:23 AM UTC 24 | Sep 11 03:33:58 AM UTC 24 | 47463251064 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4191518633 | Sep 11 03:33:06 AM UTC 24 | Sep 11 03:33:59 AM UTC 24 | 24701885992 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3894491043 | Sep 11 03:33:46 AM UTC 24 | Sep 11 03:34:00 AM UTC 24 | 174733360 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.4213869909 | Sep 11 03:33:23 AM UTC 24 | Sep 11 03:34:01 AM UTC 24 | 436668931 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.347449699 | Sep 11 03:33:47 AM UTC 24 | Sep 11 03:34:03 AM UTC 24 | 352389205 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3119454194 | Sep 11 03:33:50 AM UTC 24 | Sep 11 03:34:03 AM UTC 24 | 505904910 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1269585604 | Sep 11 03:31:48 AM UTC 24 | Sep 11 03:34:04 AM UTC 24 | 2660847763 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.989147752 | Sep 11 03:29:44 AM UTC 24 | Sep 11 03:34:05 AM UTC 24 | 30007627641 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.693412939 | Sep 11 03:33:42 AM UTC 24 | Sep 11 03:34:05 AM UTC 24 | 293996736 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3548669275 | Sep 11 03:33:37 AM UTC 24 | Sep 11 03:34:07 AM UTC 24 | 4948527372 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2781319528 | Sep 11 03:33:51 AM UTC 24 | Sep 11 03:34:07 AM UTC 24 | 1026737202 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1207551181 | Sep 11 03:33:58 AM UTC 24 | Sep 11 03:34:07 AM UTC 24 | 689468544 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2137315471 | Sep 11 03:31:41 AM UTC 24 | Sep 11 03:34:10 AM UTC 24 | 2170072370 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1744753244 | Sep 11 03:33:59 AM UTC 24 | Sep 11 03:34:12 AM UTC 24 | 194355156 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3645714935 | Sep 11 03:33:45 AM UTC 24 | Sep 11 03:34:15 AM UTC 24 | 512777075 ps |
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