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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 96.89 91.99 97.68 100.00 98.28 98.05 98.83


Total test records in report: 458
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T307 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3432241436 Sep 11 03:33:33 AM UTC 24 Sep 11 03:34:15 AM UTC 24 806835531 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2021187768 Sep 11 03:30:53 AM UTC 24 Sep 11 03:34:17 AM UTC 24 2737888144 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1867490903 Sep 11 03:34:00 AM UTC 24 Sep 11 03:34:18 AM UTC 24 273676744 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.183668663 Sep 11 03:34:05 AM UTC 24 Sep 11 03:34:19 AM UTC 24 731918650 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1535237133 Sep 11 03:34:04 AM UTC 24 Sep 11 03:34:19 AM UTC 24 881228815 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.2564450786 Sep 11 03:34:08 AM UTC 24 Sep 11 03:34:20 AM UTC 24 347094409 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3610124998 Sep 11 03:33:48 AM UTC 24 Sep 11 03:34:25 AM UTC 24 513620615 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2843752949 Sep 11 03:33:54 AM UTC 24 Sep 11 03:34:28 AM UTC 24 332421830 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.1013882263 Sep 11 03:34:02 AM UTC 24 Sep 11 03:34:28 AM UTC 24 1374570442 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1638374778 Sep 11 03:30:04 AM UTC 24 Sep 11 03:34:29 AM UTC 24 3795089391 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.952648391 Sep 11 03:34:13 AM UTC 24 Sep 11 03:34:30 AM UTC 24 1365279849 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1806808303 Sep 11 03:33:49 AM UTC 24 Sep 11 03:34:34 AM UTC 24 15065845714 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1703551452 Sep 11 03:33:47 AM UTC 24 Sep 11 03:34:34 AM UTC 24 529660708 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2131445395 Sep 11 03:28:39 AM UTC 24 Sep 11 03:34:34 AM UTC 24 25928177006 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1215339901 Sep 11 03:34:19 AM UTC 24 Sep 11 03:34:34 AM UTC 24 257943553 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4109220024 Sep 11 03:32:39 AM UTC 24 Sep 11 03:34:35 AM UTC 24 6195710212 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.951299049 Sep 11 03:32:31 AM UTC 24 Sep 11 03:34:35 AM UTC 24 13762266393 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1218316243 Sep 11 03:29:57 AM UTC 24 Sep 11 03:34:36 AM UTC 24 8070549803 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1538923776 Sep 11 03:34:07 AM UTC 24 Sep 11 03:34:37 AM UTC 24 991550166 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3172345266 Sep 11 03:33:50 AM UTC 24 Sep 11 03:34:40 AM UTC 24 1653049198 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3577904139 Sep 11 03:34:05 AM UTC 24 Sep 11 03:34:40 AM UTC 24 354565977 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.4029588175 Sep 11 03:34:11 AM UTC 24 Sep 11 03:34:41 AM UTC 24 1195930077 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1716504022 Sep 11 03:30:42 AM UTC 24 Sep 11 03:34:43 AM UTC 24 4726130257 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1762747197 Sep 11 03:34:16 AM UTC 24 Sep 11 03:34:48 AM UTC 24 2059964649 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.240950823 Sep 11 03:33:01 AM UTC 24 Sep 11 03:34:53 AM UTC 24 1946248463 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1828765306 Sep 11 03:30:16 AM UTC 24 Sep 11 03:34:56 AM UTC 24 19059300528 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2607569695 Sep 11 03:31:36 AM UTC 24 Sep 11 03:34:57 AM UTC 24 12760606172 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.677755378 Sep 11 03:32:49 AM UTC 24 Sep 11 03:35:08 AM UTC 24 14241329999 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3979710626 Sep 11 03:31:19 AM UTC 24 Sep 11 03:35:33 AM UTC 24 6702031913 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2027635643 Sep 11 03:33:45 AM UTC 24 Sep 11 03:35:37 AM UTC 24 13306676779 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.372040996 Sep 11 03:31:54 AM UTC 24 Sep 11 03:35:42 AM UTC 24 3511154693 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2131545709 Sep 11 03:32:51 AM UTC 24 Sep 11 03:35:43 AM UTC 24 2361906811 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1925796737 Sep 11 03:33:17 AM UTC 24 Sep 11 03:35:45 AM UTC 24 34536749323 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3162135330 Sep 11 03:32:38 AM UTC 24 Sep 11 03:36:00 AM UTC 24 2752482037 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.223963701 Sep 11 03:31:03 AM UTC 24 Sep 11 03:36:01 AM UTC 24 15432495459 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1813972189 Sep 11 03:33:23 AM UTC 24 Sep 11 03:36:03 AM UTC 24 8789544662 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2505344681 Sep 11 03:32:05 AM UTC 24 Sep 11 03:36:15 AM UTC 24 45709484778 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.4240222792 Sep 11 03:32:10 AM UTC 24 Sep 11 03:36:19 AM UTC 24 4471227432 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2629186727 Sep 11 03:31:26 AM UTC 24 Sep 11 03:36:21 AM UTC 24 4839823922 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3221784813 Sep 11 03:34:18 AM UTC 24 Sep 11 03:36:33 AM UTC 24 14701820707 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1176087932 Sep 11 03:33:19 AM UTC 24 Sep 11 03:36:35 AM UTC 24 22605399154 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.279740861 Sep 11 03:33:37 AM UTC 24 Sep 11 03:36:35 AM UTC 24 16818103768 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.89631919 Sep 11 03:29:29 AM UTC 24 Sep 11 03:36:38 AM UTC 24 25286290094 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.326269370 Sep 11 03:31:58 AM UTC 24 Sep 11 03:36:43 AM UTC 24 79352268197 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1159427578 Sep 11 03:33:36 AM UTC 24 Sep 11 03:36:45 AM UTC 24 3786519609 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2335190629 Sep 11 03:32:47 AM UTC 24 Sep 11 03:36:57 AM UTC 24 6348762423 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3483888012 Sep 11 03:34:16 AM UTC 24 Sep 11 03:37:00 AM UTC 24 4870081847 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.435175187 Sep 11 03:32:18 AM UTC 24 Sep 11 03:37:02 AM UTC 24 19526657082 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2599082720 Sep 11 03:34:08 AM UTC 24 Sep 11 03:37:03 AM UTC 24 3167385687 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3784139510 Sep 11 03:32:29 AM UTC 24 Sep 11 03:37:07 AM UTC 24 3734124685 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1164970548 Sep 11 03:34:04 AM UTC 24 Sep 11 03:37:10 AM UTC 24 10081470827 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2870093807 Sep 11 03:33:58 AM UTC 24 Sep 11 03:37:21 AM UTC 24 12915438416 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.865295828 Sep 11 03:33:15 AM UTC 24 Sep 11 03:37:34 AM UTC 24 9374013568 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1480038764 Sep 11 03:33:44 AM UTC 24 Sep 11 03:37:45 AM UTC 24 14859193128 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1457672961 Sep 11 03:33:30 AM UTC 24 Sep 11 03:37:57 AM UTC 24 8159398016 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.223779873 Sep 11 03:32:59 AM UTC 24 Sep 11 03:37:58 AM UTC 24 4336013410 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3809593440 Sep 11 03:33:48 AM UTC 24 Sep 11 03:38:17 AM UTC 24 8013596206 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.815331361 Sep 11 03:31:28 AM UTC 24 Sep 11 03:38:19 AM UTC 24 4627985051 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2537055548 Sep 11 03:33:53 AM UTC 24 Sep 11 03:38:43 AM UTC 24 70757672989 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3623286566 Sep 11 03:33:22 AM UTC 24 Sep 11 03:39:06 AM UTC 24 37231286846 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3700862640 Sep 11 03:34:06 AM UTC 24 Sep 11 03:39:26 AM UTC 24 5588862376 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3527592655 Sep 11 03:33:04 AM UTC 24 Sep 11 03:40:21 AM UTC 24 17542189204 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2233595435 Sep 11 03:34:01 AM UTC 24 Sep 11 03:41:07 AM UTC 24 92643066113 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3932715148 Sep 11 03:34:20 AM UTC 24 Sep 11 03:34:41 AM UTC 24 1884966302 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1316186079 Sep 11 03:35:38 AM UTC 24 Sep 11 03:35:55 AM UTC 24 250017680 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2381743307 Sep 11 03:34:29 AM UTC 24 Sep 11 03:34:42 AM UTC 24 662015093 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3637875097 Sep 11 03:34:25 AM UTC 24 Sep 11 03:34:42 AM UTC 24 3647456399 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2111446044 Sep 11 03:34:30 AM UTC 24 Sep 11 03:34:42 AM UTC 24 176175116 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4101476462 Sep 11 03:34:31 AM UTC 24 Sep 11 03:34:44 AM UTC 24 4936995054 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3083838830 Sep 11 03:34:29 AM UTC 24 Sep 11 03:34:46 AM UTC 24 169930549 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.407748792 Sep 11 03:34:34 AM UTC 24 Sep 11 03:34:46 AM UTC 24 1026457171 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1512284887 Sep 11 03:34:35 AM UTC 24 Sep 11 03:34:47 AM UTC 24 188825068 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.198273831 Sep 11 03:34:37 AM UTC 24 Sep 11 03:34:48 AM UTC 24 287121666 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3842272506 Sep 11 03:34:38 AM UTC 24 Sep 11 03:34:50 AM UTC 24 506386732 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.168246720 Sep 11 03:34:34 AM UTC 24 Sep 11 03:34:50 AM UTC 24 285527248 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4113418521 Sep 11 03:34:41 AM UTC 24 Sep 11 03:34:52 AM UTC 24 720793972 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1093381468 Sep 11 03:34:42 AM UTC 24 Sep 11 03:34:52 AM UTC 24 487961964 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3849697667 Sep 11 03:34:40 AM UTC 24 Sep 11 03:34:55 AM UTC 24 381053997 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1546500619 Sep 11 03:34:43 AM UTC 24 Sep 11 03:34:56 AM UTC 24 180562620 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1856169814 Sep 11 03:34:42 AM UTC 24 Sep 11 03:34:56 AM UTC 24 662565352 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.685889865 Sep 11 03:34:36 AM UTC 24 Sep 11 03:34:56 AM UTC 24 1031506763 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2516407481 Sep 11 03:34:42 AM UTC 24 Sep 11 03:34:58 AM UTC 24 1033371502 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2544407853 Sep 11 03:34:48 AM UTC 24 Sep 11 03:35:00 AM UTC 24 168257963 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1215371757 Sep 11 03:34:43 AM UTC 24 Sep 11 03:35:01 AM UTC 24 320119257 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2387896815 Sep 11 03:34:46 AM UTC 24 Sep 11 03:35:02 AM UTC 24 528432474 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3012645681 Sep 11 03:34:52 AM UTC 24 Sep 11 03:35:02 AM UTC 24 173925777 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.405038651 Sep 11 03:34:49 AM UTC 24 Sep 11 03:35:02 AM UTC 24 2750149785 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3810291595 Sep 11 03:34:49 AM UTC 24 Sep 11 03:35:04 AM UTC 24 1551337321 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3487718913 Sep 11 03:34:48 AM UTC 24 Sep 11 03:35:06 AM UTC 24 341261116 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4196725360 Sep 11 03:34:51 AM UTC 24 Sep 11 03:35:06 AM UTC 24 260363995 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.404095298 Sep 11 03:34:51 AM UTC 24 Sep 11 03:35:07 AM UTC 24 184742023 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3595538934 Sep 11 03:34:57 AM UTC 24 Sep 11 03:35:08 AM UTC 24 1106906171 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2944216529 Sep 11 03:34:54 AM UTC 24 Sep 11 03:35:12 AM UTC 24 174583165 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2429690187 Sep 11 03:34:56 AM UTC 24 Sep 11 03:35:12 AM UTC 24 260851703 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.815352019 Sep 11 03:34:58 AM UTC 24 Sep 11 03:35:13 AM UTC 24 991928708 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1615373837 Sep 11 03:34:59 AM UTC 24 Sep 11 03:35:14 AM UTC 24 257582959 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4263604523 Sep 11 03:35:01 AM UTC 24 Sep 11 03:35:14 AM UTC 24 415690936 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.786836926 Sep 11 03:35:02 AM UTC 24 Sep 11 03:35:14 AM UTC 24 1874761847 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2808006589 Sep 11 03:35:05 AM UTC 24 Sep 11 03:35:16 AM UTC 24 516511617 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4282066770 Sep 11 03:35:08 AM UTC 24 Sep 11 03:35:19 AM UTC 24 638045540 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3339509995 Sep 11 03:34:57 AM UTC 24 Sep 11 03:35:20 AM UTC 24 1862640520 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.883867104 Sep 11 03:34:56 AM UTC 24 Sep 11 03:35:20 AM UTC 24 1023977083 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.882804642 Sep 11 03:34:36 AM UTC 24 Sep 11 03:35:20 AM UTC 24 4065821645 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1610218378 Sep 11 03:35:03 AM UTC 24 Sep 11 03:35:20 AM UTC 24 1030373241 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3230894915 Sep 11 03:35:07 AM UTC 24 Sep 11 03:35:20 AM UTC 24 1268758289 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2878433092 Sep 11 03:34:43 AM UTC 24 Sep 11 03:35:22 AM UTC 24 899772907 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3681411656 Sep 11 03:35:12 AM UTC 24 Sep 11 03:35:23 AM UTC 24 196362809 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.74352114 Sep 11 03:35:08 AM UTC 24 Sep 11 03:35:25 AM UTC 24 1014771289 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2688628564 Sep 11 03:35:09 AM UTC 24 Sep 11 03:35:25 AM UTC 24 1892637228 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.166980576 Sep 11 03:35:12 AM UTC 24 Sep 11 03:35:27 AM UTC 24 1337737745 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2264851311 Sep 11 03:35:16 AM UTC 24 Sep 11 03:35:28 AM UTC 24 282005487 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.987866541 Sep 11 03:35:20 AM UTC 24 Sep 11 03:35:29 AM UTC 24 2836089645 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3185119544 Sep 11 03:35:17 AM UTC 24 Sep 11 03:35:30 AM UTC 24 660284244 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3985007880 Sep 11 03:35:21 AM UTC 24 Sep 11 03:35:31 AM UTC 24 503148735 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.357902737 Sep 11 03:35:15 AM UTC 24 Sep 11 03:35:33 AM UTC 24 825783565 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1248334746 Sep 11 03:35:07 AM UTC 24 Sep 11 03:35:33 AM UTC 24 262513606 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2466105258 Sep 11 03:35:23 AM UTC 24 Sep 11 03:35:36 AM UTC 24 182847076 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4225750649 Sep 11 03:35:21 AM UTC 24 Sep 11 03:35:36 AM UTC 24 989880027 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3915048433 Sep 11 03:35:28 AM UTC 24 Sep 11 03:35:42 AM UTC 24 172573523 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3882273592 Sep 11 03:35:29 AM UTC 24 Sep 11 03:35:43 AM UTC 24 169397630 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1308260686 Sep 11 03:35:25 AM UTC 24 Sep 11 03:35:44 AM UTC 24 355742702 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3303316441 Sep 11 03:35:31 AM UTC 24 Sep 11 03:35:44 AM UTC 24 638572811 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3868989084 Sep 11 03:35:34 AM UTC 24 Sep 11 03:35:44 AM UTC 24 496432759 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1292830903 Sep 11 03:35:21 AM UTC 24 Sep 11 03:35:44 AM UTC 24 2136947655 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1689926235 Sep 11 03:34:20 AM UTC 24 Sep 11 03:35:45 AM UTC 24 1644159694 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3413010232 Sep 11 03:35:34 AM UTC 24 Sep 11 03:35:46 AM UTC 24 169165912 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2843050480 Sep 11 03:35:32 AM UTC 24 Sep 11 03:35:49 AM UTC 24 332412301 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.690074412 Sep 11 03:34:21 AM UTC 24 Sep 11 03:35:53 AM UTC 24 482945769 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3899015456 Sep 11 03:35:37 AM UTC 24 Sep 11 03:35:54 AM UTC 24 1520029758 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2520924971 Sep 11 03:35:42 AM UTC 24 Sep 11 03:35:55 AM UTC 24 513820980 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2858836280 Sep 11 03:35:13 AM UTC 24 Sep 11 03:35:57 AM UTC 24 4257626787 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4275860411 Sep 11 03:35:44 AM UTC 24 Sep 11 03:35:57 AM UTC 24 172077667 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3573904668 Sep 11 03:35:46 AM UTC 24 Sep 11 03:35:57 AM UTC 24 1195397045 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2307591478 Sep 11 03:34:37 AM UTC 24 Sep 11 03:35:58 AM UTC 24 1001042093 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2236697538 Sep 11 03:35:46 AM UTC 24 Sep 11 03:36:00 AM UTC 24 345870440 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.540529176 Sep 11 03:35:43 AM UTC 24 Sep 11 03:36:02 AM UTC 24 375172090 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1644029659 Sep 11 03:35:46 AM UTC 24 Sep 11 03:36:03 AM UTC 24 8230594514 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.566040908 Sep 11 03:35:46 AM UTC 24 Sep 11 03:36:05 AM UTC 24 339482661 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1431844870 Sep 11 03:35:21 AM UTC 24 Sep 11 03:36:05 AM UTC 24 3381444245 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3724007046 Sep 11 03:35:47 AM UTC 24 Sep 11 03:36:08 AM UTC 24 254941778 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2306101418 Sep 11 03:34:53 AM UTC 24 Sep 11 03:36:07 AM UTC 24 1526105577 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3020639156 Sep 11 03:35:55 AM UTC 24 Sep 11 03:36:08 AM UTC 24 273650032 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3827729958 Sep 11 03:35:58 AM UTC 24 Sep 11 03:36:08 AM UTC 24 260062971 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3314503478 Sep 11 03:35:53 AM UTC 24 Sep 11 03:36:08 AM UTC 24 255221009 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4103613528 Sep 11 03:35:56 AM UTC 24 Sep 11 03:36:09 AM UTC 24 985471526 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1455262542 Sep 11 03:36:00 AM UTC 24 Sep 11 03:36:14 AM UTC 24 719809402 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.715369641 Sep 11 03:36:03 AM UTC 24 Sep 11 03:36:14 AM UTC 24 195537732 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3535290584 Sep 11 03:35:59 AM UTC 24 Sep 11 03:36:15 AM UTC 24 251505439 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.376310245 Sep 11 03:35:03 AM UTC 24 Sep 11 03:36:16 AM UTC 24 1528542899 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3938822977 Sep 11 03:35:32 AM UTC 24 Sep 11 03:36:16 AM UTC 24 690560049 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1442417755 Sep 11 03:35:58 AM UTC 24 Sep 11 03:36:17 AM UTC 24 255945691 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2285887190 Sep 11 03:36:05 AM UTC 24 Sep 11 03:36:17 AM UTC 24 168588885 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.916562707 Sep 11 03:36:09 AM UTC 24 Sep 11 03:36:20 AM UTC 24 535440687 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4037971276 Sep 11 03:36:09 AM UTC 24 Sep 11 03:36:21 AM UTC 24 524125443 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3465686594 Sep 11 03:34:56 AM UTC 24 Sep 11 03:36:21 AM UTC 24 916386693 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2767524648 Sep 11 03:36:02 AM UTC 24 Sep 11 03:36:22 AM UTC 24 251934516 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3696470866 Sep 11 03:36:06 AM UTC 24 Sep 11 03:36:22 AM UTC 24 528341577 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.531052709 Sep 11 03:36:09 AM UTC 24 Sep 11 03:36:22 AM UTC 24 346935453 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.22077493 Sep 11 03:36:08 AM UTC 24 Sep 11 03:36:24 AM UTC 24 662073376 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.344778235 Sep 11 03:36:16 AM UTC 24 Sep 11 03:36:26 AM UTC 24 688350742 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1509160052 Sep 11 03:35:24 AM UTC 24 Sep 11 03:36:28 AM UTC 24 1522973666 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3607251235 Sep 11 03:36:21 AM UTC 24 Sep 11 03:36:30 AM UTC 24 176446636 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.754249883 Sep 11 03:36:17 AM UTC 24 Sep 11 03:36:30 AM UTC 24 173780181 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3942064433 Sep 11 03:36:20 AM UTC 24 Sep 11 03:36:30 AM UTC 24 260419079 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2952512408 Sep 11 03:36:15 AM UTC 24 Sep 11 03:36:30 AM UTC 24 527807872 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1894649613 Sep 11 03:36:16 AM UTC 24 Sep 11 03:36:31 AM UTC 24 1543589283 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1116538331 Sep 11 03:36:18 AM UTC 24 Sep 11 03:36:32 AM UTC 24 172679784 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3698378757 Sep 11 03:36:23 AM UTC 24 Sep 11 03:36:33 AM UTC 24 869392838 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2137434433 Sep 11 03:36:23 AM UTC 24 Sep 11 03:36:34 AM UTC 24 1497138829 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4091928742 Sep 11 03:36:22 AM UTC 24 Sep 11 03:36:36 AM UTC 24 677618532 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1003097344 Sep 11 03:36:24 AM UTC 24 Sep 11 03:36:37 AM UTC 24 1234597494 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.499078256 Sep 11 03:36:22 AM UTC 24 Sep 11 03:36:40 AM UTC 24 249418179 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2117410370 Sep 11 03:36:32 AM UTC 24 Sep 11 03:36:42 AM UTC 24 868267192 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3493929071 Sep 11 03:35:37 AM UTC 24 Sep 11 03:36:42 AM UTC 24 6093817525 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4065319575 Sep 11 03:36:31 AM UTC 24 Sep 11 03:36:43 AM UTC 24 1303552292 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3587477756 Sep 11 03:35:56 AM UTC 24 Sep 11 03:36:44 AM UTC 24 1068095449 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1431291652 Sep 11 03:36:32 AM UTC 24 Sep 11 03:36:44 AM UTC 24 1037685085 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2875389236 Sep 11 03:36:29 AM UTC 24 Sep 11 03:36:44 AM UTC 24 262411724 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3569332863 Sep 11 03:36:33 AM UTC 24 Sep 11 03:36:48 AM UTC 24 189097273 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1003411110 Sep 11 03:36:34 AM UTC 24 Sep 11 03:36:50 AM UTC 24 262005307 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3505057427 Sep 11 03:36:34 AM UTC 24 Sep 11 03:36:50 AM UTC 24 256113951 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.251177515 Sep 11 03:36:35 AM UTC 24 Sep 11 03:36:53 AM UTC 24 4136206215 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1891912421 Sep 11 03:35:03 AM UTC 24 Sep 11 03:36:53 AM UTC 24 1117688451 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.922462240 Sep 11 03:36:06 AM UTC 24 Sep 11 03:37:01 AM UTC 24 4424455143 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2576732099 Sep 11 03:35:44 AM UTC 24 Sep 11 03:37:02 AM UTC 24 6363992877 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1774540156 Sep 11 03:36:01 AM UTC 24 Sep 11 03:37:02 AM UTC 24 3958497724 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.10089562 Sep 11 03:36:17 AM UTC 24 Sep 11 03:37:09 AM UTC 24 4060318982 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2967299028 Sep 11 03:35:47 AM UTC 24 Sep 11 03:37:10 AM UTC 24 2999658078 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3395642206 Sep 11 03:35:34 AM UTC 24 Sep 11 03:37:11 AM UTC 24 1190476192 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2666635991 Sep 11 03:36:10 AM UTC 24 Sep 11 03:37:13 AM UTC 24 3097374576 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.78165858 Sep 11 03:35:42 AM UTC 24 Sep 11 03:37:14 AM UTC 24 6324561278 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.31749673 Sep 11 03:36:27 AM UTC 24 Sep 11 03:37:16 AM UTC 24 1723102752 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3821791233 Sep 11 03:36:32 AM UTC 24 Sep 11 03:37:18 AM UTC 24 2118973313 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2521571682 Sep 11 03:36:22 AM UTC 24 Sep 11 03:37:21 AM UTC 24 4651904400 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3489932452 Sep 11 03:35:58 AM UTC 24 Sep 11 03:37:22 AM UTC 24 324646104 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2171085689 Sep 11 03:36:09 AM UTC 24 Sep 11 03:37:30 AM UTC 24 478359610 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1731393404 Sep 11 03:34:44 AM UTC 24 Sep 11 03:37:35 AM UTC 24 448047017 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3021161979 Sep 11 03:36:03 AM UTC 24 Sep 11 03:37:36 AM UTC 24 332535990 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4248727799 Sep 11 03:36:15 AM UTC 24 Sep 11 03:37:46 AM UTC 24 908714138 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1328430088 Sep 11 03:36:23 AM UTC 24 Sep 11 03:37:50 AM UTC 24 6313937092 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2263168849 Sep 11 03:36:18 AM UTC 24 Sep 11 03:37:51 AM UTC 24 1079299736 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.798562300 Sep 11 03:36:33 AM UTC 24 Sep 11 03:37:55 AM UTC 24 456508150 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3367593386 Sep 11 03:35:15 AM UTC 24 Sep 11 03:38:03 AM UTC 24 424747737 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4017137482 Sep 11 03:35:21 AM UTC 24 Sep 11 03:38:09 AM UTC 24 791445601 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1891958704 Sep 11 03:35:25 AM UTC 24 Sep 11 03:38:22 AM UTC 24 2065547175 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1163830584 Sep 11 03:35:46 AM UTC 24 Sep 11 03:38:22 AM UTC 24 542572153 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1998319524 Sep 11 03:35:50 AM UTC 24 Sep 11 03:38:45 AM UTC 24 791605530 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3445519256 Sep 11 03:36:31 AM UTC 24 Sep 11 03:38:59 AM UTC 24 551617704 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.736806721
Short name T9
Test name
Test status
Simulation time 544920205 ps
CPU time 11.63 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:28:57 AM UTC 24
Peak memory 225540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736806721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64k
B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.736806721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1521191699
Short name T15
Test name
Test status
Simulation time 9770794828 ps
CPU time 58.24 seconds
Started Sep 11 03:28:43 AM UTC 24
Finished Sep 11 03:29:43 AM UTC 24
Peak memory 246352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1521191699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1521191699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1791448296
Short name T29
Test name
Test status
Simulation time 1375528633 ps
CPU time 24.97 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:29:10 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791448296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1791448296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.638386924
Short name T23
Test name
Test status
Simulation time 11701439187 ps
CPU time 224.5 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:32:32 AM UTC 24
Peak memory 246188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638386924 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.638386924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3981158036
Short name T33
Test name
Test status
Simulation time 2757108905 ps
CPU time 24.61 seconds
Started Sep 11 03:29:10 AM UTC 24
Finished Sep 11 03:29:36 AM UTC 24
Peak memory 228300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981158036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3981158036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1403067082
Short name T10
Test name
Test status
Simulation time 258740398 ps
CPU time 12.7 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:28:58 AM UTC 24
Peak memory 228144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403067082 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1403067082
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2654125393
Short name T61
Test name
Test status
Simulation time 7650920716 ps
CPU time 18.8 seconds
Started Sep 11 03:28:53 AM UTC 24
Finished Sep 11 03:29:13 AM UTC 24
Peak memory 225588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654125393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2654125393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.690074412
Short name T75
Test name
Test status
Simulation time 482945769 ps
CPU time 89.79 seconds
Started Sep 11 03:34:21 AM UTC 24
Finished Sep 11 03:35:53 AM UTC 24
Peak memory 223856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690074412 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.690074412
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.518292454
Short name T14
Test name
Test status
Simulation time 2923698752 ps
CPU time 58.37 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:29:38 AM UTC 24
Peak memory 239388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=518292454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.rom_ctrl_stress_all_with_rand_reset.518292454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2562659378
Short name T32
Test name
Test status
Simulation time 2016164215 ps
CPU time 37.17 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:29:22 AM UTC 24
Peak memory 227624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256265937
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.2562659378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1992047198
Short name T35
Test name
Test status
Simulation time 1417348876 ps
CPU time 257.43 seconds
Started Sep 11 03:28:43 AM UTC 24
Finished Sep 11 03:33:05 AM UTC 24
Peak memory 258444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992047198 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1992047198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3143620883
Short name T64
Test name
Test status
Simulation time 2041839676 ps
CPU time 53.14 seconds
Started Sep 11 03:29:11 AM UTC 24
Finished Sep 11 03:30:06 AM UTC 24
Peak memory 245152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3143620883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3143620883
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.4087065002
Short name T17
Test name
Test status
Simulation time 538932522 ps
CPU time 14.54 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:29:00 AM UTC 24
Peak memory 228388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087065002 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4087065002
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1731393404
Short name T133
Test name
Test status
Simulation time 448047017 ps
CPU time 168.21 seconds
Started Sep 11 03:34:44 AM UTC 24
Finished Sep 11 03:37:35 AM UTC 24
Peak memory 226104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731393404 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.1731393404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.168246720
Short name T86
Test name
Test status
Simulation time 285527248 ps
CPU time 14.42 seconds
Started Sep 11 03:34:34 AM UTC 24
Finished Sep 11 03:34:50 AM UTC 24
Peak memory 221748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168246720 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.168246720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4017137482
Short name T136
Test name
Test status
Simulation time 791445601 ps
CPU time 164.95 seconds
Started Sep 11 03:35:21 AM UTC 24
Finished Sep 11 03:38:09 AM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017137482 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.4017137482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3334799693
Short name T12
Test name
Test status
Simulation time 507856831 ps
CPU time 22.87 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:29:02 AM UTC 24
Peak memory 228276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334799693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3334799693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2867711528
Short name T47
Test name
Test status
Simulation time 16518762872 ps
CPU time 236.24 seconds
Started Sep 11 03:28:48 AM UTC 24
Finished Sep 11 03:32:47 AM UTC 24
Peak memory 259612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867711528 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.2867711528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2858836280
Short name T145
Test name
Test status
Simulation time 4257626787 ps
CPU time 41.86 seconds
Started Sep 11 03:35:13 AM UTC 24
Finished Sep 11 03:35:57 AM UTC 24
Peak memory 226124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858836280 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.2858836280
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2016725063
Short name T73
Test name
Test status
Simulation time 548586599 ps
CPU time 36.97 seconds
Started Sep 11 03:29:09 AM UTC 24
Finished Sep 11 03:29:47 AM UTC 24
Peak memory 228704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201672506
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.2016725063
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4248727799
Short name T140
Test name
Test status
Simulation time 908714138 ps
CPU time 88.74 seconds
Started Sep 11 03:36:15 AM UTC 24
Finished Sep 11 03:37:46 AM UTC 24
Peak memory 223860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248727799 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.4248727799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1125536892
Short name T11
Test name
Test status
Simulation time 524601574 ps
CPU time 22.12 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:29:01 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112553689
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.1125536892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3083838830
Short name T82
Test name
Test status
Simulation time 169930549 ps
CPU time 15.46 seconds
Started Sep 11 03:34:29 AM UTC 24
Finished Sep 11 03:34:46 AM UTC 24
Peak memory 221928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083838830 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.3083838830
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.407748792
Short name T118
Test name
Test status
Simulation time 1026457171 ps
CPU time 10.87 seconds
Started Sep 11 03:34:34 AM UTC 24
Finished Sep 11 03:34:46 AM UTC 24
Peak memory 221668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407748792 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.407748792
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2396374150
Short name T109
Test name
Test status
Simulation time 1073969047 ps
CPU time 45.74 seconds
Started Sep 11 03:31:00 AM UTC 24
Finished Sep 11 03:31:47 AM UTC 24
Peak memory 228840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239637415
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.2396374150
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2214960070
Short name T27
Test name
Test status
Simulation time 661770480 ps
CPU time 23.23 seconds
Started Sep 11 03:28:43 AM UTC 24
Finished Sep 11 03:29:08 AM UTC 24
Peak memory 228636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214960070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2214960070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2294266344
Short name T30
Test name
Test status
Simulation time 721369179 ps
CPU time 36.41 seconds
Started Sep 11 03:28:39 AM UTC 24
Finished Sep 11 03:29:17 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229426634
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.2294266344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4101476462
Short name T81
Test name
Test status
Simulation time 4936995054 ps
CPU time 10.95 seconds
Started Sep 11 03:34:31 AM UTC 24
Finished Sep 11 03:34:44 AM UTC 24
Peak memory 221864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101476462 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.4101476462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1512284887
Short name T371
Test name
Test status
Simulation time 188825068 ps
CPU time 11.13 seconds
Started Sep 11 03:34:35 AM UTC 24
Finished Sep 11 03:34:47 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1512284887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
om_ctrl_csr_mem_rw_with_rand_reset.1512284887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2111446044
Short name T80
Test name
Test status
Simulation time 176175116 ps
CPU time 11.01 seconds
Started Sep 11 03:34:30 AM UTC 24
Finished Sep 11 03:34:42 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111446044 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2111446044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2381743307
Short name T369
Test name
Test status
Simulation time 662015093 ps
CPU time 11.24 seconds
Started Sep 11 03:34:29 AM UTC 24
Finished Sep 11 03:34:42 AM UTC 24
Peak memory 221624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381743307 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.2381743307
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3637875097
Short name T370
Test name
Test status
Simulation time 3647456399 ps
CPU time 16.06 seconds
Started Sep 11 03:34:25 AM UTC 24
Finished Sep 11 03:34:42 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637875097 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.3637875097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1689926235
Short name T94
Test name
Test status
Simulation time 1644159694 ps
CPU time 82.79 seconds
Started Sep 11 03:34:20 AM UTC 24
Finished Sep 11 03:35:45 AM UTC 24
Peak memory 225932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689926235 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.1689926235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3932715148
Short name T367
Test name
Test status
Simulation time 1884966302 ps
CPU time 20.07 seconds
Started Sep 11 03:34:20 AM UTC 24
Finished Sep 11 03:34:41 AM UTC 24
Peak memory 228048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932715148 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3932715148
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1093381468
Short name T88
Test name
Test status
Simulation time 487961964 ps
CPU time 9.17 seconds
Started Sep 11 03:34:42 AM UTC 24
Finished Sep 11 03:34:52 AM UTC 24
Peak memory 221800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093381468 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.1093381468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1856169814
Short name T375
Test name
Test status
Simulation time 662565352 ps
CPU time 12.63 seconds
Started Sep 11 03:34:42 AM UTC 24
Finished Sep 11 03:34:56 AM UTC 24
Peak memory 221800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856169814 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.1856169814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3849697667
Short name T126
Test name
Test status
Simulation time 381053997 ps
CPU time 13.88 seconds
Started Sep 11 03:34:40 AM UTC 24
Finished Sep 11 03:34:55 AM UTC 24
Peak memory 221800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849697667 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.3849697667
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1546500619
Short name T374
Test name
Test status
Simulation time 180562620 ps
CPU time 11.19 seconds
Started Sep 11 03:34:43 AM UTC 24
Finished Sep 11 03:34:56 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1546500619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
om_ctrl_csr_mem_rw_with_rand_reset.1546500619
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4113418521
Short name T87
Test name
Test status
Simulation time 720793972 ps
CPU time 9.47 seconds
Started Sep 11 03:34:41 AM UTC 24
Finished Sep 11 03:34:52 AM UTC 24
Peak memory 221740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113418521 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4113418521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3842272506
Short name T373
Test name
Test status
Simulation time 506386732 ps
CPU time 10.88 seconds
Started Sep 11 03:34:38 AM UTC 24
Finished Sep 11 03:34:50 AM UTC 24
Peak memory 221624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842272506 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.3842272506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.198273831
Short name T372
Test name
Test status
Simulation time 287121666 ps
CPU time 10.06 seconds
Started Sep 11 03:34:37 AM UTC 24
Finished Sep 11 03:34:48 AM UTC 24
Peak memory 221672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198273831 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.198273831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.882804642
Short name T391
Test name
Test status
Simulation time 4065821645 ps
CPU time 42.7 seconds
Started Sep 11 03:34:36 AM UTC 24
Finished Sep 11 03:35:20 AM UTC 24
Peak memory 226196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882804642 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.882804642
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2516407481
Short name T119
Test name
Test status
Simulation time 1033371502 ps
CPU time 14.49 seconds
Started Sep 11 03:34:42 AM UTC 24
Finished Sep 11 03:34:58 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516407481 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.2516407481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.685889865
Short name T376
Test name
Test status
Simulation time 1031506763 ps
CPU time 19.08 seconds
Started Sep 11 03:34:36 AM UTC 24
Finished Sep 11 03:34:56 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685889865 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.685889865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2307591478
Short name T76
Test name
Test status
Simulation time 1001042093 ps
CPU time 79.34 seconds
Started Sep 11 03:34:37 AM UTC 24
Finished Sep 11 03:35:58 AM UTC 24
Peak memory 223800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307591478 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.2307591478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3573904668
Short name T410
Test name
Test status
Simulation time 1195397045 ps
CPU time 9.69 seconds
Started Sep 11 03:35:46 AM UTC 24
Finished Sep 11 03:35:57 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3573904668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rom_ctrl_csr_mem_rw_with_rand_reset.3573904668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2236697538
Short name T411
Test name
Test status
Simulation time 345870440 ps
CPU time 12.78 seconds
Started Sep 11 03:35:46 AM UTC 24
Finished Sep 11 03:36:00 AM UTC 24
Peak memory 221740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236697538 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2236697538
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2576732099
Short name T100
Test name
Test status
Simulation time 6363992877 ps
CPU time 75.5 seconds
Started Sep 11 03:35:44 AM UTC 24
Finished Sep 11 03:37:02 AM UTC 24
Peak memory 226068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576732099 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.2576732099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1644029659
Short name T413
Test name
Test status
Simulation time 8230594514 ps
CPU time 15.43 seconds
Started Sep 11 03:35:46 AM UTC 24
Finished Sep 11 03:36:03 AM UTC 24
Peak memory 223916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644029659 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.1644029659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.566040908
Short name T414
Test name
Test status
Simulation time 339482661 ps
CPU time 17.11 seconds
Started Sep 11 03:35:46 AM UTC 24
Finished Sep 11 03:36:05 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566040908 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.566040908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1163830584
Short name T139
Test name
Test status
Simulation time 542572153 ps
CPU time 152.93 seconds
Started Sep 11 03:35:46 AM UTC 24
Finished Sep 11 03:38:22 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163830584 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.1163830584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4103613528
Short name T420
Test name
Test status
Simulation time 985471526 ps
CPU time 12.02 seconds
Started Sep 11 03:35:56 AM UTC 24
Finished Sep 11 03:36:09 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4103613528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rom_ctrl_csr_mem_rw_with_rand_reset.4103613528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3314503478
Short name T419
Test name
Test status
Simulation time 255221009 ps
CPU time 13.14 seconds
Started Sep 11 03:35:53 AM UTC 24
Finished Sep 11 03:36:08 AM UTC 24
Peak memory 221812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314503478 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3314503478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2967299028
Short name T102
Test name
Test status
Simulation time 2999658078 ps
CPU time 80.29 seconds
Started Sep 11 03:35:47 AM UTC 24
Finished Sep 11 03:37:10 AM UTC 24
Peak memory 226132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967299028 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.2967299028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3020639156
Short name T417
Test name
Test status
Simulation time 273650032 ps
CPU time 11.86 seconds
Started Sep 11 03:35:55 AM UTC 24
Finished Sep 11 03:36:08 AM UTC 24
Peak memory 221932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020639156 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.3020639156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3724007046
Short name T416
Test name
Test status
Simulation time 254941778 ps
CPU time 19.25 seconds
Started Sep 11 03:35:47 AM UTC 24
Finished Sep 11 03:36:08 AM UTC 24
Peak memory 228132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724007046 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3724007046
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1998319524
Short name T458
Test name
Test status
Simulation time 791605530 ps
CPU time 171.18 seconds
Started Sep 11 03:35:50 AM UTC 24
Finished Sep 11 03:38:45 AM UTC 24
Peak memory 229360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998319524 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.1998319524
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1455262542
Short name T421
Test name
Test status
Simulation time 719809402 ps
CPU time 12.68 seconds
Started Sep 11 03:36:00 AM UTC 24
Finished Sep 11 03:36:14 AM UTC 24
Peak memory 227948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1455262542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rom_ctrl_csr_mem_rw_with_rand_reset.1455262542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3827729958
Short name T418
Test name
Test status
Simulation time 260062971 ps
CPU time 9 seconds
Started Sep 11 03:35:58 AM UTC 24
Finished Sep 11 03:36:08 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827729958 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3827729958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3587477756
Short name T107
Test name
Test status
Simulation time 1068095449 ps
CPU time 46.62 seconds
Started Sep 11 03:35:56 AM UTC 24
Finished Sep 11 03:36:44 AM UTC 24
Peak memory 223824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587477756 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.3587477756
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3535290584
Short name T423
Test name
Test status
Simulation time 251505439 ps
CPU time 14.77 seconds
Started Sep 11 03:35:59 AM UTC 24
Finished Sep 11 03:36:15 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535290584 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.3535290584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1442417755
Short name T424
Test name
Test status
Simulation time 255945691 ps
CPU time 18.19 seconds
Started Sep 11 03:35:58 AM UTC 24
Finished Sep 11 03:36:17 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442417755 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1442417755
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3489932452
Short name T454
Test name
Test status
Simulation time 324646104 ps
CPU time 82.35 seconds
Started Sep 11 03:35:58 AM UTC 24
Finished Sep 11 03:37:22 AM UTC 24
Peak memory 223924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489932452 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.3489932452
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3696470866
Short name T429
Test name
Test status
Simulation time 528341577 ps
CPU time 15.64 seconds
Started Sep 11 03:36:06 AM UTC 24
Finished Sep 11 03:36:22 AM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3696470866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rom_ctrl_csr_mem_rw_with_rand_reset.3696470866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.715369641
Short name T422
Test name
Test status
Simulation time 195537732 ps
CPU time 9.59 seconds
Started Sep 11 03:36:03 AM UTC 24
Finished Sep 11 03:36:14 AM UTC 24
Peak memory 221868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715369641 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.715369641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1774540156
Short name T101
Test name
Test status
Simulation time 3958497724 ps
CPU time 58.87 seconds
Started Sep 11 03:36:01 AM UTC 24
Finished Sep 11 03:37:02 AM UTC 24
Peak memory 226000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774540156 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.1774540156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2285887190
Short name T425
Test name
Test status
Simulation time 168588885 ps
CPU time 11.64 seconds
Started Sep 11 03:36:05 AM UTC 24
Finished Sep 11 03:36:17 AM UTC 24
Peak memory 221932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285887190 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.2285887190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2767524648
Short name T428
Test name
Test status
Simulation time 251934516 ps
CPU time 18.65 seconds
Started Sep 11 03:36:02 AM UTC 24
Finished Sep 11 03:36:22 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767524648 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2767524648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3021161979
Short name T142
Test name
Test status
Simulation time 332535990 ps
CPU time 90.66 seconds
Started Sep 11 03:36:03 AM UTC 24
Finished Sep 11 03:37:36 AM UTC 24
Peak memory 223860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021161979 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.3021161979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4037971276
Short name T427
Test name
Test status
Simulation time 524125443 ps
CPU time 10.77 seconds
Started Sep 11 03:36:09 AM UTC 24
Finished Sep 11 03:36:21 AM UTC 24
Peak memory 228140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4037971276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rom_ctrl_csr_mem_rw_with_rand_reset.4037971276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.531052709
Short name T98
Test name
Test status
Simulation time 346935453 ps
CPU time 12.41 seconds
Started Sep 11 03:36:09 AM UTC 24
Finished Sep 11 03:36:22 AM UTC 24
Peak memory 221932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531052709 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.531052709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.922462240
Short name T108
Test name
Test status
Simulation time 4424455143 ps
CPU time 53.84 seconds
Started Sep 11 03:36:06 AM UTC 24
Finished Sep 11 03:37:01 AM UTC 24
Peak memory 223884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922462240 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.922462240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.916562707
Short name T426
Test name
Test status
Simulation time 535440687 ps
CPU time 9.57 seconds
Started Sep 11 03:36:09 AM UTC 24
Finished Sep 11 03:36:20 AM UTC 24
Peak memory 222004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916562707 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.916562707
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.22077493
Short name T430
Test name
Test status
Simulation time 662073376 ps
CPU time 14.99 seconds
Started Sep 11 03:36:08 AM UTC 24
Finished Sep 11 03:36:24 AM UTC 24
Peak memory 227988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22077493 -assert nopostproc +UVM_TESTNAME=rom
_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.22077493
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2171085689
Short name T132
Test name
Test status
Simulation time 478359610 ps
CPU time 79.62 seconds
Started Sep 11 03:36:09 AM UTC 24
Finished Sep 11 03:37:30 AM UTC 24
Peak memory 226036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171085689 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.2171085689
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.754249883
Short name T433
Test name
Test status
Simulation time 173780181 ps
CPU time 12.11 seconds
Started Sep 11 03:36:17 AM UTC 24
Finished Sep 11 03:36:30 AM UTC 24
Peak memory 229224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=754249883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.r
om_ctrl_csr_mem_rw_with_rand_reset.754249883
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.344778235
Short name T99
Test name
Test status
Simulation time 688350742 ps
CPU time 8.15 seconds
Started Sep 11 03:36:16 AM UTC 24
Finished Sep 11 03:36:26 AM UTC 24
Peak memory 221740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344778235 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.344778235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2666635991
Short name T450
Test name
Test status
Simulation time 3097374576 ps
CPU time 61.31 seconds
Started Sep 11 03:36:10 AM UTC 24
Finished Sep 11 03:37:13 AM UTC 24
Peak memory 226000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666635991 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.2666635991
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1894649613
Short name T435
Test name
Test status
Simulation time 1543589283 ps
CPU time 13.53 seconds
Started Sep 11 03:36:16 AM UTC 24
Finished Sep 11 03:36:31 AM UTC 24
Peak memory 223980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894649613 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.1894649613
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2952512408
Short name T434
Test name
Test status
Simulation time 527807872 ps
CPU time 14.07 seconds
Started Sep 11 03:36:15 AM UTC 24
Finished Sep 11 03:36:30 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952512408 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2952512408
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4091928742
Short name T439
Test name
Test status
Simulation time 677618532 ps
CPU time 12.73 seconds
Started Sep 11 03:36:22 AM UTC 24
Finished Sep 11 03:36:36 AM UTC 24
Peak memory 229288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4091928742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rom_ctrl_csr_mem_rw_with_rand_reset.4091928742
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3942064433
Short name T105
Test name
Test status
Simulation time 260419079 ps
CPU time 9.5 seconds
Started Sep 11 03:36:20 AM UTC 24
Finished Sep 11 03:36:30 AM UTC 24
Peak memory 221740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942064433 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3942064433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.10089562
Short name T449
Test name
Test status
Simulation time 4060318982 ps
CPU time 50.78 seconds
Started Sep 11 03:36:17 AM UTC 24
Finished Sep 11 03:37:09 AM UTC 24
Peak memory 226000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10089562 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.10089562
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3607251235
Short name T432
Test name
Test status
Simulation time 176446636 ps
CPU time 7.61 seconds
Started Sep 11 03:36:21 AM UTC 24
Finished Sep 11 03:36:30 AM UTC 24
Peak memory 221932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607251235 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.3607251235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1116538331
Short name T436
Test name
Test status
Simulation time 172679784 ps
CPU time 13.23 seconds
Started Sep 11 03:36:18 AM UTC 24
Finished Sep 11 03:36:32 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116538331 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1116538331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2263168849
Short name T456
Test name
Test status
Simulation time 1079299736 ps
CPU time 91.34 seconds
Started Sep 11 03:36:18 AM UTC 24
Finished Sep 11 03:37:51 AM UTC 24
Peak memory 225908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263168849 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.2263168849
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1003097344
Short name T440
Test name
Test status
Simulation time 1234597494 ps
CPU time 11.78 seconds
Started Sep 11 03:36:24 AM UTC 24
Finished Sep 11 03:36:37 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1003097344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rom_ctrl_csr_mem_rw_with_rand_reset.1003097344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2137434433
Short name T438
Test name
Test status
Simulation time 1497138829 ps
CPU time 9.53 seconds
Started Sep 11 03:36:23 AM UTC 24
Finished Sep 11 03:36:34 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137434433 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2137434433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2521571682
Short name T453
Test name
Test status
Simulation time 4651904400 ps
CPU time 57.91 seconds
Started Sep 11 03:36:22 AM UTC 24
Finished Sep 11 03:37:21 AM UTC 24
Peak memory 229392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521571682 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.2521571682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3698378757
Short name T437
Test name
Test status
Simulation time 869392838 ps
CPU time 8.95 seconds
Started Sep 11 03:36:23 AM UTC 24
Finished Sep 11 03:36:33 AM UTC 24
Peak memory 221932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698378757 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.3698378757
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.499078256
Short name T441
Test name
Test status
Simulation time 249418179 ps
CPU time 17.11 seconds
Started Sep 11 03:36:22 AM UTC 24
Finished Sep 11 03:36:40 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499078256 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.499078256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1328430088
Short name T455
Test name
Test status
Simulation time 6313937092 ps
CPU time 84.98 seconds
Started Sep 11 03:36:23 AM UTC 24
Finished Sep 11 03:37:50 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328430088 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.1328430088
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2117410370
Short name T442
Test name
Test status
Simulation time 868267192 ps
CPU time 8.99 seconds
Started Sep 11 03:36:32 AM UTC 24
Finished Sep 11 03:36:42 AM UTC 24
Peak memory 229280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2117410370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rom_ctrl_csr_mem_rw_with_rand_reset.2117410370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4065319575
Short name T106
Test name
Test status
Simulation time 1303552292 ps
CPU time 11.25 seconds
Started Sep 11 03:36:31 AM UTC 24
Finished Sep 11 03:36:43 AM UTC 24
Peak memory 221932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065319575 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4065319575
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.31749673
Short name T451
Test name
Test status
Simulation time 1723102752 ps
CPU time 47.68 seconds
Started Sep 11 03:36:27 AM UTC 24
Finished Sep 11 03:37:16 AM UTC 24
Peak memory 225936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31749673 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.31749673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1431291652
Short name T443
Test name
Test status
Simulation time 1037685085 ps
CPU time 11.02 seconds
Started Sep 11 03:36:32 AM UTC 24
Finished Sep 11 03:36:44 AM UTC 24
Peak memory 221916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431291652 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.1431291652
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2875389236
Short name T444
Test name
Test status
Simulation time 262411724 ps
CPU time 14.42 seconds
Started Sep 11 03:36:29 AM UTC 24
Finished Sep 11 03:36:44 AM UTC 24
Peak memory 229388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875389236 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2875389236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3445519256
Short name T137
Test name
Test status
Simulation time 551617704 ps
CPU time 145.65 seconds
Started Sep 11 03:36:31 AM UTC 24
Finished Sep 11 03:38:59 AM UTC 24
Peak memory 229164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445519256 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.3445519256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.251177515
Short name T448
Test name
Test status
Simulation time 4136206215 ps
CPU time 16.06 seconds
Started Sep 11 03:36:35 AM UTC 24
Finished Sep 11 03:36:53 AM UTC 24
Peak memory 228208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=251177515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.r
om_ctrl_csr_mem_rw_with_rand_reset.251177515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3505057427
Short name T447
Test name
Test status
Simulation time 256113951 ps
CPU time 14.35 seconds
Started Sep 11 03:36:34 AM UTC 24
Finished Sep 11 03:36:50 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505057427 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3505057427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3821791233
Short name T452
Test name
Test status
Simulation time 2118973313 ps
CPU time 44.29 seconds
Started Sep 11 03:36:32 AM UTC 24
Finished Sep 11 03:37:18 AM UTC 24
Peak memory 225936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821791233 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.3821791233
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1003411110
Short name T446
Test name
Test status
Simulation time 262005307 ps
CPU time 14.25 seconds
Started Sep 11 03:36:34 AM UTC 24
Finished Sep 11 03:36:50 AM UTC 24
Peak memory 223852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003411110 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.1003411110
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3569332863
Short name T445
Test name
Test status
Simulation time 189097273 ps
CPU time 13.59 seconds
Started Sep 11 03:36:33 AM UTC 24
Finished Sep 11 03:36:48 AM UTC 24
Peak memory 228112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569332863 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3569332863
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.798562300
Short name T138
Test name
Test status
Simulation time 456508150 ps
CPU time 79.82 seconds
Started Sep 11 03:36:33 AM UTC 24
Finished Sep 11 03:37:55 AM UTC 24
Peak memory 223976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798562300 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.798562300
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4196725360
Short name T381
Test name
Test status
Simulation time 260363995 ps
CPU time 14.41 seconds
Started Sep 11 03:34:51 AM UTC 24
Finished Sep 11 03:35:06 AM UTC 24
Peak memory 221864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196725360 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.4196725360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3810291595
Short name T128
Test name
Test status
Simulation time 1551337321 ps
CPU time 14.43 seconds
Started Sep 11 03:34:49 AM UTC 24
Finished Sep 11 03:35:04 AM UTC 24
Peak memory 221864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810291595 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.3810291595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3487718913
Short name T89
Test name
Test status
Simulation time 341261116 ps
CPU time 17.24 seconds
Started Sep 11 03:34:48 AM UTC 24
Finished Sep 11 03:35:06 AM UTC 24
Peak memory 221736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487718913 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.3487718913
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3012645681
Short name T380
Test name
Test status
Simulation time 173925777 ps
CPU time 8.81 seconds
Started Sep 11 03:34:52 AM UTC 24
Finished Sep 11 03:35:02 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3012645681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
om_ctrl_csr_mem_rw_with_rand_reset.3012645681
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.405038651
Short name T127
Test name
Test status
Simulation time 2750149785 ps
CPU time 12.12 seconds
Started Sep 11 03:34:49 AM UTC 24
Finished Sep 11 03:35:02 AM UTC 24
Peak memory 221868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405038651 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.405038651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2544407853
Short name T377
Test name
Test status
Simulation time 168257963 ps
CPU time 11.26 seconds
Started Sep 11 03:34:48 AM UTC 24
Finished Sep 11 03:35:00 AM UTC 24
Peak memory 221752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544407853 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.2544407853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2387896815
Short name T379
Test name
Test status
Simulation time 528432474 ps
CPU time 13.96 seconds
Started Sep 11 03:34:46 AM UTC 24
Finished Sep 11 03:35:02 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387896815 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.2387896815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2878433092
Short name T120
Test name
Test status
Simulation time 899772907 ps
CPU time 37.17 seconds
Started Sep 11 03:34:43 AM UTC 24
Finished Sep 11 03:35:22 AM UTC 24
Peak memory 223884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878433092 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.2878433092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.404095298
Short name T90
Test name
Test status
Simulation time 184742023 ps
CPU time 14.98 seconds
Started Sep 11 03:34:51 AM UTC 24
Finished Sep 11 03:35:07 AM UTC 24
Peak memory 223860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404095298 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.404095298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1215371757
Short name T378
Test name
Test status
Simulation time 320119257 ps
CPU time 16.1 seconds
Started Sep 11 03:34:43 AM UTC 24
Finished Sep 11 03:35:01 AM UTC 24
Peak memory 228116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215371757 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1215371757
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1615373837
Short name T386
Test name
Test status
Simulation time 257582959 ps
CPU time 13.96 seconds
Started Sep 11 03:34:59 AM UTC 24
Finished Sep 11 03:35:14 AM UTC 24
Peak memory 221800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615373837 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.1615373837
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.815352019
Short name T385
Test name
Test status
Simulation time 991928708 ps
CPU time 13.3 seconds
Started Sep 11 03:34:58 AM UTC 24
Finished Sep 11 03:35:13 AM UTC 24
Peak memory 221812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815352019 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.815352019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3339509995
Short name T389
Test name
Test status
Simulation time 1862640520 ps
CPU time 21.01 seconds
Started Sep 11 03:34:57 AM UTC 24
Finished Sep 11 03:35:20 AM UTC 24
Peak memory 223784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339509995 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.3339509995
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.786836926
Short name T387
Test name
Test status
Simulation time 1874761847 ps
CPU time 11.59 seconds
Started Sep 11 03:35:02 AM UTC 24
Finished Sep 11 03:35:14 AM UTC 24
Peak memory 229424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=786836926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ro
m_ctrl_csr_mem_rw_with_rand_reset.786836926
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3595538934
Short name T382
Test name
Test status
Simulation time 1106906171 ps
CPU time 9.32 seconds
Started Sep 11 03:34:57 AM UTC 24
Finished Sep 11 03:35:08 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595538934 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3595538934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.883867104
Short name T390
Test name
Test status
Simulation time 1023977083 ps
CPU time 22.11 seconds
Started Sep 11 03:34:56 AM UTC 24
Finished Sep 11 03:35:20 AM UTC 24
Peak memory 221748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883867104 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.883867104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2429690187
Short name T384
Test name
Test status
Simulation time 260851703 ps
CPU time 14.54 seconds
Started Sep 11 03:34:56 AM UTC 24
Finished Sep 11 03:35:12 AM UTC 24
Peak memory 221672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429690187 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.2429690187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2306101418
Short name T97
Test name
Test status
Simulation time 1526105577 ps
CPU time 72.42 seconds
Started Sep 11 03:34:53 AM UTC 24
Finished Sep 11 03:36:07 AM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306101418 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.2306101418
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4263604523
Short name T91
Test name
Test status
Simulation time 415690936 ps
CPU time 12.22 seconds
Started Sep 11 03:35:01 AM UTC 24
Finished Sep 11 03:35:14 AM UTC 24
Peak memory 221800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263604523 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.4263604523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2944216529
Short name T383
Test name
Test status
Simulation time 174583165 ps
CPU time 16.31 seconds
Started Sep 11 03:34:54 AM UTC 24
Finished Sep 11 03:35:12 AM UTC 24
Peak memory 228116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944216529 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2944216529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3465686594
Short name T77
Test name
Test status
Simulation time 916386693 ps
CPU time 82.92 seconds
Started Sep 11 03:34:56 AM UTC 24
Finished Sep 11 03:36:21 AM UTC 24
Peak memory 223792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465686594 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.3465686594
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2688628564
Short name T395
Test name
Test status
Simulation time 1892637228 ps
CPU time 14.32 seconds
Started Sep 11 03:35:09 AM UTC 24
Finished Sep 11 03:35:25 AM UTC 24
Peak memory 221800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688628564 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.2688628564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.74352114
Short name T394
Test name
Test status
Simulation time 1014771289 ps
CPU time 15.37 seconds
Started Sep 11 03:35:08 AM UTC 24
Finished Sep 11 03:35:25 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74352114 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.74352114
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1248334746
Short name T93
Test name
Test status
Simulation time 262513606 ps
CPU time 25.06 seconds
Started Sep 11 03:35:07 AM UTC 24
Finished Sep 11 03:35:33 AM UTC 24
Peak memory 223860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248334746 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.1248334746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.166980576
Short name T396
Test name
Test status
Simulation time 1337737745 ps
CPU time 13.65 seconds
Started Sep 11 03:35:12 AM UTC 24
Finished Sep 11 03:35:27 AM UTC 24
Peak memory 228148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=166980576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ro
m_ctrl_csr_mem_rw_with_rand_reset.166980576
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4282066770
Short name T92
Test name
Test status
Simulation time 638045540 ps
CPU time 9.71 seconds
Started Sep 11 03:35:08 AM UTC 24
Finished Sep 11 03:35:19 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282066770 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4282066770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3230894915
Short name T393
Test name
Test status
Simulation time 1268758289 ps
CPU time 11.81 seconds
Started Sep 11 03:35:07 AM UTC 24
Finished Sep 11 03:35:20 AM UTC 24
Peak memory 221816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230894915 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.3230894915
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2808006589
Short name T388
Test name
Test status
Simulation time 516511617 ps
CPU time 9.82 seconds
Started Sep 11 03:35:05 AM UTC 24
Finished Sep 11 03:35:16 AM UTC 24
Peak memory 221740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808006589 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.2808006589
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.376310245
Short name T103
Test name
Test status
Simulation time 1528542899 ps
CPU time 71.36 seconds
Started Sep 11 03:35:03 AM UTC 24
Finished Sep 11 03:36:16 AM UTC 24
Peak memory 226132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376310245 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.376310245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3681411656
Short name T121
Test name
Test status
Simulation time 196362809 ps
CPU time 9.46 seconds
Started Sep 11 03:35:12 AM UTC 24
Finished Sep 11 03:35:23 AM UTC 24
Peak memory 221800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681411656 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.3681411656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1610218378
Short name T392
Test name
Test status
Simulation time 1030373241 ps
CPU time 15.97 seconds
Started Sep 11 03:35:03 AM UTC 24
Finished Sep 11 03:35:20 AM UTC 24
Peak memory 228180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610218378 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1610218378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1891912421
Short name T131
Test name
Test status
Simulation time 1117688451 ps
CPU time 108.18 seconds
Started Sep 11 03:35:03 AM UTC 24
Finished Sep 11 03:36:53 AM UTC 24
Peak memory 223864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891912421 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.1891912421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.987866541
Short name T398
Test name
Test status
Simulation time 2836089645 ps
CPU time 8.42 seconds
Started Sep 11 03:35:20 AM UTC 24
Finished Sep 11 03:35:29 AM UTC 24
Peak memory 228212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=987866541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ro
m_ctrl_csr_mem_rw_with_rand_reset.987866541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2264851311
Short name T397
Test name
Test status
Simulation time 282005487 ps
CPU time 11.59 seconds
Started Sep 11 03:35:16 AM UTC 24
Finished Sep 11 03:35:28 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264851311 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2264851311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3185119544
Short name T122
Test name
Test status
Simulation time 660284244 ps
CPU time 12.54 seconds
Started Sep 11 03:35:17 AM UTC 24
Finished Sep 11 03:35:30 AM UTC 24
Peak memory 221736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185119544 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.3185119544
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.357902737
Short name T400
Test name
Test status
Simulation time 825783565 ps
CPU time 16.9 seconds
Started Sep 11 03:35:15 AM UTC 24
Finished Sep 11 03:35:33 AM UTC 24
Peak memory 228116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357902737 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.357902737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3367593386
Short name T134
Test name
Test status
Simulation time 424747737 ps
CPU time 165.49 seconds
Started Sep 11 03:35:15 AM UTC 24
Finished Sep 11 03:38:03 AM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367593386 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.3367593386
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2466105258
Short name T401
Test name
Test status
Simulation time 182847076 ps
CPU time 11.9 seconds
Started Sep 11 03:35:23 AM UTC 24
Finished Sep 11 03:35:36 AM UTC 24
Peak memory 228140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2466105258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
om_ctrl_csr_mem_rw_with_rand_reset.2466105258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3985007880
Short name T399
Test name
Test status
Simulation time 503148735 ps
CPU time 9.13 seconds
Started Sep 11 03:35:21 AM UTC 24
Finished Sep 11 03:35:31 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985007880 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3985007880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1431844870
Short name T415
Test name
Test status
Simulation time 3381444245 ps
CPU time 42.8 seconds
Started Sep 11 03:35:21 AM UTC 24
Finished Sep 11 03:36:05 AM UTC 24
Peak memory 226124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431844870 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.1431844870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4225750649
Short name T123
Test name
Test status
Simulation time 989880027 ps
CPU time 14.08 seconds
Started Sep 11 03:35:21 AM UTC 24
Finished Sep 11 03:35:36 AM UTC 24
Peak memory 221992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225750649 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.4225750649
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1292830903
Short name T406
Test name
Test status
Simulation time 2136947655 ps
CPU time 22.34 seconds
Started Sep 11 03:35:21 AM UTC 24
Finished Sep 11 03:35:44 AM UTC 24
Peak memory 228048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292830903 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1292830903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3303316441
Short name T404
Test name
Test status
Simulation time 638572811 ps
CPU time 12.45 seconds
Started Sep 11 03:35:31 AM UTC 24
Finished Sep 11 03:35:44 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3303316441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
om_ctrl_csr_mem_rw_with_rand_reset.3303316441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3915048433
Short name T124
Test name
Test status
Simulation time 172573523 ps
CPU time 12.16 seconds
Started Sep 11 03:35:28 AM UTC 24
Finished Sep 11 03:35:42 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915048433 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3915048433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1509160052
Short name T431
Test name
Test status
Simulation time 1522973666 ps
CPU time 62.08 seconds
Started Sep 11 03:35:24 AM UTC 24
Finished Sep 11 03:36:28 AM UTC 24
Peak memory 225932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509160052 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.1509160052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3882273592
Short name T402
Test name
Test status
Simulation time 169397630 ps
CPU time 12.55 seconds
Started Sep 11 03:35:29 AM UTC 24
Finished Sep 11 03:35:43 AM UTC 24
Peak memory 221864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882273592 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.3882273592
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1308260686
Short name T403
Test name
Test status
Simulation time 355742702 ps
CPU time 17.04 seconds
Started Sep 11 03:35:25 AM UTC 24
Finished Sep 11 03:35:44 AM UTC 24
Peak memory 227912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308260686 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1308260686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1891958704
Short name T457
Test name
Test status
Simulation time 2065547175 ps
CPU time 173.61 seconds
Started Sep 11 03:35:25 AM UTC 24
Finished Sep 11 03:38:22 AM UTC 24
Peak memory 229212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891958704 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.1891958704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3899015456
Short name T408
Test name
Test status
Simulation time 1520029758 ps
CPU time 15.25 seconds
Started Sep 11 03:35:37 AM UTC 24
Finished Sep 11 03:35:54 AM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3899015456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
om_ctrl_csr_mem_rw_with_rand_reset.3899015456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3413010232
Short name T95
Test name
Test status
Simulation time 169165912 ps
CPU time 10.87 seconds
Started Sep 11 03:35:34 AM UTC 24
Finished Sep 11 03:35:46 AM UTC 24
Peak memory 221804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413010232 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3413010232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3938822977
Short name T104
Test name
Test status
Simulation time 690560049 ps
CPU time 42.84 seconds
Started Sep 11 03:35:32 AM UTC 24
Finished Sep 11 03:36:16 AM UTC 24
Peak memory 225868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938822977 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.3938822977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3868989084
Short name T405
Test name
Test status
Simulation time 496432759 ps
CPU time 8.95 seconds
Started Sep 11 03:35:34 AM UTC 24
Finished Sep 11 03:35:44 AM UTC 24
Peak memory 221992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868989084 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.3868989084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2843050480
Short name T407
Test name
Test status
Simulation time 332412301 ps
CPU time 16.6 seconds
Started Sep 11 03:35:32 AM UTC 24
Finished Sep 11 03:35:49 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843050480 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2843050480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3395642206
Short name T135
Test name
Test status
Simulation time 1190476192 ps
CPU time 94.27 seconds
Started Sep 11 03:35:34 AM UTC 24
Finished Sep 11 03:37:11 AM UTC 24
Peak memory 226040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395642206 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.3395642206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4275860411
Short name T409
Test name
Test status
Simulation time 172077667 ps
CPU time 11.71 seconds
Started Sep 11 03:35:44 AM UTC 24
Finished Sep 11 03:35:57 AM UTC 24
Peak memory 229288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4275860411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
om_ctrl_csr_mem_rw_with_rand_reset.4275860411
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2520924971
Short name T96
Test name
Test status
Simulation time 513820980 ps
CPU time 11.1 seconds
Started Sep 11 03:35:42 AM UTC 24
Finished Sep 11 03:35:55 AM UTC 24
Peak memory 221688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520924971 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2520924971
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3493929071
Short name T146
Test name
Test status
Simulation time 6093817525 ps
CPU time 63.33 seconds
Started Sep 11 03:35:37 AM UTC 24
Finished Sep 11 03:36:42 AM UTC 24
Peak memory 225996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493929071 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.3493929071
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.540529176
Short name T412
Test name
Test status
Simulation time 375172090 ps
CPU time 17.93 seconds
Started Sep 11 03:35:43 AM UTC 24
Finished Sep 11 03:36:02 AM UTC 24
Peak memory 223928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540529176 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.540529176
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1316186079
Short name T368
Test name
Test status
Simulation time 250017680 ps
CPU time 15.06 seconds
Started Sep 11 03:35:38 AM UTC 24
Finished Sep 11 03:35:55 AM UTC 24
Peak memory 228048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316186079 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1316186079
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.78165858
Short name T141
Test name
Test status
Simulation time 6324561278 ps
CPU time 89.15 seconds
Started Sep 11 03:35:42 AM UTC 24
Finished Sep 11 03:37:14 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78165858 -assert nopostproc +UVM_
TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.78165858
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.764828737
Short name T2
Test name
Test status
Simulation time 468775000 ps
CPU time 10.21 seconds
Started Sep 11 03:28:38 AM UTC 24
Finished Sep 11 03:28:50 AM UTC 24
Peak memory 227660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764828737 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.764828737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.761252712
Short name T259
Test name
Test status
Simulation time 3128783014 ps
CPU time 276.26 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:33:18 AM UTC 24
Peak memory 247392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761252712 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.761252712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3312159512
Short name T1
Test name
Test status
Simulation time 181926343 ps
CPU time 9.86 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:49 AM UTC 24
Peak memory 227796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312159512 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3312159512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.3033099560
Short name T24
Test name
Test status
Simulation time 1769508583 ps
CPU time 114.64 seconds
Started Sep 11 03:28:38 AM UTC 24
Finished Sep 11 03:30:35 AM UTC 24
Peak memory 258516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033099560 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3033099560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.2141596777
Short name T3
Test name
Test status
Simulation time 1073741437 ps
CPU time 12.12 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:51 AM UTC 24
Peak memory 228528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141596777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2141596777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2031117373
Short name T5
Test name
Test status
Simulation time 2746818344 ps
CPU time 7.89 seconds
Started Sep 11 03:28:43 AM UTC 24
Finished Sep 11 03:28:53 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031117373 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2031117373
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2131445395
Short name T320
Test name
Test status
Simulation time 25928177006 ps
CPU time 349.04 seconds
Started Sep 11 03:28:39 AM UTC 24
Finished Sep 11 03:34:34 AM UTC 24
Peak memory 259608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131445395 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.2131445395
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3839763584
Short name T7
Test name
Test status
Simulation time 3201381876 ps
CPU time 14.4 seconds
Started Sep 11 03:28:39 AM UTC 24
Finished Sep 11 03:28:55 AM UTC 24
Peak memory 228680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839763584 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3839763584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3532025167
Short name T4
Test name
Test status
Simulation time 261743314 ps
CPU time 11.83 seconds
Started Sep 11 03:28:39 AM UTC 24
Finished Sep 11 03:28:52 AM UTC 24
Peak memory 228872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532025167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3532025167
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.547533018
Short name T161
Test name
Test status
Simulation time 338829172 ps
CPU time 11.92 seconds
Started Sep 11 03:29:23 AM UTC 24
Finished Sep 11 03:29:36 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547533018 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.547533018
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.900219479
Short name T46
Test name
Test status
Simulation time 7965835796 ps
CPU time 201.16 seconds
Started Sep 11 03:29:19 AM UTC 24
Finished Sep 11 03:32:43 AM UTC 24
Peak memory 227692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900219479 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.900219479
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.2952483584
Short name T165
Test name
Test status
Simulation time 335776940 ps
CPU time 30.5 seconds
Started Sep 11 03:29:19 AM UTC 24
Finished Sep 11 03:29:51 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952483584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2952483584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1383937776
Short name T151
Test name
Test status
Simulation time 185128986 ps
CPU time 16 seconds
Started Sep 11 03:29:18 AM UTC 24
Finished Sep 11 03:29:35 AM UTC 24
Peak memory 228164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383937776 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1383937776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3847061220
Short name T157
Test name
Test status
Simulation time 807815559 ps
CPU time 42.52 seconds
Started Sep 11 03:29:18 AM UTC 24
Finished Sep 11 03:30:02 AM UTC 24
Peak memory 228840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384706122
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.3847061220
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4179117759
Short name T65
Test name
Test status
Simulation time 3406706888 ps
CPU time 81.43 seconds
Started Sep 11 03:29:21 AM UTC 24
Finished Sep 11 03:30:44 AM UTC 24
Peak memory 232928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4179117759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.4179117759
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.2709354173
Short name T68
Test name
Test status
Simulation time 1034276349 ps
CPU time 11.43 seconds
Started Sep 11 03:29:26 AM UTC 24
Finished Sep 11 03:29:39 AM UTC 24
Peak memory 227996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709354173 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2709354173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4037613604
Short name T60
Test name
Test status
Simulation time 5058906951 ps
CPU time 207.27 seconds
Started Sep 11 03:29:26 AM UTC 24
Finished Sep 11 03:32:57 AM UTC 24
Peak memory 245240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037613604 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.4037613604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2972123205
Short name T164
Test name
Test status
Simulation time 662477680 ps
CPU time 21.7 seconds
Started Sep 11 03:29:26 AM UTC 24
Finished Sep 11 03:29:49 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972123205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2972123205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1279563380
Short name T69
Test name
Test status
Simulation time 190390117 ps
CPU time 13.54 seconds
Started Sep 11 03:29:25 AM UTC 24
Finished Sep 11 03:29:40 AM UTC 24
Peak memory 228296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279563380 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1279563380
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3676335743
Short name T162
Test name
Test status
Simulation time 810406912 ps
CPU time 36.8 seconds
Started Sep 11 03:29:25 AM UTC 24
Finished Sep 11 03:30:03 AM UTC 24
Peak memory 228712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367633574
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.3676335743
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.142398182
Short name T219
Test name
Test status
Simulation time 12063740451 ps
CPU time 160.79 seconds
Started Sep 11 03:29:26 AM UTC 24
Finished Sep 11 03:32:10 AM UTC 24
Peak memory 246352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=142398182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.rom_ctrl_stress_all_with_rand_reset.142398182
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.2351430018
Short name T70
Test name
Test status
Simulation time 178236293 ps
CPU time 7.74 seconds
Started Sep 11 03:29:31 AM UTC 24
Finished Sep 11 03:29:40 AM UTC 24
Peak memory 228364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351430018 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2351430018
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.89631919
Short name T346
Test name
Test status
Simulation time 25286290094 ps
CPU time 423.77 seconds
Started Sep 11 03:29:29 AM UTC 24
Finished Sep 11 03:36:38 AM UTC 24
Peak memory 232036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89631919 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.89631919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.537825729
Short name T155
Test name
Test status
Simulation time 497382925 ps
CPU time 29.79 seconds
Started Sep 11 03:29:29 AM UTC 24
Finished Sep 11 03:30:00 AM UTC 24
Peak memory 228140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537825729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.537825729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2803043224
Short name T72
Test name
Test status
Simulation time 1063105414 ps
CPU time 17.64 seconds
Started Sep 11 03:29:28 AM UTC 24
Finished Sep 11 03:29:47 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803043224 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2803043224
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1079399503
Short name T163
Test name
Test status
Simulation time 3587916389 ps
CPU time 48.37 seconds
Started Sep 11 03:29:28 AM UTC 24
Finished Sep 11 03:30:18 AM UTC 24
Peak memory 227760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107939950
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.1079399503
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2123476249
Short name T230
Test name
Test status
Simulation time 5465191001 ps
CPU time 176.54 seconds
Started Sep 11 03:29:31 AM UTC 24
Finished Sep 11 03:32:31 AM UTC 24
Peak memory 234988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2123476249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2123476249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3507215470
Short name T166
Test name
Test status
Simulation time 484717351 ps
CPU time 12.93 seconds
Started Sep 11 03:29:37 AM UTC 24
Finished Sep 11 03:29:51 AM UTC 24
Peak memory 228004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507215470 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3507215470
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.974804773
Short name T254
Test name
Test status
Simulation time 11962917740 ps
CPU time 216.74 seconds
Started Sep 11 03:29:35 AM UTC 24
Finished Sep 11 03:33:16 AM UTC 24
Peak memory 256204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974804773 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.974804773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2200733352
Short name T170
Test name
Test status
Simulation time 1008816709 ps
CPU time 28.16 seconds
Started Sep 11 03:29:36 AM UTC 24
Finished Sep 11 03:30:05 AM UTC 24
Peak memory 228948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200733352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2200733352
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1751321741
Short name T167
Test name
Test status
Simulation time 528256306 ps
CPU time 18.11 seconds
Started Sep 11 03:29:34 AM UTC 24
Finished Sep 11 03:29:53 AM UTC 24
Peak memory 228380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751321741 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1751321741
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1382053228
Short name T154
Test name
Test status
Simulation time 2059908092 ps
CPU time 18.81 seconds
Started Sep 11 03:29:33 AM UTC 24
Finished Sep 11 03:29:53 AM UTC 24
Peak memory 228712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138205322
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.1382053228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.2613967149
Short name T158
Test name
Test status
Simulation time 826855882 ps
CPU time 12.88 seconds
Started Sep 11 03:29:41 AM UTC 24
Finished Sep 11 03:29:55 AM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613967149 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2613967149
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.741591211
Short name T143
Test name
Test status
Simulation time 2184078645 ps
CPU time 200.9 seconds
Started Sep 11 03:29:39 AM UTC 24
Finished Sep 11 03:33:03 AM UTC 24
Peak memory 257500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741591211 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.741591211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.778975416
Short name T172
Test name
Test status
Simulation time 2060899348 ps
CPU time 27 seconds
Started Sep 11 03:29:40 AM UTC 24
Finished Sep 11 03:30:08 AM UTC 24
Peak memory 228316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778975416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.778975416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1990852756
Short name T74
Test name
Test status
Simulation time 2180835176 ps
CPU time 10.56 seconds
Started Sep 11 03:29:37 AM UTC 24
Finished Sep 11 03:29:48 AM UTC 24
Peak memory 228436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990852756 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1990852756
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2971019261
Short name T177
Test name
Test status
Simulation time 840239064 ps
CPU time 40.83 seconds
Started Sep 11 03:29:37 AM UTC 24
Finished Sep 11 03:30:19 AM UTC 24
Peak memory 228712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297101926
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.2971019261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.597004942
Short name T114
Test name
Test status
Simulation time 28466268359 ps
CPU time 133.94 seconds
Started Sep 11 03:29:41 AM UTC 24
Finished Sep 11 03:31:57 AM UTC 24
Peak memory 245936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=597004942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.rom_ctrl_stress_all_with_rand_reset.597004942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.952739188
Short name T153
Test name
Test status
Simulation time 2358482357 ps
CPU time 11.58 seconds
Started Sep 11 03:29:49 AM UTC 24
Finished Sep 11 03:30:02 AM UTC 24
Peak memory 228288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952739188 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.952739188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.989147752
Short name T299
Test name
Test status
Simulation time 30007627641 ps
CPU time 256.29 seconds
Started Sep 11 03:29:44 AM UTC 24
Finished Sep 11 03:34:05 AM UTC 24
Peak memory 257524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989147752 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.989147752
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.842432526
Short name T173
Test name
Test status
Simulation time 515562104 ps
CPU time 22.67 seconds
Started Sep 11 03:29:47 AM UTC 24
Finished Sep 11 03:30:11 AM UTC 24
Peak memory 228824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842432526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.842432526
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.147077125
Short name T168
Test name
Test status
Simulation time 1858200912 ps
CPU time 13.94 seconds
Started Sep 11 03:29:43 AM UTC 24
Finished Sep 11 03:29:58 AM UTC 24
Peak memory 228376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147077125 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.147077125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.491881736
Short name T156
Test name
Test status
Simulation time 537914580 ps
CPU time 18.79 seconds
Started Sep 11 03:29:42 AM UTC 24
Finished Sep 11 03:30:02 AM UTC 24
Peak memory 225448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491881736
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.491881736
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2658241824
Short name T44
Test name
Test status
Simulation time 13470978518 ps
CPU time 50.94 seconds
Started Sep 11 03:29:48 AM UTC 24
Finished Sep 11 03:30:41 AM UTC 24
Peak memory 243168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2658241824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2658241824
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.890587523
Short name T171
Test name
Test status
Simulation time 1180608032 ps
CPU time 13.2 seconds
Started Sep 11 03:29:53 AM UTC 24
Finished Sep 11 03:30:08 AM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890587523 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.890587523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2925702508
Short name T287
Test name
Test status
Simulation time 3497969700 ps
CPU time 235.05 seconds
Started Sep 11 03:29:52 AM UTC 24
Finished Sep 11 03:33:50 AM UTC 24
Peak memory 256988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925702508 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.2925702508
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3927777311
Short name T175
Test name
Test status
Simulation time 373431154 ps
CPU time 20.15 seconds
Started Sep 11 03:29:53 AM UTC 24
Finished Sep 11 03:30:15 AM UTC 24
Peak memory 228884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927777311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3927777311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.905830848
Short name T169
Test name
Test status
Simulation time 1167939510 ps
CPU time 11.77 seconds
Started Sep 11 03:29:52 AM UTC 24
Finished Sep 11 03:30:04 AM UTC 24
Peak memory 228376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905830848 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.905830848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1406431494
Short name T178
Test name
Test status
Simulation time 1055695454 ps
CPU time 28.44 seconds
Started Sep 11 03:29:50 AM UTC 24
Finished Sep 11 03:30:19 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140643149
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.1406431494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.111996922
Short name T226
Test name
Test status
Simulation time 2629077411 ps
CPU time 147.01 seconds
Started Sep 11 03:29:53 AM UTC 24
Finished Sep 11 03:32:23 AM UTC 24
Peak memory 243116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=111996922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.rom_ctrl_stress_all_with_rand_reset.111996922
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1808993564
Short name T159
Test name
Test status
Simulation time 505423551 ps
CPU time 12.85 seconds
Started Sep 11 03:30:03 AM UTC 24
Finished Sep 11 03:30:17 AM UTC 24
Peak memory 227972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808993564 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1808993564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1218316243
Short name T323
Test name
Test status
Simulation time 8070549803 ps
CPU time 275.13 seconds
Started Sep 11 03:29:57 AM UTC 24
Finished Sep 11 03:34:36 AM UTC 24
Peak memory 228884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218316243 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.1218316243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2149270944
Short name T180
Test name
Test status
Simulation time 516611494 ps
CPU time 21.12 seconds
Started Sep 11 03:29:59 AM UTC 24
Finished Sep 11 03:30:21 AM UTC 24
Peak memory 228312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149270944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2149270944
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1242813136
Short name T174
Test name
Test status
Simulation time 259760897 ps
CPU time 15.91 seconds
Started Sep 11 03:29:55 AM UTC 24
Finished Sep 11 03:30:13 AM UTC 24
Peak memory 228092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242813136 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1242813136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3101608572
Short name T183
Test name
Test status
Simulation time 534262502 ps
CPU time 37.12 seconds
Started Sep 11 03:29:54 AM UTC 24
Finished Sep 11 03:30:33 AM UTC 24
Peak memory 228712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310160857
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.3101608572
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.26686818
Short name T116
Test name
Test status
Simulation time 1870692848 ps
CPU time 119.16 seconds
Started Sep 11 03:30:01 AM UTC 24
Finished Sep 11 03:32:02 AM UTC 24
Peak memory 245144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=26686818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 17.rom_ctrl_stress_all_with_rand_reset.26686818
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2287923421
Short name T176
Test name
Test status
Simulation time 250815483 ps
CPU time 9.96 seconds
Started Sep 11 03:30:06 AM UTC 24
Finished Sep 11 03:30:17 AM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287923421 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2287923421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1638374778
Short name T316
Test name
Test status
Simulation time 3795089391 ps
CPU time 261.45 seconds
Started Sep 11 03:30:04 AM UTC 24
Finished Sep 11 03:34:29 AM UTC 24
Peak memory 257636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638374778 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.1638374778
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.1645988693
Short name T182
Test name
Test status
Simulation time 495548428 ps
CPU time 26.14 seconds
Started Sep 11 03:30:05 AM UTC 24
Finished Sep 11 03:30:33 AM UTC 24
Peak memory 225584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645988693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1645988693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3037435166
Short name T179
Test name
Test status
Simulation time 916085571 ps
CPU time 15.47 seconds
Started Sep 11 03:30:03 AM UTC 24
Finished Sep 11 03:30:19 AM UTC 24
Peak memory 228436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037435166 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3037435166
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2458101966
Short name T45
Test name
Test status
Simulation time 7118122851 ps
CPU time 37.16 seconds
Started Sep 11 03:30:03 AM UTC 24
Finished Sep 11 03:30:41 AM UTC 24
Peak memory 228888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245810196
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.2458101966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1940634973
Short name T207
Test name
Test status
Simulation time 22193754696 ps
CPU time 77.92 seconds
Started Sep 11 03:30:05 AM UTC 24
Finished Sep 11 03:31:25 AM UTC 24
Peak memory 239264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1940634973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1940634973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.907307757
Short name T160
Test name
Test status
Simulation time 993137881 ps
CPU time 11.26 seconds
Started Sep 11 03:30:12 AM UTC 24
Finished Sep 11 03:30:25 AM UTC 24
Peak memory 228128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907307757 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.907307757
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.85437557
Short name T283
Test name
Test status
Simulation time 9874688567 ps
CPU time 216.5 seconds
Started Sep 11 03:30:08 AM UTC 24
Finished Sep 11 03:33:48 AM UTC 24
Peak memory 244716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85437557 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.85437557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3716628467
Short name T184
Test name
Test status
Simulation time 345226301 ps
CPU time 23.36 seconds
Started Sep 11 03:30:09 AM UTC 24
Finished Sep 11 03:30:33 AM UTC 24
Peak memory 228756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716628467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3716628467
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2405650002
Short name T181
Test name
Test status
Simulation time 366023071 ps
CPU time 14.45 seconds
Started Sep 11 03:30:08 AM UTC 24
Finished Sep 11 03:30:23 AM UTC 24
Peak memory 228084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405650002 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2405650002
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2569796380
Short name T187
Test name
Test status
Simulation time 531576277 ps
CPU time 34.19 seconds
Started Sep 11 03:30:06 AM UTC 24
Finished Sep 11 03:30:42 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256979638
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.2569796380
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1591404217
Short name T227
Test name
Test status
Simulation time 13270287605 ps
CPU time 134.59 seconds
Started Sep 11 03:30:09 AM UTC 24
Finished Sep 11 03:32:26 AM UTC 24
Peak memory 239072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1591404217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1591404217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.532457574
Short name T21
Test name
Test status
Simulation time 9788723929 ps
CPU time 160.92 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:31:27 AM UTC 24
Peak memory 257564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532457574 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.532457574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2187484114
Short name T28
Test name
Test status
Simulation time 3296404971 ps
CPU time 24.31 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:29:09 AM UTC 24
Peak memory 228400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187484114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2187484114
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.3944647304
Short name T20
Test name
Test status
Simulation time 376922922 ps
CPU time 15.82 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:29:01 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944647304 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3944647304
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2715910737
Short name T36
Test name
Test status
Simulation time 423986731 ps
CPU time 292.35 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:33:40 AM UTC 24
Peak memory 258516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715910737 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2715910737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.4153033416
Short name T6
Test name
Test status
Simulation time 762025314 ps
CPU time 10.07 seconds
Started Sep 11 03:28:43 AM UTC 24
Finished Sep 11 03:28:55 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153033416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4153033416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2934315120
Short name T67
Test name
Test status
Simulation time 5513226499 ps
CPU time 147.32 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:31:14 AM UTC 24
Peak memory 234976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2934315120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2934315120
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3273187059
Short name T185
Test name
Test status
Simulation time 247591506 ps
CPU time 14.05 seconds
Started Sep 11 03:30:19 AM UTC 24
Finished Sep 11 03:30:34 AM UTC 24
Peak memory 227972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273187059 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3273187059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1828765306
Short name T330
Test name
Test status
Simulation time 19059300528 ps
CPU time 276.07 seconds
Started Sep 11 03:30:16 AM UTC 24
Finished Sep 11 03:34:56 AM UTC 24
Peak memory 244596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828765306 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.1828765306
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3397146687
Short name T39
Test name
Test status
Simulation time 2763778636 ps
CPU time 20.75 seconds
Started Sep 11 03:30:18 AM UTC 24
Finished Sep 11 03:30:40 AM UTC 24
Peak memory 228500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397146687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3397146687
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2165915149
Short name T37
Test name
Test status
Simulation time 276059834 ps
CPU time 19.31 seconds
Started Sep 11 03:30:16 AM UTC 24
Finished Sep 11 03:30:37 AM UTC 24
Peak memory 228372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165915149 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2165915149
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2524728280
Short name T188
Test name
Test status
Simulation time 2132243106 ps
CPU time 30.57 seconds
Started Sep 11 03:30:14 AM UTC 24
Finished Sep 11 03:30:46 AM UTC 24
Peak memory 228900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252472828
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.2524728280
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.61884784
Short name T233
Test name
Test status
Simulation time 8424480421 ps
CPU time 135.6 seconds
Started Sep 11 03:30:18 AM UTC 24
Finished Sep 11 03:32:36 AM UTC 24
Peak memory 245208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=61884784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 20.rom_ctrl_stress_all_with_rand_reset.61884784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3183202659
Short name T43
Test name
Test status
Simulation time 4119676314 ps
CPU time 14.44 seconds
Started Sep 11 03:30:25 AM UTC 24
Finished Sep 11 03:30:41 AM UTC 24
Peak memory 228220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183202659 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3183202659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.722965272
Short name T48
Test name
Test status
Simulation time 7980613230 ps
CPU time 144.79 seconds
Started Sep 11 03:30:20 AM UTC 24
Finished Sep 11 03:32:47 AM UTC 24
Peak memory 247100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722965272 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.722965272
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2125065533
Short name T191
Test name
Test status
Simulation time 1032592123 ps
CPU time 28.48 seconds
Started Sep 11 03:30:22 AM UTC 24
Finished Sep 11 03:30:52 AM UTC 24
Peak memory 228132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125065533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2125065533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3993191402
Short name T38
Test name
Test status
Simulation time 756222168 ps
CPU time 16.65 seconds
Started Sep 11 03:30:20 AM UTC 24
Finished Sep 11 03:30:38 AM UTC 24
Peak memory 228140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993191402 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3993191402
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.393350478
Short name T186
Test name
Test status
Simulation time 430603490 ps
CPU time 20.18 seconds
Started Sep 11 03:30:20 AM UTC 24
Finished Sep 11 03:30:42 AM UTC 24
Peak memory 228452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393350478
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.393350478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1846825742
Short name T270
Test name
Test status
Simulation time 18375620486 ps
CPU time 187.89 seconds
Started Sep 11 03:30:24 AM UTC 24
Finished Sep 11 03:33:35 AM UTC 24
Peak memory 241120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1846825742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1846825742
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.767698717
Short name T190
Test name
Test status
Simulation time 174333289 ps
CPU time 13.12 seconds
Started Sep 11 03:30:38 AM UTC 24
Finished Sep 11 03:30:52 AM UTC 24
Peak memory 227468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767698717 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.767698717
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1948868129
Short name T274
Test name
Test status
Simulation time 9476674482 ps
CPU time 183.48 seconds
Started Sep 11 03:30:34 AM UTC 24
Finished Sep 11 03:33:41 AM UTC 24
Peak memory 261512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948868129 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.1948868129
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.468237358
Short name T195
Test name
Test status
Simulation time 1980611723 ps
CPU time 24.58 seconds
Started Sep 11 03:30:35 AM UTC 24
Finished Sep 11 03:31:02 AM UTC 24
Peak memory 228276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468237358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.468237358
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.4165733960
Short name T189
Test name
Test status
Simulation time 178998887 ps
CPU time 11.97 seconds
Started Sep 11 03:30:33 AM UTC 24
Finished Sep 11 03:30:47 AM UTC 24
Peak memory 228500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165733960 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4165733960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2719969527
Short name T197
Test name
Test status
Simulation time 281088075 ps
CPU time 29.25 seconds
Started Sep 11 03:30:33 AM UTC 24
Finished Sep 11 03:31:04 AM UTC 24
Peak memory 225584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271996952
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.2719969527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.487208341
Short name T117
Test name
Test status
Simulation time 7760400869 ps
CPU time 86.3 seconds
Started Sep 11 03:30:37 AM UTC 24
Finished Sep 11 03:32:05 AM UTC 24
Peak memory 234976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=487208341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.rom_ctrl_stress_all_with_rand_reset.487208341
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3103584597
Short name T193
Test name
Test status
Simulation time 577392073 ps
CPU time 14.9 seconds
Started Sep 11 03:30:42 AM UTC 24
Finished Sep 11 03:30:58 AM UTC 24
Peak memory 227780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103584597 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3103584597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2021715260
Short name T281
Test name
Test status
Simulation time 3885592481 ps
CPU time 181.91 seconds
Started Sep 11 03:30:41 AM UTC 24
Finished Sep 11 03:33:46 AM UTC 24
Peak memory 257512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021715260 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.2021715260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1465279986
Short name T198
Test name
Test status
Simulation time 507915158 ps
CPU time 23.65 seconds
Started Sep 11 03:30:41 AM UTC 24
Finished Sep 11 03:31:06 AM UTC 24
Peak memory 228692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465279986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1465279986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.96508812
Short name T192
Test name
Test status
Simulation time 260583448 ps
CPU time 12.62 seconds
Started Sep 11 03:30:41 AM UTC 24
Finished Sep 11 03:30:55 AM UTC 24
Peak memory 227960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96508812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.96508812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2795222637
Short name T203
Test name
Test status
Simulation time 890060701 ps
CPU time 35.11 seconds
Started Sep 11 03:30:39 AM UTC 24
Finished Sep 11 03:31:15 AM UTC 24
Peak memory 228632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279522263
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.2795222637
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1716504022
Short name T327
Test name
Test status
Simulation time 4726130257 ps
CPU time 237.28 seconds
Started Sep 11 03:30:42 AM UTC 24
Finished Sep 11 03:34:43 AM UTC 24
Peak memory 246352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1716504022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1716504022
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.974823907
Short name T194
Test name
Test status
Simulation time 249093445 ps
CPU time 11.76 seconds
Started Sep 11 03:30:47 AM UTC 24
Finished Sep 11 03:31:00 AM UTC 24
Peak memory 228152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974823907 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.974823907
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.729815419
Short name T257
Test name
Test status
Simulation time 6196963783 ps
CPU time 151.09 seconds
Started Sep 11 03:30:43 AM UTC 24
Finished Sep 11 03:33:17 AM UTC 24
Peak memory 257220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729815419 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.729815419
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3708041606
Short name T205
Test name
Test status
Simulation time 989101265 ps
CPU time 31.41 seconds
Started Sep 11 03:30:45 AM UTC 24
Finished Sep 11 03:31:18 AM UTC 24
Peak memory 228336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708041606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3708041606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3180883059
Short name T196
Test name
Test status
Simulation time 1831215084 ps
CPU time 18.85 seconds
Started Sep 11 03:30:42 AM UTC 24
Finished Sep 11 03:31:02 AM UTC 24
Peak memory 228372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180883059 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3180883059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3094390041
Short name T211
Test name
Test status
Simulation time 11889244548 ps
CPU time 47.84 seconds
Started Sep 11 03:30:42 AM UTC 24
Finished Sep 11 03:31:31 AM UTC 24
Peak memory 228696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309439004
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.3094390041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.590649996
Short name T278
Test name
Test status
Simulation time 2572217128 ps
CPU time 174.69 seconds
Started Sep 11 03:30:46 AM UTC 24
Finished Sep 11 03:33:44 AM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=590649996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.rom_ctrl_stress_all_with_rand_reset.590649996
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2165126900
Short name T200
Test name
Test status
Simulation time 260255778 ps
CPU time 11.57 seconds
Started Sep 11 03:31:00 AM UTC 24
Finished Sep 11 03:31:12 AM UTC 24
Peak memory 227968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165126900 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2165126900
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2021187768
Short name T308
Test name
Test status
Simulation time 2737888144 ps
CPU time 200.73 seconds
Started Sep 11 03:30:53 AM UTC 24
Finished Sep 11 03:34:17 AM UTC 24
Peak memory 257444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021187768 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.2021187768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3653567356
Short name T206
Test name
Test status
Simulation time 2539602963 ps
CPU time 26.81 seconds
Started Sep 11 03:30:53 AM UTC 24
Finished Sep 11 03:31:21 AM UTC 24
Peak memory 228300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653567356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3653567356
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1682458035
Short name T199
Test name
Test status
Simulation time 261296004 ps
CPU time 15.93 seconds
Started Sep 11 03:30:50 AM UTC 24
Finished Sep 11 03:31:07 AM UTC 24
Peak memory 228084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682458035 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1682458035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1004402570
Short name T201
Test name
Test status
Simulation time 209197999 ps
CPU time 22.85 seconds
Started Sep 11 03:30:48 AM UTC 24
Finished Sep 11 03:31:13 AM UTC 24
Peak memory 228824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100440257
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.1004402570
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2254428738
Short name T223
Test name
Test status
Simulation time 22139857767 ps
CPU time 79.79 seconds
Started Sep 11 03:30:55 AM UTC 24
Finished Sep 11 03:32:17 AM UTC 24
Peak memory 246352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2254428738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2254428738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3375297130
Short name T204
Test name
Test status
Simulation time 360755050 ps
CPU time 11.05 seconds
Started Sep 11 03:31:06 AM UTC 24
Finished Sep 11 03:31:18 AM UTC 24
Peak memory 228060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375297130 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3375297130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.223963701
Short name T339
Test name
Test status
Simulation time 15432495459 ps
CPU time 293.74 seconds
Started Sep 11 03:31:03 AM UTC 24
Finished Sep 11 03:36:01 AM UTC 24
Peak memory 256552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223963701 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.223963701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2853900859
Short name T214
Test name
Test status
Simulation time 2751957760 ps
CPU time 34.65 seconds
Started Sep 11 03:31:03 AM UTC 24
Finished Sep 11 03:31:39 AM UTC 24
Peak memory 228664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853900859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2853900859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2783957266
Short name T202
Test name
Test status
Simulation time 238601217 ps
CPU time 11.53 seconds
Started Sep 11 03:31:01 AM UTC 24
Finished Sep 11 03:31:13 AM UTC 24
Peak memory 228148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783957266 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2783957266
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.709939215
Short name T250
Test name
Test status
Simulation time 5152099553 ps
CPU time 120.61 seconds
Started Sep 11 03:31:05 AM UTC 24
Finished Sep 11 03:33:08 AM UTC 24
Peak memory 232928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=709939215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.rom_ctrl_stress_all_with_rand_reset.709939215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3844270895
Short name T210
Test name
Test status
Simulation time 360444758 ps
CPU time 12.08 seconds
Started Sep 11 03:31:15 AM UTC 24
Finished Sep 11 03:31:28 AM UTC 24
Peak memory 227672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844270895 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3844270895
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3364773558
Short name T286
Test name
Test status
Simulation time 5560176385 ps
CPU time 153.81 seconds
Started Sep 11 03:31:13 AM UTC 24
Finished Sep 11 03:33:50 AM UTC 24
Peak memory 258916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364773558 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.3364773558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3081550781
Short name T216
Test name
Test status
Simulation time 346315251 ps
CPU time 25.37 seconds
Started Sep 11 03:31:13 AM UTC 24
Finished Sep 11 03:31:40 AM UTC 24
Peak memory 228692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081550781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3081550781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.574849087
Short name T209
Test name
Test status
Simulation time 270575442 ps
CPU time 16.56 seconds
Started Sep 11 03:31:08 AM UTC 24
Finished Sep 11 03:31:26 AM UTC 24
Peak memory 228152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574849087 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.574849087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.3455335116
Short name T208
Test name
Test status
Simulation time 294186389 ps
CPU time 18.48 seconds
Started Sep 11 03:31:06 AM UTC 24
Finished Sep 11 03:31:26 AM UTC 24
Peak memory 225536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345533511
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.3455335116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3540413028
Short name T213
Test name
Test status
Simulation time 174212616 ps
CPU time 8.83 seconds
Started Sep 11 03:31:27 AM UTC 24
Finished Sep 11 03:31:37 AM UTC 24
Peak memory 227736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540413028 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3540413028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3979710626
Short name T333
Test name
Test status
Simulation time 6702031913 ps
CPU time 250.87 seconds
Started Sep 11 03:31:19 AM UTC 24
Finished Sep 11 03:35:33 AM UTC 24
Peak memory 227912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979710626 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.3979710626
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3613701679
Short name T111
Test name
Test status
Simulation time 504879992 ps
CPU time 28.68 seconds
Started Sep 11 03:31:22 AM UTC 24
Finished Sep 11 03:31:52 AM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613701679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3613701679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.3596001283
Short name T212
Test name
Test status
Simulation time 270004417 ps
CPU time 15.45 seconds
Started Sep 11 03:31:19 AM UTC 24
Finished Sep 11 03:31:35 AM UTC 24
Peak memory 228152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596001283 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3596001283
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.48345822
Short name T215
Test name
Test status
Simulation time 664153299 ps
CPU time 22.92 seconds
Started Sep 11 03:31:16 AM UTC 24
Finished Sep 11 03:31:40 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48345822
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.48345822
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2629186727
Short name T343
Test name
Test status
Simulation time 4839823922 ps
CPU time 291.12 seconds
Started Sep 11 03:31:26 AM UTC 24
Finished Sep 11 03:36:21 AM UTC 24
Peak memory 239400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2629186727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2629186727
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.3223179359
Short name T110
Test name
Test status
Simulation time 281885053 ps
CPU time 11.99 seconds
Started Sep 11 03:31:37 AM UTC 24
Finished Sep 11 03:31:51 AM UTC 24
Peak memory 228388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223179359 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3223179359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.815331361
Short name T361
Test name
Test status
Simulation time 4627985051 ps
CPU time 405.33 seconds
Started Sep 11 03:31:28 AM UTC 24
Finished Sep 11 03:38:19 AM UTC 24
Peak memory 259484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815331361 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.815331361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2401265969
Short name T112
Test name
Test status
Simulation time 678184109 ps
CPU time 19.66 seconds
Started Sep 11 03:31:32 AM UTC 24
Finished Sep 11 03:31:53 AM UTC 24
Peak memory 228884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401265969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2401265969
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1427289534
Short name T217
Test name
Test status
Simulation time 692653090 ps
CPU time 15.63 seconds
Started Sep 11 03:31:28 AM UTC 24
Finished Sep 11 03:31:45 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427289534 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1427289534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.3823462478
Short name T218
Test name
Test status
Simulation time 2148395766 ps
CPU time 40.09 seconds
Started Sep 11 03:31:27 AM UTC 24
Finished Sep 11 03:32:09 AM UTC 24
Peak memory 228776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382346247
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.3823462478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2607569695
Short name T331
Test name
Test status
Simulation time 12760606172 ps
CPU time 197.77 seconds
Started Sep 11 03:31:36 AM UTC 24
Finished Sep 11 03:34:57 AM UTC 24
Peak memory 239072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2607569695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2607569695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1360186376
Short name T8
Test name
Test status
Simulation time 174585112 ps
CPU time 8.41 seconds
Started Sep 11 03:28:46 AM UTC 24
Finished Sep 11 03:28:56 AM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360186376 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1360186376
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.319228787
Short name T25
Test name
Test status
Simulation time 1672223482 ps
CPU time 137.15 seconds
Started Sep 11 03:28:46 AM UTC 24
Finished Sep 11 03:31:06 AM UTC 24
Peak memory 257620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319228787 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.319228787
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3266785739
Short name T13
Test name
Test status
Simulation time 555259241 ps
CPU time 22.21 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:29:08 AM UTC 24
Peak memory 228624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326678573
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.3266785739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2836957783
Short name T42
Test name
Test status
Simulation time 1807805771 ps
CPU time 113.91 seconds
Started Sep 11 03:28:44 AM UTC 24
Finished Sep 11 03:30:40 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2836957783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2836957783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1534351716
Short name T115
Test name
Test status
Simulation time 1773846263 ps
CPU time 8.87 seconds
Started Sep 11 03:31:52 AM UTC 24
Finished Sep 11 03:32:02 AM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534351716 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1534351716
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2137315471
Short name T304
Test name
Test status
Simulation time 2170072370 ps
CPU time 147.32 seconds
Started Sep 11 03:31:41 AM UTC 24
Finished Sep 11 03:34:10 AM UTC 24
Peak memory 257412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137315471 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.2137315471
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.1726283658
Short name T41
Test name
Test status
Simulation time 510897135 ps
CPU time 34.34 seconds
Started Sep 11 03:31:46 AM UTC 24
Finished Sep 11 03:32:22 AM UTC 24
Peak memory 228576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726283658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1726283658
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.4146702506
Short name T113
Test name
Test status
Simulation time 727833413 ps
CPU time 15.19 seconds
Started Sep 11 03:31:41 AM UTC 24
Finished Sep 11 03:31:57 AM UTC 24
Peak memory 228392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146702506 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4146702506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3073539576
Short name T222
Test name
Test status
Simulation time 1440800546 ps
CPU time 35.35 seconds
Started Sep 11 03:31:39 AM UTC 24
Finished Sep 11 03:32:16 AM UTC 24
Peak memory 228712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307353957
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.3073539576
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1269585604
Short name T298
Test name
Test status
Simulation time 2660847763 ps
CPU time 134.05 seconds
Started Sep 11 03:31:48 AM UTC 24
Finished Sep 11 03:34:04 AM UTC 24
Peak memory 238988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1269585604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1269585604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2272519984
Short name T221
Test name
Test status
Simulation time 1028822372 ps
CPU time 13.38 seconds
Started Sep 11 03:31:58 AM UTC 24
Finished Sep 11 03:32:13 AM UTC 24
Peak memory 228172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272519984 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2272519984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.372040996
Short name T335
Test name
Test status
Simulation time 3511154693 ps
CPU time 223.78 seconds
Started Sep 11 03:31:54 AM UTC 24
Finished Sep 11 03:35:42 AM UTC 24
Peak memory 227696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372040996 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.372040996
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3921180596
Short name T228
Test name
Test status
Simulation time 336098885 ps
CPU time 28.82 seconds
Started Sep 11 03:31:58 AM UTC 24
Finished Sep 11 03:32:29 AM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921180596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3921180596
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2565325073
Short name T220
Test name
Test status
Simulation time 354717558 ps
CPU time 15.44 seconds
Started Sep 11 03:31:54 AM UTC 24
Finished Sep 11 03:32:11 AM UTC 24
Peak memory 228436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565325073 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2565325073
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2630364899
Short name T232
Test name
Test status
Simulation time 1352866714 ps
CPU time 40.97 seconds
Started Sep 11 03:31:53 AM UTC 24
Finished Sep 11 03:32:35 AM UTC 24
Peak memory 228824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263036489
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.2630364899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.326269370
Short name T347
Test name
Test status
Simulation time 79352268197 ps
CPU time 280.25 seconds
Started Sep 11 03:31:58 AM UTC 24
Finished Sep 11 03:36:43 AM UTC 24
Peak memory 246352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=326269370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_stress_all_with_rand_reset.326269370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.4031938413
Short name T225
Test name
Test status
Simulation time 499364163 ps
CPU time 9.28 seconds
Started Sep 11 03:32:12 AM UTC 24
Finished Sep 11 03:32:22 AM UTC 24
Peak memory 227948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031938413 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4031938413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2505344681
Short name T341
Test name
Test status
Simulation time 45709484778 ps
CPU time 246.45 seconds
Started Sep 11 03:32:05 AM UTC 24
Finished Sep 11 03:36:15 AM UTC 24
Peak memory 259556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505344681 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.2505344681
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.190269682
Short name T234
Test name
Test status
Simulation time 662584081 ps
CPU time 26.27 seconds
Started Sep 11 03:32:09 AM UTC 24
Finished Sep 11 03:32:37 AM UTC 24
Peak memory 228632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190269682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.190269682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.811062881
Short name T224
Test name
Test status
Simulation time 1841472648 ps
CPU time 13.16 seconds
Started Sep 11 03:32:03 AM UTC 24
Finished Sep 11 03:32:18 AM UTC 24
Peak memory 228384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811062881 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.811062881
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2957026857
Short name T239
Test name
Test status
Simulation time 844755673 ps
CPU time 43.73 seconds
Started Sep 11 03:32:02 AM UTC 24
Finished Sep 11 03:32:47 AM UTC 24
Peak memory 228712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295702685
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.2957026857
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.4240222792
Short name T342
Test name
Test status
Simulation time 4471227432 ps
CPU time 244.13 seconds
Started Sep 11 03:32:10 AM UTC 24
Finished Sep 11 03:36:19 AM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4240222792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.rom_ctrl_stress_all_with_rand_reset.4240222792
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.3265146401
Short name T231
Test name
Test status
Simulation time 254647559 ps
CPU time 8.87 seconds
Started Sep 11 03:32:23 AM UTC 24
Finished Sep 11 03:32:33 AM UTC 24
Peak memory 228116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265146401 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3265146401
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.435175187
Short name T351
Test name
Test status
Simulation time 19526657082 ps
CPU time 280.18 seconds
Started Sep 11 03:32:18 AM UTC 24
Finished Sep 11 03:37:02 AM UTC 24
Peak memory 228256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435175187 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.435175187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2822718104
Short name T236
Test name
Test status
Simulation time 2243297500 ps
CPU time 23.45 seconds
Started Sep 11 03:32:19 AM UTC 24
Finished Sep 11 03:32:44 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822718104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2822718104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.192168307
Short name T229
Test name
Test status
Simulation time 272005917 ps
CPU time 12.7 seconds
Started Sep 11 03:32:17 AM UTC 24
Finished Sep 11 03:32:31 AM UTC 24
Peak memory 228112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192168307 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.192168307
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3935021395
Short name T240
Test name
Test status
Simulation time 1056013741 ps
CPU time 35.46 seconds
Started Sep 11 03:32:14 AM UTC 24
Finished Sep 11 03:32:51 AM UTC 24
Peak memory 228824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393502139
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.3935021395
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3944125369
Short name T292
Test name
Test status
Simulation time 47463251064 ps
CPU time 92.89 seconds
Started Sep 11 03:32:23 AM UTC 24
Finished Sep 11 03:33:58 AM UTC 24
Peak memory 241248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3944125369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3944125369
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.728175448
Short name T238
Test name
Test status
Simulation time 1030421163 ps
CPU time 13.69 seconds
Started Sep 11 03:32:32 AM UTC 24
Finished Sep 11 03:32:47 AM UTC 24
Peak memory 227768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728175448 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.728175448
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3784139510
Short name T353
Test name
Test status
Simulation time 3734124685 ps
CPU time 273.81 seconds
Started Sep 11 03:32:29 AM UTC 24
Finished Sep 11 03:37:07 AM UTC 24
Peak memory 244684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784139510 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.3784139510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.320657211
Short name T243
Test name
Test status
Simulation time 692930916 ps
CPU time 23.99 seconds
Started Sep 11 03:32:31 AM UTC 24
Finished Sep 11 03:32:56 AM UTC 24
Peak memory 225456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320657211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.320657211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.1959340000
Short name T237
Test name
Test status
Simulation time 538497201 ps
CPU time 18.19 seconds
Started Sep 11 03:32:27 AM UTC 24
Finished Sep 11 03:32:47 AM UTC 24
Peak memory 228140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959340000 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1959340000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1491441934
Short name T249
Test name
Test status
Simulation time 2332789857 ps
CPU time 38.57 seconds
Started Sep 11 03:32:24 AM UTC 24
Finished Sep 11 03:33:04 AM UTC 24
Peak memory 228696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149144193
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.1491441934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.951299049
Short name T144
Test name
Test status
Simulation time 13762266393 ps
CPU time 121.65 seconds
Started Sep 11 03:32:31 AM UTC 24
Finished Sep 11 03:34:35 AM UTC 24
Peak memory 246352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=951299049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.rom_ctrl_stress_all_with_rand_reset.951299049
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3649418263
Short name T242
Test name
Test status
Simulation time 333517413 ps
CPU time 13.21 seconds
Started Sep 11 03:32:40 AM UTC 24
Finished Sep 11 03:32:55 AM UTC 24
Peak memory 227672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649418263 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3649418263
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3162135330
Short name T338
Test name
Test status
Simulation time 2752482037 ps
CPU time 199.1 seconds
Started Sep 11 03:32:38 AM UTC 24
Finished Sep 11 03:36:00 AM UTC 24
Peak memory 244536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162135330 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.3162135330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.2342988206
Short name T246
Test name
Test status
Simulation time 1381661637 ps
CPU time 21.47 seconds
Started Sep 11 03:32:38 AM UTC 24
Finished Sep 11 03:33:00 AM UTC 24
Peak memory 228236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342988206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2342988206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3667282027
Short name T241
Test name
Test status
Simulation time 259808938 ps
CPU time 15.15 seconds
Started Sep 11 03:32:37 AM UTC 24
Finished Sep 11 03:32:53 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667282027 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3667282027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1057946186
Short name T258
Test name
Test status
Simulation time 563505584 ps
CPU time 42.25 seconds
Started Sep 11 03:32:33 AM UTC 24
Finished Sep 11 03:33:17 AM UTC 24
Peak memory 228632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105794618
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.1057946186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4109220024
Short name T322
Test name
Test status
Simulation time 6195710212 ps
CPU time 113.45 seconds
Started Sep 11 03:32:39 AM UTC 24
Finished Sep 11 03:34:35 AM UTC 24
Peak memory 239072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4109220024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.4109220024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3172450432
Short name T248
Test name
Test status
Simulation time 260467720 ps
CPU time 13.34 seconds
Started Sep 11 03:32:49 AM UTC 24
Finished Sep 11 03:33:03 AM UTC 24
Peak memory 227780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172450432 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3172450432
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2335190629
Short name T349
Test name
Test status
Simulation time 6348762423 ps
CPU time 246.31 seconds
Started Sep 11 03:32:47 AM UTC 24
Finished Sep 11 03:36:57 AM UTC 24
Peak memory 259596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335190629 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.2335190629
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.3032558769
Short name T256
Test name
Test status
Simulation time 1770008572 ps
CPU time 27.92 seconds
Started Sep 11 03:32:48 AM UTC 24
Finished Sep 11 03:33:17 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032558769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3032558769
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.601003682
Short name T245
Test name
Test status
Simulation time 182737189 ps
CPU time 14.23 seconds
Started Sep 11 03:32:44 AM UTC 24
Finished Sep 11 03:33:00 AM UTC 24
Peak memory 228364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601003682 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.601003682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3624585851
Short name T265
Test name
Test status
Simulation time 567482315 ps
CPU time 36.15 seconds
Started Sep 11 03:32:44 AM UTC 24
Finished Sep 11 03:33:22 AM UTC 24
Peak memory 228632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362458585
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.3624585851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.677755378
Short name T332
Test name
Test status
Simulation time 14241329999 ps
CPU time 136.92 seconds
Started Sep 11 03:32:49 AM UTC 24
Finished Sep 11 03:35:08 AM UTC 24
Peak memory 234976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=677755378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.rom_ctrl_stress_all_with_rand_reset.677755378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.2789759004
Short name T251
Test name
Test status
Simulation time 987522787 ps
CPU time 12.07 seconds
Started Sep 11 03:32:55 AM UTC 24
Finished Sep 11 03:33:08 AM UTC 24
Peak memory 227956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789759004 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2789759004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2131545709
Short name T336
Test name
Test status
Simulation time 2361906811 ps
CPU time 169.33 seconds
Started Sep 11 03:32:51 AM UTC 24
Finished Sep 11 03:35:43 AM UTC 24
Peak memory 257444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131545709 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.2131545709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3712398838
Short name T261
Test name
Test status
Simulation time 333945726 ps
CPU time 27.13 seconds
Started Sep 11 03:32:52 AM UTC 24
Finished Sep 11 03:33:20 AM UTC 24
Peak memory 228004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712398838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3712398838
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.729283104
Short name T247
Test name
Test status
Simulation time 2136262761 ps
CPU time 11.96 seconds
Started Sep 11 03:32:49 AM UTC 24
Finished Sep 11 03:33:02 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729283104 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.729283104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.570876582
Short name T252
Test name
Test status
Simulation time 297087392 ps
CPU time 23.33 seconds
Started Sep 11 03:32:49 AM UTC 24
Finished Sep 11 03:33:13 AM UTC 24
Peak memory 228896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570876582
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.570876582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2740069137
Short name T277
Test name
Test status
Simulation time 964036531 ps
CPU time 48.56 seconds
Started Sep 11 03:32:54 AM UTC 24
Finished Sep 11 03:33:44 AM UTC 24
Peak memory 235040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2740069137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2740069137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.706535198
Short name T255
Test name
Test status
Simulation time 498062248 ps
CPU time 13.39 seconds
Started Sep 11 03:33:01 AM UTC 24
Finished Sep 11 03:33:16 AM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706535198 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.706535198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.223779873
Short name T359
Test name
Test status
Simulation time 4336013410 ps
CPU time 294.95 seconds
Started Sep 11 03:32:59 AM UTC 24
Finished Sep 11 03:37:58 AM UTC 24
Peak memory 258740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223779873 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.223779873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3336519655
Short name T264
Test name
Test status
Simulation time 1319265171 ps
CPU time 20.29 seconds
Started Sep 11 03:33:00 AM UTC 24
Finished Sep 11 03:33:22 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336519655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3336519655
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2785693964
Short name T253
Test name
Test status
Simulation time 5178634172 ps
CPU time 16.33 seconds
Started Sep 11 03:32:57 AM UTC 24
Finished Sep 11 03:33:15 AM UTC 24
Peak memory 228808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785693964 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2785693964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.784494341
Short name T290
Test name
Test status
Simulation time 2800914184 ps
CPU time 57.78 seconds
Started Sep 11 03:32:57 AM UTC 24
Finished Sep 11 03:33:57 AM UTC 24
Peak memory 228728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784494341
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.784494341
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.240950823
Short name T329
Test name
Test status
Simulation time 1946248463 ps
CPU time 109.83 seconds
Started Sep 11 03:33:01 AM UTC 24
Finished Sep 11 03:34:53 AM UTC 24
Peak memory 239008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=240950823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.rom_ctrl_stress_all_with_rand_reset.240950823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.304692809
Short name T262
Test name
Test status
Simulation time 570556652 ps
CPU time 10.38 seconds
Started Sep 11 03:33:09 AM UTC 24
Finished Sep 11 03:33:20 AM UTC 24
Peak memory 227468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304692809 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.304692809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3527592655
Short name T365
Test name
Test status
Simulation time 17542189204 ps
CPU time 431.8 seconds
Started Sep 11 03:33:04 AM UTC 24
Finished Sep 11 03:40:21 AM UTC 24
Peak memory 261492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527592655 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.3527592655
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1460897120
Short name T267
Test name
Test status
Simulation time 945409964 ps
CPU time 22.71 seconds
Started Sep 11 03:33:05 AM UTC 24
Finished Sep 11 03:33:29 AM UTC 24
Peak memory 228300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460897120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1460897120
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2194833230
Short name T263
Test name
Test status
Simulation time 263717737 ps
CPU time 16.75 seconds
Started Sep 11 03:33:04 AM UTC 24
Finished Sep 11 03:33:21 AM UTC 24
Peak memory 228092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194833230 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2194833230
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.4129617964
Short name T275
Test name
Test status
Simulation time 537592873 ps
CPU time 37.59 seconds
Started Sep 11 03:33:02 AM UTC 24
Finished Sep 11 03:33:41 AM UTC 24
Peak memory 228712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412961796
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.4129617964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4191518633
Short name T293
Test name
Test status
Simulation time 24701885992 ps
CPU time 51.95 seconds
Started Sep 11 03:33:06 AM UTC 24
Finished Sep 11 03:33:59 AM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4191518633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.4191518633
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2824548064
Short name T56
Test name
Test status
Simulation time 1123374880 ps
CPU time 10.3 seconds
Started Sep 11 03:28:52 AM UTC 24
Finished Sep 11 03:29:04 AM UTC 24
Peak memory 227992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824548064 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2824548064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.4179464421
Short name T51
Test name
Test status
Simulation time 1034121684 ps
CPU time 23.74 seconds
Started Sep 11 03:28:49 AM UTC 24
Finished Sep 11 03:29:14 AM UTC 24
Peak memory 228632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179464421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4179464421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.4117908518
Short name T55
Test name
Test status
Simulation time 512740988 ps
CPU time 14.53 seconds
Started Sep 11 03:28:48 AM UTC 24
Finished Sep 11 03:29:03 AM UTC 24
Peak memory 228084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117908518 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4117908518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2455368801
Short name T26
Test name
Test status
Simulation time 1116060629 ps
CPU time 245.01 seconds
Started Sep 11 03:28:51 AM UTC 24
Finished Sep 11 03:33:00 AM UTC 24
Peak memory 258516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455368801 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2455368801
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.91116383
Short name T19
Test name
Test status
Simulation time 697981590 ps
CPU time 11.94 seconds
Started Sep 11 03:28:46 AM UTC 24
Finished Sep 11 03:28:59 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91116383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_
TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.91116383
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3438513084
Short name T31
Test name
Test status
Simulation time 4196896216 ps
CPU time 29.9 seconds
Started Sep 11 03:28:46 AM UTC 24
Finished Sep 11 03:29:17 AM UTC 24
Peak memory 228688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343851308
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.3438513084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1637462241
Short name T235
Test name
Test status
Simulation time 6055319911 ps
CPU time 226.28 seconds
Started Sep 11 03:28:50 AM UTC 24
Finished Sep 11 03:32:40 AM UTC 24
Peak memory 246608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1637462241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1637462241
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.2833270894
Short name T266
Test name
Test status
Simulation time 660897437 ps
CPU time 10.38 seconds
Started Sep 11 03:33:17 AM UTC 24
Finished Sep 11 03:33:29 AM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833270894 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2833270894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.865295828
Short name T356
Test name
Test status
Simulation time 9374013568 ps
CPU time 255.93 seconds
Started Sep 11 03:33:15 AM UTC 24
Finished Sep 11 03:37:34 AM UTC 24
Peak memory 259476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865295828 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.865295828
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2065128130
Short name T280
Test name
Test status
Simulation time 345727524 ps
CPU time 28.39 seconds
Started Sep 11 03:33:16 AM UTC 24
Finished Sep 11 03:33:46 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065128130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2065128130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.577264152
Short name T269
Test name
Test status
Simulation time 259490769 ps
CPU time 17.44 seconds
Started Sep 11 03:33:14 AM UTC 24
Finished Sep 11 03:33:33 AM UTC 24
Peak memory 228376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577264152 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.577264152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.163621690
Short name T279
Test name
Test status
Simulation time 657350120 ps
CPU time 34.84 seconds
Started Sep 11 03:33:09 AM UTC 24
Finished Sep 11 03:33:45 AM UTC 24
Peak memory 228896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163621690
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.163621690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1925796737
Short name T337
Test name
Test status
Simulation time 34536749323 ps
CPU time 145.51 seconds
Started Sep 11 03:33:17 AM UTC 24
Finished Sep 11 03:35:45 AM UTC 24
Peak memory 246352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1925796737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1925796737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2999035734
Short name T272
Test name
Test status
Simulation time 293152303 ps
CPU time 13.58 seconds
Started Sep 11 03:33:22 AM UTC 24
Finished Sep 11 03:33:36 AM UTC 24
Peak memory 227672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999035734 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2999035734
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1176087932
Short name T345
Test name
Test status
Simulation time 22605399154 ps
CPU time 192.06 seconds
Started Sep 11 03:33:19 AM UTC 24
Finished Sep 11 03:36:35 AM UTC 24
Peak memory 228812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176087932 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.1176087932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1270212941
Short name T284
Test name
Test status
Simulation time 340237601 ps
CPU time 26.49 seconds
Started Sep 11 03:33:20 AM UTC 24
Finished Sep 11 03:33:48 AM UTC 24
Peak memory 228176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270212941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1270212941
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1325478768
Short name T273
Test name
Test status
Simulation time 261032835 ps
CPU time 16.83 seconds
Started Sep 11 03:33:18 AM UTC 24
Finished Sep 11 03:33:36 AM UTC 24
Peak memory 228428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325478768 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1325478768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4026814980
Short name T276
Test name
Test status
Simulation time 1609542647 ps
CPU time 24.13 seconds
Started Sep 11 03:33:17 AM UTC 24
Finished Sep 11 03:33:43 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402681498
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.4026814980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3623286566
Short name T363
Test name
Test status
Simulation time 37231286846 ps
CPU time 340.2 seconds
Started Sep 11 03:33:22 AM UTC 24
Finished Sep 11 03:39:06 AM UTC 24
Peak memory 243360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3623286566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3623286566
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.844989404
Short name T282
Test name
Test status
Simulation time 257991437 ps
CPU time 14.06 seconds
Started Sep 11 03:33:32 AM UTC 24
Finished Sep 11 03:33:47 AM UTC 24
Peak memory 227920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844989404 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.844989404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1813972189
Short name T340
Test name
Test status
Simulation time 8789544662 ps
CPU time 157.65 seconds
Started Sep 11 03:33:23 AM UTC 24
Finished Sep 11 03:36:03 AM UTC 24
Peak memory 244732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813972189 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.1813972189
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3948863214
Short name T288
Test name
Test status
Simulation time 336036865 ps
CPU time 21.48 seconds
Started Sep 11 03:33:30 AM UTC 24
Finished Sep 11 03:33:53 AM UTC 24
Peak memory 227940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948863214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3948863214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.862113424
Short name T271
Test name
Test status
Simulation time 729544427 ps
CPU time 11.59 seconds
Started Sep 11 03:33:23 AM UTC 24
Finished Sep 11 03:33:35 AM UTC 24
Peak memory 228424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862113424 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.862113424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.4213869909
Short name T295
Test name
Test status
Simulation time 436668931 ps
CPU time 36.97 seconds
Started Sep 11 03:33:23 AM UTC 24
Finished Sep 11 03:34:01 AM UTC 24
Peak memory 228632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421386990
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.4213869909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1457672961
Short name T358
Test name
Test status
Simulation time 8159398016 ps
CPU time 262.38 seconds
Started Sep 11 03:33:30 AM UTC 24
Finished Sep 11 03:37:57 AM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1457672961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1457672961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.4076581595
Short name T289
Test name
Test status
Simulation time 340904429 ps
CPU time 10.73 seconds
Started Sep 11 03:33:41 AM UTC 24
Finished Sep 11 03:33:54 AM UTC 24
Peak memory 228108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076581595 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4076581595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1159427578
Short name T348
Test name
Test status
Simulation time 3786519609 ps
CPU time 186.36 seconds
Started Sep 11 03:33:36 AM UTC 24
Finished Sep 11 03:36:45 AM UTC 24
Peak memory 228496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159427578 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.1159427578
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3548669275
Short name T301
Test name
Test status
Simulation time 4948527372 ps
CPU time 28.24 seconds
Started Sep 11 03:33:37 AM UTC 24
Finished Sep 11 03:34:07 AM UTC 24
Peak memory 228324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548669275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3548669275
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.700261732
Short name T285
Test name
Test status
Simulation time 358923217 ps
CPU time 11.93 seconds
Started Sep 11 03:33:36 AM UTC 24
Finished Sep 11 03:33:49 AM UTC 24
Peak memory 228236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700261732 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.700261732
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3432241436
Short name T307
Test name
Test status
Simulation time 806835531 ps
CPU time 40.52 seconds
Started Sep 11 03:33:33 AM UTC 24
Finished Sep 11 03:34:15 AM UTC 24
Peak memory 228904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343224143
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.3432241436
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.279740861
Short name T147
Test name
Test status
Simulation time 16818103768 ps
CPU time 175.35 seconds
Started Sep 11 03:33:37 AM UTC 24
Finished Sep 11 03:36:35 AM UTC 24
Peak memory 241120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=279740861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.rom_ctrl_stress_all_with_rand_reset.279740861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3894491043
Short name T294
Test name
Test status
Simulation time 174733360 ps
CPU time 12.12 seconds
Started Sep 11 03:33:46 AM UTC 24
Finished Sep 11 03:34:00 AM UTC 24
Peak memory 228052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894491043 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3894491043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1480038764
Short name T357
Test name
Test status
Simulation time 14859193128 ps
CPU time 238.36 seconds
Started Sep 11 03:33:44 AM UTC 24
Finished Sep 11 03:37:45 AM UTC 24
Peak memory 244132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480038764 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.1480038764
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3645714935
Short name T306
Test name
Test status
Simulation time 512777075 ps
CPU time 28.57 seconds
Started Sep 11 03:33:45 AM UTC 24
Finished Sep 11 03:34:15 AM UTC 24
Peak memory 227940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645714935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3645714935
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.900248698
Short name T291
Test name
Test status
Simulation time 380329174 ps
CPU time 12.87 seconds
Started Sep 11 03:33:43 AM UTC 24
Finished Sep 11 03:33:57 AM UTC 24
Peak memory 228144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900248698 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.900248698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.693412939
Short name T300
Test name
Test status
Simulation time 293996736 ps
CPU time 21.01 seconds
Started Sep 11 03:33:42 AM UTC 24
Finished Sep 11 03:34:05 AM UTC 24
Peak memory 228624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693412939
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.693412939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2027635643
Short name T334
Test name
Test status
Simulation time 13306676779 ps
CPU time 110.2 seconds
Started Sep 11 03:33:45 AM UTC 24
Finished Sep 11 03:35:37 AM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2027635643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2027635643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3119454194
Short name T297
Test name
Test status
Simulation time 505904910 ps
CPU time 11.56 seconds
Started Sep 11 03:33:50 AM UTC 24
Finished Sep 11 03:34:03 AM UTC 24
Peak memory 227764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119454194 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3119454194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3809593440
Short name T360
Test name
Test status
Simulation time 8013596206 ps
CPU time 265.42 seconds
Started Sep 11 03:33:48 AM UTC 24
Finished Sep 11 03:38:17 AM UTC 24
Peak memory 256436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809593440 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.3809593440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3610124998
Short name T313
Test name
Test status
Simulation time 513620615 ps
CPU time 34.98 seconds
Started Sep 11 03:33:48 AM UTC 24
Finished Sep 11 03:34:25 AM UTC 24
Peak memory 228820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610124998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3610124998
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.347449699
Short name T296
Test name
Test status
Simulation time 352389205 ps
CPU time 14.32 seconds
Started Sep 11 03:33:47 AM UTC 24
Finished Sep 11 03:34:03 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347449699 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.347449699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1703551452
Short name T319
Test name
Test status
Simulation time 529660708 ps
CPU time 44.74 seconds
Started Sep 11 03:33:47 AM UTC 24
Finished Sep 11 03:34:34 AM UTC 24
Peak memory 228712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170355145
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.1703551452
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1806808303
Short name T318
Test name
Test status
Simulation time 15065845714 ps
CPU time 42.79 seconds
Started Sep 11 03:33:49 AM UTC 24
Finished Sep 11 03:34:34 AM UTC 24
Peak memory 239072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1806808303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1806808303
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1207551181
Short name T303
Test name
Test status
Simulation time 689468544 ps
CPU time 8.74 seconds
Started Sep 11 03:33:58 AM UTC 24
Finished Sep 11 03:34:07 AM UTC 24
Peak memory 228092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207551181 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1207551181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2537055548
Short name T362
Test name
Test status
Simulation time 70757672989 ps
CPU time 285.86 seconds
Started Sep 11 03:33:53 AM UTC 24
Finished Sep 11 03:38:43 AM UTC 24
Peak memory 258704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537055548 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.2537055548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2843752949
Short name T314
Test name
Test status
Simulation time 332421830 ps
CPU time 31.97 seconds
Started Sep 11 03:33:54 AM UTC 24
Finished Sep 11 03:34:28 AM UTC 24
Peak memory 228296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843752949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2843752949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2781319528
Short name T302
Test name
Test status
Simulation time 1026737202 ps
CPU time 14.7 seconds
Started Sep 11 03:33:51 AM UTC 24
Finished Sep 11 03:34:07 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781319528 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2781319528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3172345266
Short name T325
Test name
Test status
Simulation time 1653049198 ps
CPU time 47.54 seconds
Started Sep 11 03:33:50 AM UTC 24
Finished Sep 11 03:34:40 AM UTC 24
Peak memory 228708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317234526
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.3172345266
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2870093807
Short name T355
Test name
Test status
Simulation time 12915438416 ps
CPU time 200.14 seconds
Started Sep 11 03:33:58 AM UTC 24
Finished Sep 11 03:37:21 AM UTC 24
Peak memory 246348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2870093807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2870093807
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1535237133
Short name T311
Test name
Test status
Simulation time 881228815 ps
CPU time 13.9 seconds
Started Sep 11 03:34:04 AM UTC 24
Finished Sep 11 03:34:19 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535237133 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1535237133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2233595435
Short name T366
Test name
Test status
Simulation time 92643066113 ps
CPU time 420.82 seconds
Started Sep 11 03:34:01 AM UTC 24
Finished Sep 11 03:41:07 AM UTC 24
Peak memory 249312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233595435 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.2233595435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.1013882263
Short name T315
Test name
Test status
Simulation time 1374570442 ps
CPU time 24.79 seconds
Started Sep 11 03:34:02 AM UTC 24
Finished Sep 11 03:34:28 AM UTC 24
Peak memory 227932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013882263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1013882263
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1867490903
Short name T309
Test name
Test status
Simulation time 273676744 ps
CPU time 17.16 seconds
Started Sep 11 03:34:00 AM UTC 24
Finished Sep 11 03:34:18 AM UTC 24
Peak memory 228332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867490903 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1867490903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1744753244
Short name T305
Test name
Test status
Simulation time 194355156 ps
CPU time 11.75 seconds
Started Sep 11 03:33:59 AM UTC 24
Finished Sep 11 03:34:12 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174475324
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.1744753244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1164970548
Short name T354
Test name
Test status
Simulation time 10081470827 ps
CPU time 183.12 seconds
Started Sep 11 03:34:04 AM UTC 24
Finished Sep 11 03:37:10 AM UTC 24
Peak memory 235664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1164970548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1164970548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.2564450786
Short name T312
Test name
Test status
Simulation time 347094409 ps
CPU time 10.69 seconds
Started Sep 11 03:34:08 AM UTC 24
Finished Sep 11 03:34:20 AM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564450786 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2564450786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3700862640
Short name T364
Test name
Test status
Simulation time 5588862376 ps
CPU time 315.37 seconds
Started Sep 11 03:34:06 AM UTC 24
Finished Sep 11 03:39:26 AM UTC 24
Peak memory 258884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700862640 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.3700862640
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1538923776
Short name T324
Test name
Test status
Simulation time 991550166 ps
CPU time 28.35 seconds
Started Sep 11 03:34:07 AM UTC 24
Finished Sep 11 03:34:37 AM UTC 24
Peak memory 228320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538923776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1538923776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.183668663
Short name T310
Test name
Test status
Simulation time 731918650 ps
CPU time 12.72 seconds
Started Sep 11 03:34:05 AM UTC 24
Finished Sep 11 03:34:19 AM UTC 24
Peak memory 228708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183668663 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.183668663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3577904139
Short name T125
Test name
Test status
Simulation time 354565977 ps
CPU time 33.82 seconds
Started Sep 11 03:34:05 AM UTC 24
Finished Sep 11 03:34:40 AM UTC 24
Peak memory 228632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357790413
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.3577904139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2599082720
Short name T352
Test name
Test status
Simulation time 3167385687 ps
CPU time 171.62 seconds
Started Sep 11 03:34:08 AM UTC 24
Finished Sep 11 03:37:03 AM UTC 24
Peak memory 245472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2599082720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2599082720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1215339901
Short name T321
Test name
Test status
Simulation time 257943553 ps
CPU time 14.38 seconds
Started Sep 11 03:34:19 AM UTC 24
Finished Sep 11 03:34:34 AM UTC 24
Peak memory 227948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215339901 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1215339901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3483888012
Short name T350
Test name
Test status
Simulation time 4870081847 ps
CPU time 161.75 seconds
Started Sep 11 03:34:16 AM UTC 24
Finished Sep 11 03:37:00 AM UTC 24
Peak memory 246076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483888012 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.3483888012
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1762747197
Short name T328
Test name
Test status
Simulation time 2059964649 ps
CPU time 31.09 seconds
Started Sep 11 03:34:16 AM UTC 24
Finished Sep 11 03:34:48 AM UTC 24
Peak memory 225344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762747197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1762747197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.952648391
Short name T317
Test name
Test status
Simulation time 1365279849 ps
CPU time 16.7 seconds
Started Sep 11 03:34:13 AM UTC 24
Finished Sep 11 03:34:30 AM UTC 24
Peak memory 228692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952648391 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.952648391
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.4029588175
Short name T326
Test name
Test status
Simulation time 1195930077 ps
CPU time 28.54 seconds
Started Sep 11 03:34:11 AM UTC 24
Finished Sep 11 03:34:41 AM UTC 24
Peak memory 223340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402958817
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.4029588175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3221784813
Short name T344
Test name
Test status
Simulation time 14701820707 ps
CPU time 132.53 seconds
Started Sep 11 03:34:18 AM UTC 24
Finished Sep 11 03:36:33 AM UTC 24
Peak memory 239260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3221784813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3221784813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2576914794
Short name T57
Test name
Test status
Simulation time 614348280 ps
CPU time 8.44 seconds
Started Sep 11 03:28:56 AM UTC 24
Finished Sep 11 03:29:06 AM UTC 24
Peak memory 228056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576914794 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2576914794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2891686771
Short name T22
Test name
Test status
Simulation time 7759348166 ps
CPU time 178.56 seconds
Started Sep 11 03:28:55 AM UTC 24
Finished Sep 11 03:31:57 AM UTC 24
Peak memory 259484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891686771 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.2891686771
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1710002239
Short name T52
Test name
Test status
Simulation time 350615760 ps
CPU time 20.37 seconds
Started Sep 11 03:28:56 AM UTC 24
Finished Sep 11 03:29:18 AM UTC 24
Peak memory 228232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710002239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1710002239
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3487187983
Short name T59
Test name
Test status
Simulation time 728622722 ps
CPU time 16.37 seconds
Started Sep 11 03:28:55 AM UTC 24
Finished Sep 11 03:29:13 AM UTC 24
Peak memory 228372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487187983 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3487187983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.932784156
Short name T63
Test name
Test status
Simulation time 2108118872 ps
CPU time 30.93 seconds
Started Sep 11 03:28:53 AM UTC 24
Finished Sep 11 03:29:26 AM UTC 24
Peak memory 228640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932784156
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.932784156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1111362843
Short name T40
Test name
Test status
Simulation time 20910556218 ps
CPU time 102.06 seconds
Started Sep 11 03:28:56 AM UTC 24
Finished Sep 11 03:30:40 AM UTC 24
Peak memory 246608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1111362843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1111362843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1604246226
Short name T83
Test name
Test status
Simulation time 985779577 ps
CPU time 11.67 seconds
Started Sep 11 03:29:01 AM UTC 24
Finished Sep 11 03:29:14 AM UTC 24
Peak memory 227952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604246226 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1604246226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.373532533
Short name T49
Test name
Test status
Simulation time 14439619275 ps
CPU time 224.5 seconds
Started Sep 11 03:29:00 AM UTC 24
Finished Sep 11 03:32:48 AM UTC 24
Peak memory 247292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373532533 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.373532533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3168781103
Short name T53
Test name
Test status
Simulation time 333839662 ps
CPU time 23.33 seconds
Started Sep 11 03:29:00 AM UTC 24
Finished Sep 11 03:29:24 AM UTC 24
Peak memory 227936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168781103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3168781103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3660152496
Short name T58
Test name
Test status
Simulation time 270907810 ps
CPU time 11.77 seconds
Started Sep 11 03:28:59 AM UTC 24
Finished Sep 11 03:29:11 AM UTC 24
Peak memory 228148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660152496 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3660152496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1319190966
Short name T18
Test name
Test status
Simulation time 714193356 ps
CPU time 15.64 seconds
Started Sep 11 03:28:57 AM UTC 24
Finished Sep 11 03:29:14 AM UTC 24
Peak memory 225524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319190966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1319190966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.376536836
Short name T71
Test name
Test status
Simulation time 1550369213 ps
CPU time 43.44 seconds
Started Sep 11 03:28:57 AM UTC 24
Finished Sep 11 03:29:42 AM UTC 24
Peak memory 228900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376536836
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.376536836
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2030992477
Short name T244
Test name
Test status
Simulation time 18245096441 ps
CPU time 233.64 seconds
Started Sep 11 03:29:01 AM UTC 24
Finished Sep 11 03:32:58 AM UTC 24
Peak memory 238160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2030992477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2030992477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.844491998
Short name T84
Test name
Test status
Simulation time 1031357920 ps
CPU time 9.57 seconds
Started Sep 11 03:29:06 AM UTC 24
Finished Sep 11 03:29:17 AM UTC 24
Peak memory 227788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844491998 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.844491998
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.78958926
Short name T268
Test name
Test status
Simulation time 52496020037 ps
CPU time 263.61 seconds
Started Sep 11 03:29:04 AM UTC 24
Finished Sep 11 03:33:31 AM UTC 24
Peak memory 261440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78958926 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.78958926
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.150388410
Short name T34
Test name
Test status
Simulation time 1984419932 ps
CPU time 22.11 seconds
Started Sep 11 03:29:05 AM UTC 24
Finished Sep 11 03:29:28 AM UTC 24
Peak memory 228632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150388410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.150388410
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1707719827
Short name T148
Test name
Test status
Simulation time 262434625 ps
CPU time 16.09 seconds
Started Sep 11 03:29:03 AM UTC 24
Finished Sep 11 03:29:20 AM UTC 24
Peak memory 228420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707719827 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1707719827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1982196956
Short name T62
Test name
Test status
Simulation time 186498584 ps
CPU time 13.66 seconds
Started Sep 11 03:29:01 AM UTC 24
Finished Sep 11 03:29:16 AM UTC 24
Peak memory 225860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982196956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1982196956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1501609269
Short name T149
Test name
Test status
Simulation time 2427745756 ps
CPU time 22.23 seconds
Started Sep 11 03:29:02 AM UTC 24
Finished Sep 11 03:29:26 AM UTC 24
Peak memory 227704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150160926
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.1501609269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3218779911
Short name T16
Test name
Test status
Simulation time 1110815100 ps
CPU time 48.54 seconds
Started Sep 11 03:29:06 AM UTC 24
Finished Sep 11 03:29:56 AM UTC 24
Peak memory 230816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3218779911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3218779911
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1383148454
Short name T85
Test name
Test status
Simulation time 972068545 ps
CPU time 12.51 seconds
Started Sep 11 03:29:11 AM UTC 24
Finished Sep 11 03:29:25 AM UTC 24
Peak memory 228184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383148454 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1383148454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4232189573
Short name T260
Test name
Test status
Simulation time 20493920703 ps
CPU time 247.86 seconds
Started Sep 11 03:29:09 AM UTC 24
Finished Sep 11 03:33:20 AM UTC 24
Peak memory 246564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232189573 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.4232189573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.801169411
Short name T150
Test name
Test status
Simulation time 1111630259 ps
CPU time 16.1 seconds
Started Sep 11 03:29:09 AM UTC 24
Finished Sep 11 03:29:26 AM UTC 24
Peak memory 228732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801169411 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.801169411
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2348736162
Short name T152
Test name
Test status
Simulation time 397682369 ps
CPU time 16.07 seconds
Started Sep 11 03:29:07 AM UTC 24
Finished Sep 11 03:29:25 AM UTC 24
Peak memory 225524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348736162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2348736162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1659948586
Short name T78
Test name
Test status
Simulation time 339020306 ps
CPU time 7.98 seconds
Started Sep 11 03:29:17 AM UTC 24
Finished Sep 11 03:29:26 AM UTC 24
Peak memory 228040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659948586 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1659948586
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3586638456
Short name T50
Test name
Test status
Simulation time 7614411179 ps
CPU time 211.99 seconds
Started Sep 11 03:29:14 AM UTC 24
Finished Sep 11 03:32:50 AM UTC 24
Peak memory 228588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586638456 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.3586638456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1181295504
Short name T54
Test name
Test status
Simulation time 3308371532 ps
CPU time 25.94 seconds
Started Sep 11 03:29:15 AM UTC 24
Finished Sep 11 03:29:42 AM UTC 24
Peak memory 228512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181295504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1181295504
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2015990291
Short name T129
Test name
Test status
Simulation time 839625796 ps
CPU time 14.81 seconds
Started Sep 11 03:29:14 AM UTC 24
Finished Sep 11 03:29:30 AM UTC 24
Peak memory 228436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015990291 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2015990291
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3294220784
Short name T79
Test name
Test status
Simulation time 1108535043 ps
CPU time 14.06 seconds
Started Sep 11 03:29:12 AM UTC 24
Finished Sep 11 03:29:27 AM UTC 24
Peak memory 225444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294220784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3294220784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3366436609
Short name T130
Test name
Test status
Simulation time 748662161 ps
CPU time 21.27 seconds
Started Sep 11 03:29:13 AM UTC 24
Finished Sep 11 03:29:36 AM UTC 24
Peak memory 228768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336643660
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.3366436609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1984312331
Short name T66
Test name
Test status
Simulation time 1653625484 ps
CPU time 90.43 seconds
Started Sep 11 03:29:15 AM UTC 24
Finished Sep 11 03:30:47 AM UTC 24
Peak memory 239008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1984312331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1984312331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest
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