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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.46 96.77 92.28 97.68 100.00 98.55 97.91 99.06


Total test records in report: 458
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T305 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.243355223 Sep 18 06:18:25 AM UTC 24 Sep 18 06:23:04 AM UTC 24 6431597371 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3570193585 Sep 18 06:19:22 AM UTC 24 Sep 18 06:19:50 AM UTC 24 343046601 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1582176822 Sep 18 06:19:37 AM UTC 24 Sep 18 06:19:50 AM UTC 24 292761185 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3709810466 Sep 18 06:19:07 AM UTC 24 Sep 18 06:19:51 AM UTC 24 288708477 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2160292856 Sep 18 06:19:01 AM UTC 24 Sep 18 06:19:52 AM UTC 24 4659157351 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1938424926 Sep 18 06:18:52 AM UTC 24 Sep 18 06:19:55 AM UTC 24 1517180458 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1822104254 Sep 18 06:19:41 AM UTC 24 Sep 18 06:19:55 AM UTC 24 701047661 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2292539856 Sep 18 06:19:29 AM UTC 24 Sep 18 06:19:57 AM UTC 24 9904062777 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3094015246 Sep 18 06:19:45 AM UTC 24 Sep 18 06:19:57 AM UTC 24 167467640 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.840498069 Sep 18 06:17:22 AM UTC 24 Sep 18 06:19:59 AM UTC 24 3649201352 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1033317849 Sep 18 06:16:59 AM UTC 24 Sep 18 06:19:59 AM UTC 24 25675063667 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.746376230 Sep 18 06:19:36 AM UTC 24 Sep 18 06:19:59 AM UTC 24 501632076 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.4155031045 Sep 18 06:19:13 AM UTC 24 Sep 18 06:20:00 AM UTC 24 10389614045 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1658866923 Sep 18 06:19:49 AM UTC 24 Sep 18 06:20:00 AM UTC 24 1061040076 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3391787021 Sep 18 06:18:28 AM UTC 24 Sep 18 06:20:02 AM UTC 24 7556562934 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.382620476 Sep 18 06:19:51 AM UTC 24 Sep 18 06:20:03 AM UTC 24 168405163 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1677996243 Sep 18 06:16:14 AM UTC 24 Sep 18 06:20:07 AM UTC 24 5191941715 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.181760135 Sep 18 06:15:55 AM UTC 24 Sep 18 06:20:10 AM UTC 24 19997278788 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.626847695 Sep 18 06:19:34 AM UTC 24 Sep 18 06:20:10 AM UTC 24 9183232025 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.929835346 Sep 18 06:19:48 AM UTC 24 Sep 18 06:20:11 AM UTC 24 540257604 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3579520417 Sep 18 06:19:49 AM UTC 24 Sep 18 06:20:14 AM UTC 24 953013321 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3182224937 Sep 18 06:16:40 AM UTC 24 Sep 18 06:20:15 AM UTC 24 3630067643 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.797270189 Sep 18 06:19:42 AM UTC 24 Sep 18 06:20:15 AM UTC 24 2069381294 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1716850028 Sep 18 06:19:41 AM UTC 24 Sep 18 06:20:16 AM UTC 24 2151569175 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3214281447 Sep 18 06:15:55 AM UTC 24 Sep 18 06:20:16 AM UTC 24 51696086476 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2324185042 Sep 18 06:15:10 AM UTC 24 Sep 18 06:20:18 AM UTC 24 10558891454 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.462428585 Sep 18 06:16:50 AM UTC 24 Sep 18 06:20:30 AM UTC 24 13495075328 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.103882695 Sep 18 06:19:44 AM UTC 24 Sep 18 06:20:39 AM UTC 24 10678880856 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4268663455 Sep 18 06:19:37 AM UTC 24 Sep 18 06:20:40 AM UTC 24 5457319948 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3879370385 Sep 18 06:18:39 AM UTC 24 Sep 18 06:20:40 AM UTC 24 11311960470 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1052128521 Sep 18 06:15:27 AM UTC 24 Sep 18 06:20:44 AM UTC 24 5023286788 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2934879329 Sep 18 06:17:16 AM UTC 24 Sep 18 06:20:44 AM UTC 24 14326328041 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2496412867 Sep 18 06:19:51 AM UTC 24 Sep 18 06:20:50 AM UTC 24 5777252426 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3913216963 Sep 18 06:19:03 AM UTC 24 Sep 18 06:20:51 AM UTC 24 5484647695 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2133517200 Sep 18 06:17:51 AM UTC 24 Sep 18 06:21:00 AM UTC 24 8968533573 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.441471311 Sep 18 06:17:59 AM UTC 24 Sep 18 06:21:04 AM UTC 24 4517682819 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1689738822 Sep 18 06:17:31 AM UTC 24 Sep 18 06:21:09 AM UTC 24 14800754718 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2882015453 Sep 18 06:18:18 AM UTC 24 Sep 18 06:21:14 AM UTC 24 3487379767 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.531115321 Sep 18 06:19:19 AM UTC 24 Sep 18 06:21:32 AM UTC 24 11843446704 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1765235834 Sep 18 06:15:01 AM UTC 24 Sep 18 06:21:35 AM UTC 24 80259497422 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.375914450 Sep 18 06:14:37 AM UTC 24 Sep 18 06:21:39 AM UTC 24 70026004717 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2452102740 Sep 18 06:16:10 AM UTC 24 Sep 18 06:21:47 AM UTC 24 79062758922 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2428909575 Sep 18 06:17:56 AM UTC 24 Sep 18 06:21:48 AM UTC 24 8471339901 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2923776536 Sep 18 06:19:36 AM UTC 24 Sep 18 06:21:48 AM UTC 24 2064995315 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.781965927 Sep 18 06:14:31 AM UTC 24 Sep 18 06:21:51 AM UTC 24 155310142633 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.955327751 Sep 18 06:18:17 AM UTC 24 Sep 18 06:22:07 AM UTC 24 4711793160 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1961195676 Sep 18 06:17:38 AM UTC 24 Sep 18 06:22:08 AM UTC 24 27269370223 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4180239169 Sep 18 06:18:42 AM UTC 24 Sep 18 06:22:20 AM UTC 24 9851115794 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1309793505 Sep 18 06:16:27 AM UTC 24 Sep 18 06:22:56 AM UTC 24 25779376485 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2153585583 Sep 18 06:19:49 AM UTC 24 Sep 18 06:22:56 AM UTC 24 13623191768 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.17689207 Sep 18 06:17:08 AM UTC 24 Sep 18 06:23:01 AM UTC 24 4332958183 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1794461725 Sep 18 06:18:07 AM UTC 24 Sep 18 06:23:10 AM UTC 24 5399705663 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3625558780 Sep 18 06:19:11 AM UTC 24 Sep 18 06:23:14 AM UTC 24 16023071438 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1633167305 Sep 18 06:17:48 AM UTC 24 Sep 18 06:23:25 AM UTC 24 12126460261 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.465665475 Sep 18 06:19:27 AM UTC 24 Sep 18 06:23:27 AM UTC 24 7471292519 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3760744082 Sep 18 06:19:18 AM UTC 24 Sep 18 06:23:34 AM UTC 24 6569805833 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2020377394 Sep 18 06:19:02 AM UTC 24 Sep 18 06:24:16 AM UTC 24 20781652687 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1633548036 Sep 18 06:18:46 AM UTC 24 Sep 18 06:24:26 AM UTC 24 6275479835 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.854040161 Sep 18 06:19:42 AM UTC 24 Sep 18 06:24:29 AM UTC 24 19201970292 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.825891744 Sep 18 06:19:30 AM UTC 24 Sep 18 06:24:34 AM UTC 24 4344193731 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3202854490 Sep 18 06:18:34 AM UTC 24 Sep 18 06:25:13 AM UTC 24 29231936145 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2036713675 Sep 18 06:18:19 AM UTC 24 Sep 18 06:26:01 AM UTC 24 7655756844 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.623130157 Sep 18 06:18:58 AM UTC 24 Sep 18 06:26:04 AM UTC 24 22959884492 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1060052073 Sep 18 06:19:56 AM UTC 24 Sep 18 06:20:05 AM UTC 24 186509733 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4090218995 Sep 18 06:19:56 AM UTC 24 Sep 18 06:20:07 AM UTC 24 250965233 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2538492661 Sep 18 06:19:59 AM UTC 24 Sep 18 06:20:09 AM UTC 24 332592294 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3409079986 Sep 18 06:19:52 AM UTC 24 Sep 18 06:20:09 AM UTC 24 169491885 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2095791267 Sep 18 06:19:58 AM UTC 24 Sep 18 06:20:11 AM UTC 24 661348746 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2664326331 Sep 18 06:19:59 AM UTC 24 Sep 18 06:20:12 AM UTC 24 176499304 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.561032996 Sep 18 06:20:00 AM UTC 24 Sep 18 06:20:12 AM UTC 24 261085702 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3643153398 Sep 18 06:19:58 AM UTC 24 Sep 18 06:20:15 AM UTC 24 264878710 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2588317228 Sep 18 06:20:06 AM UTC 24 Sep 18 06:20:16 AM UTC 24 688430354 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3361012018 Sep 18 06:20:02 AM UTC 24 Sep 18 06:20:16 AM UTC 24 296628326 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3794354861 Sep 18 06:20:08 AM UTC 24 Sep 18 06:20:17 AM UTC 24 174175140 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4105776583 Sep 18 06:20:01 AM UTC 24 Sep 18 06:20:18 AM UTC 24 263405107 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.699359683 Sep 18 06:20:10 AM UTC 24 Sep 18 06:20:21 AM UTC 24 506526615 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.313857802 Sep 18 06:20:11 AM UTC 24 Sep 18 06:20:23 AM UTC 24 1029294625 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.728974070 Sep 18 06:20:10 AM UTC 24 Sep 18 06:20:24 AM UTC 24 1034492009 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4064581815 Sep 18 06:20:09 AM UTC 24 Sep 18 06:20:24 AM UTC 24 176486226 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1984826812 Sep 18 06:20:16 AM UTC 24 Sep 18 06:20:25 AM UTC 24 1269443928 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3097341642 Sep 18 06:20:15 AM UTC 24 Sep 18 06:20:26 AM UTC 24 345386173 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3076359908 Sep 18 06:20:11 AM UTC 24 Sep 18 06:20:26 AM UTC 24 1001743851 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1967516172 Sep 18 06:20:14 AM UTC 24 Sep 18 06:20:26 AM UTC 24 611954891 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.611990419 Sep 18 06:20:11 AM UTC 24 Sep 18 06:20:26 AM UTC 24 274104343 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2709675125 Sep 18 06:20:16 AM UTC 24 Sep 18 06:20:27 AM UTC 24 404589927 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.596881454 Sep 18 06:20:18 AM UTC 24 Sep 18 06:20:29 AM UTC 24 332706738 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1695746002 Sep 18 06:20:16 AM UTC 24 Sep 18 06:20:31 AM UTC 24 250597101 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3423697984 Sep 18 06:20:12 AM UTC 24 Sep 18 06:20:32 AM UTC 24 612788223 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1560255189 Sep 18 06:20:19 AM UTC 24 Sep 18 06:20:32 AM UTC 24 1183310970 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1965330054 Sep 18 06:20:22 AM UTC 24 Sep 18 06:20:33 AM UTC 24 1449946797 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4287353920 Sep 18 06:20:16 AM UTC 24 Sep 18 06:20:33 AM UTC 24 264857354 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.667140281 Sep 18 06:20:24 AM UTC 24 Sep 18 06:20:33 AM UTC 24 2751730550 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3986167574 Sep 18 06:20:18 AM UTC 24 Sep 18 06:20:36 AM UTC 24 2223399466 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3681249059 Sep 18 06:20:25 AM UTC 24 Sep 18 06:20:38 AM UTC 24 718984574 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1412566016 Sep 18 06:20:26 AM UTC 24 Sep 18 06:20:38 AM UTC 24 1099594417 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.176291378 Sep 18 06:20:27 AM UTC 24 Sep 18 06:20:39 AM UTC 24 174601211 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.303182207 Sep 18 06:20:27 AM UTC 24 Sep 18 06:20:41 AM UTC 24 260925273 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1631259792 Sep 18 06:20:31 AM UTC 24 Sep 18 06:20:43 AM UTC 24 970554855 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3413613992 Sep 18 06:20:27 AM UTC 24 Sep 18 06:20:43 AM UTC 24 1643654929 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.606723965 Sep 18 06:20:25 AM UTC 24 Sep 18 06:20:43 AM UTC 24 1477540867 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.603513570 Sep 18 06:20:27 AM UTC 24 Sep 18 06:20:44 AM UTC 24 585678430 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.506320836 Sep 18 06:20:34 AM UTC 24 Sep 18 06:20:44 AM UTC 24 660732712 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3875423878 Sep 18 06:20:32 AM UTC 24 Sep 18 06:20:46 AM UTC 24 1029177161 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3646132746 Sep 18 06:20:33 AM UTC 24 Sep 18 06:20:47 AM UTC 24 171572568 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4260717644 Sep 18 06:20:34 AM UTC 24 Sep 18 06:20:48 AM UTC 24 663819137 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1994924134 Sep 18 06:20:34 AM UTC 24 Sep 18 06:20:48 AM UTC 24 1043239969 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2318107059 Sep 18 06:20:34 AM UTC 24 Sep 18 06:20:49 AM UTC 24 252397878 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1649098883 Sep 18 06:20:37 AM UTC 24 Sep 18 06:20:50 AM UTC 24 687553657 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2327973229 Sep 18 06:20:40 AM UTC 24 Sep 18 06:20:50 AM UTC 24 247734970 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3024485131 Sep 18 06:19:51 AM UTC 24 Sep 18 06:20:51 AM UTC 24 1079372959 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.620654517 Sep 18 06:20:41 AM UTC 24 Sep 18 06:20:52 AM UTC 24 177772823 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3966263225 Sep 18 06:20:39 AM UTC 24 Sep 18 06:20:53 AM UTC 24 174514772 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3229604975 Sep 18 06:20:44 AM UTC 24 Sep 18 06:20:55 AM UTC 24 327287964 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2868738258 Sep 18 06:20:45 AM UTC 24 Sep 18 06:20:59 AM UTC 24 318162849 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4267324331 Sep 18 06:20:41 AM UTC 24 Sep 18 06:21:00 AM UTC 24 532375896 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2655185217 Sep 18 06:20:01 AM UTC 24 Sep 18 06:21:01 AM UTC 24 1041528552 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1983817550 Sep 18 06:20:43 AM UTC 24 Sep 18 06:21:01 AM UTC 24 250116333 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2835616072 Sep 18 06:20:45 AM UTC 24 Sep 18 06:21:02 AM UTC 24 494737242 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1726224620 Sep 18 06:20:48 AM UTC 24 Sep 18 06:21:02 AM UTC 24 1033301308 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1187343529 Sep 18 06:20:49 AM UTC 24 Sep 18 06:21:02 AM UTC 24 3524387672 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3769974663 Sep 18 06:20:12 AM UTC 24 Sep 18 06:21:04 AM UTC 24 1782901687 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3100401139 Sep 18 06:20:44 AM UTC 24 Sep 18 06:21:05 AM UTC 24 1019152902 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2897653955 Sep 18 06:20:51 AM UTC 24 Sep 18 06:21:05 AM UTC 24 507777338 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3326200738 Sep 18 06:20:49 AM UTC 24 Sep 18 06:21:05 AM UTC 24 969895810 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.478741872 Sep 18 06:20:51 AM UTC 24 Sep 18 06:21:07 AM UTC 24 3081179191 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2929574332 Sep 18 06:20:52 AM UTC 24 Sep 18 06:21:07 AM UTC 24 261971131 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.32369919 Sep 18 06:20:53 AM UTC 24 Sep 18 06:21:08 AM UTC 24 507949433 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.576971687 Sep 18 06:20:52 AM UTC 24 Sep 18 06:21:14 AM UTC 24 268767581 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2219617422 Sep 18 06:21:01 AM UTC 24 Sep 18 06:21:14 AM UTC 24 174221328 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3669353763 Sep 18 06:21:04 AM UTC 24 Sep 18 06:21:14 AM UTC 24 361106459 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2304763044 Sep 18 06:21:00 AM UTC 24 Sep 18 06:21:14 AM UTC 24 1031314870 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3147116419 Sep 18 06:21:03 AM UTC 24 Sep 18 06:21:15 AM UTC 24 1586677917 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1278893880 Sep 18 06:21:02 AM UTC 24 Sep 18 06:21:15 AM UTC 24 2063755512 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1351628239 Sep 18 06:21:02 AM UTC 24 Sep 18 06:21:19 AM UTC 24 1079321266 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2415901415 Sep 18 06:21:06 AM UTC 24 Sep 18 06:21:19 AM UTC 24 254338465 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1198283261 Sep 18 06:20:42 AM UTC 24 Sep 18 06:21:22 AM UTC 24 1439317829 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2545354892 Sep 18 06:21:03 AM UTC 24 Sep 18 06:21:22 AM UTC 24 3529352797 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3849611522 Sep 18 06:20:18 AM UTC 24 Sep 18 06:21:23 AM UTC 24 1061695612 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.146133555 Sep 18 06:21:08 AM UTC 24 Sep 18 06:21:25 AM UTC 24 518938575 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.169404398 Sep 18 06:21:05 AM UTC 24 Sep 18 06:21:25 AM UTC 24 497399394 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1684743759 Sep 18 06:21:10 AM UTC 24 Sep 18 06:21:26 AM UTC 24 694612843 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2972171737 Sep 18 06:21:15 AM UTC 24 Sep 18 06:21:28 AM UTC 24 1372843709 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2765996650 Sep 18 06:21:16 AM UTC 24 Sep 18 06:21:28 AM UTC 24 682284237 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3179896957 Sep 18 06:21:07 AM UTC 24 Sep 18 06:21:29 AM UTC 24 1032262566 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2428536478 Sep 18 06:21:19 AM UTC 24 Sep 18 06:21:29 AM UTC 24 663373612 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.715052080 Sep 18 06:21:16 AM UTC 24 Sep 18 06:21:31 AM UTC 24 494887259 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3766102285 Sep 18 06:21:20 AM UTC 24 Sep 18 06:21:32 AM UTC 24 169476379 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3110310585 Sep 18 06:20:45 AM UTC 24 Sep 18 06:21:35 AM UTC 24 1056685648 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1667984902 Sep 18 06:21:22 AM UTC 24 Sep 18 06:21:37 AM UTC 24 953282011 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.774634896 Sep 18 06:21:23 AM UTC 24 Sep 18 06:21:38 AM UTC 24 853428602 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1882083300 Sep 18 06:21:16 AM UTC 24 Sep 18 06:21:38 AM UTC 24 254185284 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.612662064 Sep 18 06:21:25 AM UTC 24 Sep 18 06:21:39 AM UTC 24 251212161 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.631574882 Sep 18 06:21:27 AM UTC 24 Sep 18 06:21:39 AM UTC 24 506550131 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.937309216 Sep 18 06:21:29 AM UTC 24 Sep 18 06:21:39 AM UTC 24 657844511 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2366871686 Sep 18 06:20:39 AM UTC 24 Sep 18 06:21:41 AM UTC 24 1377518771 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.457116114 Sep 18 06:21:32 AM UTC 24 Sep 18 06:21:42 AM UTC 24 720179614 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1819524309 Sep 18 06:21:02 AM UTC 24 Sep 18 06:21:46 AM UTC 24 4229323265 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3500663157 Sep 18 06:21:33 AM UTC 24 Sep 18 06:21:48 AM UTC 24 266910511 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3559048906 Sep 18 06:21:38 AM UTC 24 Sep 18 06:21:48 AM UTC 24 664104291 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2920237377 Sep 18 06:20:50 AM UTC 24 Sep 18 06:21:50 AM UTC 24 3169635330 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2534166091 Sep 18 06:21:31 AM UTC 24 Sep 18 06:21:51 AM UTC 24 997563268 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2690960236 Sep 18 06:21:39 AM UTC 24 Sep 18 06:21:52 AM UTC 24 345696293 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3584080114 Sep 18 06:21:33 AM UTC 24 Sep 18 06:21:52 AM UTC 24 357878073 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4023224155 Sep 18 06:21:39 AM UTC 24 Sep 18 06:21:53 AM UTC 24 249218288 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3424805761 Sep 18 06:21:36 AM UTC 24 Sep 18 06:21:53 AM UTC 24 516136034 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.740413503 Sep 18 06:20:19 AM UTC 24 Sep 18 06:21:54 AM UTC 24 323229029 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.735401705 Sep 18 06:21:39 AM UTC 24 Sep 18 06:21:54 AM UTC 24 271462215 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3084284642 Sep 18 06:21:42 AM UTC 24 Sep 18 06:21:54 AM UTC 24 495730030 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4101766825 Sep 18 06:21:44 AM UTC 24 Sep 18 06:21:56 AM UTC 24 1185234763 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3639860951 Sep 18 06:20:52 AM UTC 24 Sep 18 06:21:56 AM UTC 24 11209649953 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3877521324 Sep 18 06:20:30 AM UTC 24 Sep 18 06:21:57 AM UTC 24 538375202 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1506865747 Sep 18 06:21:49 AM UTC 24 Sep 18 06:21:58 AM UTC 24 174924359 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2773904216 Sep 18 06:21:53 AM UTC 24 Sep 18 06:22:02 AM UTC 24 662584827 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.583762896 Sep 18 06:21:49 AM UTC 24 Sep 18 06:22:03 AM UTC 24 615657521 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1181429692 Sep 18 06:21:49 AM UTC 24 Sep 18 06:22:04 AM UTC 24 661295053 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1767712748 Sep 18 06:21:47 AM UTC 24 Sep 18 06:22:04 AM UTC 24 271368552 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3537172996 Sep 18 06:20:27 AM UTC 24 Sep 18 06:22:04 AM UTC 24 12922438144 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4064900523 Sep 18 06:21:51 AM UTC 24 Sep 18 06:22:06 AM UTC 24 275338597 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.143421824 Sep 18 06:21:52 AM UTC 24 Sep 18 06:22:07 AM UTC 24 689785655 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.74012522 Sep 18 06:21:08 AM UTC 24 Sep 18 06:22:07 AM UTC 24 28329973513 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3851856306 Sep 18 06:21:54 AM UTC 24 Sep 18 06:22:08 AM UTC 24 1048042385 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4083092342 Sep 18 06:21:53 AM UTC 24 Sep 18 06:22:09 AM UTC 24 1005337324 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1921396708 Sep 18 06:21:23 AM UTC 24 Sep 18 06:22:13 AM UTC 24 2026802456 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3163248447 Sep 18 06:21:05 AM UTC 24 Sep 18 06:22:15 AM UTC 24 1035393192 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.864884477 Sep 18 06:20:55 AM UTC 24 Sep 18 06:22:18 AM UTC 24 2052862057 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1863580570 Sep 18 06:21:16 AM UTC 24 Sep 18 06:22:33 AM UTC 24 1541207339 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2660458235 Sep 18 06:21:39 AM UTC 24 Sep 18 06:22:36 AM UTC 24 1043429923 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1338239345 Sep 18 06:19:53 AM UTC 24 Sep 18 06:22:42 AM UTC 24 893284796 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2620842516 Sep 18 06:20:51 AM UTC 24 Sep 18 06:22:43 AM UTC 24 333598661 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2575288073 Sep 18 06:21:51 AM UTC 24 Sep 18 06:22:45 AM UTC 24 2129412553 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1566414969 Sep 18 06:21:15 AM UTC 24 Sep 18 06:22:48 AM UTC 24 240995398 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3551942211 Sep 18 06:21:30 AM UTC 24 Sep 18 06:22:49 AM UTC 24 1574587083 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.292146904 Sep 18 06:21:40 AM UTC 24 Sep 18 06:23:05 AM UTC 24 631291509 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1656334751 Sep 18 06:20:04 AM UTC 24 Sep 18 06:23:07 AM UTC 24 1234081674 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.17408383 Sep 18 06:21:37 AM UTC 24 Sep 18 06:23:07 AM UTC 24 1283493255 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.725358206 Sep 18 06:20:12 AM UTC 24 Sep 18 06:23:08 AM UTC 24 404754296 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3427475936 Sep 18 06:21:48 AM UTC 24 Sep 18 06:23:11 AM UTC 24 1567996864 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.75354187 Sep 18 06:20:47 AM UTC 24 Sep 18 06:23:19 AM UTC 24 642314688 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1335352625 Sep 18 06:21:49 AM UTC 24 Sep 18 06:23:19 AM UTC 24 347504810 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4006466953 Sep 18 06:21:36 AM UTC 24 Sep 18 06:23:19 AM UTC 24 24837466050 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1140812057 Sep 18 06:20:43 AM UTC 24 Sep 18 06:23:32 AM UTC 24 869089518 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3486691297 Sep 18 06:21:53 AM UTC 24 Sep 18 06:23:33 AM UTC 24 4195864207 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1479861327 Sep 18 06:20:40 AM UTC 24 Sep 18 06:23:43 AM UTC 24 299354909 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2087846824 Sep 18 06:21:03 AM UTC 24 Sep 18 06:23:59 AM UTC 24 462399781 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2752568251 Sep 18 06:21:31 AM UTC 24 Sep 18 06:24:17 AM UTC 24 1438048950 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.189344112 Sep 18 06:21:25 AM UTC 24 Sep 18 06:24:22 AM UTC 24 1575490180 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3554532015 Sep 18 06:21:05 AM UTC 24 Sep 18 06:24:36 AM UTC 24 1493910260 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.424611076 Sep 18 06:21:16 AM UTC 24 Sep 18 06:24:38 AM UTC 24 658877739 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3135560673
Short name T5
Test name
Test status
Simulation time 187555738 ps
CPU time 9.58 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:42 AM UTC 24
Peak memory 227648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135560673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3135560673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.899811653
Short name T15
Test name
Test status
Simulation time 15887481341 ps
CPU time 47.54 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:15:20 AM UTC 24
Peak memory 247508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=899811653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.rom_ctrl_stress_all_with_rand_reset.899811653
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.4233066634
Short name T37
Test name
Test status
Simulation time 332650966 ps
CPU time 20.26 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:14:58 AM UTC 24
Peak memory 230988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233066634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4233066634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.658649518
Short name T55
Test name
Test status
Simulation time 5152371480 ps
CPU time 215.05 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:18:15 AM UTC 24
Peak memory 248948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658649518 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.658649518
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.3880695292
Short name T4
Test name
Test status
Simulation time 1120608130 ps
CPU time 8.72 seconds
Started Sep 18 06:14:32 AM UTC 24
Finished Sep 18 06:14:42 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880695292 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3880695292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1172686697
Short name T32
Test name
Test status
Simulation time 518903173 ps
CPU time 24.31 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:57 AM UTC 24
Peak memory 230964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172686697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1172686697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1835934829
Short name T78
Test name
Test status
Simulation time 13947841922 ps
CPU time 275.09 seconds
Started Sep 18 06:14:42 AM UTC 24
Finished Sep 18 06:19:21 AM UTC 24
Peak memory 259896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835934829 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.1835934829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3662709440
Short name T34
Test name
Test status
Simulation time 2268161612 ps
CPU time 26.56 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:59 AM UTC 24
Peak memory 231132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366270944
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.3662709440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.864884477
Short name T93
Test name
Test status
Simulation time 2052862057 ps
CPU time 80.96 seconds
Started Sep 18 06:20:55 AM UTC 24
Finished Sep 18 06:22:18 AM UTC 24
Peak memory 226216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864884477 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.864884477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1843740250
Short name T20
Test name
Test status
Simulation time 4172492808 ps
CPU time 89.98 seconds
Started Sep 18 06:14:50 AM UTC 24
Finished Sep 18 06:16:22 AM UTC 24
Peak memory 245268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1843740250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1843740250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3404435565
Short name T11
Test name
Test status
Simulation time 523281681 ps
CPU time 20.71 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:53 AM UTC 24
Peak memory 230796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404435565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3404435565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.3757176657
Short name T43
Test name
Test status
Simulation time 988728710 ps
CPU time 250.17 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:18:45 AM UTC 24
Peak memory 261948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757176657 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3757176657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1656334751
Short name T141
Test name
Test status
Simulation time 1234081674 ps
CPU time 180.13 seconds
Started Sep 18 06:20:04 AM UTC 24
Finished Sep 18 06:23:07 AM UTC 24
Peak memory 226232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656334751 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.1656334751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1570862936
Short name T183
Test name
Test status
Simulation time 718321982 ps
CPU time 42.33 seconds
Started Sep 18 06:15:09 AM UTC 24
Finished Sep 18 06:15:53 AM UTC 24
Peak memory 230536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157086293
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.1570862936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2664326331
Short name T97
Test name
Test status
Simulation time 176499304 ps
CPU time 11.27 seconds
Started Sep 18 06:19:59 AM UTC 24
Finished Sep 18 06:20:12 AM UTC 24
Peak memory 222260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664326331 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.2664326331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1438104593
Short name T19
Test name
Test status
Simulation time 181066732 ps
CPU time 13.42 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:14:51 AM UTC 24
Peak memory 230456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438104593 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1438104593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2298821018
Short name T152
Test name
Test status
Simulation time 4463329905 ps
CPU time 190.49 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:17:45 AM UTC 24
Peak memory 248372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2298821018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2298821018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1541809313
Short name T172
Test name
Test status
Simulation time 16395801156 ps
CPU time 35.49 seconds
Started Sep 18 06:14:55 AM UTC 24
Finished Sep 18 06:15:32 AM UTC 24
Peak memory 231116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541809313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1541809313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2752568251
Short name T143
Test name
Test status
Simulation time 1438048950 ps
CPU time 163.44 seconds
Started Sep 18 06:21:31 AM UTC 24
Finished Sep 18 06:24:17 AM UTC 24
Peak memory 226148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752568251 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.2752568251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2299910007
Short name T26
Test name
Test status
Simulation time 3535234163 ps
CPU time 164.4 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:17:18 AM UTC 24
Peak memory 262000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299910007 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.2299910007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1904851643
Short name T77
Test name
Test status
Simulation time 2063214516 ps
CPU time 27.17 seconds
Started Sep 18 06:17:12 AM UTC 24
Finished Sep 18 06:17:40 AM UTC 24
Peak memory 230792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904851643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1904851643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1630731006
Short name T16
Test name
Test status
Simulation time 11419442273 ps
CPU time 43.21 seconds
Started Sep 18 06:15:09 AM UTC 24
Finished Sep 18 06:15:54 AM UTC 24
Peak memory 237116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1630731006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1630731006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.663804838
Short name T38
Test name
Test status
Simulation time 1976482357 ps
CPU time 31.71 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:15:04 AM UTC 24
Peak memory 230784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663804838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.663804838
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.424611076
Short name T149
Test name
Test status
Simulation time 658877739 ps
CPU time 198.73 seconds
Started Sep 18 06:21:16 AM UTC 24
Finished Sep 18 06:24:38 AM UTC 24
Peak memory 226224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424611076 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.424611076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.307359639
Short name T9
Test name
Test status
Simulation time 182001236 ps
CPU time 11.3 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:43 AM UTC 24
Peak memory 227368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307359639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64k
B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.307359639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3024485131
Short name T113
Test name
Test status
Simulation time 1079372959 ps
CPU time 58.4 seconds
Started Sep 18 06:19:51 AM UTC 24
Finished Sep 18 06:20:51 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024485131 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.3024485131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2541578884
Short name T21
Test name
Test status
Simulation time 3691002500 ps
CPU time 123.77 seconds
Started Sep 18 06:15:03 AM UTC 24
Finished Sep 18 06:17:09 AM UTC 24
Peak memory 247308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2541578884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2541578884
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.637818368
Short name T68
Test name
Test status
Simulation time 592751438 ps
CPU time 20.98 seconds
Started Sep 18 06:15:01 AM UTC 24
Finished Sep 18 06:15:23 AM UTC 24
Peak memory 230668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637818368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.637818368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1244585587
Short name T3
Test name
Test status
Simulation time 176091434 ps
CPU time 9.16 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:41 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244585587 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1244585587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2426507645
Short name T190
Test name
Test status
Simulation time 663553597 ps
CPU time 19.64 seconds
Started Sep 18 06:15:42 AM UTC 24
Finished Sep 18 06:16:02 AM UTC 24
Peak memory 230796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426507645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2426507645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.4169469424
Short name T174
Test name
Test status
Simulation time 1964376203 ps
CPU time 37.14 seconds
Started Sep 18 06:14:58 AM UTC 24
Finished Sep 18 06:15:36 AM UTC 24
Peak memory 230792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169469424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4169469424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2538492661
Short name T95
Test name
Test status
Simulation time 332592294 ps
CPU time 8.62 seconds
Started Sep 18 06:19:59 AM UTC 24
Finished Sep 18 06:20:09 AM UTC 24
Peak memory 222132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538492661 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.2538492661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3643153398
Short name T133
Test name
Test status
Simulation time 264878710 ps
CPU time 14.93 seconds
Started Sep 18 06:19:58 AM UTC 24
Finished Sep 18 06:20:15 AM UTC 24
Peak memory 222068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643153398 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.3643153398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4105776583
Short name T374
Test name
Test status
Simulation time 263405107 ps
CPU time 15.11 seconds
Started Sep 18 06:20:01 AM UTC 24
Finished Sep 18 06:20:18 AM UTC 24
Peak memory 228396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4105776583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
om_ctrl_csr_mem_rw_with_rand_reset.4105776583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2095791267
Short name T96
Test name
Test status
Simulation time 661348746 ps
CPU time 11.92 seconds
Started Sep 18 06:19:58 AM UTC 24
Finished Sep 18 06:20:11 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095791267 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2095791267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4090218995
Short name T369
Test name
Test status
Simulation time 250965233 ps
CPU time 10.4 seconds
Started Sep 18 06:19:56 AM UTC 24
Finished Sep 18 06:20:07 AM UTC 24
Peak memory 222000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090218995 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.4090218995
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1060052073
Short name T368
Test name
Test status
Simulation time 186509733 ps
CPU time 8.34 seconds
Started Sep 18 06:19:56 AM UTC 24
Finished Sep 18 06:20:05 AM UTC 24
Peak memory 222064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060052073 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.1060052073
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.561032996
Short name T99
Test name
Test status
Simulation time 261085702 ps
CPU time 10.41 seconds
Started Sep 18 06:20:00 AM UTC 24
Finished Sep 18 06:20:12 AM UTC 24
Peak memory 222136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561032996 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.561032996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3409079986
Short name T370
Test name
Test status
Simulation time 169491885 ps
CPU time 16.2 seconds
Started Sep 18 06:19:52 AM UTC 24
Finished Sep 18 06:20:09 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409079986 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3409079986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1338239345
Short name T136
Test name
Test status
Simulation time 893284796 ps
CPU time 166.19 seconds
Started Sep 18 06:19:53 AM UTC 24
Finished Sep 18 06:22:42 AM UTC 24
Peak memory 226232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338239345 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.1338239345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.313857802
Short name T135
Test name
Test status
Simulation time 1029294625 ps
CPU time 11.1 seconds
Started Sep 18 06:20:11 AM UTC 24
Finished Sep 18 06:20:23 AM UTC 24
Peak memory 222128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313857802 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.313857802
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.728974070
Short name T375
Test name
Test status
Simulation time 1034492009 ps
CPU time 13.05 seconds
Started Sep 18 06:20:10 AM UTC 24
Finished Sep 18 06:20:24 AM UTC 24
Peak memory 222128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728974070 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.728974070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4064581815
Short name T100
Test name
Test status
Simulation time 176486226 ps
CPU time 14.41 seconds
Started Sep 18 06:20:09 AM UTC 24
Finished Sep 18 06:20:24 AM UTC 24
Peak memory 222068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064581815 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.4064581815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.611990419
Short name T378
Test name
Test status
Simulation time 274104343 ps
CPU time 14.37 seconds
Started Sep 18 06:20:11 AM UTC 24
Finished Sep 18 06:20:26 AM UTC 24
Peak memory 228408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=611990419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ro
m_ctrl_csr_mem_rw_with_rand_reset.611990419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.699359683
Short name T134
Test name
Test status
Simulation time 506526615 ps
CPU time 10.19 seconds
Started Sep 18 06:20:10 AM UTC 24
Finished Sep 18 06:20:21 AM UTC 24
Peak memory 222068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699359683 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.699359683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3794354861
Short name T373
Test name
Test status
Simulation time 174175140 ps
CPU time 8.45 seconds
Started Sep 18 06:20:08 AM UTC 24
Finished Sep 18 06:20:17 AM UTC 24
Peak memory 221936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794354861 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.3794354861
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2588317228
Short name T371
Test name
Test status
Simulation time 688430354 ps
CPU time 9.52 seconds
Started Sep 18 06:20:06 AM UTC 24
Finished Sep 18 06:20:16 AM UTC 24
Peak memory 222000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588317228 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.2588317228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2655185217
Short name T114
Test name
Test status
Simulation time 1041528552 ps
CPU time 58.34 seconds
Started Sep 18 06:20:01 AM UTC 24
Finished Sep 18 06:21:01 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655185217 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.2655185217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3076359908
Short name T102
Test name
Test status
Simulation time 1001743851 ps
CPU time 14.32 seconds
Started Sep 18 06:20:11 AM UTC 24
Finished Sep 18 06:20:26 AM UTC 24
Peak memory 224168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076359908 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.3076359908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3361012018
Short name T372
Test name
Test status
Simulation time 296628326 ps
CPU time 12.68 seconds
Started Sep 18 06:20:02 AM UTC 24
Finished Sep 18 06:20:16 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361012018 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3361012018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3669353763
Short name T407
Test name
Test status
Simulation time 361106459 ps
CPU time 9.25 seconds
Started Sep 18 06:21:04 AM UTC 24
Finished Sep 18 06:21:14 AM UTC 24
Peak memory 228332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3669353763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rom_ctrl_csr_mem_rw_with_rand_reset.3669353763
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2545354892
Short name T412
Test name
Test status
Simulation time 3529352797 ps
CPU time 18.3 seconds
Started Sep 18 06:21:03 AM UTC 24
Finished Sep 18 06:21:22 AM UTC 24
Peak memory 221944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545354892 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2545354892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1819524309
Short name T428
Test name
Test status
Simulation time 4229323265 ps
CPU time 43.01 seconds
Started Sep 18 06:21:02 AM UTC 24
Finished Sep 18 06:21:46 AM UTC 24
Peak memory 226316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819524309 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.1819524309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3147116419
Short name T409
Test name
Test status
Simulation time 1586677917 ps
CPU time 11.37 seconds
Started Sep 18 06:21:03 AM UTC 24
Finished Sep 18 06:21:15 AM UTC 24
Peak memory 224236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147116419 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.3147116419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1278893880
Short name T410
Test name
Test status
Simulation time 2063755512 ps
CPU time 12.64 seconds
Started Sep 18 06:21:02 AM UTC 24
Finished Sep 18 06:21:15 AM UTC 24
Peak memory 228364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278893880 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1278893880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2087846824
Short name T140
Test name
Test status
Simulation time 462399781 ps
CPU time 173.13 seconds
Started Sep 18 06:21:03 AM UTC 24
Finished Sep 18 06:23:59 AM UTC 24
Peak memory 226220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087846824 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.2087846824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.146133555
Short name T413
Test name
Test status
Simulation time 518938575 ps
CPU time 14.56 seconds
Started Sep 18 06:21:08 AM UTC 24
Finished Sep 18 06:21:25 AM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=146133555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.r
om_ctrl_csr_mem_rw_with_rand_reset.146133555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2415901415
Short name T124
Test name
Test status
Simulation time 254338465 ps
CPU time 11.46 seconds
Started Sep 18 06:21:06 AM UTC 24
Finished Sep 18 06:21:19 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415901415 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2415901415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3163248447
Short name T450
Test name
Test status
Simulation time 1035393192 ps
CPU time 68.65 seconds
Started Sep 18 06:21:05 AM UTC 24
Finished Sep 18 06:22:15 AM UTC 24
Peak memory 226316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163248447 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.3163248447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3179896957
Short name T417
Test name
Test status
Simulation time 1032262566 ps
CPU time 20.71 seconds
Started Sep 18 06:21:07 AM UTC 24
Finished Sep 18 06:21:29 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179896957 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.3179896957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.169404398
Short name T414
Test name
Test status
Simulation time 497399394 ps
CPU time 18.31 seconds
Started Sep 18 06:21:05 AM UTC 24
Finished Sep 18 06:21:25 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169404398 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.169404398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3554532015
Short name T458
Test name
Test status
Simulation time 1493910260 ps
CPU time 207.43 seconds
Started Sep 18 06:21:05 AM UTC 24
Finished Sep 18 06:24:36 AM UTC 24
Peak memory 226284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554532015 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.3554532015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2765996650
Short name T416
Test name
Test status
Simulation time 682284237 ps
CPU time 11.1 seconds
Started Sep 18 06:21:16 AM UTC 24
Finished Sep 18 06:21:28 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2765996650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rom_ctrl_csr_mem_rw_with_rand_reset.2765996650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2972171737
Short name T127
Test name
Test status
Simulation time 1372843709 ps
CPU time 12.06 seconds
Started Sep 18 06:21:15 AM UTC 24
Finished Sep 18 06:21:28 AM UTC 24
Peak memory 222060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972171737 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2972171737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.74012522
Short name T447
Test name
Test status
Simulation time 28329973513 ps
CPU time 56.7 seconds
Started Sep 18 06:21:08 AM UTC 24
Finished Sep 18 06:22:07 AM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74012522 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.74012522
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.715052080
Short name T419
Test name
Test status
Simulation time 494887259 ps
CPU time 14 seconds
Started Sep 18 06:21:16 AM UTC 24
Finished Sep 18 06:21:31 AM UTC 24
Peak memory 222116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715052080 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.715052080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1684743759
Short name T415
Test name
Test status
Simulation time 694612843 ps
CPU time 15.64 seconds
Started Sep 18 06:21:10 AM UTC 24
Finished Sep 18 06:21:26 AM UTC 24
Peak memory 228300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684743759 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1684743759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1566414969
Short name T138
Test name
Test status
Simulation time 240995398 ps
CPU time 90.76 seconds
Started Sep 18 06:21:15 AM UTC 24
Finished Sep 18 06:22:48 AM UTC 24
Peak memory 224172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566414969 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.1566414969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1667984902
Short name T422
Test name
Test status
Simulation time 953282011 ps
CPU time 12.09 seconds
Started Sep 18 06:21:22 AM UTC 24
Finished Sep 18 06:21:37 AM UTC 24
Peak memory 226284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1667984902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rom_ctrl_csr_mem_rw_with_rand_reset.1667984902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2428536478
Short name T418
Test name
Test status
Simulation time 663373612 ps
CPU time 9.31 seconds
Started Sep 18 06:21:19 AM UTC 24
Finished Sep 18 06:21:29 AM UTC 24
Peak memory 222252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428536478 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2428536478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1863580570
Short name T123
Test name
Test status
Simulation time 1541207339 ps
CPU time 75.23 seconds
Started Sep 18 06:21:16 AM UTC 24
Finished Sep 18 06:22:33 AM UTC 24
Peak memory 226316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863580570 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.1863580570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3766102285
Short name T420
Test name
Test status
Simulation time 169476379 ps
CPU time 11.25 seconds
Started Sep 18 06:21:20 AM UTC 24
Finished Sep 18 06:21:32 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766102285 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.3766102285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1882083300
Short name T424
Test name
Test status
Simulation time 254185284 ps
CPU time 21.18 seconds
Started Sep 18 06:21:16 AM UTC 24
Finished Sep 18 06:21:38 AM UTC 24
Peak memory 227488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882083300 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1882083300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.937309216
Short name T427
Test name
Test status
Simulation time 657844511 ps
CPU time 9 seconds
Started Sep 18 06:21:29 AM UTC 24
Finished Sep 18 06:21:39 AM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=937309216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.r
om_ctrl_csr_mem_rw_with_rand_reset.937309216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.612662064
Short name T425
Test name
Test status
Simulation time 251212161 ps
CPU time 11.87 seconds
Started Sep 18 06:21:25 AM UTC 24
Finished Sep 18 06:21:39 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612662064 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.612662064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1921396708
Short name T122
Test name
Test status
Simulation time 2026802456 ps
CPU time 48.33 seconds
Started Sep 18 06:21:23 AM UTC 24
Finished Sep 18 06:22:13 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921396708 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.1921396708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.631574882
Short name T426
Test name
Test status
Simulation time 506550131 ps
CPU time 9.86 seconds
Started Sep 18 06:21:27 AM UTC 24
Finished Sep 18 06:21:39 AM UTC 24
Peak memory 222120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631574882 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.631574882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.774634896
Short name T423
Test name
Test status
Simulation time 853428602 ps
CPU time 13.04 seconds
Started Sep 18 06:21:23 AM UTC 24
Finished Sep 18 06:21:38 AM UTC 24
Peak memory 228372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774634896 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.774634896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.189344112
Short name T457
Test name
Test status
Simulation time 1575490180 ps
CPU time 173.31 seconds
Started Sep 18 06:21:25 AM UTC 24
Finished Sep 18 06:24:22 AM UTC 24
Peak memory 226224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189344112 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.189344112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3500663157
Short name T429
Test name
Test status
Simulation time 266910511 ps
CPU time 13.89 seconds
Started Sep 18 06:21:33 AM UTC 24
Finished Sep 18 06:21:48 AM UTC 24
Peak memory 228368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3500663157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rom_ctrl_csr_mem_rw_with_rand_reset.3500663157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.457116114
Short name T117
Test name
Test status
Simulation time 720179614 ps
CPU time 9.15 seconds
Started Sep 18 06:21:32 AM UTC 24
Finished Sep 18 06:21:42 AM UTC 24
Peak memory 222060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457116114 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.457116114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3551942211
Short name T453
Test name
Test status
Simulation time 1574587083 ps
CPU time 77.43 seconds
Started Sep 18 06:21:30 AM UTC 24
Finished Sep 18 06:22:49 AM UTC 24
Peak memory 226316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551942211 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.3551942211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3584080114
Short name T433
Test name
Test status
Simulation time 357878073 ps
CPU time 17.81 seconds
Started Sep 18 06:21:33 AM UTC 24
Finished Sep 18 06:21:52 AM UTC 24
Peak memory 222136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584080114 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.3584080114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2534166091
Short name T431
Test name
Test status
Simulation time 997563268 ps
CPU time 18.17 seconds
Started Sep 18 06:21:31 AM UTC 24
Finished Sep 18 06:21:51 AM UTC 24
Peak memory 228300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534166091 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2534166091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.735401705
Short name T436
Test name
Test status
Simulation time 271462215 ps
CPU time 13.65 seconds
Started Sep 18 06:21:39 AM UTC 24
Finished Sep 18 06:21:54 AM UTC 24
Peak memory 228460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=735401705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.r
om_ctrl_csr_mem_rw_with_rand_reset.735401705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3559048906
Short name T430
Test name
Test status
Simulation time 664104291 ps
CPU time 9.08 seconds
Started Sep 18 06:21:38 AM UTC 24
Finished Sep 18 06:21:48 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559048906 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3559048906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4006466953
Short name T455
Test name
Test status
Simulation time 24837466050 ps
CPU time 101.06 seconds
Started Sep 18 06:21:36 AM UTC 24
Finished Sep 18 06:23:19 AM UTC 24
Peak memory 228492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006466953 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.4006466953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4023224155
Short name T434
Test name
Test status
Simulation time 249218288 ps
CPU time 12.2 seconds
Started Sep 18 06:21:39 AM UTC 24
Finished Sep 18 06:21:53 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023224155 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.4023224155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3424805761
Short name T435
Test name
Test status
Simulation time 516136034 ps
CPU time 15.97 seconds
Started Sep 18 06:21:36 AM UTC 24
Finished Sep 18 06:21:53 AM UTC 24
Peak memory 228364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424805761 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3424805761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.17408383
Short name T148
Test name
Test status
Simulation time 1283493255 ps
CPU time 87.82 seconds
Started Sep 18 06:21:37 AM UTC 24
Finished Sep 18 06:23:07 AM UTC 24
Peak memory 226292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17408383 -assert nopostproc +UVM_
TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.17408383
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1767712748
Short name T443
Test name
Test status
Simulation time 271368552 ps
CPU time 16.61 seconds
Started Sep 18 06:21:47 AM UTC 24
Finished Sep 18 06:22:04 AM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1767712748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rom_ctrl_csr_mem_rw_with_rand_reset.1767712748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3084284642
Short name T437
Test name
Test status
Simulation time 495730030 ps
CPU time 11.78 seconds
Started Sep 18 06:21:42 AM UTC 24
Finished Sep 18 06:21:54 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084284642 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3084284642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2660458235
Short name T451
Test name
Test status
Simulation time 1043429923 ps
CPU time 55.26 seconds
Started Sep 18 06:21:39 AM UTC 24
Finished Sep 18 06:22:36 AM UTC 24
Peak memory 224268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660458235 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.2660458235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4101766825
Short name T438
Test name
Test status
Simulation time 1185234763 ps
CPU time 10.82 seconds
Started Sep 18 06:21:44 AM UTC 24
Finished Sep 18 06:21:56 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101766825 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.4101766825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2690960236
Short name T432
Test name
Test status
Simulation time 345696293 ps
CPU time 11.59 seconds
Started Sep 18 06:21:39 AM UTC 24
Finished Sep 18 06:21:52 AM UTC 24
Peak memory 228300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690960236 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2690960236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.292146904
Short name T147
Test name
Test status
Simulation time 631291509 ps
CPU time 83.25 seconds
Started Sep 18 06:21:40 AM UTC 24
Finished Sep 18 06:23:05 AM UTC 24
Peak memory 226224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292146904 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.292146904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4064900523
Short name T445
Test name
Test status
Simulation time 275338597 ps
CPU time 13.7 seconds
Started Sep 18 06:21:51 AM UTC 24
Finished Sep 18 06:22:06 AM UTC 24
Peak memory 228332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4064900523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rom_ctrl_csr_mem_rw_with_rand_reset.4064900523
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1506865747
Short name T440
Test name
Test status
Simulation time 174924359 ps
CPU time 8.33 seconds
Started Sep 18 06:21:49 AM UTC 24
Finished Sep 18 06:21:58 AM UTC 24
Peak memory 222252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506865747 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1506865747
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3427475936
Short name T454
Test name
Test status
Simulation time 1567996864 ps
CPU time 81.26 seconds
Started Sep 18 06:21:48 AM UTC 24
Finished Sep 18 06:23:11 AM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427475936 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.3427475936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.583762896
Short name T441
Test name
Test status
Simulation time 615657521 ps
CPU time 12.59 seconds
Started Sep 18 06:21:49 AM UTC 24
Finished Sep 18 06:22:03 AM UTC 24
Peak memory 222120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583762896 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.583762896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1181429692
Short name T442
Test name
Test status
Simulation time 661295053 ps
CPU time 13.81 seconds
Started Sep 18 06:21:49 AM UTC 24
Finished Sep 18 06:22:04 AM UTC 24
Peak memory 228364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181429692 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1181429692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1335352625
Short name T145
Test name
Test status
Simulation time 347504810 ps
CPU time 88.43 seconds
Started Sep 18 06:21:49 AM UTC 24
Finished Sep 18 06:23:19 AM UTC 24
Peak memory 224172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335352625 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.1335352625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3851856306
Short name T448
Test name
Test status
Simulation time 1048042385 ps
CPU time 12.07 seconds
Started Sep 18 06:21:54 AM UTC 24
Finished Sep 18 06:22:08 AM UTC 24
Peak memory 228332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3851856306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rom_ctrl_csr_mem_rw_with_rand_reset.3851856306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2773904216
Short name T121
Test name
Test status
Simulation time 662584827 ps
CPU time 7.5 seconds
Started Sep 18 06:21:53 AM UTC 24
Finished Sep 18 06:22:02 AM UTC 24
Peak memory 222060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773904216 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2773904216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2575288073
Short name T452
Test name
Test status
Simulation time 2129412553 ps
CPU time 52.58 seconds
Started Sep 18 06:21:51 AM UTC 24
Finished Sep 18 06:22:45 AM UTC 24
Peak memory 226188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575288073 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.2575288073
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4083092342
Short name T449
Test name
Test status
Simulation time 1005337324 ps
CPU time 14.55 seconds
Started Sep 18 06:21:53 AM UTC 24
Finished Sep 18 06:22:09 AM UTC 24
Peak memory 224300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083092342 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.4083092342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.143421824
Short name T446
Test name
Test status
Simulation time 689785655 ps
CPU time 13.5 seconds
Started Sep 18 06:21:52 AM UTC 24
Finished Sep 18 06:22:07 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143421824 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.143421824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3486691297
Short name T146
Test name
Test status
Simulation time 4195864207 ps
CPU time 97.37 seconds
Started Sep 18 06:21:53 AM UTC 24
Finished Sep 18 06:23:33 AM UTC 24
Peak memory 224236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486691297 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.3486691297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2709675125
Short name T103
Test name
Test status
Simulation time 404589927 ps
CPU time 9.21 seconds
Started Sep 18 06:20:16 AM UTC 24
Finished Sep 18 06:20:27 AM UTC 24
Peak memory 222132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709675125 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.2709675125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1695746002
Short name T379
Test name
Test status
Simulation time 250597101 ps
CPU time 13.38 seconds
Started Sep 18 06:20:16 AM UTC 24
Finished Sep 18 06:20:31 AM UTC 24
Peak memory 222196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695746002 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.1695746002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4287353920
Short name T383
Test name
Test status
Simulation time 264857354 ps
CPU time 15.79 seconds
Started Sep 18 06:20:16 AM UTC 24
Finished Sep 18 06:20:33 AM UTC 24
Peak memory 222132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287353920 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.4287353920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3986167574
Short name T385
Test name
Test status
Simulation time 2223399466 ps
CPU time 16.91 seconds
Started Sep 18 06:20:18 AM UTC 24
Finished Sep 18 06:20:36 AM UTC 24
Peak memory 228560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3986167574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
om_ctrl_csr_mem_rw_with_rand_reset.3986167574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1984826812
Short name T101
Test name
Test status
Simulation time 1269443928 ps
CPU time 7.89 seconds
Started Sep 18 06:20:16 AM UTC 24
Finished Sep 18 06:20:25 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984826812 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1984826812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3097341642
Short name T376
Test name
Test status
Simulation time 345386173 ps
CPU time 9.54 seconds
Started Sep 18 06:20:15 AM UTC 24
Finished Sep 18 06:20:26 AM UTC 24
Peak memory 221936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097341642 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.3097341642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1967516172
Short name T377
Test name
Test status
Simulation time 611954891 ps
CPU time 11.14 seconds
Started Sep 18 06:20:14 AM UTC 24
Finished Sep 18 06:20:26 AM UTC 24
Peak memory 222068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967516172 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.1967516172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3769974663
Short name T154
Test name
Test status
Simulation time 1782901687 ps
CPU time 50.23 seconds
Started Sep 18 06:20:12 AM UTC 24
Finished Sep 18 06:21:04 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769974663 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.3769974663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.596881454
Short name T104
Test name
Test status
Simulation time 332706738 ps
CPU time 10.63 seconds
Started Sep 18 06:20:18 AM UTC 24
Finished Sep 18 06:20:29 AM UTC 24
Peak memory 222136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596881454 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.596881454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3423697984
Short name T380
Test name
Test status
Simulation time 612788223 ps
CPU time 18.33 seconds
Started Sep 18 06:20:12 AM UTC 24
Finished Sep 18 06:20:32 AM UTC 24
Peak memory 228232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423697984 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3423697984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.725358206
Short name T142
Test name
Test status
Simulation time 404754296 ps
CPU time 172.61 seconds
Started Sep 18 06:20:12 AM UTC 24
Finished Sep 18 06:23:08 AM UTC 24
Peak memory 226220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725358206 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.725358206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.303182207
Short name T387
Test name
Test status
Simulation time 260925273 ps
CPU time 13.03 seconds
Started Sep 18 06:20:27 AM UTC 24
Finished Sep 18 06:20:41 AM UTC 24
Peak memory 222028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303182207 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.303182207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1412566016
Short name T106
Test name
Test status
Simulation time 1099594417 ps
CPU time 11.24 seconds
Started Sep 18 06:20:26 AM UTC 24
Finished Sep 18 06:20:38 AM UTC 24
Peak memory 222132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412566016 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.1412566016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.606723965
Short name T389
Test name
Test status
Simulation time 1477540867 ps
CPU time 16.95 seconds
Started Sep 18 06:20:25 AM UTC 24
Finished Sep 18 06:20:43 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606723965 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.606723965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.603513570
Short name T390
Test name
Test status
Simulation time 585678430 ps
CPU time 15.56 seconds
Started Sep 18 06:20:27 AM UTC 24
Finished Sep 18 06:20:44 AM UTC 24
Peak memory 228512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=603513570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ro
m_ctrl_csr_mem_rw_with_rand_reset.603513570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3681249059
Short name T105
Test name
Test status
Simulation time 718984574 ps
CPU time 12.1 seconds
Started Sep 18 06:20:25 AM UTC 24
Finished Sep 18 06:20:38 AM UTC 24
Peak memory 222252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681249059 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3681249059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.667140281
Short name T384
Test name
Test status
Simulation time 2751730550 ps
CPU time 8.4 seconds
Started Sep 18 06:20:24 AM UTC 24
Finished Sep 18 06:20:33 AM UTC 24
Peak memory 221992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667140281 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.667140281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1965330054
Short name T382
Test name
Test status
Simulation time 1449946797 ps
CPU time 10.13 seconds
Started Sep 18 06:20:22 AM UTC 24
Finished Sep 18 06:20:33 AM UTC 24
Peak memory 222000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965330054 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.1965330054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3849611522
Short name T126
Test name
Test status
Simulation time 1061695612 ps
CPU time 63.68 seconds
Started Sep 18 06:20:18 AM UTC 24
Finished Sep 18 06:21:23 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849611522 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.3849611522
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3413613992
Short name T128
Test name
Test status
Simulation time 1643654929 ps
CPU time 14.59 seconds
Started Sep 18 06:20:27 AM UTC 24
Finished Sep 18 06:20:43 AM UTC 24
Peak memory 222120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413613992 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.3413613992
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1560255189
Short name T381
Test name
Test status
Simulation time 1183310970 ps
CPU time 12.68 seconds
Started Sep 18 06:20:19 AM UTC 24
Finished Sep 18 06:20:32 AM UTC 24
Peak memory 228304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560255189 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1560255189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.740413503
Short name T91
Test name
Test status
Simulation time 323229029 ps
CPU time 93.25 seconds
Started Sep 18 06:20:19 AM UTC 24
Finished Sep 18 06:21:54 AM UTC 24
Peak memory 224168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740413503 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.740413503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4260717644
Short name T392
Test name
Test status
Simulation time 663819137 ps
CPU time 12.92 seconds
Started Sep 18 06:20:34 AM UTC 24
Finished Sep 18 06:20:48 AM UTC 24
Peak memory 222132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260717644 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.4260717644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2318107059
Short name T393
Test name
Test status
Simulation time 252397878 ps
CPU time 14 seconds
Started Sep 18 06:20:34 AM UTC 24
Finished Sep 18 06:20:49 AM UTC 24
Peak memory 222072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318107059 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.2318107059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3646132746
Short name T112
Test name
Test status
Simulation time 171572568 ps
CPU time 13.16 seconds
Started Sep 18 06:20:33 AM UTC 24
Finished Sep 18 06:20:47 AM UTC 24
Peak memory 222132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646132746 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.3646132746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1649098883
Short name T394
Test name
Test status
Simulation time 687553657 ps
CPU time 12.19 seconds
Started Sep 18 06:20:37 AM UTC 24
Finished Sep 18 06:20:50 AM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1649098883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
om_ctrl_csr_mem_rw_with_rand_reset.1649098883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.506320836
Short name T107
Test name
Test status
Simulation time 660732712 ps
CPU time 9.28 seconds
Started Sep 18 06:20:34 AM UTC 24
Finished Sep 18 06:20:44 AM UTC 24
Peak memory 222068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506320836 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.506320836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3875423878
Short name T391
Test name
Test status
Simulation time 1029177161 ps
CPU time 13.26 seconds
Started Sep 18 06:20:32 AM UTC 24
Finished Sep 18 06:20:46 AM UTC 24
Peak memory 221936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875423878 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.3875423878
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1631259792
Short name T388
Test name
Test status
Simulation time 970554855 ps
CPU time 10.05 seconds
Started Sep 18 06:20:31 AM UTC 24
Finished Sep 18 06:20:43 AM UTC 24
Peak memory 222000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631259792 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.1631259792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3537172996
Short name T444
Test name
Test status
Simulation time 12922438144 ps
CPU time 95.24 seconds
Started Sep 18 06:20:27 AM UTC 24
Finished Sep 18 06:22:04 AM UTC 24
Peak memory 228372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537172996 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.3537172996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1994924134
Short name T129
Test name
Test status
Simulation time 1043239969 ps
CPU time 13.06 seconds
Started Sep 18 06:20:34 AM UTC 24
Finished Sep 18 06:20:48 AM UTC 24
Peak memory 224168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994924134 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.1994924134
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.176291378
Short name T386
Test name
Test status
Simulation time 174601211 ps
CPU time 10.71 seconds
Started Sep 18 06:20:27 AM UTC 24
Finished Sep 18 06:20:39 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176291378 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.176291378
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3877521324
Short name T92
Test name
Test status
Simulation time 538375202 ps
CPU time 84.78 seconds
Started Sep 18 06:20:30 AM UTC 24
Finished Sep 18 06:21:57 AM UTC 24
Peak memory 226164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877521324 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.3877521324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.620654517
Short name T395
Test name
Test status
Simulation time 177772823 ps
CPU time 9.57 seconds
Started Sep 18 06:20:41 AM UTC 24
Finished Sep 18 06:20:52 AM UTC 24
Peak memory 228336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=620654517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ro
m_ctrl_csr_mem_rw_with_rand_reset.620654517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2327973229
Short name T130
Test name
Test status
Simulation time 247734970 ps
CPU time 9.26 seconds
Started Sep 18 06:20:40 AM UTC 24
Finished Sep 18 06:20:50 AM UTC 24
Peak memory 222000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327973229 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2327973229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2366871686
Short name T119
Test name
Test status
Simulation time 1377518771 ps
CPU time 60.49 seconds
Started Sep 18 06:20:39 AM UTC 24
Finished Sep 18 06:21:41 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366871686 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.2366871686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4267324331
Short name T132
Test name
Test status
Simulation time 532375896 ps
CPU time 18.13 seconds
Started Sep 18 06:20:41 AM UTC 24
Finished Sep 18 06:21:00 AM UTC 24
Peak memory 224172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267324331 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.4267324331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3966263225
Short name T396
Test name
Test status
Simulation time 174514772 ps
CPU time 12.79 seconds
Started Sep 18 06:20:39 AM UTC 24
Finished Sep 18 06:20:53 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966263225 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3966263225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1479861327
Short name T456
Test name
Test status
Simulation time 299354909 ps
CPU time 180.38 seconds
Started Sep 18 06:20:40 AM UTC 24
Finished Sep 18 06:23:43 AM UTC 24
Peak memory 226140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479861327 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.1479861327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2868738258
Short name T397
Test name
Test status
Simulation time 318162849 ps
CPU time 13.56 seconds
Started Sep 18 06:20:45 AM UTC 24
Finished Sep 18 06:20:59 AM UTC 24
Peak memory 226220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2868738258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
om_ctrl_csr_mem_rw_with_rand_reset.2868738258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3100401139
Short name T115
Test name
Test status
Simulation time 1019152902 ps
CPU time 19.09 seconds
Started Sep 18 06:20:44 AM UTC 24
Finished Sep 18 06:21:05 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100401139 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3100401139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1198283261
Short name T125
Test name
Test status
Simulation time 1439317829 ps
CPU time 38 seconds
Started Sep 18 06:20:42 AM UTC 24
Finished Sep 18 06:21:22 AM UTC 24
Peak memory 224212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198283261 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.1198283261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3229604975
Short name T131
Test name
Test status
Simulation time 327287964 ps
CPU time 9.37 seconds
Started Sep 18 06:20:44 AM UTC 24
Finished Sep 18 06:20:55 AM UTC 24
Peak memory 222120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229604975 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.3229604975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1983817550
Short name T398
Test name
Test status
Simulation time 250116333 ps
CPU time 16.87 seconds
Started Sep 18 06:20:43 AM UTC 24
Finished Sep 18 06:21:01 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983817550 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1983817550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1140812057
Short name T139
Test name
Test status
Simulation time 869089518 ps
CPU time 165.84 seconds
Started Sep 18 06:20:43 AM UTC 24
Finished Sep 18 06:23:32 AM UTC 24
Peak memory 226232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140812057 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.1140812057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3326200738
Short name T401
Test name
Test status
Simulation time 969895810 ps
CPU time 15.02 seconds
Started Sep 18 06:20:49 AM UTC 24
Finished Sep 18 06:21:05 AM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3326200738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
om_ctrl_csr_mem_rw_with_rand_reset.3326200738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1726224620
Short name T118
Test name
Test status
Simulation time 1033301308 ps
CPU time 13.56 seconds
Started Sep 18 06:20:48 AM UTC 24
Finished Sep 18 06:21:02 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726224620 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1726224620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3110310585
Short name T421
Test name
Test status
Simulation time 1056685648 ps
CPU time 49.18 seconds
Started Sep 18 06:20:45 AM UTC 24
Finished Sep 18 06:21:35 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110310585 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.3110310585
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1187343529
Short name T400
Test name
Test status
Simulation time 3524387672 ps
CPU time 12.47 seconds
Started Sep 18 06:20:49 AM UTC 24
Finished Sep 18 06:21:02 AM UTC 24
Peak memory 222184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187343529 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.1187343529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2835616072
Short name T399
Test name
Test status
Simulation time 494737242 ps
CPU time 16.55 seconds
Started Sep 18 06:20:45 AM UTC 24
Finished Sep 18 06:21:02 AM UTC 24
Peak memory 228372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835616072 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2835616072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.75354187
Short name T144
Test name
Test status
Simulation time 642314688 ps
CPU time 149.56 seconds
Started Sep 18 06:20:47 AM UTC 24
Finished Sep 18 06:23:19 AM UTC 24
Peak memory 226296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75354187 -assert nopostproc +UVM_
TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.75354187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2929574332
Short name T403
Test name
Test status
Simulation time 261971131 ps
CPU time 13.8 seconds
Started Sep 18 06:20:52 AM UTC 24
Finished Sep 18 06:21:07 AM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2929574332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
om_ctrl_csr_mem_rw_with_rand_reset.2929574332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2897653955
Short name T116
Test name
Test status
Simulation time 507777338 ps
CPU time 12.37 seconds
Started Sep 18 06:20:51 AM UTC 24
Finished Sep 18 06:21:05 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897653955 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2897653955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2920237377
Short name T120
Test name
Test status
Simulation time 3169635330 ps
CPU time 58.87 seconds
Started Sep 18 06:20:50 AM UTC 24
Finished Sep 18 06:21:50 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920237377 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.2920237377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.576971687
Short name T405
Test name
Test status
Simulation time 268767581 ps
CPU time 20.38 seconds
Started Sep 18 06:20:52 AM UTC 24
Finished Sep 18 06:21:14 AM UTC 24
Peak memory 224248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576971687 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.576971687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.478741872
Short name T402
Test name
Test status
Simulation time 3081179191 ps
CPU time 14.53 seconds
Started Sep 18 06:20:51 AM UTC 24
Finished Sep 18 06:21:07 AM UTC 24
Peak memory 228372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478741872 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.478741872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2620842516
Short name T137
Test name
Test status
Simulation time 333598661 ps
CPU time 109.18 seconds
Started Sep 18 06:20:51 AM UTC 24
Finished Sep 18 06:22:43 AM UTC 24
Peak memory 226232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620842516 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.2620842516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1351628239
Short name T411
Test name
Test status
Simulation time 1079321266 ps
CPU time 15.68 seconds
Started Sep 18 06:21:02 AM UTC 24
Finished Sep 18 06:21:19 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1351628239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
om_ctrl_csr_mem_rw_with_rand_reset.1351628239
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2304763044
Short name T408
Test name
Test status
Simulation time 1031314870 ps
CPU time 13.79 seconds
Started Sep 18 06:21:00 AM UTC 24
Finished Sep 18 06:21:14 AM UTC 24
Peak memory 222124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304763044 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2304763044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3639860951
Short name T439
Test name
Test status
Simulation time 11209649953 ps
CPU time 61.7 seconds
Started Sep 18 06:20:52 AM UTC 24
Finished Sep 18 06:21:56 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639860951 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.3639860951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2219617422
Short name T406
Test name
Test status
Simulation time 174221328 ps
CPU time 12.23 seconds
Started Sep 18 06:21:01 AM UTC 24
Finished Sep 18 06:21:14 AM UTC 24
Peak memory 222060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219617422 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.2219617422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.32369919
Short name T404
Test name
Test status
Simulation time 507949433 ps
CPU time 13.6 seconds
Started Sep 18 06:20:53 AM UTC 24
Finished Sep 18 06:21:08 AM UTC 24
Peak memory 228228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32369919 -assert nopostproc +UVM_TESTNAME=rom
_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.32369919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2475843389
Short name T1
Test name
Test status
Simulation time 972178514 ps
CPU time 8.15 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:40 AM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475843389 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2475843389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3739512982
Short name T8
Test name
Test status
Simulation time 1112840764 ps
CPU time 10.55 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:43 AM UTC 24
Peak memory 229988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739512982 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3739512982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.3266451201
Short name T29
Test name
Test status
Simulation time 487198655 ps
CPU time 221.53 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:18:16 AM UTC 24
Peak memory 261252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266451201 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3266451201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.797266921
Short name T13
Test name
Test status
Simulation time 2035202116 ps
CPU time 23.92 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:56 AM UTC 24
Peak memory 230736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797266921
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.797266921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.548883710
Short name T14
Test name
Test status
Simulation time 3756687767 ps
CPU time 27.96 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:15:00 AM UTC 24
Peak memory 232976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=548883710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.rom_ctrl_stress_all_with_rand_reset.548883710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.781965927
Short name T349
Test name
Test status
Simulation time 155310142633 ps
CPU time 434.25 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:21:51 AM UTC 24
Peak memory 259488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781965927 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.781965927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3457257277
Short name T6
Test name
Test status
Simulation time 716811618 ps
CPU time 10.06 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:42 AM UTC 24
Peak memory 230584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457257277 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3457257277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.2086172742
Short name T22
Test name
Test status
Simulation time 1037681042 ps
CPU time 14.42 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:47 AM UTC 24
Peak memory 230740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086172742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2086172742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2945540772
Short name T2
Test name
Test status
Simulation time 660561973 ps
CPU time 8.96 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:41 AM UTC 24
Peak memory 230516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294554077
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.2945540772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.235861380
Short name T163
Test name
Test status
Simulation time 176938752 ps
CPU time 8.3 seconds
Started Sep 18 06:14:58 AM UTC 24
Finished Sep 18 06:15:07 AM UTC 24
Peak memory 229880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235861380 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.235861380
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2824250214
Short name T56
Test name
Test status
Simulation time 2811202146 ps
CPU time 207.62 seconds
Started Sep 18 06:14:58 AM UTC 24
Finished Sep 18 06:18:29 AM UTC 24
Peak memory 258904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824250214 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.2824250214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1377811635
Short name T150
Test name
Test status
Simulation time 3979878387 ps
CPU time 17.53 seconds
Started Sep 18 06:14:58 AM UTC 24
Finished Sep 18 06:15:16 AM UTC 24
Peak memory 230852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377811635 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1377811635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3734800655
Short name T41
Test name
Test status
Simulation time 536228944 ps
CPU time 25.98 seconds
Started Sep 18 06:14:56 AM UTC 24
Finished Sep 18 06:15:23 AM UTC 24
Peak memory 230720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373480065
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.3734800655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2923237381
Short name T245
Test name
Test status
Simulation time 16283554809 ps
CPU time 202.77 seconds
Started Sep 18 06:14:58 AM UTC 24
Finished Sep 18 06:18:24 AM UTC 24
Peak memory 247604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2923237381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2923237381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.438686219
Short name T165
Test name
Test status
Simulation time 992446004 ps
CPU time 10 seconds
Started Sep 18 06:15:03 AM UTC 24
Finished Sep 18 06:15:14 AM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438686219 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.438686219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1765235834
Short name T344
Test name
Test status
Simulation time 80259497422 ps
CPU time 389.53 seconds
Started Sep 18 06:15:01 AM UTC 24
Finished Sep 18 06:21:35 AM UTC 24
Peak memory 259420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765235834 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.1765235834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.521488899
Short name T156
Test name
Test status
Simulation time 500631542 ps
CPU time 13.37 seconds
Started Sep 18 06:15:01 AM UTC 24
Finished Sep 18 06:15:15 AM UTC 24
Peak memory 230388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521488899 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.521488899
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1797760524
Short name T110
Test name
Test status
Simulation time 560024098 ps
CPU time 29.41 seconds
Started Sep 18 06:15:00 AM UTC 24
Finished Sep 18 06:15:31 AM UTC 24
Peak memory 230800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179776052
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.1797760524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1071637319
Short name T57
Test name
Test status
Simulation time 10644227840 ps
CPU time 135.36 seconds
Started Sep 18 06:15:01 AM UTC 24
Finished Sep 18 06:17:18 AM UTC 24
Peak memory 247304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1071637319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1071637319
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.4255999043
Short name T167
Test name
Test status
Simulation time 787693068 ps
CPU time 11.38 seconds
Started Sep 18 06:15:05 AM UTC 24
Finished Sep 18 06:15:18 AM UTC 24
Peak memory 230212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255999043 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4255999043
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.230244358
Short name T270
Test name
Test status
Simulation time 9291424096 ps
CPU time 234.86 seconds
Started Sep 18 06:15:03 AM UTC 24
Finished Sep 18 06:19:01 AM UTC 24
Peak memory 258816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230244358 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.230244358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2075550383
Short name T159
Test name
Test status
Simulation time 665956908 ps
CPU time 22.96 seconds
Started Sep 18 06:15:03 AM UTC 24
Finished Sep 18 06:15:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075550383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2075550383
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1944720060
Short name T155
Test name
Test status
Simulation time 280843383 ps
CPU time 9.87 seconds
Started Sep 18 06:15:03 AM UTC 24
Finished Sep 18 06:15:14 AM UTC 24
Peak memory 230448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944720060 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1944720060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.16474615
Short name T74
Test name
Test status
Simulation time 295475624 ps
CPU time 19.99 seconds
Started Sep 18 06:15:03 AM UTC 24
Finished Sep 18 06:15:24 AM UTC 24
Peak memory 230868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16474615
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.16474615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1696962255
Short name T168
Test name
Test status
Simulation time 616335120 ps
CPU time 11.91 seconds
Started Sep 18 06:15:09 AM UTC 24
Finished Sep 18 06:15:23 AM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696962255 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1696962255
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1388534733
Short name T45
Test name
Test status
Simulation time 3298707947 ps
CPU time 188.12 seconds
Started Sep 18 06:15:05 AM UTC 24
Finished Sep 18 06:18:17 AM UTC 24
Peak memory 259764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388534733 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.1388534733
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2584238484
Short name T181
Test name
Test status
Simulation time 17921147059 ps
CPU time 41.77 seconds
Started Sep 18 06:15:07 AM UTC 24
Finished Sep 18 06:15:51 AM UTC 24
Peak memory 229872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584238484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2584238484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.3391239485
Short name T166
Test name
Test status
Simulation time 182535489 ps
CPU time 11.22 seconds
Started Sep 18 06:15:05 AM UTC 24
Finished Sep 18 06:15:18 AM UTC 24
Peak memory 230456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391239485 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3391239485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1391666359
Short name T164
Test name
Test status
Simulation time 1445632819 ps
CPU time 30.66 seconds
Started Sep 18 06:15:05 AM UTC 24
Finished Sep 18 06:15:38 AM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139166635
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.1391666359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.38755703
Short name T169
Test name
Test status
Simulation time 377508538 ps
CPU time 11.41 seconds
Started Sep 18 06:15:12 AM UTC 24
Finished Sep 18 06:15:24 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38755703 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.38755703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2324185042
Short name T330
Test name
Test status
Simulation time 10558891454 ps
CPU time 304.29 seconds
Started Sep 18 06:15:10 AM UTC 24
Finished Sep 18 06:20:18 AM UTC 24
Peak memory 258904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324185042 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.2324185042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.676970757
Short name T177
Test name
Test status
Simulation time 1767579920 ps
CPU time 29.45 seconds
Started Sep 18 06:15:10 AM UTC 24
Finished Sep 18 06:15:40 AM UTC 24
Peak memory 230580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676970757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.676970757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.4048847674
Short name T170
Test name
Test status
Simulation time 264396582 ps
CPU time 14.43 seconds
Started Sep 18 06:15:10 AM UTC 24
Finished Sep 18 06:15:25 AM UTC 24
Peak memory 230576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048847674 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4048847674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3316807937
Short name T82
Test name
Test status
Simulation time 1830846841 ps
CPU time 74.09 seconds
Started Sep 18 06:15:10 AM UTC 24
Finished Sep 18 06:16:26 AM UTC 24
Peak memory 241224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3316807937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3316807937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3036268965
Short name T160
Test name
Test status
Simulation time 259226110 ps
CPU time 11.58 seconds
Started Sep 18 06:15:20 AM UTC 24
Finished Sep 18 06:15:33 AM UTC 24
Peak memory 229816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036268965 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3036268965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3891714763
Short name T47
Test name
Test status
Simulation time 4791644564 ps
CPU time 178.82 seconds
Started Sep 18 06:15:16 AM UTC 24
Finished Sep 18 06:18:17 AM UTC 24
Peak memory 230268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891714763 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.3891714763
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3437917640
Short name T176
Test name
Test status
Simulation time 664179896 ps
CPU time 21.51 seconds
Started Sep 18 06:15:16 AM UTC 24
Finished Sep 18 06:15:39 AM UTC 24
Peak memory 230448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437917640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3437917640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3638585211
Short name T171
Test name
Test status
Simulation time 472000194 ps
CPU time 13.89 seconds
Started Sep 18 06:15:16 AM UTC 24
Finished Sep 18 06:15:31 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638585211 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3638585211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.392236580
Short name T75
Test name
Test status
Simulation time 561022017 ps
CPU time 22.43 seconds
Started Sep 18 06:15:14 AM UTC 24
Finished Sep 18 06:15:38 AM UTC 24
Peak memory 230812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392236580
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.392236580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.682670112
Short name T81
Test name
Test status
Simulation time 4168613124 ps
CPU time 44.66 seconds
Started Sep 18 06:15:18 AM UTC 24
Finished Sep 18 06:16:04 AM UTC 24
Peak memory 245524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=682670112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.rom_ctrl_stress_all_with_rand_reset.682670112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1346619878
Short name T173
Test name
Test status
Simulation time 347593691 ps
CPU time 7.55 seconds
Started Sep 18 06:15:24 AM UTC 24
Finished Sep 18 06:15:33 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346619878 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1346619878
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2772076771
Short name T286
Test name
Test status
Simulation time 15622709394 ps
CPU time 237.28 seconds
Started Sep 18 06:15:22 AM UTC 24
Finished Sep 18 06:19:23 AM UTC 24
Peak memory 259760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772076771 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.2772076771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1941432035
Short name T179
Test name
Test status
Simulation time 771725049 ps
CPU time 18.96 seconds
Started Sep 18 06:15:24 AM UTC 24
Finished Sep 18 06:15:44 AM UTC 24
Peak memory 229964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941432035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1941432035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3539805583
Short name T175
Test name
Test status
Simulation time 726223004 ps
CPU time 15.47 seconds
Started Sep 18 06:15:20 AM UTC 24
Finished Sep 18 06:15:37 AM UTC 24
Peak memory 230392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539805583 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3539805583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.2396786481
Short name T161
Test name
Test status
Simulation time 388258521 ps
CPU time 36.81 seconds
Started Sep 18 06:15:20 AM UTC 24
Finished Sep 18 06:15:58 AM UTC 24
Peak memory 230720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239678648
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.2396786481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3985469459
Short name T297
Test name
Test status
Simulation time 16306771330 ps
CPU time 251.77 seconds
Started Sep 18 06:15:24 AM UTC 24
Finished Sep 18 06:19:40 AM UTC 24
Peak memory 248556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3985469459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3985469459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.510679828
Short name T180
Test name
Test status
Simulation time 2068949013 ps
CPU time 12.72 seconds
Started Sep 18 06:15:33 AM UTC 24
Finished Sep 18 06:15:47 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510679828 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.510679828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1052128521
Short name T335
Test name
Test status
Simulation time 5023286788 ps
CPU time 312.87 seconds
Started Sep 18 06:15:27 AM UTC 24
Finished Sep 18 06:20:44 AM UTC 24
Peak memory 230128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052128521 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.1052128521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1009032110
Short name T182
Test name
Test status
Simulation time 1027762493 ps
CPU time 21.23 seconds
Started Sep 18 06:15:29 AM UTC 24
Finished Sep 18 06:15:51 AM UTC 24
Peak memory 230388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009032110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1009032110
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.56680106
Short name T178
Test name
Test status
Simulation time 692478749 ps
CPU time 12.77 seconds
Started Sep 18 06:15:27 AM UTC 24
Finished Sep 18 06:15:40 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56680106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.56680106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2926885071
Short name T111
Test name
Test status
Simulation time 3047513975 ps
CPU time 42.76 seconds
Started Sep 18 06:15:27 AM UTC 24
Finished Sep 18 06:16:11 AM UTC 24
Peak memory 229800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292688507
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.2926885071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3597027201
Short name T76
Test name
Test status
Simulation time 2073418208 ps
CPU time 91.26 seconds
Started Sep 18 06:15:33 AM UTC 24
Finished Sep 18 06:17:06 AM UTC 24
Peak memory 248236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3597027201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3597027201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.3432724691
Short name T162
Test name
Test status
Simulation time 1833680606 ps
CPU time 12.67 seconds
Started Sep 18 06:15:39 AM UTC 24
Finished Sep 18 06:15:53 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432724691 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3432724691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2273873791
Short name T49
Test name
Test status
Simulation time 10644699310 ps
CPU time 160.92 seconds
Started Sep 18 06:15:35 AM UTC 24
Finished Sep 18 06:18:19 AM UTC 24
Peak memory 246404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273873791 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.2273873791
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3603864262
Short name T188
Test name
Test status
Simulation time 664477898 ps
CPU time 21.4 seconds
Started Sep 18 06:15:37 AM UTC 24
Finished Sep 18 06:15:59 AM UTC 24
Peak memory 230796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603864262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3603864262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.660254574
Short name T184
Test name
Test status
Simulation time 524662329 ps
CPU time 17.22 seconds
Started Sep 18 06:15:35 AM UTC 24
Finished Sep 18 06:15:53 AM UTC 24
Peak memory 230380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660254574 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.660254574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.91682632
Short name T189
Test name
Test status
Simulation time 538339377 ps
CPU time 28.15 seconds
Started Sep 18 06:15:33 AM UTC 24
Finished Sep 18 06:16:02 AM UTC 24
Peak memory 230804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91682632
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.91682632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.586086467
Short name T151
Test name
Test status
Simulation time 11245505469 ps
CPU time 116.33 seconds
Started Sep 18 06:15:39 AM UTC 24
Finished Sep 18 06:17:37 AM UTC 24
Peak memory 247312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=586086467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.rom_ctrl_stress_all_with_rand_reset.586086467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3727510260
Short name T186
Test name
Test status
Simulation time 993961736 ps
CPU time 11.68 seconds
Started Sep 18 06:15:42 AM UTC 24
Finished Sep 18 06:15:55 AM UTC 24
Peak memory 230312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727510260 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3727510260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1867219607
Short name T294
Test name
Test status
Simulation time 15620955986 ps
CPU time 230.12 seconds
Started Sep 18 06:15:42 AM UTC 24
Finished Sep 18 06:19:35 AM UTC 24
Peak memory 258828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867219607 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.1867219607
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1867260916
Short name T185
Test name
Test status
Simulation time 185035639 ps
CPU time 14.38 seconds
Started Sep 18 06:15:39 AM UTC 24
Finished Sep 18 06:15:54 AM UTC 24
Peak memory 230368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867260916 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1867260916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.4212385887
Short name T187
Test name
Test status
Simulation time 696948900 ps
CPU time 15.28 seconds
Started Sep 18 06:15:39 AM UTC 24
Finished Sep 18 06:15:55 AM UTC 24
Peak memory 230496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421238588
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.4212385887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3240022018
Short name T228
Test name
Test status
Simulation time 2854530557 ps
CPU time 121.4 seconds
Started Sep 18 06:15:42 AM UTC 24
Finished Sep 18 06:17:45 AM UTC 24
Peak memory 241164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3240022018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3240022018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3404552828
Short name T24
Test name
Test status
Simulation time 265513130 ps
CPU time 12.63 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:45 AM UTC 24
Peak memory 229624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404552828 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3404552828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3161267270
Short name T79
Test name
Test status
Simulation time 26637030832 ps
CPU time 312.54 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:19:48 AM UTC 24
Peak memory 231300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161267270 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.3161267270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2736555205
Short name T10
Test name
Test status
Simulation time 267183766 ps
CPU time 10.9 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:43 AM UTC 24
Peak memory 230144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736555205 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2736555205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1184618180
Short name T31
Test name
Test status
Simulation time 866661056 ps
CPU time 244.24 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:18:39 AM UTC 24
Peak memory 259720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184618180 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1184618180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.735129421
Short name T236
Test name
Test status
Simulation time 4052226051 ps
CPU time 203.83 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:17:58 AM UTC 24
Peak memory 237072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=735129421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.rom_ctrl_stress_all_with_rand_reset.735129421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.2402915691
Short name T192
Test name
Test status
Simulation time 662805222 ps
CPU time 9.9 seconds
Started Sep 18 06:15:54 AM UTC 24
Finished Sep 18 06:16:05 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402915691 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2402915691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1787442902
Short name T283
Test name
Test status
Simulation time 4909291293 ps
CPU time 203.85 seconds
Started Sep 18 06:15:52 AM UTC 24
Finished Sep 18 06:19:19 AM UTC 24
Peak memory 230508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787442902 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.1787442902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1167409414
Short name T196
Test name
Test status
Simulation time 1138538079 ps
CPU time 24.82 seconds
Started Sep 18 06:15:52 AM UTC 24
Finished Sep 18 06:16:18 AM UTC 24
Peak memory 230536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167409414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1167409414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1691111354
Short name T191
Test name
Test status
Simulation time 178165681 ps
CPU time 16.03 seconds
Started Sep 18 06:15:48 AM UTC 24
Finished Sep 18 06:16:05 AM UTC 24
Peak memory 230184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691111354 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1691111354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.57540294
Short name T200
Test name
Test status
Simulation time 3983026417 ps
CPU time 37.06 seconds
Started Sep 18 06:15:46 AM UTC 24
Finished Sep 18 06:16:24 AM UTC 24
Peak memory 231044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57540294
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.57540294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.301148546
Short name T153
Test name
Test status
Simulation time 14322859542 ps
CPU time 151.76 seconds
Started Sep 18 06:15:54 AM UTC 24
Finished Sep 18 06:18:28 AM UTC 24
Peak memory 248368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=301148546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.rom_ctrl_stress_all_with_rand_reset.301148546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1014317625
Short name T193
Test name
Test status
Simulation time 988178831 ps
CPU time 12.73 seconds
Started Sep 18 06:15:56 AM UTC 24
Finished Sep 18 06:16:10 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014317625 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1014317625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3214281447
Short name T329
Test name
Test status
Simulation time 51696086476 ps
CPU time 257.28 seconds
Started Sep 18 06:15:55 AM UTC 24
Finished Sep 18 06:20:16 AM UTC 24
Peak memory 261800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214281447 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.3214281447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.881006436
Short name T197
Test name
Test status
Simulation time 738880139 ps
CPU time 25.3 seconds
Started Sep 18 06:15:55 AM UTC 24
Finished Sep 18 06:16:22 AM UTC 24
Peak memory 230788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881006436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.881006436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.4259477735
Short name T194
Test name
Test status
Simulation time 185138974 ps
CPU time 16.05 seconds
Started Sep 18 06:15:55 AM UTC 24
Finished Sep 18 06:16:12 AM UTC 24
Peak memory 230232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259477735 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4259477735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.15006382
Short name T199
Test name
Test status
Simulation time 1389401319 ps
CPU time 28.47 seconds
Started Sep 18 06:15:54 AM UTC 24
Finished Sep 18 06:16:24 AM UTC 24
Peak memory 230740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15006382
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.15006382
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.181760135
Short name T322
Test name
Test status
Simulation time 19997278788 ps
CPU time 251.1 seconds
Started Sep 18 06:15:55 AM UTC 24
Finished Sep 18 06:20:10 AM UTC 24
Peak memory 241364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=181760135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.rom_ctrl_stress_all_with_rand_reset.181760135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3287263068
Short name T201
Test name
Test status
Simulation time 1028945471 ps
CPU time 19.03 seconds
Started Sep 18 06:16:06 AM UTC 24
Finished Sep 18 06:16:26 AM UTC 24
Peak memory 229816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287263068 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3287263068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.195752535
Short name T73
Test name
Test status
Simulation time 2112824800 ps
CPU time 129.72 seconds
Started Sep 18 06:16:04 AM UTC 24
Finished Sep 18 06:18:16 AM UTC 24
Peak memory 261800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195752535 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.195752535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.1341588776
Short name T204
Test name
Test status
Simulation time 1031284312 ps
CPU time 28.06 seconds
Started Sep 18 06:16:04 AM UTC 24
Finished Sep 18 06:16:33 AM UTC 24
Peak memory 230792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341588776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1341588776
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2068698277
Short name T195
Test name
Test status
Simulation time 186511418 ps
CPU time 10.88 seconds
Started Sep 18 06:16:00 AM UTC 24
Finished Sep 18 06:16:12 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068698277 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2068698277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.1143119790
Short name T208
Test name
Test status
Simulation time 2290200807 ps
CPU time 40.85 seconds
Started Sep 18 06:15:59 AM UTC 24
Finished Sep 18 06:16:42 AM UTC 24
Peak memory 231056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114311979
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.1143119790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4042000332
Short name T223
Test name
Test status
Simulation time 1007194915 ps
CPU time 69.95 seconds
Started Sep 18 06:16:05 AM UTC 24
Finished Sep 18 06:17:16 AM UTC 24
Peak memory 248236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4042000332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4042000332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2758574100
Short name T202
Test name
Test status
Simulation time 516664785 ps
CPU time 13.11 seconds
Started Sep 18 06:16:14 AM UTC 24
Finished Sep 18 06:16:28 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758574100 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2758574100
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2452102740
Short name T346
Test name
Test status
Simulation time 79062758922 ps
CPU time 332.21 seconds
Started Sep 18 06:16:10 AM UTC 24
Finished Sep 18 06:21:47 AM UTC 24
Peak memory 248628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452102740 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.2452102740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1491551848
Short name T205
Test name
Test status
Simulation time 2064529823 ps
CPU time 25.52 seconds
Started Sep 18 06:16:11 AM UTC 24
Finished Sep 18 06:16:38 AM UTC 24
Peak memory 230796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491551848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1491551848
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2587969371
Short name T198
Test name
Test status
Simulation time 184822304 ps
CPU time 14.89 seconds
Started Sep 18 06:16:07 AM UTC 24
Finished Sep 18 06:16:23 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587969371 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2587969371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.4156868324
Short name T215
Test name
Test status
Simulation time 837877273 ps
CPU time 51.27 seconds
Started Sep 18 06:16:06 AM UTC 24
Finished Sep 18 06:16:59 AM UTC 24
Peak memory 230992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415686832
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.4156868324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1677996243
Short name T321
Test name
Test status
Simulation time 5191941715 ps
CPU time 229.93 seconds
Started Sep 18 06:16:14 AM UTC 24
Finished Sep 18 06:20:07 AM UTC 24
Peak memory 248364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1677996243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1677996243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4190295502
Short name T206
Test name
Test status
Simulation time 993944171 ps
CPU time 13.59 seconds
Started Sep 18 06:16:25 AM UTC 24
Finished Sep 18 06:16:39 AM UTC 24
Peak memory 229816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190295502 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4190295502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2963196395
Short name T80
Test name
Test status
Simulation time 2427128325 ps
CPU time 203.53 seconds
Started Sep 18 06:16:22 AM UTC 24
Finished Sep 18 06:19:50 AM UTC 24
Peak memory 259856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963196395 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.2963196395
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1049057516
Short name T210
Test name
Test status
Simulation time 503198645 ps
CPU time 20.96 seconds
Started Sep 18 06:16:23 AM UTC 24
Finished Sep 18 06:16:46 AM UTC 24
Peak memory 230456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049057516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1049057516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1792242025
Short name T203
Test name
Test status
Simulation time 350586804 ps
CPU time 10.39 seconds
Started Sep 18 06:16:18 AM UTC 24
Finished Sep 18 06:16:30 AM UTC 24
Peak memory 230584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792242025 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1792242025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2007780497
Short name T207
Test name
Test status
Simulation time 634453373 ps
CPU time 20.63 seconds
Started Sep 18 06:16:17 AM UTC 24
Finished Sep 18 06:16:40 AM UTC 24
Peak memory 230736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200778049
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.2007780497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1949147419
Short name T241
Test name
Test status
Simulation time 2200764092 ps
CPU time 99.78 seconds
Started Sep 18 06:16:24 AM UTC 24
Finished Sep 18 06:18:06 AM UTC 24
Peak memory 237320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1949147419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1949147419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3209032957
Short name T211
Test name
Test status
Simulation time 2070464131 ps
CPU time 11.99 seconds
Started Sep 18 06:16:34 AM UTC 24
Finished Sep 18 06:16:47 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209032957 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3209032957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1309793505
Short name T353
Test name
Test status
Simulation time 25779376485 ps
CPU time 384.09 seconds
Started Sep 18 06:16:27 AM UTC 24
Finished Sep 18 06:22:56 AM UTC 24
Peak memory 260048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309793505 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.1309793505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.4179831135
Short name T212
Test name
Test status
Simulation time 874665425 ps
CPU time 19.63 seconds
Started Sep 18 06:16:29 AM UTC 24
Finished Sep 18 06:16:50 AM UTC 24
Peak memory 230924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179831135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4179831135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1138375726
Short name T209
Test name
Test status
Simulation time 564950771 ps
CPU time 15.93 seconds
Started Sep 18 06:16:27 AM UTC 24
Finished Sep 18 06:16:44 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138375726 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1138375726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.261029553
Short name T217
Test name
Test status
Simulation time 4808174494 ps
CPU time 43.42 seconds
Started Sep 18 06:16:25 AM UTC 24
Finished Sep 18 06:17:10 AM UTC 24
Peak memory 230860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261029553
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.261029553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.982673234
Short name T222
Test name
Test status
Simulation time 3783793947 ps
CPU time 42.73 seconds
Started Sep 18 06:16:31 AM UTC 24
Finished Sep 18 06:17:15 AM UTC 24
Peak memory 235024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=982673234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.rom_ctrl_stress_all_with_rand_reset.982673234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.1902135057
Short name T214
Test name
Test status
Simulation time 1034022585 ps
CPU time 12.56 seconds
Started Sep 18 06:16:44 AM UTC 24
Finished Sep 18 06:16:58 AM UTC 24
Peak memory 229996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902135057 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1902135057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3182224937
Short name T326
Test name
Test status
Simulation time 3630067643 ps
CPU time 211.48 seconds
Started Sep 18 06:16:40 AM UTC 24
Finished Sep 18 06:20:15 AM UTC 24
Peak memory 248392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182224937 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.3182224937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2357234366
Short name T221
Test name
Test status
Simulation time 496111946 ps
CPU time 32.98 seconds
Started Sep 18 06:16:40 AM UTC 24
Finished Sep 18 06:17:14 AM UTC 24
Peak memory 230988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357234366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2357234366
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2372995752
Short name T213
Test name
Test status
Simulation time 184641808 ps
CPU time 15.29 seconds
Started Sep 18 06:16:39 AM UTC 24
Finished Sep 18 06:16:56 AM UTC 24
Peak memory 230176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372995752 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2372995752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2813370731
Short name T220
Test name
Test status
Simulation time 367745840 ps
CPU time 36.75 seconds
Started Sep 18 06:16:35 AM UTC 24
Finished Sep 18 06:17:13 AM UTC 24
Peak memory 230736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281337073
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.2813370731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.347883149
Short name T53
Test name
Test status
Simulation time 6855607458 ps
CPU time 99.32 seconds
Started Sep 18 06:16:42 AM UTC 24
Finished Sep 18 06:18:24 AM UTC 24
Peak memory 237248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=347883149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.rom_ctrl_stress_all_with_rand_reset.347883149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.13688321
Short name T219
Test name
Test status
Simulation time 167964878 ps
CPU time 11.81 seconds
Started Sep 18 06:16:59 AM UTC 24
Finished Sep 18 06:17:12 AM UTC 24
Peak memory 229692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13688321 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.13688321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.462428585
Short name T331
Test name
Test status
Simulation time 13495075328 ps
CPU time 216.36 seconds
Started Sep 18 06:16:50 AM UTC 24
Finished Sep 18 06:20:30 AM UTC 24
Peak memory 261812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462428585 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.462428585
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1543354820
Short name T59
Test name
Test status
Simulation time 349719796 ps
CPU time 21.98 seconds
Started Sep 18 06:16:57 AM UTC 24
Finished Sep 18 06:17:20 AM UTC 24
Peak memory 230860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543354820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1543354820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.3763741584
Short name T216
Test name
Test status
Simulation time 258937611 ps
CPU time 16.92 seconds
Started Sep 18 06:16:48 AM UTC 24
Finished Sep 18 06:17:06 AM UTC 24
Peak memory 230320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763741584 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3763741584
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2995309190
Short name T58
Test name
Test status
Simulation time 538890564 ps
CPU time 32.42 seconds
Started Sep 18 06:16:46 AM UTC 24
Finished Sep 18 06:17:20 AM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299530919
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.2995309190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1033317849
Short name T315
Test name
Test status
Simulation time 25675063667 ps
CPU time 176.49 seconds
Started Sep 18 06:16:59 AM UTC 24
Finished Sep 18 06:19:59 AM UTC 24
Peak memory 239952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1033317849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1033317849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.1598376974
Short name T62
Test name
Test status
Simulation time 660579583 ps
CPU time 12.27 seconds
Started Sep 18 06:17:12 AM UTC 24
Finished Sep 18 06:17:25 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598376974 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1598376974
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.17689207
Short name T355
Test name
Test status
Simulation time 4332958183 ps
CPU time 348.66 seconds
Started Sep 18 06:17:08 AM UTC 24
Finished Sep 18 06:23:01 AM UTC 24
Peak memory 264004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17689207 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.17689207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.434866354
Short name T61
Test name
Test status
Simulation time 184148947 ps
CPU time 13.62 seconds
Started Sep 18 06:17:07 AM UTC 24
Finished Sep 18 06:17:22 AM UTC 24
Peak memory 230364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434866354 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.434866354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.2326850999
Short name T60
Test name
Test status
Simulation time 581684758 ps
CPU time 21.22 seconds
Started Sep 18 06:16:59 AM UTC 24
Finished Sep 18 06:17:22 AM UTC 24
Peak memory 230800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232685099
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.2326850999
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4158454934
Short name T267
Test name
Test status
Simulation time 10968794720 ps
CPU time 106.88 seconds
Started Sep 18 06:17:12 AM UTC 24
Finished Sep 18 06:19:00 AM UTC 24
Peak memory 237332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4158454934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.4158454934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2502240547
Short name T65
Test name
Test status
Simulation time 664766308 ps
CPU time 11.63 seconds
Started Sep 18 06:17:19 AM UTC 24
Finished Sep 18 06:17:32 AM UTC 24
Peak memory 229584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502240547 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2502240547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2934879329
Short name T336
Test name
Test status
Simulation time 14326328041 ps
CPU time 204.99 seconds
Started Sep 18 06:17:16 AM UTC 24
Finished Sep 18 06:20:44 AM UTC 24
Peak memory 259584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934879329 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.2934879329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2186773779
Short name T225
Test name
Test status
Simulation time 661261378 ps
CPU time 18.6 seconds
Started Sep 18 06:17:17 AM UTC 24
Finished Sep 18 06:17:37 AM UTC 24
Peak memory 230304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186773779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2186773779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.634514968
Short name T63
Test name
Test status
Simulation time 736870420 ps
CPU time 11.92 seconds
Started Sep 18 06:17:14 AM UTC 24
Finished Sep 18 06:17:27 AM UTC 24
Peak memory 230520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634514968 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.634514968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2273209286
Short name T230
Test name
Test status
Simulation time 315169428 ps
CPU time 32.64 seconds
Started Sep 18 06:17:14 AM UTC 24
Finished Sep 18 06:17:48 AM UTC 24
Peak memory 230512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227320928
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.2273209286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3909706787
Short name T52
Test name
Test status
Simulation time 2410717442 ps
CPU time 64.84 seconds
Started Sep 18 06:17:17 AM UTC 24
Finished Sep 18 06:18:24 AM UTC 24
Peak memory 245260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3909706787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3909706787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1467521151
Short name T27
Test name
Test status
Simulation time 11890537528 ps
CPU time 180.2 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:17:35 AM UTC 24
Peak memory 259520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467521151 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.1467521151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2917320717
Short name T12
Test name
Test status
Simulation time 4500271259 ps
CPU time 20.24 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:53 AM UTC 24
Peak memory 230924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917320717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2917320717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1364663721
Short name T7
Test name
Test status
Simulation time 719744137 ps
CPU time 9.72 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:42 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364663721 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1364663721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3814269854
Short name T44
Test name
Test status
Simulation time 416780381 ps
CPU time 266.91 seconds
Started Sep 18 06:14:32 AM UTC 24
Finished Sep 18 06:19:03 AM UTC 24
Peak memory 261828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814269854 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3814269854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3902136063
Short name T17
Test name
Test status
Simulation time 270650099 ps
CPU time 11.13 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:44 AM UTC 24
Peak memory 227648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902136063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3902136063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.246572054
Short name T35
Test name
Test status
Simulation time 560990975 ps
CPU time 28.99 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:15:02 AM UTC 24
Peak memory 230744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246572054
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.246572054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.4160661240
Short name T224
Test name
Test status
Simulation time 2062895883 ps
CPU time 11.9 seconds
Started Sep 18 06:17:23 AM UTC 24
Finished Sep 18 06:17:36 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160661240 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4160661240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.915860603
Short name T269
Test name
Test status
Simulation time 2302150523 ps
CPU time 98.18 seconds
Started Sep 18 06:17:21 AM UTC 24
Finished Sep 18 06:19:01 AM UTC 24
Peak memory 246976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915860603 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.915860603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2206155924
Short name T232
Test name
Test status
Simulation time 2605167957 ps
CPU time 29.13 seconds
Started Sep 18 06:17:22 AM UTC 24
Finished Sep 18 06:17:53 AM UTC 24
Peak memory 230924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206155924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2206155924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3776468517
Short name T229
Test name
Test status
Simulation time 1072110715 ps
CPU time 24.52 seconds
Started Sep 18 06:17:21 AM UTC 24
Finished Sep 18 06:17:47 AM UTC 24
Peak memory 230788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776468517 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3776468517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.250721273
Short name T235
Test name
Test status
Simulation time 2109114763 ps
CPU time 37.27 seconds
Started Sep 18 06:17:19 AM UTC 24
Finished Sep 18 06:17:58 AM UTC 24
Peak memory 230988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250721273
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.250721273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.840498069
Short name T314
Test name
Test status
Simulation time 3649201352 ps
CPU time 153.83 seconds
Started Sep 18 06:17:22 AM UTC 24
Finished Sep 18 06:19:59 AM UTC 24
Peak memory 248368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=840498069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.rom_ctrl_stress_all_with_rand_reset.840498069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1770045891
Short name T226
Test name
Test status
Simulation time 718563705 ps
CPU time 12.19 seconds
Started Sep 18 06:17:37 AM UTC 24
Finished Sep 18 06:17:50 AM UTC 24
Peak memory 230132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770045891 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1770045891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1689738822
Short name T341
Test name
Test status
Simulation time 14800754718 ps
CPU time 215.15 seconds
Started Sep 18 06:17:31 AM UTC 24
Finished Sep 18 06:21:09 AM UTC 24
Peak memory 261944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689738822 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.1689738822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.72710956
Short name T234
Test name
Test status
Simulation time 661739535 ps
CPU time 20.94 seconds
Started Sep 18 06:17:33 AM UTC 24
Finished Sep 18 06:17:55 AM UTC 24
Peak memory 230784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72710956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_
TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ct
rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.72710956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3985768833
Short name T227
Test name
Test status
Simulation time 364098840 ps
CPU time 15.23 seconds
Started Sep 18 06:17:28 AM UTC 24
Finished Sep 18 06:17:44 AM UTC 24
Peak memory 230312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985768833 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3985768833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2297594267
Short name T231
Test name
Test status
Simulation time 266980617 ps
CPU time 22.85 seconds
Started Sep 18 06:17:26 AM UTC 24
Finished Sep 18 06:17:50 AM UTC 24
Peak memory 230652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229759426
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.2297594267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3901625705
Short name T263
Test name
Test status
Simulation time 1644312571 ps
CPU time 74.61 seconds
Started Sep 18 06:17:36 AM UTC 24
Finished Sep 18 06:18:52 AM UTC 24
Peak memory 234892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3901625705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3901625705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2623849013
Short name T238
Test name
Test status
Simulation time 4106955695 ps
CPU time 15.56 seconds
Started Sep 18 06:17:46 AM UTC 24
Finished Sep 18 06:18:03 AM UTC 24
Peak memory 229816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623849013 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2623849013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1961195676
Short name T351
Test name
Test status
Simulation time 27269370223 ps
CPU time 265.9 seconds
Started Sep 18 06:17:38 AM UTC 24
Finished Sep 18 06:22:08 AM UTC 24
Peak memory 259804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961195676 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.1961195676
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3152933598
Short name T242
Test name
Test status
Simulation time 347264511 ps
CPU time 27.98 seconds
Started Sep 18 06:17:41 AM UTC 24
Finished Sep 18 06:18:10 AM UTC 24
Peak memory 230192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152933598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3152933598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2021053541
Short name T233
Test name
Test status
Simulation time 174910010 ps
CPU time 15.1 seconds
Started Sep 18 06:17:38 AM UTC 24
Finished Sep 18 06:17:54 AM UTC 24
Peak memory 230328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021053541 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2021053541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3617970205
Short name T240
Test name
Test status
Simulation time 1278898425 ps
CPU time 28.21 seconds
Started Sep 18 06:17:37 AM UTC 24
Finished Sep 18 06:18:06 AM UTC 24
Peak memory 230720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361797020
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.3617970205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3193982543
Short name T262
Test name
Test status
Simulation time 5856890882 ps
CPU time 64.95 seconds
Started Sep 18 06:17:45 AM UTC 24
Finished Sep 18 06:18:52 AM UTC 24
Peak memory 235084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3193982543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3193982543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1518290741
Short name T239
Test name
Test status
Simulation time 368293469 ps
CPU time 11.75 seconds
Started Sep 18 06:17:51 AM UTC 24
Finished Sep 18 06:18:04 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518290741 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1518290741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1633167305
Short name T358
Test name
Test status
Simulation time 12126460261 ps
CPU time 331.99 seconds
Started Sep 18 06:17:48 AM UTC 24
Finished Sep 18 06:23:25 AM UTC 24
Peak memory 261988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633167305 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.1633167305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3932967316
Short name T244
Test name
Test status
Simulation time 498330810 ps
CPU time 25.5 seconds
Started Sep 18 06:17:49 AM UTC 24
Finished Sep 18 06:18:16 AM UTC 24
Peak memory 231052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932967316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3932967316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2891145209
Short name T237
Test name
Test status
Simulation time 467848701 ps
CPU time 12.43 seconds
Started Sep 18 06:17:47 AM UTC 24
Finished Sep 18 06:18:01 AM UTC 24
Peak memory 230648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891145209 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2891145209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.372094030
Short name T51
Test name
Test status
Simulation time 1155398368 ps
CPU time 35.47 seconds
Started Sep 18 06:17:46 AM UTC 24
Finished Sep 18 06:18:23 AM UTC 24
Peak memory 230748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372094030
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.372094030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2133517200
Short name T339
Test name
Test status
Simulation time 8968533573 ps
CPU time 184.94 seconds
Started Sep 18 06:17:51 AM UTC 24
Finished Sep 18 06:21:00 AM UTC 24
Peak memory 237716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2133517200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2133517200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1386267449
Short name T46
Test name
Test status
Simulation time 2054420078 ps
CPU time 13.91 seconds
Started Sep 18 06:18:02 AM UTC 24
Finished Sep 18 06:18:17 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386267449 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1386267449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2428909575
Short name T347
Test name
Test status
Simulation time 8471339901 ps
CPU time 228.51 seconds
Started Sep 18 06:17:56 AM UTC 24
Finished Sep 18 06:21:48 AM UTC 24
Peak memory 259840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428909575 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.2428909575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2499427506
Short name T248
Test name
Test status
Simulation time 1028463863 ps
CPU time 30.05 seconds
Started Sep 18 06:17:59 AM UTC 24
Finished Sep 18 06:18:30 AM UTC 24
Peak memory 230792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499427506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2499427506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3717204937
Short name T243
Test name
Test status
Simulation time 1015880407 ps
CPU time 17.4 seconds
Started Sep 18 06:17:55 AM UTC 24
Finished Sep 18 06:18:13 AM UTC 24
Peak memory 230304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717204937 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3717204937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.548867543
Short name T253
Test name
Test status
Simulation time 4265243091 ps
CPU time 46.18 seconds
Started Sep 18 06:17:54 AM UTC 24
Finished Sep 18 06:18:41 AM UTC 24
Peak memory 230856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548867543
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.548867543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.441471311
Short name T340
Test name
Test status
Simulation time 4517682819 ps
CPU time 181.67 seconds
Started Sep 18 06:17:59 AM UTC 24
Finished Sep 18 06:21:04 AM UTC 24
Peak memory 237076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=441471311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.rom_ctrl_stress_all_with_rand_reset.441471311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.189940327
Short name T247
Test name
Test status
Simulation time 287858899 ps
CPU time 12.54 seconds
Started Sep 18 06:18:14 AM UTC 24
Finished Sep 18 06:18:28 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189940327 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.189940327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1794461725
Short name T356
Test name
Test status
Simulation time 5399705663 ps
CPU time 298.37 seconds
Started Sep 18 06:18:07 AM UTC 24
Finished Sep 18 06:23:10 AM UTC 24
Peak memory 261916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794461725 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.1794461725
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3494971601
Short name T251
Test name
Test status
Simulation time 332261738 ps
CPU time 29.47 seconds
Started Sep 18 06:18:07 AM UTC 24
Finished Sep 18 06:18:38 AM UTC 24
Peak memory 230984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494971601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3494971601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2797014518
Short name T48
Test name
Test status
Simulation time 198120692 ps
CPU time 11.98 seconds
Started Sep 18 06:18:05 AM UTC 24
Finished Sep 18 06:18:18 AM UTC 24
Peak memory 230176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797014518 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2797014518
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2163276890
Short name T50
Test name
Test status
Simulation time 208014848 ps
CPU time 14.64 seconds
Started Sep 18 06:18:04 AM UTC 24
Finished Sep 18 06:18:20 AM UTC 24
Peak memory 227640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216327689
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.2163276890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.349166260
Short name T277
Test name
Test status
Simulation time 1247533043 ps
CPU time 56.91 seconds
Started Sep 18 06:18:11 AM UTC 24
Finished Sep 18 06:19:10 AM UTC 24
Peak memory 234896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=349166260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.rom_ctrl_stress_all_with_rand_reset.349166260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2897471877
Short name T246
Test name
Test status
Simulation time 174611423 ps
CPU time 7.86 seconds
Started Sep 18 06:18:18 AM UTC 24
Finished Sep 18 06:18:27 AM UTC 24
Peak memory 229880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897471877 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2897471877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.955327751
Short name T350
Test name
Test status
Simulation time 4711793160 ps
CPU time 227.03 seconds
Started Sep 18 06:18:17 AM UTC 24
Finished Sep 18 06:22:07 AM UTC 24
Peak memory 259788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955327751 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.955327751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.844482831
Short name T260
Test name
Test status
Simulation time 515364548 ps
CPU time 27.5 seconds
Started Sep 18 06:18:17 AM UTC 24
Finished Sep 18 06:18:45 AM UTC 24
Peak memory 230788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844482831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.844482831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2401583233
Short name T249
Test name
Test status
Simulation time 614972312 ps
CPU time 15.41 seconds
Started Sep 18 06:18:17 AM UTC 24
Finished Sep 18 06:18:33 AM UTC 24
Peak memory 230584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401583233 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2401583233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2678527091
Short name T257
Test name
Test status
Simulation time 201240905 ps
CPU time 26.41 seconds
Started Sep 18 06:18:15 AM UTC 24
Finished Sep 18 06:18:43 AM UTC 24
Peak memory 230720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267852709
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.2678527091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2882015453
Short name T342
Test name
Test status
Simulation time 3487379767 ps
CPU time 173.55 seconds
Started Sep 18 06:18:18 AM UTC 24
Finished Sep 18 06:21:14 AM UTC 24
Peak memory 247496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2882015453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2882015453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1251853181
Short name T252
Test name
Test status
Simulation time 250058174 ps
CPU time 13.86 seconds
Started Sep 18 06:18:24 AM UTC 24
Finished Sep 18 06:18:39 AM UTC 24
Peak memory 229964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251853181 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1251853181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2036713675
Short name T366
Test name
Test status
Simulation time 7655756844 ps
CPU time 455.93 seconds
Started Sep 18 06:18:19 AM UTC 24
Finished Sep 18 06:26:01 AM UTC 24
Peak memory 251704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036713675 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.2036713675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1652433984
Short name T254
Test name
Test status
Simulation time 664070474 ps
CPU time 19.27 seconds
Started Sep 18 06:18:21 AM UTC 24
Finished Sep 18 06:18:41 AM UTC 24
Peak memory 230988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652433984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1652433984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3339598156
Short name T250
Test name
Test status
Simulation time 1087751967 ps
CPU time 16.57 seconds
Started Sep 18 06:18:19 AM UTC 24
Finished Sep 18 06:18:37 AM UTC 24
Peak memory 230648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339598156 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3339598156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.1024844764
Short name T266
Test name
Test status
Simulation time 1471902084 ps
CPU time 40.17 seconds
Started Sep 18 06:18:18 AM UTC 24
Finished Sep 18 06:18:59 AM UTC 24
Peak memory 230736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102484476
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.1024844764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.4122316332
Short name T276
Test name
Test status
Simulation time 4617550937 ps
CPU time 44.04 seconds
Started Sep 18 06:18:24 AM UTC 24
Finished Sep 18 06:19:10 AM UTC 24
Peak memory 237064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4122316332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.4122316332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1524227064
Short name T258
Test name
Test status
Simulation time 250121281 ps
CPU time 12.55 seconds
Started Sep 18 06:18:30 AM UTC 24
Finished Sep 18 06:18:43 AM UTC 24
Peak memory 229880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524227064 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1524227064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.243355223
Short name T305
Test name
Test status
Simulation time 6431597371 ps
CPU time 274.36 seconds
Started Sep 18 06:18:25 AM UTC 24
Finished Sep 18 06:23:04 AM UTC 24
Peak memory 261812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243355223 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.243355223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.467840646
Short name T264
Test name
Test status
Simulation time 1387652303 ps
CPU time 26.56 seconds
Started Sep 18 06:18:27 AM UTC 24
Finished Sep 18 06:18:55 AM UTC 24
Peak memory 230256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467840646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.467840646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.4250197308
Short name T255
Test name
Test status
Simulation time 3677969666 ps
CPU time 16.22 seconds
Started Sep 18 06:18:24 AM UTC 24
Finished Sep 18 06:18:42 AM UTC 24
Peak memory 231108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250197308 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4250197308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.1436758862
Short name T256
Test name
Test status
Simulation time 1555848792 ps
CPU time 16.71 seconds
Started Sep 18 06:18:24 AM UTC 24
Finished Sep 18 06:18:42 AM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143675886
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.1436758862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3391787021
Short name T319
Test name
Test status
Simulation time 7556562934 ps
CPU time 91.16 seconds
Started Sep 18 06:18:28 AM UTC 24
Finished Sep 18 06:20:02 AM UTC 24
Peak memory 237068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3391787021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3391787021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2619309322
Short name T261
Test name
Test status
Simulation time 345855099 ps
CPU time 9.73 seconds
Started Sep 18 06:18:40 AM UTC 24
Finished Sep 18 06:18:51 AM UTC 24
Peak memory 230148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619309322 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2619309322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3202854490
Short name T365
Test name
Test status
Simulation time 29231936145 ps
CPU time 394.52 seconds
Started Sep 18 06:18:34 AM UTC 24
Finished Sep 18 06:25:13 AM UTC 24
Peak memory 251632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202854490 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.3202854490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1739802672
Short name T274
Test name
Test status
Simulation time 678370621 ps
CPU time 26.2 seconds
Started Sep 18 06:18:38 AM UTC 24
Finished Sep 18 06:19:05 AM UTC 24
Peak memory 230860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739802672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1739802672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3774091075
Short name T259
Test name
Test status
Simulation time 537016409 ps
CPU time 13.12 seconds
Started Sep 18 06:18:31 AM UTC 24
Finished Sep 18 06:18:45 AM UTC 24
Peak memory 230128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774091075 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3774091075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3994650967
Short name T284
Test name
Test status
Simulation time 794025544 ps
CPU time 47.59 seconds
Started Sep 18 06:18:30 AM UTC 24
Finished Sep 18 06:19:19 AM UTC 24
Peak memory 230736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399465096
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.3994650967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3879370385
Short name T334
Test name
Test status
Simulation time 11311960470 ps
CPU time 119.35 seconds
Started Sep 18 06:18:39 AM UTC 24
Finished Sep 18 06:20:40 AM UTC 24
Peak memory 237068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3879370385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3879370385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.4266692232
Short name T98
Test name
Test status
Simulation time 516399120 ps
CPU time 10.81 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:14:49 AM UTC 24
Peak memory 230004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266692232 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4266692232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1361962055
Short name T66
Test name
Test status
Simulation time 524209304 ps
CPU time 23.09 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:15:01 AM UTC 24
Peak memory 230796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361962055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1361962055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2287756810
Short name T30
Test name
Test status
Simulation time 521381903 ps
CPU time 224.34 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:18:24 AM UTC 24
Peak memory 259744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287756810 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2287756810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1896706156
Short name T23
Test name
Test status
Simulation time 263386911 ps
CPU time 10.98 seconds
Started Sep 18 06:14:32 AM UTC 24
Finished Sep 18 06:14:44 AM UTC 24
Peak memory 227648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896706156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1896706156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1277560167
Short name T218
Test name
Test status
Simulation time 3731001477 ps
CPU time 150.66 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:17:10 AM UTC 24
Peak memory 248364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1277560167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1277560167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3064756037
Short name T265
Test name
Test status
Simulation time 496386529 ps
CPU time 11.53 seconds
Started Sep 18 06:18:44 AM UTC 24
Finished Sep 18 06:18:57 AM UTC 24
Peak memory 229552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064756037 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3064756037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4180239169
Short name T352
Test name
Test status
Simulation time 9851115794 ps
CPU time 214.77 seconds
Started Sep 18 06:18:42 AM UTC 24
Finished Sep 18 06:22:20 AM UTC 24
Peak memory 248584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180239169 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.4180239169
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.428107411
Short name T278
Test name
Test status
Simulation time 332515441 ps
CPU time 29.01 seconds
Started Sep 18 06:18:42 AM UTC 24
Finished Sep 18 06:19:12 AM UTC 24
Peak memory 230788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428107411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.428107411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3584826908
Short name T272
Test name
Test status
Simulation time 7600107206 ps
CPU time 18.33 seconds
Started Sep 18 06:18:42 AM UTC 24
Finished Sep 18 06:19:02 AM UTC 24
Peak memory 230852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584826908 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3584826908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2701132507
Short name T275
Test name
Test status
Simulation time 1561786653 ps
CPU time 26.8 seconds
Started Sep 18 06:18:40 AM UTC 24
Finished Sep 18 06:19:08 AM UTC 24
Peak memory 229812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270113250
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.2701132507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3128929824
Short name T299
Test name
Test status
Simulation time 10280393801 ps
CPU time 56.19 seconds
Started Sep 18 06:18:43 AM UTC 24
Finished Sep 18 06:19:41 AM UTC 24
Peak memory 247304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3128929824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3128929824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.4183945131
Short name T273
Test name
Test status
Simulation time 688211476 ps
CPU time 10.8 seconds
Started Sep 18 06:18:53 AM UTC 24
Finished Sep 18 06:19:05 AM UTC 24
Peak memory 229676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183945131 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4183945131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1633548036
Short name T362
Test name
Test status
Simulation time 6275479835 ps
CPU time 335.53 seconds
Started Sep 18 06:18:46 AM UTC 24
Finished Sep 18 06:24:26 AM UTC 24
Peak memory 230360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633548036 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.1633548036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.947870512
Short name T291
Test name
Test status
Simulation time 17854854328 ps
CPU time 44.44 seconds
Started Sep 18 06:18:47 AM UTC 24
Finished Sep 18 06:19:32 AM UTC 24
Peak memory 231048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947870512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.947870512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2778183675
Short name T271
Test name
Test status
Simulation time 3629864188 ps
CPU time 14.98 seconds
Started Sep 18 06:18:45 AM UTC 24
Finished Sep 18 06:19:02 AM UTC 24
Peak memory 230760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778183675 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2778183675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3048785375
Short name T293
Test name
Test status
Simulation time 1064543112 ps
CPU time 48.96 seconds
Started Sep 18 06:18:44 AM UTC 24
Finished Sep 18 06:19:35 AM UTC 24
Peak memory 230840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304878537
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.3048785375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1938424926
Short name T310
Test name
Test status
Simulation time 1517180458 ps
CPU time 61.48 seconds
Started Sep 18 06:18:52 AM UTC 24
Finished Sep 18 06:19:55 AM UTC 24
Peak memory 234892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1938424926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1938424926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.339980821
Short name T280
Test name
Test status
Simulation time 260096842 ps
CPU time 11.01 seconds
Started Sep 18 06:19:02 AM UTC 24
Finished Sep 18 06:19:14 AM UTC 24
Peak memory 229600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339980821 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.339980821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.623130157
Short name T367
Test name
Test status
Simulation time 22959884492 ps
CPU time 420.8 seconds
Started Sep 18 06:18:58 AM UTC 24
Finished Sep 18 06:26:04 AM UTC 24
Peak memory 259032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623130157 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.623130157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.4149289020
Short name T279
Test name
Test status
Simulation time 2806741325 ps
CPU time 17.06 seconds
Started Sep 18 06:18:56 AM UTC 24
Finished Sep 18 06:19:14 AM UTC 24
Peak memory 230512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149289020 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4149289020
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.962036699
Short name T285
Test name
Test status
Simulation time 2200794107 ps
CPU time 27.49 seconds
Started Sep 18 06:18:53 AM UTC 24
Finished Sep 18 06:19:21 AM UTC 24
Peak memory 230004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962036699
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.962036699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2160292856
Short name T309
Test name
Test status
Simulation time 4659157351 ps
CPU time 49.78 seconds
Started Sep 18 06:19:01 AM UTC 24
Finished Sep 18 06:19:52 AM UTC 24
Peak memory 248364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2160292856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2160292856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2227198922
Short name T282
Test name
Test status
Simulation time 346236811 ps
CPU time 10.91 seconds
Started Sep 18 06:19:05 AM UTC 24
Finished Sep 18 06:19:17 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227198922 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2227198922
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2020377394
Short name T361
Test name
Test status
Simulation time 20781652687 ps
CPU time 309.54 seconds
Started Sep 18 06:19:02 AM UTC 24
Finished Sep 18 06:24:16 AM UTC 24
Peak memory 246676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020377394 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.2020377394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3687067243
Short name T295
Test name
Test status
Simulation time 39350628522 ps
CPU time 32.61 seconds
Started Sep 18 06:19:02 AM UTC 24
Finished Sep 18 06:19:36 AM UTC 24
Peak memory 230924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687067243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3687067243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2716133985
Short name T281
Test name
Test status
Simulation time 1276185785 ps
CPU time 13.18 seconds
Started Sep 18 06:19:02 AM UTC 24
Finished Sep 18 06:19:16 AM UTC 24
Peak memory 230164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716133985 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2716133985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1026358834
Short name T292
Test name
Test status
Simulation time 591869268 ps
CPU time 29.57 seconds
Started Sep 18 06:19:02 AM UTC 24
Finished Sep 18 06:19:33 AM UTC 24
Peak memory 230724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102635883
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.1026358834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3913216963
Short name T338
Test name
Test status
Simulation time 5484647695 ps
CPU time 105.85 seconds
Started Sep 18 06:19:03 AM UTC 24
Finished Sep 18 06:20:51 AM UTC 24
Peak memory 237068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3913216963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3913216963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1610987368
Short name T289
Test name
Test status
Simulation time 6589043774 ps
CPU time 13.1 seconds
Started Sep 18 06:19:15 AM UTC 24
Finished Sep 18 06:19:29 AM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610987368 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1610987368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3625558780
Short name T357
Test name
Test status
Simulation time 16023071438 ps
CPU time 239.62 seconds
Started Sep 18 06:19:11 AM UTC 24
Finished Sep 18 06:23:14 AM UTC 24
Peak memory 263424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625558780 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.3625558780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2571896670
Short name T298
Test name
Test status
Simulation time 1380538964 ps
CPU time 28.63 seconds
Started Sep 18 06:19:11 AM UTC 24
Finished Sep 18 06:19:41 AM UTC 24
Peak memory 230924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571896670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2571896670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.4188112813
Short name T287
Test name
Test status
Simulation time 257474951 ps
CPU time 16.86 seconds
Started Sep 18 06:19:09 AM UTC 24
Finished Sep 18 06:19:27 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188112813 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4188112813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3709810466
Short name T308
Test name
Test status
Simulation time 288708477 ps
CPU time 42.7 seconds
Started Sep 18 06:19:07 AM UTC 24
Finished Sep 18 06:19:51 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370981046
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.3709810466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.4155031045
Short name T317
Test name
Test status
Simulation time 10389614045 ps
CPU time 45.97 seconds
Started Sep 18 06:19:13 AM UTC 24
Finished Sep 18 06:20:00 AM UTC 24
Peak memory 245516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4155031045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.rom_ctrl_stress_all_with_rand_reset.4155031045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.2982581468
Short name T290
Test name
Test status
Simulation time 170827595 ps
CPU time 7.62 seconds
Started Sep 18 06:19:22 AM UTC 24
Finished Sep 18 06:19:31 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982581468 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2982581468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3760744082
Short name T360
Test name
Test status
Simulation time 6569805833 ps
CPU time 252.66 seconds
Started Sep 18 06:19:18 AM UTC 24
Finished Sep 18 06:23:34 AM UTC 24
Peak memory 261812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760744082 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.3760744082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.365989101
Short name T301
Test name
Test status
Simulation time 1073129698 ps
CPU time 23.05 seconds
Started Sep 18 06:19:19 AM UTC 24
Finished Sep 18 06:19:43 AM UTC 24
Peak memory 230792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365989101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.365989101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.519344695
Short name T296
Test name
Test status
Simulation time 4267051181 ps
CPU time 18.22 seconds
Started Sep 18 06:19:17 AM UTC 24
Finished Sep 18 06:19:36 AM UTC 24
Peak memory 230496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519344695 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.519344695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2519012659
Short name T304
Test name
Test status
Simulation time 535234113 ps
CPU time 31.84 seconds
Started Sep 18 06:19:15 AM UTC 24
Finished Sep 18 06:19:48 AM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251901265
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.2519012659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.531115321
Short name T343
Test name
Test status
Simulation time 11843446704 ps
CPU time 130.08 seconds
Started Sep 18 06:19:19 AM UTC 24
Finished Sep 18 06:21:32 AM UTC 24
Peak memory 237524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=531115321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_stress_all_with_rand_reset.531115321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4021655619
Short name T302
Test name
Test status
Simulation time 1034810673 ps
CPU time 11.82 seconds
Started Sep 18 06:19:32 AM UTC 24
Finished Sep 18 06:19:45 AM UTC 24
Peak memory 229988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021655619 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4021655619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.465665475
Short name T359
Test name
Test status
Simulation time 7471292519 ps
CPU time 235.89 seconds
Started Sep 18 06:19:27 AM UTC 24
Finished Sep 18 06:23:27 AM UTC 24
Peak memory 230060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465665475 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.465665475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2292539856
Short name T312
Test name
Test status
Simulation time 9904062777 ps
CPU time 27.33 seconds
Started Sep 18 06:19:29 AM UTC 24
Finished Sep 18 06:19:57 AM UTC 24
Peak memory 231116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292539856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2292539856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1236851351
Short name T300
Test name
Test status
Simulation time 696440846 ps
CPU time 15.6 seconds
Started Sep 18 06:19:24 AM UTC 24
Finished Sep 18 06:19:41 AM UTC 24
Peak memory 230584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236851351 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1236851351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3570193585
Short name T306
Test name
Test status
Simulation time 343046601 ps
CPU time 26.54 seconds
Started Sep 18 06:19:22 AM UTC 24
Finished Sep 18 06:19:50 AM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357019358
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.3570193585
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.825891744
Short name T364
Test name
Test status
Simulation time 4344193731 ps
CPU time 300.19 seconds
Started Sep 18 06:19:30 AM UTC 24
Finished Sep 18 06:24:34 AM UTC 24
Peak memory 248360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=825891744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.rom_ctrl_stress_all_with_rand_reset.825891744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1582176822
Short name T307
Test name
Test status
Simulation time 292761185 ps
CPU time 12.1 seconds
Started Sep 18 06:19:37 AM UTC 24
Finished Sep 18 06:19:50 AM UTC 24
Peak memory 229924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582176822 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1582176822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2923776536
Short name T348
Test name
Test status
Simulation time 2064995315 ps
CPU time 129.45 seconds
Started Sep 18 06:19:36 AM UTC 24
Finished Sep 18 06:21:48 AM UTC 24
Peak memory 260788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923776536 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.2923776536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.746376230
Short name T316
Test name
Test status
Simulation time 501632076 ps
CPU time 22.21 seconds
Started Sep 18 06:19:36 AM UTC 24
Finished Sep 18 06:19:59 AM UTC 24
Peak memory 230380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746376230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.746376230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.698010314
Short name T303
Test name
Test status
Simulation time 346367581 ps
CPU time 12.71 seconds
Started Sep 18 06:19:34 AM UTC 24
Finished Sep 18 06:19:48 AM UTC 24
Peak memory 230452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698010314 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.698010314
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.626847695
Short name T323
Test name
Test status
Simulation time 9183232025 ps
CPU time 34.84 seconds
Started Sep 18 06:19:34 AM UTC 24
Finished Sep 18 06:20:10 AM UTC 24
Peak memory 230924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626847695
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.626847695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4268663455
Short name T333
Test name
Test status
Simulation time 5457319948 ps
CPU time 61.25 seconds
Started Sep 18 06:19:37 AM UTC 24
Finished Sep 18 06:20:40 AM UTC 24
Peak memory 237068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4268663455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4268663455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3094015246
Short name T313
Test name
Test status
Simulation time 167467640 ps
CPU time 10.81 seconds
Started Sep 18 06:19:45 AM UTC 24
Finished Sep 18 06:19:57 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094015246 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3094015246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.854040161
Short name T363
Test name
Test status
Simulation time 19201970292 ps
CPU time 282.84 seconds
Started Sep 18 06:19:42 AM UTC 24
Finished Sep 18 06:24:29 AM UTC 24
Peak memory 261684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854040161 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.854040161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.797270189
Short name T327
Test name
Test status
Simulation time 2069381294 ps
CPU time 31.65 seconds
Started Sep 18 06:19:42 AM UTC 24
Finished Sep 18 06:20:15 AM UTC 24
Peak memory 230484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797270189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.797270189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1822104254
Short name T311
Test name
Test status
Simulation time 701047661 ps
CPU time 13.01 seconds
Started Sep 18 06:19:41 AM UTC 24
Finished Sep 18 06:19:55 AM UTC 24
Peak memory 230456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822104254 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1822104254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1716850028
Short name T328
Test name
Test status
Simulation time 2151569175 ps
CPU time 33.06 seconds
Started Sep 18 06:19:41 AM UTC 24
Finished Sep 18 06:20:16 AM UTC 24
Peak memory 231040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171685002
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.1716850028
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.103882695
Short name T332
Test name
Test status
Simulation time 10678880856 ps
CPU time 52.75 seconds
Started Sep 18 06:19:44 AM UTC 24
Finished Sep 18 06:20:39 AM UTC 24
Peak memory 245332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=103882695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.rom_ctrl_stress_all_with_rand_reset.103882695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.382620476
Short name T320
Test name
Test status
Simulation time 168405163 ps
CPU time 10.82 seconds
Started Sep 18 06:19:51 AM UTC 24
Finished Sep 18 06:20:03 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382620476 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.382620476
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2153585583
Short name T354
Test name
Test status
Simulation time 13623191768 ps
CPU time 184.68 seconds
Started Sep 18 06:19:49 AM UTC 24
Finished Sep 18 06:22:56 AM UTC 24
Peak memory 259192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153585583 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.2153585583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3579520417
Short name T325
Test name
Test status
Simulation time 953013321 ps
CPU time 24.18 seconds
Started Sep 18 06:19:49 AM UTC 24
Finished Sep 18 06:20:14 AM UTC 24
Peak memory 230284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579520417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3579520417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1658866923
Short name T318
Test name
Test status
Simulation time 1061040076 ps
CPU time 10.92 seconds
Started Sep 18 06:19:49 AM UTC 24
Finished Sep 18 06:20:00 AM UTC 24
Peak memory 230392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658866923 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1658866923
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.929835346
Short name T324
Test name
Test status
Simulation time 540257604 ps
CPU time 21 seconds
Started Sep 18 06:19:48 AM UTC 24
Finished Sep 18 06:20:11 AM UTC 24
Peak memory 230728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929835346
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.929835346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2496412867
Short name T337
Test name
Test status
Simulation time 5777252426 ps
CPU time 57.91 seconds
Started Sep 18 06:19:51 AM UTC 24
Finished Sep 18 06:20:50 AM UTC 24
Peak memory 245260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2496412867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2496412867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.4274818879
Short name T25
Test name
Test status
Simulation time 615108399 ps
CPU time 8.38 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:14:47 AM UTC 24
Peak memory 230220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274818879 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4274818879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.375914450
Short name T345
Test name
Test status
Simulation time 70026004717 ps
CPU time 416.85 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:21:39 AM UTC 24
Peak memory 250616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375914450 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.375914450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1374825924
Short name T18
Test name
Test status
Simulation time 703552852 ps
CPU time 12.14 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:14:50 AM UTC 24
Peak memory 230640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374825924 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1374825924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.869138662
Short name T94
Test name
Test status
Simulation time 2482137540 ps
CPU time 14.88 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:14:53 AM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869138662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64k
B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.869138662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2814322701
Short name T36
Test name
Test status
Simulation time 1829320801 ps
CPU time 29.06 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:15:07 AM UTC 24
Peak memory 230936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281432270
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.2814322701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2193953622
Short name T268
Test name
Test status
Simulation time 20198795695 ps
CPU time 260.1 seconds
Started Sep 18 06:14:37 AM UTC 24
Finished Sep 18 06:19:01 AM UTC 24
Peak memory 243220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2193953622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2193953622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2334604754
Short name T70
Test name
Test status
Simulation time 518534718 ps
CPU time 11.78 seconds
Started Sep 18 06:14:43 AM UTC 24
Finished Sep 18 06:14:55 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334604754 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2334604754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.722675596
Short name T39
Test name
Test status
Simulation time 1975066737 ps
CPU time 23.92 seconds
Started Sep 18 06:14:42 AM UTC 24
Finished Sep 18 06:15:08 AM UTC 24
Peak memory 230764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722675596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c
trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.722675596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1496373305
Short name T69
Test name
Test status
Simulation time 1063300375 ps
CPU time 11.71 seconds
Started Sep 18 06:14:42 AM UTC 24
Finished Sep 18 06:14:55 AM UTC 24
Peak memory 230368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496373305 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1496373305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3069202882
Short name T33
Test name
Test status
Simulation time 184087997 ps
CPU time 13.25 seconds
Started Sep 18 06:14:41 AM UTC 24
Finished Sep 18 06:14:55 AM UTC 24
Peak memory 227712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069202882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3069202882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1541372204
Short name T88
Test name
Test status
Simulation time 1064268777 ps
CPU time 21.05 seconds
Started Sep 18 06:14:41 AM UTC 24
Finished Sep 18 06:15:03 AM UTC 24
Peak memory 230664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154137220
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.1541372204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2092081055
Short name T83
Test name
Test status
Simulation time 7462552799 ps
CPU time 109.49 seconds
Started Sep 18 06:14:42 AM UTC 24
Finished Sep 18 06:16:34 AM UTC 24
Peak memory 237268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2092081055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2092081055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.610395172
Short name T72
Test name
Test status
Simulation time 972083787 ps
CPU time 11.41 seconds
Started Sep 18 06:14:46 AM UTC 24
Finished Sep 18 06:14:59 AM UTC 24
Peak memory 229884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610395172 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.610395172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3546552280
Short name T54
Test name
Test status
Simulation time 3049559770 ps
CPU time 179.67 seconds
Started Sep 18 06:14:45 AM UTC 24
Finished Sep 18 06:17:48 AM UTC 24
Peak memory 259456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546552280 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.3546552280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1159025532
Short name T40
Test name
Test status
Simulation time 1741768041 ps
CPU time 21.28 seconds
Started Sep 18 06:14:45 AM UTC 24
Finished Sep 18 06:15:08 AM UTC 24
Peak memory 230796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159025532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1159025532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.946253594
Short name T71
Test name
Test status
Simulation time 954849008 ps
CPU time 11.77 seconds
Started Sep 18 06:14:45 AM UTC 24
Finished Sep 18 06:14:58 AM UTC 24
Peak memory 229964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946253594 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.946253594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.106957933
Short name T108
Test name
Test status
Simulation time 265157463 ps
CPU time 14.78 seconds
Started Sep 18 06:14:44 AM UTC 24
Finished Sep 18 06:15:00 AM UTC 24
Peak memory 230800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106957933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64k
B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.106957933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.337225817
Short name T42
Test name
Test status
Simulation time 546433833 ps
CPU time 21.6 seconds
Started Sep 18 06:14:45 AM UTC 24
Finished Sep 18 06:15:08 AM UTC 24
Peak memory 229936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337225817
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.337225817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4013297513
Short name T64
Test name
Test status
Simulation time 2991007492 ps
CPU time 160.46 seconds
Started Sep 18 06:14:46 AM UTC 24
Finished Sep 18 06:17:30 AM UTC 24
Peak memory 237076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4013297513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.4013297513
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3543038570
Short name T85
Test name
Test status
Simulation time 167468379 ps
CPU time 9.31 seconds
Started Sep 18 06:14:50 AM UTC 24
Finished Sep 18 06:15:01 AM UTC 24
Peak memory 229640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543038570 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3543038570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3111337227
Short name T288
Test name
Test status
Simulation time 87738567874 ps
CPU time 273.11 seconds
Started Sep 18 06:14:50 AM UTC 24
Finished Sep 18 06:19:28 AM UTC 24
Peak memory 258884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111337227 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.3111337227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2043591622
Short name T67
Test name
Test status
Simulation time 332726896 ps
CPU time 20.08 seconds
Started Sep 18 06:14:50 AM UTC 24
Finished Sep 18 06:15:12 AM UTC 24
Peak memory 230956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043591622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_
ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2043591622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3529730557
Short name T86
Test name
Test status
Simulation time 272212354 ps
CPU time 10.24 seconds
Started Sep 18 06:14:50 AM UTC 24
Finished Sep 18 06:15:02 AM UTC 24
Peak memory 230312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529730557 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3529730557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1111431521
Short name T87
Test name
Test status
Simulation time 264049692 ps
CPU time 15.15 seconds
Started Sep 18 06:14:46 AM UTC 24
Finished Sep 18 06:15:03 AM UTC 24
Peak memory 227840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111431521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1111431521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3577240629
Short name T109
Test name
Test status
Simulation time 1194834954 ps
CPU time 18.52 seconds
Started Sep 18 06:14:50 AM UTC 24
Finished Sep 18 06:15:10 AM UTC 24
Peak memory 227556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357724062
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.3577240629
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2143857220
Short name T90
Test name
Test status
Simulation time 167406913 ps
CPU time 9.13 seconds
Started Sep 18 06:14:56 AM UTC 24
Finished Sep 18 06:15:06 AM UTC 24
Peak memory 229948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143857220 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2143857220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3581164893
Short name T28
Test name
Test status
Simulation time 3072209139 ps
CPU time 158.17 seconds
Started Sep 18 06:14:55 AM UTC 24
Finished Sep 18 06:17:36 AM UTC 24
Peak memory 230204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581164893 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.3581164893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.1487757565
Short name T89
Test name
Test status
Simulation time 182245803 ps
CPU time 10.93 seconds
Started Sep 18 06:14:52 AM UTC 24
Finished Sep 18 06:15:04 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487757565 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1487757565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3045962610
Short name T158
Test name
Test status
Simulation time 1019583357 ps
CPU time 14.21 seconds
Started Sep 18 06:14:52 AM UTC 24
Finished Sep 18 06:15:08 AM UTC 24
Peak memory 227644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045962610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3045962610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1782904095
Short name T157
Test name
Test status
Simulation time 2160317481 ps
CPU time 25.63 seconds
Started Sep 18 06:14:52 AM UTC 24
Finished Sep 18 06:15:19 AM UTC 24
Peak memory 230876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178290409
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.1782904095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.866925013
Short name T84
Test name
Test status
Simulation time 3335193231 ps
CPU time 120.2 seconds
Started Sep 18 06:14:55 AM UTC 24
Finished Sep 18 06:16:58 AM UTC 24
Peak memory 235024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=866925013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.rom_ctrl_stress_all_with_rand_reset.866925013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest
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