| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.46 | 96.77 | 92.28 | 97.68 | 100.00 | 98.55 | 97.91 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 61.57 | 61.57 | 92.31 | 92.31 | 67.28 | 67.28 | 36.68 | 36.68 | 40.00 | 40.00 | 90.22 | 90.22 | 93.73 | 93.73 | 10.77 | 10.77 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3135560673 |
| 76.86 | 15.29 | 92.68 | 0.37 | 74.30 | 7.02 | 59.85 | 23.16 | 40.00 | 0.00 | 91.67 | 1.45 | 95.22 | 1.49 | 84.31 | 73.54 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.899811653 |
| 83.21 | 6.35 | 93.30 | 0.62 | 79.49 | 5.20 | 73.36 | 13.52 | 60.00 | 20.00 | 94.93 | 3.26 | 95.67 | 0.45 | 85.71 | 1.41 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.4233066634 |
| 87.47 | 4.26 | 93.30 | 0.00 | 81.74 | 2.25 | 73.54 | 0.17 | 86.67 | 26.67 | 95.29 | 0.36 | 95.82 | 0.15 | 85.95 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.658649518 |
| 89.53 | 2.06 | 96.40 | 3.10 | 87.22 | 5.48 | 76.11 | 2.57 | 86.67 | 0.00 | 96.38 | 1.09 | 96.12 | 0.30 | 87.82 | 1.87 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.3880695292 |
| 91.49 | 1.96 | 96.40 | 0.00 | 87.64 | 0.42 | 82.36 | 6.25 | 93.33 | 6.67 | 96.74 | 0.36 | 96.12 | 0.00 | 87.82 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1172686697 |
| 92.66 | 1.18 | 96.53 | 0.12 | 87.78 | 0.14 | 82.36 | 0.00 | 100.00 | 6.67 | 97.10 | 0.36 | 96.12 | 0.00 | 88.76 | 0.94 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1835934829 |
| 93.75 | 1.09 | 96.53 | 0.00 | 89.75 | 1.97 | 87.56 | 5.20 | 100.00 | 0.00 | 97.10 | 0.00 | 96.12 | 0.00 | 89.23 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3662709440 |
| 94.81 | 1.06 | 96.77 | 0.25 | 90.45 | 0.70 | 87.56 | 0.00 | 100.00 | 0.00 | 98.19 | 1.09 | 96.12 | 0.00 | 94.61 | 5.39 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.864884477 |
| 95.48 | 0.66 | 96.77 | 0.00 | 90.45 | 0.00 | 91.50 | 3.95 | 100.00 | 0.00 | 98.19 | 0.00 | 96.12 | 0.00 | 95.32 | 0.70 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1843740250 |
| 95.77 | 0.29 | 96.77 | 0.00 | 90.45 | 0.00 | 93.53 | 2.02 | 100.00 | 0.00 | 98.19 | 0.00 | 96.12 | 0.00 | 95.32 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3404435565 |
| 95.99 | 0.23 | 96.77 | 0.00 | 91.01 | 0.56 | 93.78 | 0.25 | 100.00 | 0.00 | 98.19 | 0.00 | 96.42 | 0.30 | 95.78 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.3757176657 |
| 96.19 | 0.20 | 96.77 | 0.00 | 91.01 | 0.00 | 93.78 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 96.42 | 0.00 | 97.19 | 1.41 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1656334751 |
| 96.39 | 0.19 | 96.77 | 0.00 | 91.01 | 0.00 | 95.13 | 1.35 | 100.00 | 0.00 | 98.19 | 0.00 | 96.42 | 0.00 | 97.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1570862936 |
| 96.58 | 0.19 | 96.77 | 0.00 | 91.15 | 0.14 | 95.13 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.61 | 1.19 | 97.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2664326331 |
| 96.73 | 0.15 | 96.77 | 0.00 | 91.29 | 0.14 | 95.45 | 0.32 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.15 | 97.66 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1438104593 |
| 96.85 | 0.12 | 96.77 | 0.00 | 91.43 | 0.14 | 95.90 | 0.45 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 97.89 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2298821018 |
| 96.96 | 0.11 | 96.77 | 0.00 | 91.43 | 0.00 | 96.45 | 0.55 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 98.13 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1541809313 |
| 97.06 | 0.10 | 96.77 | 0.00 | 91.43 | 0.00 | 96.45 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 98.83 | 0.70 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2752568251 |
| 97.14 | 0.08 | 96.77 | 0.00 | 91.99 | 0.56 | 96.45 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2299910007 |
| 97.21 | 0.07 | 96.77 | 0.00 | 92.13 | 0.14 | 96.45 | 0.00 | 100.00 | 0.00 | 98.55 | 0.36 | 97.76 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1904851643 |
| 97.28 | 0.06 | 96.77 | 0.00 | 92.13 | 0.00 | 96.88 | 0.42 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1630731006 |
| 97.31 | 0.04 | 96.77 | 0.00 | 92.13 | 0.00 | 97.13 | 0.25 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.00 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.663804838 |
| 97.34 | 0.03 | 96.77 | 0.00 | 92.13 | 0.00 | 97.13 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.424611076 |
| 97.38 | 0.03 | 96.77 | 0.00 | 92.13 | 0.00 | 97.35 | 0.22 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.307359639 |
| 97.40 | 0.02 | 96.77 | 0.00 | 92.13 | 0.00 | 97.35 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3024485131 |
| 97.42 | 0.02 | 96.77 | 0.00 | 92.28 | 0.14 | 97.35 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2541578884 |
| 97.44 | 0.02 | 96.77 | 0.00 | 92.28 | 0.00 | 97.48 | 0.12 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.637818368 |
| 97.45 | 0.01 | 96.77 | 0.00 | 92.28 | 0.00 | 97.55 | 0.07 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1244585587 |
| 97.46 | 0.01 | 96.77 | 0.00 | 92.28 | 0.00 | 97.63 | 0.07 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2426507645 |
| 97.46 | 0.01 | 96.77 | 0.00 | 92.28 | 0.00 | 97.68 | 0.05 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.4169469424 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2538492661 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3643153398 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4105776583 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2095791267 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4090218995 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1060052073 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.561032996 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3409079986 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1338239345 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.313857802 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.728974070 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4064581815 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.611990419 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.699359683 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3794354861 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2588317228 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2655185217 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3076359908 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3361012018 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3669353763 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2545354892 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1819524309 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3147116419 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1278893880 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2087846824 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.146133555 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2415901415 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3163248447 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3179896957 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.169404398 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3554532015 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2765996650 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2972171737 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.74012522 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.715052080 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1684743759 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1566414969 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1667984902 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2428536478 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1863580570 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3766102285 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1882083300 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.937309216 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.612662064 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1921396708 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.631574882 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.774634896 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.189344112 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3500663157 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.457116114 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3551942211 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3584080114 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2534166091 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.735401705 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3559048906 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4006466953 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4023224155 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3424805761 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.17408383 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1767712748 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3084284642 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2660458235 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4101766825 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2690960236 |
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| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1739802672 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3774091075 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3994650967 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3879370385 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.4266692232 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1361962055 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2287756810 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1896706156 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1277560167 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3064756037 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4180239169 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.428107411 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3584826908 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2701132507 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3128929824 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.4183945131 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1633548036 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.947870512 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2778183675 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3048785375 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1938424926 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.339980821 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.623130157 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.4149289020 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.962036699 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2160292856 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2227198922 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2020377394 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3687067243 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2716133985 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1026358834 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3913216963 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1610987368 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3625558780 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2571896670 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.4188112813 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3709810466 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.4155031045 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.2982581468 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3760744082 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.365989101 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.519344695 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2519012659 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.531115321 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4021655619 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.465665475 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2292539856 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1236851351 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3570193585 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.825891744 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1582176822 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2923776536 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.746376230 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.698010314 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.626847695 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4268663455 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3094015246 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.854040161 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.797270189 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1822104254 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1716850028 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.103882695 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.382620476 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2153585583 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3579520417 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1658866923 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.929835346 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2496412867 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.4274818879 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.375914450 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1374825924 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.869138662 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2814322701 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2193953622 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2334604754 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.722675596 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1496373305 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3069202882 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1541372204 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2092081055 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.610395172 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3546552280 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1159025532 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.946253594 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.106957933 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.337225817 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4013297513 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3543038570 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3111337227 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2043591622 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3529730557 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1111431521 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3577240629 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2143857220 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3581164893 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.1487757565 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3045962610 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1782904095 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.866925013 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2475843389 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:40 AM UTC 24 | 972178514 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2945540772 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:41 AM UTC 24 | 660561973 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1244585587 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:41 AM UTC 24 | 176091434 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.3880695292 | Sep 18 06:14:32 AM UTC 24 | Sep 18 06:14:42 AM UTC 24 | 1120608130 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3135560673 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:42 AM UTC 24 | 187555738 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3457257277 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:42 AM UTC 24 | 716811618 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1364663721 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:42 AM UTC 24 | 719744137 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3739512982 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:43 AM UTC 24 | 1112840764 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.307359639 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:43 AM UTC 24 | 182001236 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2736555205 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:43 AM UTC 24 | 267183766 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3902136063 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:44 AM UTC 24 | 270650099 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1896706156 | Sep 18 06:14:32 AM UTC 24 | Sep 18 06:14:44 AM UTC 24 | 263386911 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3404552828 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:45 AM UTC 24 | 265513130 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.4274818879 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:14:47 AM UTC 24 | 615108399 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.2086172742 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:47 AM UTC 24 | 1037681042 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.4266692232 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:14:49 AM UTC 24 | 516399120 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1374825924 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:14:50 AM UTC 24 | 703552852 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1438104593 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:14:51 AM UTC 24 | 181066732 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.869138662 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:14:53 AM UTC 24 | 2482137540 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3404435565 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:53 AM UTC 24 | 523281681 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2917320717 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:53 AM UTC 24 | 4500271259 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3069202882 | Sep 18 06:14:41 AM UTC 24 | Sep 18 06:14:55 AM UTC 24 | 184087997 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1496373305 | Sep 18 06:14:42 AM UTC 24 | Sep 18 06:14:55 AM UTC 24 | 1063300375 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2334604754 | Sep 18 06:14:43 AM UTC 24 | Sep 18 06:14:55 AM UTC 24 | 518534718 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.797266921 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:56 AM UTC 24 | 2035202116 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1172686697 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:57 AM UTC 24 | 518903173 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.946253594 | Sep 18 06:14:45 AM UTC 24 | Sep 18 06:14:58 AM UTC 24 | 954849008 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.4233066634 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:14:58 AM UTC 24 | 332650966 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.610395172 | Sep 18 06:14:46 AM UTC 24 | Sep 18 06:14:59 AM UTC 24 | 972083787 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3662709440 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:14:59 AM UTC 24 | 2268161612 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.106957933 | Sep 18 06:14:44 AM UTC 24 | Sep 18 06:15:00 AM UTC 24 | 265157463 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.548883710 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:15:00 AM UTC 24 | 3756687767 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3543038570 | Sep 18 06:14:50 AM UTC 24 | Sep 18 06:15:01 AM UTC 24 | 167468379 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1361962055 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:15:01 AM UTC 24 | 524209304 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3529730557 | Sep 18 06:14:50 AM UTC 24 | Sep 18 06:15:02 AM UTC 24 | 272212354 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.246572054 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:15:02 AM UTC 24 | 560990975 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1111431521 | Sep 18 06:14:46 AM UTC 24 | Sep 18 06:15:03 AM UTC 24 | 264049692 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1541372204 | Sep 18 06:14:41 AM UTC 24 | Sep 18 06:15:03 AM UTC 24 | 1064268777 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.663804838 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:15:04 AM UTC 24 | 1976482357 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.1487757565 | Sep 18 06:14:52 AM UTC 24 | Sep 18 06:15:04 AM UTC 24 | 182245803 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2143857220 | Sep 18 06:14:56 AM UTC 24 | Sep 18 06:15:06 AM UTC 24 | 167406913 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.235861380 | Sep 18 06:14:58 AM UTC 24 | Sep 18 06:15:07 AM UTC 24 | 176938752 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2814322701 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:15:07 AM UTC 24 | 1829320801 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3045962610 | Sep 18 06:14:52 AM UTC 24 | Sep 18 06:15:08 AM UTC 24 | 1019583357 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.722675596 | Sep 18 06:14:42 AM UTC 24 | Sep 18 06:15:08 AM UTC 24 | 1975066737 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1159025532 | Sep 18 06:14:45 AM UTC 24 | Sep 18 06:15:08 AM UTC 24 | 1741768041 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.337225817 | Sep 18 06:14:45 AM UTC 24 | Sep 18 06:15:08 AM UTC 24 | 546433833 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3577240629 | Sep 18 06:14:50 AM UTC 24 | Sep 18 06:15:10 AM UTC 24 | 1194834954 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2043591622 | Sep 18 06:14:50 AM UTC 24 | Sep 18 06:15:12 AM UTC 24 | 332726896 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.438686219 | Sep 18 06:15:03 AM UTC 24 | Sep 18 06:15:14 AM UTC 24 | 992446004 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1944720060 | Sep 18 06:15:03 AM UTC 24 | Sep 18 06:15:14 AM UTC 24 | 280843383 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.521488899 | Sep 18 06:15:01 AM UTC 24 | Sep 18 06:15:15 AM UTC 24 | 500631542 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1377811635 | Sep 18 06:14:58 AM UTC 24 | Sep 18 06:15:16 AM UTC 24 | 3979878387 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.3391239485 | Sep 18 06:15:05 AM UTC 24 | Sep 18 06:15:18 AM UTC 24 | 182535489 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.4255999043 | Sep 18 06:15:05 AM UTC 24 | Sep 18 06:15:18 AM UTC 24 | 787693068 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1782904095 | Sep 18 06:14:52 AM UTC 24 | Sep 18 06:15:19 AM UTC 24 | 2160317481 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.899811653 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:15:20 AM UTC 24 | 15887481341 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1696962255 | Sep 18 06:15:09 AM UTC 24 | Sep 18 06:15:23 AM UTC 24 | 616335120 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.637818368 | Sep 18 06:15:01 AM UTC 24 | Sep 18 06:15:23 AM UTC 24 | 592751438 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3734800655 | Sep 18 06:14:56 AM UTC 24 | Sep 18 06:15:23 AM UTC 24 | 536228944 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.38755703 | Sep 18 06:15:12 AM UTC 24 | Sep 18 06:15:24 AM UTC 24 | 377508538 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.16474615 | Sep 18 06:15:03 AM UTC 24 | Sep 18 06:15:24 AM UTC 24 | 295475624 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.4048847674 | Sep 18 06:15:10 AM UTC 24 | Sep 18 06:15:25 AM UTC 24 | 264396582 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2075550383 | Sep 18 06:15:03 AM UTC 24 | Sep 18 06:15:27 AM UTC 24 | 665956908 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3638585211 | Sep 18 06:15:16 AM UTC 24 | Sep 18 06:15:31 AM UTC 24 | 472000194 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1797760524 | Sep 18 06:15:00 AM UTC 24 | Sep 18 06:15:31 AM UTC 24 | 560024098 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1541809313 | Sep 18 06:14:55 AM UTC 24 | Sep 18 06:15:32 AM UTC 24 | 16395801156 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3036268965 | Sep 18 06:15:20 AM UTC 24 | Sep 18 06:15:33 AM UTC 24 | 259226110 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1346619878 | Sep 18 06:15:24 AM UTC 24 | Sep 18 06:15:33 AM UTC 24 | 347593691 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.4169469424 | Sep 18 06:14:58 AM UTC 24 | Sep 18 06:15:36 AM UTC 24 | 1964376203 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3539805583 | Sep 18 06:15:20 AM UTC 24 | Sep 18 06:15:37 AM UTC 24 | 726223004 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1391666359 | Sep 18 06:15:05 AM UTC 24 | Sep 18 06:15:38 AM UTC 24 | 1445632819 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.392236580 | Sep 18 06:15:14 AM UTC 24 | Sep 18 06:15:38 AM UTC 24 | 561022017 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3437917640 | Sep 18 06:15:16 AM UTC 24 | Sep 18 06:15:39 AM UTC 24 | 664179896 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.676970757 | Sep 18 06:15:10 AM UTC 24 | Sep 18 06:15:40 AM UTC 24 | 1767579920 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.56680106 | Sep 18 06:15:27 AM UTC 24 | Sep 18 06:15:40 AM UTC 24 | 692478749 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1941432035 | Sep 18 06:15:24 AM UTC 24 | Sep 18 06:15:44 AM UTC 24 | 771725049 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.510679828 | Sep 18 06:15:33 AM UTC 24 | Sep 18 06:15:47 AM UTC 24 | 2068949013 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2584238484 | Sep 18 06:15:07 AM UTC 24 | Sep 18 06:15:51 AM UTC 24 | 17921147059 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1009032110 | Sep 18 06:15:29 AM UTC 24 | Sep 18 06:15:51 AM UTC 24 | 1027762493 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.3432724691 | Sep 18 06:15:39 AM UTC 24 | Sep 18 06:15:53 AM UTC 24 | 1833680606 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1570862936 | Sep 18 06:15:09 AM UTC 24 | Sep 18 06:15:53 AM UTC 24 | 718321982 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.660254574 | Sep 18 06:15:35 AM UTC 24 | Sep 18 06:15:53 AM UTC 24 | 524662329 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1630731006 | Sep 18 06:15:09 AM UTC 24 | Sep 18 06:15:54 AM UTC 24 | 11419442273 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1867260916 | Sep 18 06:15:39 AM UTC 24 | Sep 18 06:15:54 AM UTC 24 | 185035639 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3727510260 | Sep 18 06:15:42 AM UTC 24 | Sep 18 06:15:55 AM UTC 24 | 993961736 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.4212385887 | Sep 18 06:15:39 AM UTC 24 | Sep 18 06:15:55 AM UTC 24 | 696948900 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.2396786481 | Sep 18 06:15:20 AM UTC 24 | Sep 18 06:15:58 AM UTC 24 | 388258521 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3603864262 | Sep 18 06:15:37 AM UTC 24 | Sep 18 06:15:59 AM UTC 24 | 664477898 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.91682632 | Sep 18 06:15:33 AM UTC 24 | Sep 18 06:16:02 AM UTC 24 | 538339377 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2426507645 | Sep 18 06:15:42 AM UTC 24 | Sep 18 06:16:02 AM UTC 24 | 663553597 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.682670112 | Sep 18 06:15:18 AM UTC 24 | Sep 18 06:16:04 AM UTC 24 | 4168613124 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1691111354 | Sep 18 06:15:48 AM UTC 24 | Sep 18 06:16:05 AM UTC 24 | 178165681 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.2402915691 | Sep 18 06:15:54 AM UTC 24 | Sep 18 06:16:05 AM UTC 24 | 662805222 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1014317625 | Sep 18 06:15:56 AM UTC 24 | Sep 18 06:16:10 AM UTC 24 | 988178831 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2926885071 | Sep 18 06:15:27 AM UTC 24 | Sep 18 06:16:11 AM UTC 24 | 3047513975 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.4259477735 | Sep 18 06:15:55 AM UTC 24 | Sep 18 06:16:12 AM UTC 24 | 185138974 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2068698277 | Sep 18 06:16:00 AM UTC 24 | Sep 18 06:16:12 AM UTC 24 | 186511418 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1167409414 | Sep 18 06:15:52 AM UTC 24 | Sep 18 06:16:18 AM UTC 24 | 1138538079 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.881006436 | Sep 18 06:15:55 AM UTC 24 | Sep 18 06:16:22 AM UTC 24 | 738880139 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1843740250 | Sep 18 06:14:50 AM UTC 24 | Sep 18 06:16:22 AM UTC 24 | 4172492808 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2587969371 | Sep 18 06:16:07 AM UTC 24 | Sep 18 06:16:23 AM UTC 24 | 184822304 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.15006382 | Sep 18 06:15:54 AM UTC 24 | Sep 18 06:16:24 AM UTC 24 | 1389401319 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.57540294 | Sep 18 06:15:46 AM UTC 24 | Sep 18 06:16:24 AM UTC 24 | 3983026417 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3316807937 | Sep 18 06:15:10 AM UTC 24 | Sep 18 06:16:26 AM UTC 24 | 1830846841 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3287263068 | Sep 18 06:16:06 AM UTC 24 | Sep 18 06:16:26 AM UTC 24 | 1028945471 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2758574100 | Sep 18 06:16:14 AM UTC 24 | Sep 18 06:16:28 AM UTC 24 | 516664785 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1792242025 | Sep 18 06:16:18 AM UTC 24 | Sep 18 06:16:30 AM UTC 24 | 350586804 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.1341588776 | Sep 18 06:16:04 AM UTC 24 | Sep 18 06:16:33 AM UTC 24 | 1031284312 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2092081055 | Sep 18 06:14:42 AM UTC 24 | Sep 18 06:16:34 AM UTC 24 | 7462552799 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1491551848 | Sep 18 06:16:11 AM UTC 24 | Sep 18 06:16:38 AM UTC 24 | 2064529823 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4190295502 | Sep 18 06:16:25 AM UTC 24 | Sep 18 06:16:39 AM UTC 24 | 993944171 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2007780497 | Sep 18 06:16:17 AM UTC 24 | Sep 18 06:16:40 AM UTC 24 | 634453373 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.1143119790 | Sep 18 06:15:59 AM UTC 24 | Sep 18 06:16:42 AM UTC 24 | 2290200807 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1138375726 | Sep 18 06:16:27 AM UTC 24 | Sep 18 06:16:44 AM UTC 24 | 564950771 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1049057516 | Sep 18 06:16:23 AM UTC 24 | Sep 18 06:16:46 AM UTC 24 | 503198645 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3209032957 | Sep 18 06:16:34 AM UTC 24 | Sep 18 06:16:47 AM UTC 24 | 2070464131 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.4179831135 | Sep 18 06:16:29 AM UTC 24 | Sep 18 06:16:50 AM UTC 24 | 874665425 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2372995752 | Sep 18 06:16:39 AM UTC 24 | Sep 18 06:16:56 AM UTC 24 | 184641808 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.1902135057 | Sep 18 06:16:44 AM UTC 24 | Sep 18 06:16:58 AM UTC 24 | 1034022585 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.866925013 | Sep 18 06:14:55 AM UTC 24 | Sep 18 06:16:58 AM UTC 24 | 3335193231 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.4156868324 | Sep 18 06:16:06 AM UTC 24 | Sep 18 06:16:59 AM UTC 24 | 837877273 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3597027201 | Sep 18 06:15:33 AM UTC 24 | Sep 18 06:17:06 AM UTC 24 | 2073418208 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.3763741584 | Sep 18 06:16:48 AM UTC 24 | Sep 18 06:17:06 AM UTC 24 | 258937611 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2541578884 | Sep 18 06:15:03 AM UTC 24 | Sep 18 06:17:09 AM UTC 24 | 3691002500 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.261029553 | Sep 18 06:16:25 AM UTC 24 | Sep 18 06:17:10 AM UTC 24 | 4808174494 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1277560167 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:17:10 AM UTC 24 | 3731001477 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.13688321 | Sep 18 06:16:59 AM UTC 24 | Sep 18 06:17:12 AM UTC 24 | 167964878 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2813370731 | Sep 18 06:16:35 AM UTC 24 | Sep 18 06:17:13 AM UTC 24 | 367745840 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2357234366 | Sep 18 06:16:40 AM UTC 24 | Sep 18 06:17:14 AM UTC 24 | 496111946 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.982673234 | Sep 18 06:16:31 AM UTC 24 | Sep 18 06:17:15 AM UTC 24 | 3783793947 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4042000332 | Sep 18 06:16:05 AM UTC 24 | Sep 18 06:17:16 AM UTC 24 | 1007194915 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2299910007 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:17:18 AM UTC 24 | 3535234163 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1071637319 | Sep 18 06:15:01 AM UTC 24 | Sep 18 06:17:18 AM UTC 24 | 10644227840 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2995309190 | Sep 18 06:16:46 AM UTC 24 | Sep 18 06:17:20 AM UTC 24 | 538890564 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1543354820 | Sep 18 06:16:57 AM UTC 24 | Sep 18 06:17:20 AM UTC 24 | 349719796 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.2326850999 | Sep 18 06:16:59 AM UTC 24 | Sep 18 06:17:22 AM UTC 24 | 581684758 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.434866354 | Sep 18 06:17:07 AM UTC 24 | Sep 18 06:17:22 AM UTC 24 | 184148947 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.1598376974 | Sep 18 06:17:12 AM UTC 24 | Sep 18 06:17:25 AM UTC 24 | 660579583 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.634514968 | Sep 18 06:17:14 AM UTC 24 | Sep 18 06:17:27 AM UTC 24 | 736870420 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4013297513 | Sep 18 06:14:46 AM UTC 24 | Sep 18 06:17:30 AM UTC 24 | 2991007492 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2502240547 | Sep 18 06:17:19 AM UTC 24 | Sep 18 06:17:32 AM UTC 24 | 664766308 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1467521151 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:17:35 AM UTC 24 | 11890537528 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3581164893 | Sep 18 06:14:55 AM UTC 24 | Sep 18 06:17:36 AM UTC 24 | 3072209139 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.4160661240 | Sep 18 06:17:23 AM UTC 24 | Sep 18 06:17:36 AM UTC 24 | 2062895883 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2186773779 | Sep 18 06:17:17 AM UTC 24 | Sep 18 06:17:37 AM UTC 24 | 661261378 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1770045891 | Sep 18 06:17:37 AM UTC 24 | Sep 18 06:17:50 AM UTC 24 | 718563705 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.586086467 | Sep 18 06:15:39 AM UTC 24 | Sep 18 06:17:37 AM UTC 24 | 11245505469 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1904851643 | Sep 18 06:17:12 AM UTC 24 | Sep 18 06:17:40 AM UTC 24 | 2063214516 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3985768833 | Sep 18 06:17:28 AM UTC 24 | Sep 18 06:17:44 AM UTC 24 | 364098840 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2298821018 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:17:45 AM UTC 24 | 4463329905 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3240022018 | Sep 18 06:15:42 AM UTC 24 | Sep 18 06:17:45 AM UTC 24 | 2854530557 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3776468517 | Sep 18 06:17:21 AM UTC 24 | Sep 18 06:17:47 AM UTC 24 | 1072110715 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2273209286 | Sep 18 06:17:14 AM UTC 24 | Sep 18 06:17:48 AM UTC 24 | 315169428 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3546552280 | Sep 18 06:14:45 AM UTC 24 | Sep 18 06:17:48 AM UTC 24 | 3049559770 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2297594267 | Sep 18 06:17:26 AM UTC 24 | Sep 18 06:17:50 AM UTC 24 | 266980617 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2206155924 | Sep 18 06:17:22 AM UTC 24 | Sep 18 06:17:53 AM UTC 24 | 2605167957 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2021053541 | Sep 18 06:17:38 AM UTC 24 | Sep 18 06:17:54 AM UTC 24 | 174910010 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.72710956 | Sep 18 06:17:33 AM UTC 24 | Sep 18 06:17:55 AM UTC 24 | 661739535 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.250721273 | Sep 18 06:17:19 AM UTC 24 | Sep 18 06:17:58 AM UTC 24 | 2109114763 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.735129421 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:17:58 AM UTC 24 | 4052226051 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2891145209 | Sep 18 06:17:47 AM UTC 24 | Sep 18 06:18:01 AM UTC 24 | 467848701 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2623849013 | Sep 18 06:17:46 AM UTC 24 | Sep 18 06:18:03 AM UTC 24 | 4106955695 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1518290741 | Sep 18 06:17:51 AM UTC 24 | Sep 18 06:18:04 AM UTC 24 | 368293469 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3617970205 | Sep 18 06:17:37 AM UTC 24 | Sep 18 06:18:06 AM UTC 24 | 1278898425 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1949147419 | Sep 18 06:16:24 AM UTC 24 | Sep 18 06:18:06 AM UTC 24 | 2200764092 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3152933598 | Sep 18 06:17:41 AM UTC 24 | Sep 18 06:18:10 AM UTC 24 | 347264511 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3717204937 | Sep 18 06:17:55 AM UTC 24 | Sep 18 06:18:13 AM UTC 24 | 1015880407 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.658649518 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:18:15 AM UTC 24 | 5152371480 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3932967316 | Sep 18 06:17:49 AM UTC 24 | Sep 18 06:18:16 AM UTC 24 | 498330810 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.195752535 | Sep 18 06:16:04 AM UTC 24 | Sep 18 06:18:16 AM UTC 24 | 2112824800 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.3266451201 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:18:16 AM UTC 24 | 487198655 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1388534733 | Sep 18 06:15:05 AM UTC 24 | Sep 18 06:18:17 AM UTC 24 | 3298707947 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1386267449 | Sep 18 06:18:02 AM UTC 24 | Sep 18 06:18:17 AM UTC 24 | 2054420078 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3891714763 | Sep 18 06:15:16 AM UTC 24 | Sep 18 06:18:17 AM UTC 24 | 4791644564 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2797014518 | Sep 18 06:18:05 AM UTC 24 | Sep 18 06:18:18 AM UTC 24 | 198120692 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2273873791 | Sep 18 06:15:35 AM UTC 24 | Sep 18 06:18:19 AM UTC 24 | 10644699310 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2163276890 | Sep 18 06:18:04 AM UTC 24 | Sep 18 06:18:20 AM UTC 24 | 208014848 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.372094030 | Sep 18 06:17:46 AM UTC 24 | Sep 18 06:18:23 AM UTC 24 | 1155398368 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3909706787 | Sep 18 06:17:17 AM UTC 24 | Sep 18 06:18:24 AM UTC 24 | 2410717442 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.347883149 | Sep 18 06:16:42 AM UTC 24 | Sep 18 06:18:24 AM UTC 24 | 6855607458 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2923237381 | Sep 18 06:14:58 AM UTC 24 | Sep 18 06:18:24 AM UTC 24 | 16283554809 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2287756810 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:18:24 AM UTC 24 | 521381903 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2897471877 | Sep 18 06:18:18 AM UTC 24 | Sep 18 06:18:27 AM UTC 24 | 174611423 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.189940327 | Sep 18 06:18:14 AM UTC 24 | Sep 18 06:18:28 AM UTC 24 | 287858899 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.301148546 | Sep 18 06:15:54 AM UTC 24 | Sep 18 06:18:28 AM UTC 24 | 14322859542 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2824250214 | Sep 18 06:14:58 AM UTC 24 | Sep 18 06:18:29 AM UTC 24 | 2811202146 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2499427506 | Sep 18 06:17:59 AM UTC 24 | Sep 18 06:18:30 AM UTC 24 | 1028463863 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2401583233 | Sep 18 06:18:17 AM UTC 24 | Sep 18 06:18:33 AM UTC 24 | 614972312 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3339598156 | Sep 18 06:18:19 AM UTC 24 | Sep 18 06:18:37 AM UTC 24 | 1087751967 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3494971601 | Sep 18 06:18:07 AM UTC 24 | Sep 18 06:18:38 AM UTC 24 | 332261738 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1251853181 | Sep 18 06:18:24 AM UTC 24 | Sep 18 06:18:39 AM UTC 24 | 250058174 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1184618180 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:18:39 AM UTC 24 | 866661056 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.548867543 | Sep 18 06:17:54 AM UTC 24 | Sep 18 06:18:41 AM UTC 24 | 4265243091 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1652433984 | Sep 18 06:18:21 AM UTC 24 | Sep 18 06:18:41 AM UTC 24 | 664070474 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.4250197308 | Sep 18 06:18:24 AM UTC 24 | Sep 18 06:18:42 AM UTC 24 | 3677969666 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.1436758862 | Sep 18 06:18:24 AM UTC 24 | Sep 18 06:18:42 AM UTC 24 | 1555848792 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2678527091 | Sep 18 06:18:15 AM UTC 24 | Sep 18 06:18:43 AM UTC 24 | 201240905 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1524227064 | Sep 18 06:18:30 AM UTC 24 | Sep 18 06:18:43 AM UTC 24 | 250121281 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.3757176657 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:18:45 AM UTC 24 | 988728710 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3774091075 | Sep 18 06:18:31 AM UTC 24 | Sep 18 06:18:45 AM UTC 24 | 537016409 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.844482831 | Sep 18 06:18:17 AM UTC 24 | Sep 18 06:18:45 AM UTC 24 | 515364548 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2619309322 | Sep 18 06:18:40 AM UTC 24 | Sep 18 06:18:51 AM UTC 24 | 345855099 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3193982543 | Sep 18 06:17:45 AM UTC 24 | Sep 18 06:18:52 AM UTC 24 | 5856890882 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3901625705 | Sep 18 06:17:36 AM UTC 24 | Sep 18 06:18:52 AM UTC 24 | 1644312571 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.467840646 | Sep 18 06:18:27 AM UTC 24 | Sep 18 06:18:55 AM UTC 24 | 1387652303 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3064756037 | Sep 18 06:18:44 AM UTC 24 | Sep 18 06:18:57 AM UTC 24 | 496386529 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.1024844764 | Sep 18 06:18:18 AM UTC 24 | Sep 18 06:18:59 AM UTC 24 | 1471902084 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4158454934 | Sep 18 06:17:12 AM UTC 24 | Sep 18 06:19:00 AM UTC 24 | 10968794720 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2193953622 | Sep 18 06:14:37 AM UTC 24 | Sep 18 06:19:01 AM UTC 24 | 20198795695 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.915860603 | Sep 18 06:17:21 AM UTC 24 | Sep 18 06:19:01 AM UTC 24 | 2302150523 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.230244358 | Sep 18 06:15:03 AM UTC 24 | Sep 18 06:19:01 AM UTC 24 | 9291424096 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2778183675 | Sep 18 06:18:45 AM UTC 24 | Sep 18 06:19:02 AM UTC 24 | 3629864188 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3584826908 | Sep 18 06:18:42 AM UTC 24 | Sep 18 06:19:02 AM UTC 24 | 7600107206 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3814269854 | Sep 18 06:14:32 AM UTC 24 | Sep 18 06:19:03 AM UTC 24 | 416780381 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.4183945131 | Sep 18 06:18:53 AM UTC 24 | Sep 18 06:19:05 AM UTC 24 | 688211476 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1739802672 | Sep 18 06:18:38 AM UTC 24 | Sep 18 06:19:05 AM UTC 24 | 678370621 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2701132507 | Sep 18 06:18:40 AM UTC 24 | Sep 18 06:19:08 AM UTC 24 | 1561786653 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.4122316332 | Sep 18 06:18:24 AM UTC 24 | Sep 18 06:19:10 AM UTC 24 | 4617550937 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.349166260 | Sep 18 06:18:11 AM UTC 24 | Sep 18 06:19:10 AM UTC 24 | 1247533043 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.428107411 | Sep 18 06:18:42 AM UTC 24 | Sep 18 06:19:12 AM UTC 24 | 332515441 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.4149289020 | Sep 18 06:18:56 AM UTC 24 | Sep 18 06:19:14 AM UTC 24 | 2806741325 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.339980821 | Sep 18 06:19:02 AM UTC 24 | Sep 18 06:19:14 AM UTC 24 | 260096842 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2716133985 | Sep 18 06:19:02 AM UTC 24 | Sep 18 06:19:16 AM UTC 24 | 1276185785 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2227198922 | Sep 18 06:19:05 AM UTC 24 | Sep 18 06:19:17 AM UTC 24 | 346236811 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1787442902 | Sep 18 06:15:52 AM UTC 24 | Sep 18 06:19:19 AM UTC 24 | 4909291293 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3994650967 | Sep 18 06:18:30 AM UTC 24 | Sep 18 06:19:19 AM UTC 24 | 794025544 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1835934829 | Sep 18 06:14:42 AM UTC 24 | Sep 18 06:19:21 AM UTC 24 | 13947841922 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.962036699 | Sep 18 06:18:53 AM UTC 24 | Sep 18 06:19:21 AM UTC 24 | 2200794107 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2772076771 | Sep 18 06:15:22 AM UTC 24 | Sep 18 06:19:23 AM UTC 24 | 15622709394 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.4188112813 | Sep 18 06:19:09 AM UTC 24 | Sep 18 06:19:27 AM UTC 24 | 257474951 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3111337227 | Sep 18 06:14:50 AM UTC 24 | Sep 18 06:19:28 AM UTC 24 | 87738567874 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1610987368 | Sep 18 06:19:15 AM UTC 24 | Sep 18 06:19:29 AM UTC 24 | 6589043774 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.2982581468 | Sep 18 06:19:22 AM UTC 24 | Sep 18 06:19:31 AM UTC 24 | 170827595 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.947870512 | Sep 18 06:18:47 AM UTC 24 | Sep 18 06:19:32 AM UTC 24 | 17854854328 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1026358834 | Sep 18 06:19:02 AM UTC 24 | Sep 18 06:19:33 AM UTC 24 | 591869268 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3048785375 | Sep 18 06:18:44 AM UTC 24 | Sep 18 06:19:35 AM UTC 24 | 1064543112 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1867219607 | Sep 18 06:15:42 AM UTC 24 | Sep 18 06:19:35 AM UTC 24 | 15620955986 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3687067243 | Sep 18 06:19:02 AM UTC 24 | Sep 18 06:19:36 AM UTC 24 | 39350628522 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.519344695 | Sep 18 06:19:17 AM UTC 24 | Sep 18 06:19:36 AM UTC 24 | 4267051181 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3985469459 | Sep 18 06:15:24 AM UTC 24 | Sep 18 06:19:40 AM UTC 24 | 16306771330 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2571896670 | Sep 18 06:19:11 AM UTC 24 | Sep 18 06:19:41 AM UTC 24 | 1380538964 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3128929824 | Sep 18 06:18:43 AM UTC 24 | Sep 18 06:19:41 AM UTC 24 | 10280393801 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1236851351 | Sep 18 06:19:24 AM UTC 24 | Sep 18 06:19:41 AM UTC 24 | 696440846 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.365989101 | Sep 18 06:19:19 AM UTC 24 | Sep 18 06:19:43 AM UTC 24 | 1073129698 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4021655619 | Sep 18 06:19:32 AM UTC 24 | Sep 18 06:19:45 AM UTC 24 | 1034810673 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.698010314 | Sep 18 06:19:34 AM UTC 24 | Sep 18 06:19:48 AM UTC 24 | 346367581 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2519012659 | Sep 18 06:19:15 AM UTC 24 | Sep 18 06:19:48 AM UTC 24 | 535234113 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3161267270 | Sep 18 06:14:31 AM UTC 24 | Sep 18 06:19:48 AM UTC 24 | 26637030832 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2963196395 | Sep 18 06:16:22 AM UTC 24 | Sep 18 06:19:50 AM UTC 24 | 2427128325 ps |
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