Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 96.77 92.13 97.68 100.00 98.19 97.91 99.06


Total tests in report: 458
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.92 63.92 92.31 92.31 75.56 75.56 46.78 46.78 40.00 40.00 89.49 89.49 93.73 93.73 9.60 9.60 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1185214405
77.59 13.66 96.15 3.85 85.96 10.39 61.24 14.47 53.33 13.33 93.84 4.35 95.67 1.94 56.91 47.31 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2859915565
83.21 5.63 96.15 0.00 86.10 0.14 73.79 12.54 53.33 0.00 93.84 0.00 95.67 0.00 83.61 26.70 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4181868162
87.51 4.30 96.15 0.00 88.76 2.67 73.79 0.00 80.00 26.67 94.20 0.36 95.82 0.15 83.84 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3432540559
90.46 2.95 96.28 0.12 89.04 0.28 79.76 5.97 93.33 13.33 94.93 0.72 95.82 0.00 84.07 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.3950573807
92.68 2.21 96.53 0.25 89.75 0.70 85.16 5.40 100.00 6.67 97.10 2.17 96.12 0.30 84.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.3964277343
93.89 1.21 96.53 0.00 89.75 0.00 91.30 6.15 100.00 0.00 97.10 0.00 96.12 0.00 86.42 2.34 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1209094917
94.91 1.03 96.77 0.25 90.45 0.70 91.30 0.00 100.00 0.00 98.19 1.09 96.12 0.00 91.57 5.15 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1952672785
95.51 0.60 96.77 0.00 90.59 0.14 94.65 3.35 100.00 0.00 98.19 0.00 96.12 0.00 92.27 0.70 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.27271261
95.83 0.32 96.77 0.00 91.29 0.70 94.70 0.05 100.00 0.00 98.19 0.00 96.42 0.30 93.44 1.17 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2885256330
96.13 0.30 96.77 0.00 91.29 0.00 94.70 0.00 100.00 0.00 98.19 0.00 96.42 0.00 95.55 2.11 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2464285262
96.36 0.22 96.77 0.00 91.85 0.56 95.70 1.00 100.00 0.00 98.19 0.00 96.42 0.00 95.55 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.4136209694
96.56 0.20 96.77 0.00 91.85 0.00 95.70 0.00 100.00 0.00 98.19 0.00 96.42 0.00 96.96 1.41 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1486552051
96.72 0.16 96.77 0.00 91.85 0.00 95.70 0.00 100.00 0.00 98.19 0.00 97.31 0.90 97.19 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2276219417
96.86 0.14 96.77 0.00 91.85 0.00 96.30 0.60 100.00 0.00 98.19 0.00 97.46 0.15 97.42 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.320741982
96.96 0.10 96.77 0.00 91.85 0.00 96.30 0.00 100.00 0.00 98.19 0.00 97.46 0.00 98.13 0.70 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1938925739
97.05 0.09 96.77 0.00 91.85 0.00 96.95 0.65 100.00 0.00 98.19 0.00 97.46 0.00 98.13 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.470522922
97.13 0.08 96.77 0.00 91.85 0.00 96.95 0.00 100.00 0.00 98.19 0.00 97.76 0.30 98.36 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.965155327
97.19 0.07 96.77 0.00 91.85 0.00 96.95 0.00 100.00 0.00 98.19 0.00 97.76 0.00 98.83 0.47 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3413279259
97.25 0.05 96.77 0.00 91.85 0.00 97.10 0.15 100.00 0.00 98.19 0.00 97.76 0.00 99.06 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.257268144
97.30 0.05 96.77 0.00 91.85 0.00 97.43 0.32 100.00 0.00 98.19 0.00 97.76 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.68157617
97.34 0.04 96.77 0.00 91.99 0.14 97.43 0.00 100.00 0.00 98.19 0.00 97.91 0.15 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2493310616
97.36 0.02 96.77 0.00 92.13 0.14 97.43 0.00 100.00 0.00 98.19 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2690384384
97.37 0.02 96.77 0.00 92.13 0.00 97.55 0.12 100.00 0.00 98.19 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2559184934
97.39 0.01 96.77 0.00 92.13 0.00 97.63 0.07 100.00 0.00 98.19 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.285688961
97.39 0.01 96.77 0.00 92.13 0.00 97.65 0.02 100.00 0.00 98.19 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.482352154
97.39 0.01 96.77 0.00 92.13 0.00 97.68 0.02 100.00 0.00 98.19 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1739830171

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1989787129
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3737563128
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3712265604
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.816758993
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.88615630
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.516684493
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3834463366
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2358455322
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2121494322
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2909763738
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2941175102
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3750203744
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1799546164
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2745208557
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.99463541
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1198464389
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2700987011
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1407288848
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3170710340
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.973154573
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1626091343
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2626210959
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.277227032
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2821964162
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.332438517
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2594127160
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.920353438
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1262432715
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2818378688
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2412728540
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2060210068
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4037799710
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2230875629
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3069138461
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2886583062
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.341353039
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2801496655
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.161808429
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4111582579
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1078473772
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3985251711
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.624963892
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1814140694
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1904027453
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2931997209
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.312268868
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1508671450
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2815752019
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4122521009
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1591176160
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.487532801
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3210606300
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3528305820
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2567357701
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2414194596
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1958796486
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3165179264
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4226743463
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2191080990
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2059070362
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2672149910
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1253402151
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4265610811
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3020904938
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3341135638
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2280876871
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1243410863
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.224134492
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1611766957
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1400910622
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2992742949
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3734975470
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4052502059
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4051675327
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1942597327
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4161568881
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1704296182
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3865360017
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3982666008
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.736817636
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Total test records in report: 458
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.482352154 Sep 24 06:50:07 AM UTC 24 Sep 24 06:50:17 AM UTC 24 255926541 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1288844049 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:17 AM UTC 24 517641683 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1004339489 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:19 AM UTC 24 519890762 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.569088454 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:19 AM UTC 24 688499096 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.721994353 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:21 AM UTC 24 520271311 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.4136209694 Sep 24 06:50:10 AM UTC 24 Sep 24 06:50:21 AM UTC 24 654106047 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.2283071670 Sep 24 06:50:07 AM UTC 24 Sep 24 06:50:21 AM UTC 24 521726346 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3218138002 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:21 AM UTC 24 261624986 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.257268144 Sep 24 06:50:07 AM UTC 24 Sep 24 06:50:22 AM UTC 24 348685486 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1185214405 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:24 AM UTC 24 292350439 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3072174431 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:25 AM UTC 24 526878706 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.2856716014 Sep 24 06:50:10 AM UTC 24 Sep 24 06:50:25 AM UTC 24 1987272281 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.53011489 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:26 AM UTC 24 699640112 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1591062454 Sep 24 06:50:10 AM UTC 24 Sep 24 06:50:26 AM UTC 24 918809816 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.4169112928 Sep 24 06:50:12 AM UTC 24 Sep 24 06:50:26 AM UTC 24 170071918 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2350183525 Sep 24 06:50:10 AM UTC 24 Sep 24 06:50:27 AM UTC 24 312662220 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.320741982 Sep 24 06:50:07 AM UTC 24 Sep 24 06:50:28 AM UTC 24 2393547958 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.27271261 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:30 AM UTC 24 1076414780 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2559184934 Sep 24 06:50:07 AM UTC 24 Sep 24 06:50:31 AM UTC 24 518160306 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3644265919 Sep 24 06:50:12 AM UTC 24 Sep 24 06:50:31 AM UTC 24 1033568811 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.629385557 Sep 24 06:50:13 AM UTC 24 Sep 24 06:50:31 AM UTC 24 1023769677 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1155025419 Sep 24 06:50:20 AM UTC 24 Sep 24 06:50:31 AM UTC 24 170979742 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.4192768678 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:33 AM UTC 24 512540186 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2974973256 Sep 24 06:50:20 AM UTC 24 Sep 24 06:50:35 AM UTC 24 1027875734 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.582136767 Sep 24 06:50:22 AM UTC 24 Sep 24 06:50:35 AM UTC 24 270760800 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2064549483 Sep 24 06:50:08 AM UTC 24 Sep 24 06:50:35 AM UTC 24 2099248808 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3809629196 Sep 24 06:50:23 AM UTC 24 Sep 24 06:50:37 AM UTC 24 988982690 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2859915565 Sep 24 06:50:07 AM UTC 24 Sep 24 06:50:37 AM UTC 24 1129990787 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3827368590 Sep 24 06:50:25 AM UTC 24 Sep 24 06:50:38 AM UTC 24 529190853 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1664267884 Sep 24 06:50:27 AM UTC 24 Sep 24 06:50:39 AM UTC 24 2249180361 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3191498120 Sep 24 06:50:13 AM UTC 24 Sep 24 06:50:39 AM UTC 24 1112469225 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.3964277343 Sep 24 06:50:10 AM UTC 24 Sep 24 06:50:41 AM UTC 24 636814825 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2155593976 Sep 24 06:50:26 AM UTC 24 Sep 24 06:50:42 AM UTC 24 263909888 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1870311005 Sep 24 06:50:18 AM UTC 24 Sep 24 06:50:43 AM UTC 24 9855945433 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1816438609 Sep 24 06:50:10 AM UTC 24 Sep 24 06:50:46 AM UTC 24 7863610835 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.2432821286 Sep 24 06:50:31 AM UTC 24 Sep 24 06:50:46 AM UTC 24 184910201 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3131855094 Sep 24 06:50:32 AM UTC 24 Sep 24 06:50:46 AM UTC 24 1027097681 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.914670159 Sep 24 06:50:33 AM UTC 24 Sep 24 06:50:46 AM UTC 24 759267719 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2262895990 Sep 24 06:50:29 AM UTC 24 Sep 24 06:50:47 AM UTC 24 1069966475 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1855017711 Sep 24 06:50:36 AM UTC 24 Sep 24 06:50:49 AM UTC 24 687998384 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3606408312 Sep 24 06:50:26 AM UTC 24 Sep 24 06:50:50 AM UTC 24 517986313 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.539628688 Sep 24 06:50:34 AM UTC 24 Sep 24 06:50:50 AM UTC 24 993073901 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2882327393 Sep 24 06:50:22 AM UTC 24 Sep 24 06:50:50 AM UTC 24 7094946928 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2657378653 Sep 24 06:50:38 AM UTC 24 Sep 24 06:50:51 AM UTC 24 1063749642 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.470522922 Sep 24 06:50:10 AM UTC 24 Sep 24 06:50:55 AM UTC 24 2174496334 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.4475077 Sep 24 06:50:42 AM UTC 24 Sep 24 06:50:55 AM UTC 24 249748328 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2464285262 Sep 24 06:50:11 AM UTC 24 Sep 24 06:50:55 AM UTC 24 6304623405 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2050299353 Sep 24 06:50:26 AM UTC 24 Sep 24 06:50:57 AM UTC 24 1142086279 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3338439288 Sep 24 06:50:30 AM UTC 24 Sep 24 06:50:58 AM UTC 24 2118992860 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.4210135795 Sep 24 06:50:51 AM UTC 24 Sep 24 06:51:00 AM UTC 24 338939982 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.940238380 Sep 24 06:50:47 AM UTC 24 Sep 24 06:51:00 AM UTC 24 1031709933 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.205576675 Sep 24 06:50:35 AM UTC 24 Sep 24 06:51:00 AM UTC 24 495425759 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.3228053161 Sep 24 06:50:51 AM UTC 24 Sep 24 06:51:02 AM UTC 24 178981013 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1209094917 Sep 24 06:50:10 AM UTC 24 Sep 24 06:51:03 AM UTC 24 1554844115 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.90470056 Sep 24 06:50:44 AM UTC 24 Sep 24 06:51:04 AM UTC 24 262669289 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1945472111 Sep 24 06:50:38 AM UTC 24 Sep 24 06:51:05 AM UTC 24 745464337 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.149858665 Sep 24 06:50:32 AM UTC 24 Sep 24 06:51:06 AM UTC 24 39450658018 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.782743878 Sep 24 06:50:48 AM UTC 24 Sep 24 06:51:07 AM UTC 24 270710663 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1513615052 Sep 24 06:50:56 AM UTC 24 Sep 24 06:51:07 AM UTC 24 251077635 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.3950573807 Sep 24 06:50:46 AM UTC 24 Sep 24 06:51:09 AM UTC 24 516341408 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1224968660 Sep 24 06:51:01 AM UTC 24 Sep 24 06:51:12 AM UTC 24 331910460 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3568504743 Sep 24 06:51:01 AM UTC 24 Sep 24 06:51:12 AM UTC 24 362508090 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2188614996 Sep 24 06:50:22 AM UTC 24 Sep 24 06:51:12 AM UTC 24 4548894195 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.341987101 Sep 24 06:50:40 AM UTC 24 Sep 24 06:51:13 AM UTC 24 1974511547 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.4133667483 Sep 24 06:50:56 AM UTC 24 Sep 24 06:51:13 AM UTC 24 1028845181 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3074353968 Sep 24 06:50:50 AM UTC 24 Sep 24 06:51:15 AM UTC 24 522594068 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.285688961 Sep 24 06:50:34 AM UTC 24 Sep 24 06:51:16 AM UTC 24 8316289080 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1771508202 Sep 24 06:50:43 AM UTC 24 Sep 24 06:51:16 AM UTC 24 2304669487 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2064778697 Sep 24 06:50:47 AM UTC 24 Sep 24 06:51:16 AM UTC 24 1250026854 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2496995577 Sep 24 06:51:06 AM UTC 24 Sep 24 06:51:17 AM UTC 24 169673607 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2387957085 Sep 24 06:50:56 AM UTC 24 Sep 24 06:51:18 AM UTC 24 1058309272 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3506253077 Sep 24 06:51:07 AM UTC 24 Sep 24 06:51:20 AM UTC 24 729265432 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.229578104 Sep 24 06:50:53 AM UTC 24 Sep 24 06:51:22 AM UTC 24 2048489544 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1359319269 Sep 24 06:51:13 AM UTC 24 Sep 24 06:51:22 AM UTC 24 509667698 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.535641784 Sep 24 06:50:51 AM UTC 24 Sep 24 06:51:24 AM UTC 24 196614993 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1739830171 Sep 24 06:50:58 AM UTC 24 Sep 24 06:51:25 AM UTC 24 848319322 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3016661516 Sep 24 06:51:03 AM UTC 24 Sep 24 06:51:26 AM UTC 24 1765663664 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.378690996 Sep 24 06:50:32 AM UTC 24 Sep 24 06:51:27 AM UTC 24 2149106767 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1105785391 Sep 24 06:51:17 AM UTC 24 Sep 24 06:51:28 AM UTC 24 174287522 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.996882836 Sep 24 06:51:14 AM UTC 24 Sep 24 06:51:30 AM UTC 24 179051907 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.1618397623 Sep 24 06:51:01 AM UTC 24 Sep 24 06:51:31 AM UTC 24 2285986308 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.4134291221 Sep 24 06:51:17 AM UTC 24 Sep 24 06:51:33 AM UTC 24 2319383755 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3557518008 Sep 24 06:51:06 AM UTC 24 Sep 24 06:51:34 AM UTC 24 1539906848 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4181868162 Sep 24 06:50:36 AM UTC 24 Sep 24 06:51:34 AM UTC 24 2726619862 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.68157617 Sep 24 06:50:41 AM UTC 24 Sep 24 06:51:35 AM UTC 24 8142175588 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2091524376 Sep 24 06:51:21 AM UTC 24 Sep 24 06:51:35 AM UTC 24 259284147 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3008554426 Sep 24 06:51:17 AM UTC 24 Sep 24 06:51:35 AM UTC 24 1144321654 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3741391045 Sep 24 06:51:24 AM UTC 24 Sep 24 06:51:36 AM UTC 24 874979811 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.14268030 Sep 24 06:51:10 AM UTC 24 Sep 24 06:51:38 AM UTC 24 350447530 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2917256782 Sep 24 06:51:13 AM UTC 24 Sep 24 06:51:39 AM UTC 24 512123943 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.4154788510 Sep 24 06:51:26 AM UTC 24 Sep 24 06:51:41 AM UTC 24 250518073 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.138140114 Sep 24 06:53:08 AM UTC 24 Sep 24 06:53:21 AM UTC 24 621058003 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.4093265698 Sep 24 06:51:27 AM UTC 24 Sep 24 06:51:42 AM UTC 24 540519063 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2465843793 Sep 24 06:51:23 AM UTC 24 Sep 24 06:51:43 AM UTC 24 213089805 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3402250030 Sep 24 06:51:34 AM UTC 24 Sep 24 06:51:44 AM UTC 24 175384794 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1154971722 Sep 24 06:51:16 AM UTC 24 Sep 24 06:51:47 AM UTC 24 332690778 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3226649752 Sep 24 06:51:18 AM UTC 24 Sep 24 06:51:49 AM UTC 24 1981510225 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.832677295 Sep 24 06:51:30 AM UTC 24 Sep 24 06:51:50 AM UTC 24 332279986 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3154796707 Sep 24 06:51:35 AM UTC 24 Sep 24 06:51:51 AM UTC 24 179887022 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.129350088 Sep 24 06:51:37 AM UTC 24 Sep 24 06:51:52 AM UTC 24 1238075922 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3819445786 Sep 24 06:50:14 AM UTC 24 Sep 24 06:51:53 AM UTC 24 3440250927 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1834756589 Sep 24 06:51:27 AM UTC 24 Sep 24 06:51:54 AM UTC 24 289213641 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.913099902 Sep 24 06:51:26 AM UTC 24 Sep 24 06:51:55 AM UTC 24 689767789 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.127423671 Sep 24 06:51:38 AM UTC 24 Sep 24 06:51:55 AM UTC 24 1252355169 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3275616535 Sep 24 06:51:40 AM UTC 24 Sep 24 06:51:56 AM UTC 24 273015399 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2831874102 Sep 24 06:51:36 AM UTC 24 Sep 24 06:51:57 AM UTC 24 677716596 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3207846910 Sep 24 06:51:44 AM UTC 24 Sep 24 06:51:58 AM UTC 24 257899038 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.808111143 Sep 24 06:50:08 AM UTC 24 Sep 24 06:51:59 AM UTC 24 10120082651 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3153057444 Sep 24 06:51:49 AM UTC 24 Sep 24 06:52:03 AM UTC 24 270681157 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1084180007 Sep 24 06:51:35 AM UTC 24 Sep 24 06:52:05 AM UTC 24 10721664137 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2188774227 Sep 24 06:50:59 AM UTC 24 Sep 24 06:52:07 AM UTC 24 4807633471 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3226253807 Sep 24 06:51:54 AM UTC 24 Sep 24 06:52:08 AM UTC 24 1128095843 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.1585021905 Sep 24 06:51:59 AM UTC 24 Sep 24 06:52:11 AM UTC 24 1181259553 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.770132821 Sep 24 06:51:56 AM UTC 24 Sep 24 06:52:12 AM UTC 24 1075142194 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.567998189 Sep 24 06:50:23 AM UTC 24 Sep 24 06:52:13 AM UTC 24 23258260830 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.46182233 Sep 24 06:51:43 AM UTC 24 Sep 24 06:52:16 AM UTC 24 496189162 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1422037756 Sep 24 06:52:03 AM UTC 24 Sep 24 06:52:21 AM UTC 24 179440448 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.4112322766 Sep 24 06:51:48 AM UTC 24 Sep 24 06:52:21 AM UTC 24 553236324 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3547778100 Sep 24 06:50:22 AM UTC 24 Sep 24 06:52:22 AM UTC 24 1814083246 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.2956299176 Sep 24 06:51:51 AM UTC 24 Sep 24 06:52:23 AM UTC 24 2539831229 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2092187478 Sep 24 06:52:00 AM UTC 24 Sep 24 06:52:26 AM UTC 24 284135478 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1928839799 Sep 24 06:52:12 AM UTC 24 Sep 24 06:52:26 AM UTC 24 170730702 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3951695018 Sep 24 06:51:26 AM UTC 24 Sep 24 06:52:26 AM UTC 24 1288363962 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3382355918 Sep 24 06:51:55 AM UTC 24 Sep 24 06:52:27 AM UTC 24 2227708363 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.432031638 Sep 24 06:51:57 AM UTC 24 Sep 24 06:52:27 AM UTC 24 675801407 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.290260168 Sep 24 06:52:15 AM UTC 24 Sep 24 06:52:31 AM UTC 24 343952259 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3991092218 Sep 24 06:50:32 AM UTC 24 Sep 24 06:52:33 AM UTC 24 2482750274 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.977845384 Sep 24 06:50:26 AM UTC 24 Sep 24 06:52:34 AM UTC 24 3368320070 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3454615765 Sep 24 06:52:07 AM UTC 24 Sep 24 06:52:36 AM UTC 24 349652059 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2460323840 Sep 24 06:50:08 AM UTC 24 Sep 24 06:52:38 AM UTC 24 15185430729 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.526591126 Sep 24 06:52:23 AM UTC 24 Sep 24 06:52:39 AM UTC 24 992317965 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2873430548 Sep 24 06:50:26 AM UTC 24 Sep 24 06:52:40 AM UTC 24 3415901233 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4118022491 Sep 24 06:51:13 AM UTC 24 Sep 24 06:52:42 AM UTC 24 4320001318 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2226499688 Sep 24 06:52:28 AM UTC 24 Sep 24 06:52:44 AM UTC 24 988167891 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.701494245 Sep 24 06:51:32 AM UTC 24 Sep 24 06:52:45 AM UTC 24 3127247534 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.1356961943 Sep 24 06:52:26 AM UTC 24 Sep 24 06:52:46 AM UTC 24 488720613 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1808641495 Sep 24 06:50:07 AM UTC 24 Sep 24 06:52:51 AM UTC 24 4559380724 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1287402400 Sep 24 06:52:27 AM UTC 24 Sep 24 06:52:51 AM UTC 24 517633393 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1481191031 Sep 24 06:52:34 AM UTC 24 Sep 24 06:52:53 AM UTC 24 267942298 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1281424650 Sep 24 06:52:22 AM UTC 24 Sep 24 06:52:54 AM UTC 24 991528519 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.306396325 Sep 24 06:52:22 AM UTC 24 Sep 24 06:52:55 AM UTC 24 3953440727 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1400886791 Sep 24 06:52:31 AM UTC 24 Sep 24 06:52:58 AM UTC 24 535598163 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3705911266 Sep 24 06:52:43 AM UTC 24 Sep 24 06:52:59 AM UTC 24 692988571 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2728500863 Sep 24 06:52:24 AM UTC 24 Sep 24 06:53:01 AM UTC 24 2222131711 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1752446404 Sep 24 06:52:52 AM UTC 24 Sep 24 06:53:02 AM UTC 24 506328936 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3599035965 Sep 24 06:50:46 AM UTC 24 Sep 24 06:53:02 AM UTC 24 3537274886 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.440810378 Sep 24 06:52:41 AM UTC 24 Sep 24 06:53:03 AM UTC 24 1037780188 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.508065873 Sep 24 06:52:36 AM UTC 24 Sep 24 06:53:05 AM UTC 24 1272616348 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.324159887 Sep 24 06:52:13 AM UTC 24 Sep 24 06:53:07 AM UTC 24 819158873 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.739258863 Sep 24 06:52:54 AM UTC 24 Sep 24 06:53:11 AM UTC 24 266302758 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.693805676 Sep 24 06:52:46 AM UTC 24 Sep 24 06:53:12 AM UTC 24 421326474 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1885291987 Sep 24 06:52:59 AM UTC 24 Sep 24 06:53:12 AM UTC 24 989495038 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1803175812 Sep 24 06:50:10 AM UTC 24 Sep 24 06:53:12 AM UTC 24 3345516664 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2144004252 Sep 24 06:51:19 AM UTC 24 Sep 24 06:53:13 AM UTC 24 2075513112 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.3019260938 Sep 24 06:53:02 AM UTC 24 Sep 24 06:53:17 AM UTC 24 1139964821 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3432540559 Sep 24 06:50:08 AM UTC 24 Sep 24 06:53:18 AM UTC 24 6515243392 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.1300785904 Sep 24 06:52:56 AM UTC 24 Sep 24 06:53:24 AM UTC 24 1378868896 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3097287422 Sep 24 06:53:03 AM UTC 24 Sep 24 06:53:23 AM UTC 24 543673544 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1089454037 Sep 24 06:51:04 AM UTC 24 Sep 24 06:53:27 AM UTC 24 44560691152 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.998774125 Sep 24 06:51:36 AM UTC 24 Sep 24 06:53:27 AM UTC 24 1841407430 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.851711640 Sep 24 06:53:13 AM UTC 24 Sep 24 06:53:27 AM UTC 24 183299688 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1857491417 Sep 24 06:53:17 AM UTC 24 Sep 24 06:53:28 AM UTC 24 188709963 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.4040008171 Sep 24 06:52:41 AM UTC 24 Sep 24 06:53:31 AM UTC 24 602339320 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2300973279 Sep 24 06:53:19 AM UTC 24 Sep 24 06:53:32 AM UTC 24 1503671301 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4250084592 Sep 24 06:51:17 AM UTC 24 Sep 24 06:53:33 AM UTC 24 9827192877 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2552370776 Sep 24 06:52:52 AM UTC 24 Sep 24 06:53:34 AM UTC 24 718283182 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2831265813 Sep 24 06:53:22 AM UTC 24 Sep 24 06:53:35 AM UTC 24 180378434 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2777168350 Sep 24 06:53:04 AM UTC 24 Sep 24 06:53:35 AM UTC 24 1768970750 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2610352088 Sep 24 06:53:27 AM UTC 24 Sep 24 06:53:39 AM UTC 24 167718672 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3542619233 Sep 24 06:51:44 AM UTC 24 Sep 24 06:53:39 AM UTC 24 10454043459 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2349679889 Sep 24 06:52:47 AM UTC 24 Sep 24 06:53:39 AM UTC 24 1210038964 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.424612652 Sep 24 06:53:28 AM UTC 24 Sep 24 06:53:39 AM UTC 24 2509902820 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3583154174 Sep 24 06:53:13 AM UTC 24 Sep 24 06:53:41 AM UTC 24 679203318 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2155114783 Sep 24 06:50:52 AM UTC 24 Sep 24 06:53:41 AM UTC 24 8568186769 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3022394019 Sep 24 06:53:12 AM UTC 24 Sep 24 06:53:43 AM UTC 24 2162118803 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2679175572 Sep 24 06:53:34 AM UTC 24 Sep 24 06:53:43 AM UTC 24 274026560 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1855028290 Sep 24 06:50:55 AM UTC 24 Sep 24 06:53:45 AM UTC 24 3898973702 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3599480087 Sep 24 06:53:25 AM UTC 24 Sep 24 06:53:46 AM UTC 24 1320083594 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.121060597 Sep 24 06:53:29 AM UTC 24 Sep 24 06:53:48 AM UTC 24 2325974722 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2964399030 Sep 24 06:53:36 AM UTC 24 Sep 24 06:53:53 AM UTC 24 954048109 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3560884940 Sep 24 06:53:40 AM UTC 24 Sep 24 06:53:53 AM UTC 24 176229079 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3469022918 Sep 24 06:53:42 AM UTC 24 Sep 24 06:53:54 AM UTC 24 365062182 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.931377600 Sep 24 06:50:10 AM UTC 24 Sep 24 06:53:56 AM UTC 24 1592522138 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.627175751 Sep 24 06:53:32 AM UTC 24 Sep 24 06:53:56 AM UTC 24 1434523952 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3038667786 Sep 24 06:50:19 AM UTC 24 Sep 24 06:53:58 AM UTC 24 3770649826 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.118495195 Sep 24 06:50:57 AM UTC 24 Sep 24 06:53:59 AM UTC 24 31089620885 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2885256330 Sep 24 06:50:07 AM UTC 24 Sep 24 06:54:00 AM UTC 24 1460553349 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.883071744 Sep 24 06:53:46 AM UTC 24 Sep 24 06:54:01 AM UTC 24 516262451 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1980522677 Sep 24 06:53:49 AM UTC 24 Sep 24 06:54:05 AM UTC 24 271533293 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3583645916 Sep 24 06:51:58 AM UTC 24 Sep 24 06:54:06 AM UTC 24 2549071111 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3250143696 Sep 24 06:53:56 AM UTC 24 Sep 24 06:54:06 AM UTC 24 338943820 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3913234382 Sep 24 06:51:26 AM UTC 24 Sep 24 06:54:06 AM UTC 24 2396470247 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1224478230 Sep 24 06:53:44 AM UTC 24 Sep 24 06:54:06 AM UTC 24 1320527210 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3180593370 Sep 24 06:53:40 AM UTC 24 Sep 24 06:54:08 AM UTC 24 2102160139 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2679990286 Sep 24 06:53:35 AM UTC 24 Sep 24 06:54:09 AM UTC 24 742373790 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2474690269 Sep 24 06:52:40 AM UTC 24 Sep 24 06:54:10 AM UTC 24 2246826228 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1631928623 Sep 24 06:51:53 AM UTC 24 Sep 24 06:54:11 AM UTC 24 10211328385 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.897051209 Sep 24 06:53:39 AM UTC 24 Sep 24 06:54:11 AM UTC 24 502556569 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1428878205 Sep 24 06:53:59 AM UTC 24 Sep 24 06:54:12 AM UTC 24 178947392 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2818146614 Sep 24 06:50:08 AM UTC 24 Sep 24 06:54:16 AM UTC 24 3072844373 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.926148233 Sep 24 06:53:39 AM UTC 24 Sep 24 06:54:17 AM UTC 24 1920433380 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.4223899013 Sep 24 06:53:47 AM UTC 24 Sep 24 06:54:17 AM UTC 24 2162343640 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2941243764 Sep 24 06:53:54 AM UTC 24 Sep 24 06:54:18 AM UTC 24 509075583 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1733112949 Sep 24 06:50:08 AM UTC 24 Sep 24 06:54:20 AM UTC 24 2458641683 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3675072331 Sep 24 06:54:10 AM UTC 24 Sep 24 06:54:20 AM UTC 24 1073885875 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.231767380 Sep 24 06:54:06 AM UTC 24 Sep 24 06:54:20 AM UTC 24 3955652816 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3853994211 Sep 24 06:52:28 AM UTC 24 Sep 24 06:54:23 AM UTC 24 3072131322 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2803656721 Sep 24 06:54:08 AM UTC 24 Sep 24 06:54:25 AM UTC 24 822269227 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.502047602 Sep 24 06:54:01 AM UTC 24 Sep 24 06:54:26 AM UTC 24 332307900 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1644438354 Sep 24 06:53:45 AM UTC 24 Sep 24 06:54:27 AM UTC 24 1878676201 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1901736960 Sep 24 06:54:15 AM UTC 24 Sep 24 06:54:28 AM UTC 24 257108327 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.347601353 Sep 24 06:50:10 AM UTC 24 Sep 24 06:54:28 AM UTC 24 14299348918 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3352715764 Sep 24 06:54:12 AM UTC 24 Sep 24 06:54:28 AM UTC 24 513886065 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1169209876 Sep 24 06:54:08 AM UTC 24 Sep 24 06:54:31 AM UTC 24 1378121646 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.4099914702 Sep 24 06:53:59 AM UTC 24 Sep 24 06:54:32 AM UTC 24 375502650 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2071101501 Sep 24 06:50:12 AM UTC 24 Sep 24 06:54:34 AM UTC 24 1174197780 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2842018034 Sep 24 06:54:19 AM UTC 24 Sep 24 06:54:34 AM UTC 24 559527094 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.743870027 Sep 24 06:50:48 AM UTC 24 Sep 24 06:54:35 AM UTC 24 12791152500 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2099386851 Sep 24 06:54:22 AM UTC 24 Sep 24 06:54:37 AM UTC 24 3536200845 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3366572440 Sep 24 06:51:42 AM UTC 24 Sep 24 06:54:37 AM UTC 24 8971725612 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.675523420 Sep 24 06:54:22 AM UTC 24 Sep 24 06:54:37 AM UTC 24 2141903540 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.585103561 Sep 24 06:54:27 AM UTC 24 Sep 24 06:54:39 AM UTC 24 175372487 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3565921875 Sep 24 06:54:06 AM UTC 24 Sep 24 06:54:40 AM UTC 24 3663117953 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.522161862 Sep 24 06:54:19 AM UTC 24 Sep 24 06:54:40 AM UTC 24 379198566 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2701595245 Sep 24 06:54:23 AM UTC 24 Sep 24 06:54:43 AM UTC 24 1289941897 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.505622159 Sep 24 06:51:15 AM UTC 24 Sep 24 06:54:43 AM UTC 24 2493469893 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.3619614183 Sep 24 06:54:28 AM UTC 24 Sep 24 06:54:44 AM UTC 24 268435794 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2964863424 Sep 24 06:50:44 AM UTC 24 Sep 24 06:54:44 AM UTC 24 6144283977 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.189927008 Sep 24 06:54:12 AM UTC 24 Sep 24 06:54:45 AM UTC 24 1074657062 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2261985692 Sep 24 06:54:20 AM UTC 24 Sep 24 06:54:46 AM UTC 24 350077032 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2166395900 Sep 24 06:54:35 AM UTC 24 Sep 24 06:54:48 AM UTC 24 661955361 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2481532113 Sep 24 06:54:36 AM UTC 24 Sep 24 06:54:51 AM UTC 24 1021532475 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1997251939 Sep 24 06:54:39 AM UTC 24 Sep 24 06:54:51 AM UTC 24 991212529 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1346051260 Sep 24 06:54:26 AM UTC 24 Sep 24 06:54:52 AM UTC 24 1502276955 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3332454313 Sep 24 06:54:10 AM UTC 24 Sep 24 06:54:52 AM UTC 24 1568588230 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1061354300 Sep 24 06:51:29 AM UTC 24 Sep 24 06:54:55 AM UTC 24 7829812745 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.358975976 Sep 24 06:54:45 AM UTC 24 Sep 24 06:54:57 AM UTC 24 395528448 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3324966734 Sep 24 06:50:50 AM UTC 24 Sep 24 06:54:57 AM UTC 24 12904499278 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.2423561210 Sep 24 06:54:32 AM UTC 24 Sep 24 06:54:57 AM UTC 24 2056602791 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.2572170394 Sep 24 06:54:41 AM UTC 24 Sep 24 06:54:58 AM UTC 24 269812176 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1662734821 Sep 24 06:54:12 AM UTC 24 Sep 24 06:54:59 AM UTC 24 1055379096 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.203789968 Sep 24 06:54:53 AM UTC 24 Sep 24 06:55:03 AM UTC 24 172498957 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.871487007 Sep 24 06:54:47 AM UTC 24 Sep 24 06:55:04 AM UTC 24 1033521505 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1118886023 Sep 24 06:54:38 AM UTC 24 Sep 24 06:55:08 AM UTC 24 2371184765 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.557344379 Sep 24 06:54:40 AM UTC 24 Sep 24 06:55:10 AM UTC 24 6060799714 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1591714336 Sep 24 06:54:24 AM UTC 24 Sep 24 06:58:24 AM UTC 24 45777978052 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.3381586508 Sep 24 06:54:56 AM UTC 24 Sep 24 06:55:10 AM UTC 24 701020530 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.981406072 Sep 24 06:54:58 AM UTC 24 Sep 24 06:55:11 AM UTC 24 169463846 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.754244099 Sep 24 06:54:35 AM UTC 24 Sep 24 06:55:12 AM UTC 24 553707875 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2566767497 Sep 24 06:54:28 AM UTC 24 Sep 24 06:55:13 AM UTC 24 720723964 ps
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