Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

540682

1

T1

30

T2

233

T3

116

full_word

331876

1

T1

3

T2

23

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	872248	1			T1	33		T2	256		T3	121
auto[TlIntgErrCmd]	97	1			T61	3		T62	6		T63	4
auto[TlIntgErrData]	99	1			T61	1		T62	1		T63	2
auto[TlIntgErrBoth]	114	1			T61	6		T62	3		T63	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159799

1

T1

33

T2

256

T3

121

auto[1]

712759

1

T8

3182

T15

11232

T16

15057

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	79328	1			T1	30		T2	233		T3	116
auto[TlIntgErrNone]	partial	auto[1]	461071	1			T8	1976		T15	6874		T16	10311
auto[TlIntgErrNone]	full_word	auto[0]	80329	1			T1	3		T2	23		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	251520	1			T8	1206		T15	4358		T16	4746
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T61	2		T63	2		T115	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T61	1		T62	5		T63	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T118	1		T123	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T62	1		T63	1		T116	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T61	1		T62	1		T115	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T63	2		T115	3		T118	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T115	1		T116	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T116	1		T124	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T61	2		T63	1		T115	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T61	3		T62	3		T63	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T119	1		T125	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T61	1		T114	1		T119	1