Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender	100.00	100.00					100.00

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Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.53	100.00	97.67		100.00	100.00	100.00	u_compare

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	41689278	41525349	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41689278	41525349	0	0
T1	17229	17160	0	0
T2	25567	25472	0	0
T3	53602	53389	0	0
T4	98791	98724	0	0
T5	49559	49417	0	0
T6	17596	17542	0	0
T7	25366	25292	0	0
T8	91300	91197	0	0
T9	16528	16453	0	0
T10	26098	26010	0	0