Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.36 92.28 97.68 100.00 98.55 97.91 99.06


Total tests in report: 458
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.37 62.37 94.52 94.52 68.54 68.54 42.20 42.20 40.00 40.00 88.04 88.04 93.43 93.43 9.84 9.84 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1193466941
78.81 16.45 95.03 0.51 77.25 8.71 70.06 27.86 46.67 6.67 90.94 2.90 94.93 1.49 76.81 66.98 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2356764920
83.30 4.49 98.73 3.69 82.58 5.34 73.06 3.00 60.00 13.33 94.20 3.26 95.37 0.45 79.16 2.34 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3911122689
87.65 4.34 98.73 0.00 85.11 2.53 73.06 0.00 86.67 26.67 94.57 0.36 95.52 0.15 79.86 0.70 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1327878439
90.50 2.85 98.98 0.25 86.94 1.83 81.56 8.50 93.33 6.67 96.38 1.81 95.97 0.45 80.33 0.47 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.382156046
92.20 1.70 98.98 0.00 87.36 0.42 86.03 4.47 100.00 6.67 96.74 0.36 95.97 0.00 80.33 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2827577164
93.57 1.37 98.98 0.00 88.06 0.70 87.06 1.02 100.00 0.00 96.74 0.00 96.12 0.15 88.06 7.73 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.998579374
94.60 1.03 99.24 0.25 88.76 0.70 87.06 0.00 100.00 0.00 97.83 1.09 96.12 0.00 93.21 5.15 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.288270682
95.39 0.79 99.24 0.00 90.31 1.54 89.71 2.65 100.00 0.00 97.83 0.00 96.27 0.15 94.38 1.17 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1564816155
95.97 0.59 99.24 0.00 90.31 0.00 93.80 4.10 100.00 0.00 97.83 0.00 96.27 0.00 94.38 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1026492333
96.24 0.27 99.24 0.00 90.31 0.00 95.43 1.62 100.00 0.00 97.83 0.00 96.27 0.00 94.61 0.23 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.878742547
96.50 0.26 99.36 0.13 90.87 0.56 95.93 0.50 100.00 0.00 98.19 0.36 96.27 0.00 94.85 0.23 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1151275994
96.73 0.23 99.36 0.00 90.87 0.00 95.93 0.00 100.00 0.00 98.19 0.00 96.27 0.00 96.49 1.64 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3894965024
96.96 0.23 99.36 0.00 91.43 0.56 95.98 0.05 100.00 0.00 98.19 0.00 96.57 0.30 97.19 0.70 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1956717245
97.13 0.17 99.36 0.00 91.43 0.00 95.98 0.00 100.00 0.00 98.19 0.00 97.76 1.19 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2637533172
97.27 0.14 99.36 0.00 91.57 0.14 96.43 0.45 100.00 0.00 98.55 0.36 97.76 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3051057534
97.37 0.10 99.36 0.00 91.57 0.00 96.43 0.00 100.00 0.00 98.55 0.00 97.76 0.00 97.89 0.70 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1179075911
97.44 0.07 99.36 0.00 91.71 0.14 96.78 0.35 100.00 0.00 98.55 0.00 97.76 0.00 97.89 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1222197884
97.50 0.07 99.36 0.00 91.71 0.00 96.78 0.00 100.00 0.00 98.55 0.00 97.76 0.00 98.36 0.47 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1006222987
97.57 0.07 99.36 0.00 91.71 0.00 96.78 0.00 100.00 0.00 98.55 0.00 97.76 0.00 98.83 0.47 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4012228711
97.62 0.05 99.36 0.00 91.71 0.00 97.13 0.35 100.00 0.00 98.55 0.00 97.76 0.00 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2424711075
97.66 0.04 99.36 0.00 91.85 0.14 97.13 0.00 100.00 0.00 98.55 0.00 97.91 0.15 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3276718135
97.70 0.04 99.36 0.00 92.13 0.28 97.13 0.00 100.00 0.00 98.55 0.00 97.91 0.00 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.15590966
97.74 0.03 99.36 0.00 92.13 0.00 97.13 0.00 100.00 0.00 98.55 0.00 97.91 0.00 99.06 0.23 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.597135836
97.76 0.03 99.36 0.00 92.28 0.14 97.18 0.05 100.00 0.00 98.55 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1226543162
97.79 0.02 99.36 0.00 92.28 0.00 97.35 0.17 100.00 0.00 98.55 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.4043733535
97.81 0.02 99.36 0.00 92.28 0.00 97.50 0.15 100.00 0.00 98.55 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1492766202
97.83 0.02 99.36 0.00 92.28 0.00 97.63 0.12 100.00 0.00 98.55 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2286589916
97.83 0.01 99.36 0.00 92.28 0.00 97.68 0.05 100.00 0.00 98.55 0.00 97.91 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3295441626

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2210530753
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3785737420
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3029458509
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3829706351
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.963338213
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4053053221
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4228169020
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3293782495
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.613671199
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1555878361
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1415958175
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3098959608
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.375443920
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3892510213
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.203423405
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2002978828
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.540717616
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2762055578
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3103852115
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.709064525
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.340230395
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1791861201
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.627779512
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3567707934
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2177128901
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1468857876
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1141452994
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1518203452
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2065371283
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1419135704
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1057743080
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3167678985
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1353206030
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.692720811
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1855914849
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.436881115
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1529201620
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1256810973
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3261528547
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.411010075
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3559711766
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3634118488
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.546607705
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3140348547
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1418654468
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3950084634
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2936123
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3411198689
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.695867658
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4084065369
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3518841289
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2777821625
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1908970179
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3320025791
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3234634087
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1754357219
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.522915284
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4157326530
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.307574504
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.365685003
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2069683845
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2852584217
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2704930424
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.673552469
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1282091225
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3613082128
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.907328881
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.396808218
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.524905201
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2261834391
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.281244704
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3794565374
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3785066063
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1403363030
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2284957697
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.621364231
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2278638915
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Total test records in report: 458
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2698076827 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:24 AM UTC 24 212180295 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.970957771 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:24 AM UTC 24 205642079 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.2199072442 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:26 AM UTC 24 1142076974 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1193466941 Oct 09 07:30:16 AM UTC 24 Oct 09 07:30:27 AM UTC 24 708566892 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.998579374 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:27 AM UTC 24 1074330645 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.572811751 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:28 AM UTC 24 303769841 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.2202497830 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:29 AM UTC 24 304617015 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2058973874 Oct 09 07:30:16 AM UTC 24 Oct 09 07:30:29 AM UTC 24 534444556 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1749977599 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:30 AM UTC 24 212380449 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1151275994 Oct 09 07:30:19 AM UTC 24 Oct 09 07:30:32 AM UTC 24 221755912 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.512694163 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:32 AM UTC 24 221753349 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1492766202 Oct 09 07:30:19 AM UTC 24 Oct 09 07:30:32 AM UTC 24 1408586242 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1816757679 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:33 AM UTC 24 945628258 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3911122689 Oct 09 07:30:23 AM UTC 24 Oct 09 07:30:34 AM UTC 24 1066879248 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1015830228 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:34 AM UTC 24 1070078011 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.450079682 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:34 AM UTC 24 1328962144 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3899789074 Oct 09 07:30:59 AM UTC 24 Oct 09 07:31:14 AM UTC 24 316058893 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3584235056 Oct 09 07:30:23 AM UTC 24 Oct 09 07:30:35 AM UTC 24 390912377 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.2690763538 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:36 AM UTC 24 298701808 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1999316160 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:37 AM UTC 24 566409517 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.4043733535 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:38 AM UTC 24 1068370935 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.145159091 Oct 09 07:30:25 AM UTC 24 Oct 09 07:30:38 AM UTC 24 289089475 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2424711075 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:39 AM UTC 24 2096482474 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1209929619 Oct 09 07:30:23 AM UTC 24 Oct 09 07:30:40 AM UTC 24 4004513481 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2615558710 Oct 09 07:30:25 AM UTC 24 Oct 09 07:30:40 AM UTC 24 575817747 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2205257092 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:41 AM UTC 24 2500802071 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2710355879 Oct 09 07:30:30 AM UTC 24 Oct 09 07:30:41 AM UTC 24 742737213 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2286589916 Oct 09 07:30:16 AM UTC 24 Oct 09 07:30:42 AM UTC 24 2156477674 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1564816155 Oct 09 07:30:14 AM UTC 24 Oct 09 07:30:42 AM UTC 24 422807588 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3051057534 Oct 09 07:30:19 AM UTC 24 Oct 09 07:30:43 AM UTC 24 939119990 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.729222388 Oct 09 07:30:25 AM UTC 24 Oct 09 07:30:43 AM UTC 24 233235187 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.4047776162 Oct 09 07:30:29 AM UTC 24 Oct 09 07:30:44 AM UTC 24 297619457 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.382156046 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:44 AM UTC 24 533988579 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1234953358 Oct 09 07:30:30 AM UTC 24 Oct 09 07:30:45 AM UTC 24 762698641 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1442668642 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:46 AM UTC 24 608584339 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.887111782 Oct 09 07:30:34 AM UTC 24 Oct 09 07:30:46 AM UTC 24 221650256 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.4118291931 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:47 AM UTC 24 2218973519 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4012228711 Oct 09 07:30:33 AM UTC 24 Oct 09 07:30:48 AM UTC 24 4353550206 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3173597678 Oct 09 07:30:23 AM UTC 24 Oct 09 07:30:51 AM UTC 24 1024573156 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2827577164 Oct 09 07:30:23 AM UTC 24 Oct 09 07:30:52 AM UTC 24 2095827601 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2760894707 Oct 09 07:30:35 AM UTC 24 Oct 09 07:30:52 AM UTC 24 763652449 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1550580595 Oct 09 07:30:39 AM UTC 24 Oct 09 07:30:53 AM UTC 24 1735099532 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3532226016 Oct 09 07:30:39 AM UTC 24 Oct 09 07:30:53 AM UTC 24 287497575 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.216217882 Oct 09 07:30:42 AM UTC 24 Oct 09 07:30:53 AM UTC 24 700004906 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3084265616 Oct 09 07:30:20 AM UTC 24 Oct 09 07:30:54 AM UTC 24 456500119 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.847806495 Oct 09 07:30:33 AM UTC 24 Oct 09 07:30:54 AM UTC 24 699972564 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.2712007429 Oct 09 07:30:27 AM UTC 24 Oct 09 07:30:55 AM UTC 24 1009027279 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.502043325 Oct 09 07:30:43 AM UTC 24 Oct 09 07:30:56 AM UTC 24 925721036 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3798100384 Oct 09 07:30:23 AM UTC 24 Oct 09 07:30:58 AM UTC 24 801306894 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3260182617 Oct 09 07:30:35 AM UTC 24 Oct 09 07:30:58 AM UTC 24 330296664 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.4049288663 Oct 09 07:30:35 AM UTC 24 Oct 09 07:30:58 AM UTC 24 1359964323 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.4099666850 Oct 09 07:30:39 AM UTC 24 Oct 09 07:30:58 AM UTC 24 2348612213 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.3332089174 Oct 09 07:30:45 AM UTC 24 Oct 09 07:30:58 AM UTC 24 205796684 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1963335749 Oct 09 07:30:45 AM UTC 24 Oct 09 07:31:00 AM UTC 24 1108972478 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2270709185 Oct 09 07:30:30 AM UTC 24 Oct 09 07:31:00 AM UTC 24 406448088 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.1832530214 Oct 09 07:30:47 AM UTC 24 Oct 09 07:31:00 AM UTC 24 756778648 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1604638573 Oct 09 07:30:45 AM UTC 24 Oct 09 07:31:01 AM UTC 24 321908731 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1026492333 Oct 09 07:30:20 AM UTC 24 Oct 09 07:31:02 AM UTC 24 1077012717 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.586587378 Oct 09 07:30:47 AM UTC 24 Oct 09 07:31:03 AM UTC 24 1386064270 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1591928836 Oct 09 07:30:53 AM UTC 24 Oct 09 07:31:03 AM UTC 24 227849611 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.418824221 Oct 09 07:30:41 AM UTC 24 Oct 09 07:31:04 AM UTC 24 533958567 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4232985754 Oct 09 07:30:23 AM UTC 24 Oct 09 07:31:04 AM UTC 24 11071995058 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.508040393 Oct 09 07:30:25 AM UTC 24 Oct 09 07:31:05 AM UTC 24 1519972561 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3465332749 Oct 09 07:30:56 AM UTC 24 Oct 09 07:31:06 AM UTC 24 1488594223 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1675761655 Oct 09 07:30:53 AM UTC 24 Oct 09 07:31:07 AM UTC 24 309282337 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2896997746 Oct 09 07:30:44 AM UTC 24 Oct 09 07:31:07 AM UTC 24 4749270456 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2393495466 Oct 09 07:30:46 AM UTC 24 Oct 09 07:31:11 AM UTC 24 535760265 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1418082981 Oct 09 07:30:42 AM UTC 24 Oct 09 07:31:11 AM UTC 24 1284343723 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.2362013205 Oct 09 07:31:01 AM UTC 24 Oct 09 07:31:12 AM UTC 24 735463436 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1129103417 Oct 09 07:30:52 AM UTC 24 Oct 09 07:31:16 AM UTC 24 550023794 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3258281020 Oct 09 07:30:58 AM UTC 24 Oct 09 07:31:16 AM UTC 24 215848794 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1852744661 Oct 09 07:31:04 AM UTC 24 Oct 09 07:31:17 AM UTC 24 543850680 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2219797627 Oct 09 07:30:47 AM UTC 24 Oct 09 07:31:18 AM UTC 24 4130762945 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.578217963 Oct 09 07:31:01 AM UTC 24 Oct 09 07:31:19 AM UTC 24 5544531024 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2356764920 Oct 09 07:30:14 AM UTC 24 Oct 09 07:31:21 AM UTC 24 1625707854 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.161989341 Oct 09 07:31:09 AM UTC 24 Oct 09 07:31:21 AM UTC 24 212705697 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.764137095 Oct 09 07:31:05 AM UTC 24 Oct 09 07:31:21 AM UTC 24 1113543102 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3213970665 Oct 09 07:30:55 AM UTC 24 Oct 09 07:31:22 AM UTC 24 533466849 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3879621493 Oct 09 07:30:57 AM UTC 24 Oct 09 07:31:23 AM UTC 24 4016388485 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.656520159 Oct 09 07:30:59 AM UTC 24 Oct 09 07:31:23 AM UTC 24 371517888 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1518485546 Oct 09 07:30:53 AM UTC 24 Oct 09 07:31:25 AM UTC 24 569713471 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.4031882260 Oct 09 07:31:11 AM UTC 24 Oct 09 07:31:27 AM UTC 24 737505270 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1007454445 Oct 09 07:31:06 AM UTC 24 Oct 09 07:31:27 AM UTC 24 370208622 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3295441626 Oct 09 07:31:04 AM UTC 24 Oct 09 07:31:31 AM UTC 24 1140752238 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.4045110342 Oct 09 07:31:19 AM UTC 24 Oct 09 07:31:32 AM UTC 24 357745770 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1754218966 Oct 09 07:31:03 AM UTC 24 Oct 09 07:31:33 AM UTC 24 3838643359 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.4050860825 Oct 09 07:31:22 AM UTC 24 Oct 09 07:31:34 AM UTC 24 208827144 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.878742547 Oct 09 07:30:46 AM UTC 24 Oct 09 07:31:35 AM UTC 24 1042982940 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3154691648 Oct 09 07:31:19 AM UTC 24 Oct 09 07:31:35 AM UTC 24 1938986447 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2237998764 Oct 09 07:30:20 AM UTC 24 Oct 09 07:31:36 AM UTC 24 2043326302 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2078474129 Oct 09 07:31:13 AM UTC 24 Oct 09 07:31:39 AM UTC 24 377304291 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.245604206 Oct 09 07:31:23 AM UTC 24 Oct 09 07:31:39 AM UTC 24 1870864058 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.717464173 Oct 09 07:31:09 AM UTC 24 Oct 09 07:31:41 AM UTC 24 2074797088 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3554697455 Oct 09 07:31:27 AM UTC 24 Oct 09 07:31:42 AM UTC 24 321927333 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2813352651 Oct 09 07:31:20 AM UTC 24 Oct 09 07:31:49 AM UTC 24 2096084998 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.2266060379 Oct 09 07:31:36 AM UTC 24 Oct 09 07:31:50 AM UTC 24 205364855 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2205464662 Oct 09 07:31:33 AM UTC 24 Oct 09 07:31:51 AM UTC 24 1107450736 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.737520425 Oct 09 07:31:24 AM UTC 24 Oct 09 07:31:54 AM UTC 24 2014637661 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2049243982 Oct 09 07:31:37 AM UTC 24 Oct 09 07:31:54 AM UTC 24 381353347 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.695196675 Oct 09 07:31:19 AM UTC 24 Oct 09 07:31:55 AM UTC 24 2276683973 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3220044216 Oct 09 07:31:22 AM UTC 24 Oct 09 07:31:57 AM UTC 24 1129873931 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1278822886 Oct 09 07:31:43 AM UTC 24 Oct 09 07:31:58 AM UTC 24 673642743 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2207612371 Oct 09 07:31:34 AM UTC 24 Oct 09 07:31:59 AM UTC 24 533425443 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2328867067 Oct 09 07:31:36 AM UTC 24 Oct 09 07:32:00 AM UTC 24 778581605 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2811841225 Oct 09 07:31:52 AM UTC 24 Oct 09 07:32:05 AM UTC 24 997694831 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1222197884 Oct 09 07:30:28 AM UTC 24 Oct 09 07:32:08 AM UTC 24 1989743858 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4256375512 Oct 09 07:31:40 AM UTC 24 Oct 09 07:32:12 AM UTC 24 380667784 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2501929341 Oct 09 07:31:59 AM UTC 24 Oct 09 07:32:16 AM UTC 24 309234727 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.202201052 Oct 09 07:31:56 AM UTC 24 Oct 09 07:32:19 AM UTC 24 3968098942 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.2551233491 Oct 09 07:31:55 AM UTC 24 Oct 09 07:32:19 AM UTC 24 388219290 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.573377428 Oct 09 07:30:36 AM UTC 24 Oct 09 07:32:21 AM UTC 24 1834307078 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.3195342540 Oct 09 07:31:28 AM UTC 24 Oct 09 07:32:22 AM UTC 24 9948921483 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2018952809 Oct 09 07:31:22 AM UTC 24 Oct 09 07:32:24 AM UTC 24 1103656872 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3276491223 Oct 09 07:32:09 AM UTC 24 Oct 09 07:32:24 AM UTC 24 212845397 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3047062964 Oct 09 07:30:20 AM UTC 24 Oct 09 07:32:24 AM UTC 24 319422841 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.4240390622 Oct 09 07:31:16 AM UTC 24 Oct 09 07:32:25 AM UTC 24 2091928762 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.682643184 Oct 09 07:32:01 AM UTC 24 Oct 09 07:32:27 AM UTC 24 2008389134 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.625660016 Oct 09 07:31:58 AM UTC 24 Oct 09 07:32:28 AM UTC 24 1041738625 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2970956854 Oct 09 07:32:23 AM UTC 24 Oct 09 07:32:32 AM UTC 24 257548575 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1785877517 Oct 09 07:31:49 AM UTC 24 Oct 09 07:32:35 AM UTC 24 1142741757 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2881855861 Oct 09 07:32:17 AM UTC 24 Oct 09 07:32:35 AM UTC 24 1070543772 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1634921068 Oct 09 07:32:13 AM UTC 24 Oct 09 07:32:37 AM UTC 24 248120287 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2817735639 Oct 09 07:32:28 AM UTC 24 Oct 09 07:32:40 AM UTC 24 390600020 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1785742104 Oct 09 07:32:21 AM UTC 24 Oct 09 07:32:41 AM UTC 24 699465218 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2684917929 Oct 09 07:32:25 AM UTC 24 Oct 09 07:32:44 AM UTC 24 548797736 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1516006340 Oct 09 07:32:25 AM UTC 24 Oct 09 07:32:44 AM UTC 24 448288482 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3706377413 Oct 09 07:30:45 AM UTC 24 Oct 09 07:32:47 AM UTC 24 2096737789 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3993612241 Oct 09 07:30:41 AM UTC 24 Oct 09 07:32:48 AM UTC 24 12226937298 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4232367729 Oct 09 07:30:33 AM UTC 24 Oct 09 07:32:48 AM UTC 24 15832206141 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.200964578 Oct 09 07:32:35 AM UTC 24 Oct 09 07:32:52 AM UTC 24 609285503 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3214430354 Oct 09 07:30:20 AM UTC 24 Oct 09 07:32:55 AM UTC 24 3883836172 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.870784018 Oct 09 07:32:42 AM UTC 24 Oct 09 07:32:58 AM UTC 24 293464441 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3920550984 Oct 09 07:32:26 AM UTC 24 Oct 09 07:33:00 AM UTC 24 547797935 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2656504046 Oct 09 07:32:45 AM UTC 24 Oct 09 07:33:01 AM UTC 24 1058997575 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3327216274 Oct 09 07:32:38 AM UTC 24 Oct 09 07:33:03 AM UTC 24 1936940999 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1148425383 Oct 09 07:32:33 AM UTC 24 Oct 09 07:33:10 AM UTC 24 573448262 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.2441443709 Oct 09 07:32:49 AM UTC 24 Oct 09 07:33:13 AM UTC 24 1310194307 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.15590966 Oct 09 07:30:40 AM UTC 24 Oct 09 07:33:14 AM UTC 24 2706928965 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3930073246 Oct 09 07:32:53 AM UTC 24 Oct 09 07:33:15 AM UTC 24 1022611313 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1912824936 Oct 09 07:32:59 AM UTC 24 Oct 09 07:33:15 AM UTC 24 3474820390 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.316310536 Oct 09 07:32:55 AM UTC 24 Oct 09 07:33:16 AM UTC 24 870339174 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.625535962 Oct 09 07:32:45 AM UTC 24 Oct 09 07:33:17 AM UTC 24 1456920179 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1055281457 Oct 09 07:32:06 AM UTC 24 Oct 09 07:33:20 AM UTC 24 7645233764 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2299081986 Oct 09 07:31:07 AM UTC 24 Oct 09 07:33:24 AM UTC 24 9555021385 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1039867866 Oct 09 07:33:12 AM UTC 24 Oct 09 07:33:28 AM UTC 24 290503557 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.993212613 Oct 09 07:33:15 AM UTC 24 Oct 09 07:33:29 AM UTC 24 421146294 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4054126350 Oct 09 07:30:52 AM UTC 24 Oct 09 07:33:32 AM UTC 24 8812348248 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3087654035 Oct 09 07:31:04 AM UTC 24 Oct 09 07:33:33 AM UTC 24 12036903915 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2476090067 Oct 09 07:33:01 AM UTC 24 Oct 09 07:33:35 AM UTC 24 2786709559 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3756341684 Oct 09 07:33:14 AM UTC 24 Oct 09 07:33:36 AM UTC 24 782719612 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1641459571 Oct 09 07:33:25 AM UTC 24 Oct 09 07:33:38 AM UTC 24 1019331770 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1605230831 Oct 09 07:33:18 AM UTC 24 Oct 09 07:33:41 AM UTC 24 1946696023 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.4057722086 Oct 09 07:33:16 AM UTC 24 Oct 09 07:33:50 AM UTC 24 540158900 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3499782256 Oct 09 07:30:14 AM UTC 24 Oct 09 07:33:42 AM UTC 24 13091044233 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.4197496392 Oct 09 07:33:34 AM UTC 24 Oct 09 07:33:45 AM UTC 24 205584575 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3198836438 Oct 09 07:31:42 AM UTC 24 Oct 09 07:33:47 AM UTC 24 14881368380 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2542446534 Oct 09 07:30:55 AM UTC 24 Oct 09 07:33:51 AM UTC 24 6595983468 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1690166736 Oct 09 07:31:25 AM UTC 24 Oct 09 07:33:51 AM UTC 24 3561403309 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2479597650 Oct 09 07:33:04 AM UTC 24 Oct 09 07:33:53 AM UTC 24 4399286712 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.3144941674 Oct 09 07:33:37 AM UTC 24 Oct 09 07:33:55 AM UTC 24 561867850 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.1152197592 Oct 09 07:33:29 AM UTC 24 Oct 09 07:33:56 AM UTC 24 789778263 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.952162506 Oct 09 07:33:43 AM UTC 24 Oct 09 07:33:57 AM UTC 24 287928222 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3673272035 Oct 09 07:30:23 AM UTC 24 Oct 09 07:34:01 AM UTC 24 15549372388 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.362146842 Oct 09 07:33:47 AM UTC 24 Oct 09 07:34:02 AM UTC 24 307463170 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.506642169 Oct 09 07:33:42 AM UTC 24 Oct 09 07:34:04 AM UTC 24 1557372245 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1981200674 Oct 09 07:33:53 AM UTC 24 Oct 09 07:34:07 AM UTC 24 726771390 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2038877964 Oct 09 07:33:46 AM UTC 24 Oct 09 07:34:13 AM UTC 24 2831815559 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.688184587 Oct 09 07:33:20 AM UTC 24 Oct 09 07:34:13 AM UTC 24 863084433 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1226543162 Oct 09 07:30:59 AM UTC 24 Oct 09 07:34:13 AM UTC 24 3316061261 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.334175328 Oct 09 07:33:36 AM UTC 24 Oct 09 07:34:14 AM UTC 24 1014157840 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2896237367 Oct 09 07:30:14 AM UTC 24 Oct 09 07:34:14 AM UTC 24 27007321801 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3019973425 Oct 09 07:33:57 AM UTC 24 Oct 09 07:34:16 AM UTC 24 2899101384 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3128290362 Oct 09 07:33:42 AM UTC 24 Oct 09 07:34:16 AM UTC 24 1067925807 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.808548623 Oct 09 07:34:05 AM UTC 24 Oct 09 07:34:17 AM UTC 24 725604419 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.420389131 Oct 09 07:31:12 AM UTC 24 Oct 09 07:34:19 AM UTC 24 13798540758 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3766866759 Oct 09 07:30:19 AM UTC 24 Oct 09 07:34:22 AM UTC 24 4115084588 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3353378704 Oct 09 07:33:51 AM UTC 24 Oct 09 07:34:25 AM UTC 24 535536291 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.4111999319 Oct 09 07:34:15 AM UTC 24 Oct 09 07:34:27 AM UTC 24 1207944832 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.67351118 Oct 09 07:34:15 AM UTC 24 Oct 09 07:34:29 AM UTC 24 210725131 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.938082756 Oct 09 07:30:14 AM UTC 24 Oct 09 07:34:35 AM UTC 24 315314282 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1742854366 Oct 09 07:34:24 AM UTC 24 Oct 09 07:34:36 AM UTC 24 516181843 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1388367326 Oct 09 07:34:18 AM UTC 24 Oct 09 07:34:36 AM UTC 24 214132387 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1327878439 Oct 09 07:30:20 AM UTC 24 Oct 09 07:34:38 AM UTC 24 3636377546 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1116978463 Oct 09 07:34:09 AM UTC 24 Oct 09 07:34:39 AM UTC 24 353731549 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2866808942 Oct 09 07:30:14 AM UTC 24 Oct 09 07:34:39 AM UTC 24 5419895907 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2047709812 Oct 09 07:30:20 AM UTC 24 Oct 09 07:34:40 AM UTC 24 360232991 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.313400469 Oct 09 07:33:57 AM UTC 24 Oct 09 07:34:40 AM UTC 24 3494438004 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2019042190 Oct 09 07:31:35 AM UTC 24 Oct 09 07:34:41 AM UTC 24 6663698897 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.1060425713 Oct 09 07:34:03 AM UTC 24 Oct 09 07:34:42 AM UTC 24 2097824040 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1935274277 Oct 09 07:34:28 AM UTC 24 Oct 09 07:34:44 AM UTC 24 1109105986 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.3368264715 Oct 09 07:34:20 AM UTC 24 Oct 09 07:34:50 AM UTC 24 534477204 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3661542386 Oct 09 07:34:15 AM UTC 24 Oct 09 07:34:51 AM UTC 24 577175266 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3628360630 Oct 09 07:34:37 AM UTC 24 Oct 09 07:34:52 AM UTC 24 960014235 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.707989410 Oct 09 07:30:23 AM UTC 24 Oct 09 07:34:54 AM UTC 24 13354337978 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.946559789 Oct 09 07:30:19 AM UTC 24 Oct 09 07:34:54 AM UTC 24 599075244 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1348357685 Oct 09 07:32:49 AM UTC 24 Oct 09 07:34:54 AM UTC 24 2640797012 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.3178579709 Oct 09 07:35:16 AM UTC 24 Oct 09 07:35:34 AM UTC 24 413563763 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1956717245 Oct 09 07:30:14 AM UTC 24 Oct 09 07:34:55 AM UTC 24 775078790 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1458191331 Oct 09 07:34:41 AM UTC 24 Oct 09 07:34:55 AM UTC 24 207284214 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.178556742 Oct 09 07:34:40 AM UTC 24 Oct 09 07:34:58 AM UTC 24 299835093 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3835705238 Oct 09 07:33:33 AM UTC 24 Oct 09 07:34:59 AM UTC 24 5416699969 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.646062708 Oct 09 07:34:46 AM UTC 24 Oct 09 07:35:01 AM UTC 24 1063968473 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1296936695 Oct 09 07:30:31 AM UTC 24 Oct 09 07:35:04 AM UTC 24 5293332545 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3526190885 Oct 09 07:34:40 AM UTC 24 Oct 09 07:35:06 AM UTC 24 1415156124 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3536702215 Oct 09 07:30:43 AM UTC 24 Oct 09 07:35:06 AM UTC 24 4717296613 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3013645698 Oct 09 07:34:18 AM UTC 24 Oct 09 07:35:06 AM UTC 24 2234428395 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1263876099 Oct 09 07:32:22 AM UTC 24 Oct 09 07:35:07 AM UTC 24 2515487848 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.344798113 Oct 09 07:34:36 AM UTC 24 Oct 09 07:35:07 AM UTC 24 713743889 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.844875401 Oct 09 07:34:26 AM UTC 24 Oct 09 07:35:08 AM UTC 24 1158033937 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.699769872 Oct 09 07:30:59 AM UTC 24 Oct 09 07:35:08 AM UTC 24 14714473962 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2743510928 Oct 09 07:34:55 AM UTC 24 Oct 09 07:35:10 AM UTC 24 543913157 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.619782954 Oct 09 07:35:00 AM UTC 24 Oct 09 07:35:13 AM UTC 24 1027957243 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2399699875 Oct 09 07:31:55 AM UTC 24 Oct 09 07:35:14 AM UTC 24 39939866944 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.970562455 Oct 09 07:34:55 AM UTC 24 Oct 09 07:35:14 AM UTC 24 225859494 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1470124743 Oct 09 07:30:23 AM UTC 24 Oct 09 07:35:16 AM UTC 24 10891649884 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1360326096 Oct 09 07:30:27 AM UTC 24 Oct 09 07:35:17 AM UTC 24 4142204930 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.4021604884 Oct 09 07:35:05 AM UTC 24 Oct 09 07:35:18 AM UTC 24 1054821342 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3835345957 Oct 09 07:35:08 AM UTC 24 Oct 09 07:35:19 AM UTC 24 672102600 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.311713573 Oct 09 07:30:35 AM UTC 24 Oct 09 07:35:20 AM UTC 24 11556734105 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.632372150 Oct 09 07:34:52 AM UTC 24 Oct 09 07:35:20 AM UTC 24 2016534063 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.458654135 Oct 09 07:31:05 AM UTC 24 Oct 09 07:35:21 AM UTC 24 9941614223 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3724732854 Oct 09 07:35:02 AM UTC 24 Oct 09 07:35:22 AM UTC 24 366835552 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.3792645253 Oct 09 07:34:56 AM UTC 24 Oct 09 07:35:22 AM UTC 24 386605572 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.854612543 Oct 09 07:32:25 AM UTC 24 Oct 09 07:35:22 AM UTC 24 2185777933 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1682076712 Oct 09 07:32:21 AM UTC 24 Oct 09 07:35:27 AM UTC 24 12667994471 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3124588572 Oct 09 07:35:14 AM UTC 24 Oct 09 07:35:27 AM UTC 24 953806009 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2370224915 Oct 09 07:34:39 AM UTC 24 Oct 09 07:35:27 AM UTC 24 581454113 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.977432275 Oct 09 07:35:09 AM UTC 24 Oct 09 07:35:28 AM UTC 24 2905861157 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2668380403 Oct 09 07:31:19 AM UTC 24 Oct 09 07:35:30 AM UTC 24 8211710653 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.2479028728 Oct 09 07:35:08 AM UTC 24 Oct 09 07:35:30 AM UTC 24 653694929 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.2243914955 Oct 09 07:34:43 AM UTC 24 Oct 09 07:35:32 AM UTC 24 3186695931 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3419936088 Oct 09 07:35:20 AM UTC 24 Oct 09 07:35:34 AM UTC 24 212613140 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1796827866 Oct 09 07:35:11 AM UTC 24 Oct 09 07:35:36 AM UTC 24 381141570 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2332087296 Oct 09 07:30:19 AM UTC 24 Oct 09 07:35:36 AM UTC 24 11529440948 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.184861338 Oct 09 07:34:55 AM UTC 24 Oct 09 07:35:37 AM UTC 24 2164750212 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.499156719 Oct 09 07:35:24 AM UTC 24 Oct 09 07:35:37 AM UTC 24 345559263 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.130249404 Oct 09 07:35:07 AM UTC 24 Oct 09 07:35:38 AM UTC 24 8264443801 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.346592512 Oct 09 07:35:21 AM UTC 24 Oct 09 07:35:39 AM UTC 24 226024439 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3644618709 Oct 09 07:35:28 AM UTC 24 Oct 09 07:35:41 AM UTC 24 2606898832 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3259986473 Oct 09 07:35:14 AM UTC 24 Oct 09 07:35:43 AM UTC 24 1402135280 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3041057417 Oct 09 07:35:30 AM UTC 24 Oct 09 07:35:43 AM UTC 24 207234055 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4255645513 Oct 09 07:30:20 AM UTC 24 Oct 09 07:35:44 AM UTC 24 78422513956 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3761345175 Oct 09 07:35:23 AM UTC 24 Oct 09 07:35:47 AM UTC 24 700916589 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4186421693 Oct 09 07:30:45 AM UTC 24 Oct 09 07:35:48 AM UTC 24 6129002821 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.3102429279 Oct 09 07:35:37 AM UTC 24 Oct 09 07:35:51 AM UTC 24 290140219 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3863442601 Oct 09 07:35:28 AM UTC 24 Oct 09 07:35:52 AM UTC 24 700442519 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.604290228 Oct 09 07:35:33 AM UTC 24 Oct 09 07:35:52 AM UTC 24 1257442546 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.4133688264 Oct 09 07:35:39 AM UTC 24 Oct 09 07:35:54 AM UTC 24 758190087 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.924824610 Oct 09 07:35:24 AM UTC 24 Oct 09 07:35:55 AM UTC 24 333540352 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.2801727561 Oct 09 07:35:19 AM UTC 24 Oct 09 07:35:55 AM UTC 24 1065728749 ps
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